JP6600959B2 - Fault processing apparatus, information processing apparatus using the apparatus, fault processing method, and fault processing program - Google Patents

Description

  The present invention relates to a failure processing device, an information processing device using the device, a failure processing method, and a failure processing program.

  In high-speed interfaces, especially serial transmission, it is often used to transmit information in packets. A transmission method using a packet is used for connection with a peripheral device, and is also used for connection between a processor and a peripheral device in an information processing device. As a connection method in the apparatus of the information processing apparatus, for example, there is a bus architecture of PCI Express (registered trademark) (hereinafter referred to as PCIe).

  PCIe is used in a general information processing apparatus because it can realize high-speed operation. However, if reception of a response to packet transmission is not completed normally due to some failure, the host of the host information processing device does not correctly handle the failure and the wrong information is received later. continue processing. There is a drawback that the system becomes unstable as a result.

  This PCIe is widely used in various information processing apparatuses including general-purpose machines, and in recent years, it has been used more often in mainframes where stable operation of the system is regarded as important. In order to apply PCIe to a mainframe that requires stable operation of the system, it is required to secure the stable operation of the system by overcoming the above-described drawbacks of PCIe.

  For example, in Patent Document 1, it is determined that an interface device that interfaces with a lower device is timed out when there is no response from a lower device to a request packet from the upper device within a specified time in PCIe. To the host device. Upon receiving the notification, the host device retransmits a new packet in place of the time-out request packet. At this time, the higher-level apparatus writes a flag indicating that the packet is different from the packet requested first in the packet itself newly created for retransmission. Even if a response packet for the first request packet is sent from the lower-level device after the retransmission is executed based on the written information, the interface device looks at the received packet flag to determine whether it is an old packet. recognize. When the interface device recognizes that the packet is a response from the lower device to the old request, it ignores this packet and recognizes the newly retransmitted packet as a normal packet.

  In the technique described in Patent Document 2, in order to confirm the normality of the lower-level device connected to the higher-level device, the input / output connection device generates a test-dedicated packet and sends it to the target lower-level device. . When the response is an inspection packet response, the input / output connection device analyzes the received packet and determines whether or not the lower-level device is abnormal. Further, the input / output connection device suppresses packets from the host to the lower device until the inspection of the lower device is completed for a packet having the same tag as the inspection packet.

JP 2007-249646 A JP 2011-192216 A

  The technology of Patent Document 1 describes information (the above-mentioned flag) indicating retransmission in a spare information description area of a header that constitutes a packet that is not clearly defined as the PCIe specification, and based on this information. This is a technology for identifying packets. However, the information described in the spare information description area of the header is not clearly defined in the PCIe standard. Therefore, there is a concern that the information may cause an unexpected operation in these devices, or may cause a malfunction such as stopping the operation because it is illegal information. Also in the host device, there is a concern that various software created on the premise of complying with the PCIe specification may cause an unintended operation such as abnormal termination when unexpected information is detected. Therefore, there is a problem that the technique of Patent Document 1 cannot be applied to a mainframe that requires stable operation.

  Patent Document 2 does not describe a technique for avoiding a failure that occurs when a packet is received after a response from a lower-level device is delayed, a timeout is determined, and the packet with the delayed response is discarded. Therefore, if the response is delayed from the lower-level device and, as a result, a significant delay in the operation due to waiting for information acquisition such as a response from the lower-level device occurs in the higher-level device, various failures that occur because the received information is incorrect There is a problem that cannot be solved.

  An object of the present invention is to provide a failure processing device that solves the above-described problems, an information processing device that uses the device, a failure processing method, and a failure processing program.

  Specifically, according to the present invention, erroneous data generated due to a failure such as a delay in a response from a lower-level device to a command requested by the higher-level device is read by software operating on the higher-level device and the higher-level device. The main purpose is to prevent.

  The failure processing apparatus includes a list of identifiers assigned to uniquely distinguish the information from the information group, and a first storage area associated with the identifier, and the first storage area includes the identifier Identifier storage means for storing second information extracted from the information itself and information indicating whether or not the identifier is in use; and A second storage area associated with each identifier listed in the list of identifiers, wherein the second storage area is an elapsed time measured starting from the time at which the identifier was assigned; and the elapsed time Information indicating whether or not a predetermined threshold has been reached, and an elapsed time storage means for storing, and when the identifier is unused, assigning the identifier as an identifier of other information And a control unit that does not allow the identifier to be assigned as an identifier of other information when the identifier is in use and the elapsed time associated with the identifier reaches the threshold. .

  The failure processing method includes a list of identifiers assigned to uniquely distinguish the information from the information group and a first storage area associated with the identifiers, and the identifier is stored in the first storage area. Second information extracted from the information itself and information indicating whether or not the identifier is in use are stored in the list of identifiers in the identifier storage unit. A second storage area associated with each of the identifiers described, an elapsed time measured starting from the time when the identifier was assigned to the second storage area, and a predetermined threshold value Information indicating whether or not the identifier has been reached, and if the identifier is not used, the identifier is allowed to be assigned as an identifier of other information. When the elapsed time associated with the identifier it reaches the threshold does not allow to assign the identifier as an identifier of the other information.

  The failure processing program includes a list of identifiers assigned to uniquely distinguish the information from the information group and a first storage area associated with the identifier, and the identifier is stored in the first storage area. Second information extracted from the information itself and information indicating whether or not the identifier is in use are stored in the list of identifiers in the identifier storage unit. A second storage area associated with each of the identifiers described, an elapsed time measured starting from the time when the identifier was assigned to the second storage area, and a predetermined threshold value Information indicating whether or not the identifier has been reached, and when the identifier is unused, permits the identifier to be assigned as an identifier of other information, and the identifier is in use and When the elapsed time associated with the front Symbol identifier reaches the threshold value to execute processing that permits to assign the identifier as an identifier of the other information into the computer.

  The present invention can prevent erroneous data generated due to a failure such as a delay in a response from a lower-level device to a command requested by the higher-level device from being read by software operating on the higher-level device and the higher-level device.

It is a block diagram which shows the failure processing apparatus in the 1st Embodiment of this invention. It is a block diagram which shows the failure processing apparatus in the 2nd Embodiment of this invention. FIG. 3 is a diagram illustrating an identifier (tag entry) storage unit 20. 3 is a diagram illustrating an elapsed time (timer entry) storage unit 30. FIG. It is a flowchart which shows a read process. It is a flowchart of a response process. It is a flowchart of a timeout process. It is a figure explaining operation | movement of a memory read. It is a figure explaining operation | movement when a response timeout is detected. It is a figure explaining operation | movement when a failure generate | occur | produces by response time-out. FIG. 3 is a diagram illustrating an identifier (tag entry) storage unit 20. It is a response processing flowchart. It is a timeout o processing flowchart. It is a tag entry release process flowchart. It is a figure explaining operation | movement at the time of performing subsequent memory read after memory read time-out response. It is a figure of the TLP header used by the memory access request of a 64-bit address format. It is a figure of the TLP header used by the memory access request of a 32-bit address format. It is a figure of the TLP header used by a response access request. It is a figure of the TLP header of the response with respect to a memory read request or a structure access request. It is a block diagram which shows the failure processing system in the 3rd Embodiment of this invention. It is a functional block diagram of the failure processing apparatus 101 of the present invention. FIG. 3 is a diagram showing an identifier (tag entry) storage unit 22. It is a figure which shows the elapsed time (timer entry) memory | storage part 32. FIG.

[First embodiment]
A first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a failure processing apparatus 180 according to the first embodiment of this invention.

  The failure processing apparatus 180 includes a control unit 6, an identifier storage unit 21, and an elapsed time storage unit 31. The identifier storage unit 21 and the elapsed time storage unit 31 are connected to the control unit 6. The control unit 6 receives the command information from the higher-level device 2 and outputs it to the lower-level device 3. The control unit 6 receives response information from the lower apparatus 3 and outputs it to the upper apparatus 2. The present invention is not limited to the configuration shown in FIG.

  The identifier storage unit 21 includes a storage area to which an identifier is attached. The storage area of the identifier associated with the command (command information) sent from the higher-level device 2 in the identifier storage unit 21 is in use by the information that characterizes the lower-level device 3 extracted from the command information and the identifier related to the command information. An identifier use flag indicating whether or not there is present is stored.

  The elapsed time storage unit 31 includes a counter that stores the elapsed time in association with each identifier arranged in the identifier storage unit 21. That is, a counter is set for each identifier. The counter of the elapsed time storage unit 31 stores, for each identifier, the elapsed time counted from the time when the command information to which the identifier is assigned is sent from the control unit 1 to the lower-level device 3.

  When the control unit 6 receives the command information directed from the higher-level device 2 to the lower-level device 3, the control unit 6 selects from the identifier storage unit 21 an identifier whose use flag is OFF, that is, unused. The control unit 6 writes a part of the command information in the storage area of the selected identifier in the identifier storage unit 21. Further, the control unit 6 outputs the command information to which the selected identifier is assigned to the lower level device 3, and at the same time, the elapsed time storage unit 31 associated with the selected identifier is time elapsed every time a certain time elapses. It is updated to the value added with.

  When the counter of the identifier in the elapsed time storage unit 31 matches a predetermined threshold, the control unit 6 determines that the counter of the identifier has timed out.

  When the control unit 6 receives response information for the command information from the lower apparatus 3 during a period when the identifier counter of the elapsed time storage unit 31 has not timed out, the identifier assigned to the response information is stored in the identifier storage unit 21. It searches whether it exists in the storage area. As a result of the search, when the identifier use flag stored in the identifier storage unit 21 is valid, the control unit 6 transmits the received response information (hereinafter also simply referred to as “response”) to the higher-level device 2. The storage area of the identifier in the identifier storage device 21 is reset. By this operation, the control unit 6 can assign the identifier for identification of the next process from the higher-level device 2 that has newly generated.

  Next, a case where the numerical value of the elapsed time associated with the identifier of the elapsed time storage unit 31 exceeds the timeout threshold will be described.

  When the value of the elapsed time associated with the identifier reaches a separately determined threshold value, the control unit 6 recognizes that the response waiting for the command of the identifier has passed a specified time. In this case, the control unit 6 sets a timeout flag arranged in the storage area of the identifier in the identifier storage unit 21 to ON, and records that it is a timeout. Furthermore, the control unit 6 notifies the host device 2 that there is no response to the command information related to the identifier and timed out. With this process, the identifier is held until the process for the command information is completed, and is not assigned to another command. The host apparatus 2 recognizes that the processing of the identifier has received the timeout notification and has timed out.

  Furthermore, when the control unit 6 receives a response corresponding to the identifier from the lower-level device 3 after the identifier counter times out, the control unit 6 discards the received response information. The control unit 6 erases the storage area corresponding to the identifier in the identifier storage unit 21 elapsed time storage unit 31 and resets the stored contents. This process prevents the above-mentioned time-out identifier from being assigned to a new command from the host apparatus 2.

  As described above, according to the first embodiment of the present invention, a timed-out identifier is assigned to another command, and the response of the command at the time of the previous assignment is the information of the same identifier assigned later. It is possible to prevent being mistakenly recognized as being. This is because the control unit 6 prohibits the reassignment of the identifier with respect to the timed out identifier and permits the reassignment of the identifier after the response of the previously assigned identifier is completed.

[Second Embodiment]
A second embodiment will be described. In the second embodiment, a case where the failure handling apparatus of the present invention is applied to PCIe will be described.

  PCIe employs a packet-based protocol. A plurality of processes that are related and dependent on each other are grouped together and handled as an integral indivisible processing unit is called transaction processing, and such a processing unit is called a transaction. There is also a transaction layer in the protocol layer in PCIe, and that layer constructs and processes transaction layer packets. The packet in the transaction layer is called Transaction_Layer_Packet (hereinafter TLP), and information on the request for the connected peripheral device is stored in the header of the TLP.

  A second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram showing a failure processing apparatus 150 according to the second embodiment of the present invention.

  The failure processing apparatus 150 includes a control unit 1, an identifier storage unit 22 (hereinafter referred to as a tag entry storage unit 22), and an elapsed time storage unit 32 (hereinafter referred to as a timer entry storage unit 32).

  The tag entry storage unit 22 and the timer entry storage unit 32 are connected to the control unit 1. The control unit 1 includes a request buffer 4 and a response buffer 5. The control unit 1 receives command information from the higher-level device 2 and outputs it to the lower-level device 3. The control unit 1 receives response information from the lower apparatus 3 and outputs it to the upper apparatus 2. The present invention is not limited to the configuration of FIG.

  In this example, the host device 2 is a processor or a card equipped with a processor. The subordinate device 3 is an interface device that connects to peripheral devices represented by a PCIe switch or the like.

  The tag entry storage unit 22 shown in FIG. 22 includes a tag entry number (0, 1, 2, 3,..., N; n is an integer) that is an identifier of command information sent from the upper apparatus 2 to the lower apparatus 3. The storage device includes the storage area 22-0 to the storage area 22-n to which the number is assigned. Each of the storage areas 22-0 to 22-n has a data area 22-nm that stores information characterizing the lower device 3 extracted from the command information sent from the upper device 2 to the lower device 3. It includes a valid flag 22-n-1 indicating whether or not the tag entry number is in use and a timeout flag 22-n-4 indicating that a timeout has occurred while waiting for a response to which the tag entry number is assigned. .

  The timer entry storage unit 32 shown in FIG. 23 is a storage device including the tag entry number associated with the tag entry storage unit 22 and the timer areas 32-0 to 32-n to which the tag entry numbers are assigned. . The timer area 32-0 to the timer area 32-n are timer counts (referred to as timer count values) 32-n-2 that store an elapsed time that is measured from the time when the control unit 1 sends a command to the lower-level device 3. And a valid flag 32-n-1 indicating whether or not the timer count 32-n-2 is valid.

  The request buffer 4 shown in FIG. 2 temporarily stores a request TLP from the lower apparatus 3 to the upper apparatus 2. The response buffer 5 shown in FIG. 2 temporarily stores a response TLP from the lower apparatus 3 to the upper apparatus 2. Each information temporarily stored in the request buffer 4 and the response buffer 5 is sequentially read out by the control unit 1.

  When the control unit 1 receives the command information directed from the higher-level device 2 to the lower-level device 3, the control unit 1 searches the storage area of the tag entry storage unit 22 and selects a tag entry number for which the valid flag 22-n-1 is unused. . The control unit 1 writes a part of the command information in the storage area to which the tag entry number is assigned. The control unit 1 outputs the command information assigned with the tag entry number to the lower order device 3. Further, the control unit 1 updates the stored contents of the timer area 32-n in the timer entry storage unit 32 associated with the tag entry number to a numerical value obtained by adding the elapsed time every time a predetermined time elapses. To do.

  The control unit 1 receives response information from the lower-level device 3 during a period in which the value of the timer counter that stores the elapsed time of the timer area associated with the tag entry number does not exceed a predetermined threshold. Is received, it is searched whether or not the same number as the tag entry number assigned to the response information exists in the storage area of the tag entry storage unit 22.

  When the valid flag 22-n-1 in the storage area of the tag entry number stored in the tag entry storage unit 22 is valid as a result of the search by the control unit 1, the response information received by the control unit 1 is obtained. Transmit to the host device 2.

  Further, the control unit 1 resets the information in the storage area of the tag entry number in the tag entry storage unit 22. This operation enables the control unit 1 to assign the tag entry number to identification of the next command from the higher-level device 2 in which the tag entry number is newly generated.

  Next, a case where the timer count value of the timer area associated with the tag entry number in the timer entry storage unit 32 exceeds the timeout threshold will be described.

  When the value of the timer count in the timer area associated with the tag entry number reaches a separately determined threshold value, the control unit 1 recognizes that the waiting for a response to the command of the tag entry number has passed a specified time. The control unit 1 sets the timeout flag arranged in the storage area of the tag entry number in the tag entry storage unit 22 to ON, and displays that it is a timeout. The control unit 1 notifies the host device 2 that the response to the command of the tag entry number has timed out. By this process, the tag entry number is held until the process for the command is completed, and is not assigned to another command. The host device 2 recognizes that the processing of the tag entry number has received the notification of the timeout and has timed out.

  Further, when the control unit 1 receives a response corresponding to the tag entry number from the lower level device 3 after the timer count of the timer area associated with the tag entry number times out, the control unit 1 The information of the response received from 3 is discarded. The control unit 1 erases the storage of the storage area and the timer area corresponding to the tag entry number in the tag entry storage unit 22 and the timer entry storage unit 32. This process can prevent the control unit 1 from being assigned the time-out tag entry number in response to a new command from the host device 2. In this example, the request buffer 4 and the response buffer 5 are arranged inside the control unit 1. However, the configuration may be arranged outside the control unit 1.

  As described above, according to the second embodiment of the present invention, when the response of a packet is delayed for some reason, the transaction process is not completed due to a timeout, and is associated with the tag entry number. It is possible to prevent malfunction caused by discarding the storage contents of the storage area and erroneously receiving the response information stored in the storage area before the discard. Because it is prohibited to reassign the tag entry number for the timed out tag entry number, and the reassignment of the tag entry number is permitted after the response of the command with the previously assigned tag entry number is completed Because it does.

[Third embodiment]
A third embodiment of the present invention will be described with reference to the drawings. FIG. 20 is a block diagram of an information processing apparatus to which the failure processing apparatus of the present invention of the information processing apparatus 1000 is applied.

  The information processing apparatus 1000 includes a central processing unit 300, a device (DEV) 130, a PCIe switch 120, a PCIe card 140 to a PCIe card 143, an external storage device 2000, and an external storage device 3000.

  The central processing unit 300 includes a processor 100 that performs arithmetic processing, a failure processing device 101, a failure processing device 102, and a memory (MEM) 110 that stores data.

The program 200 is expanded on the processor 100 and controls the processor 100 to perform various processes. (The program 200 is not shown.)
FIG. 21 is a functional block diagram of the failure processing apparatus 101. A failure processing device (hereinafter referred to as a PCIe controller) 101 includes a control unit 1, an identifier storage unit 20 (hereinafter referred to as a tag entry storage unit 20), and an elapsed time storage unit 30 (hereinafter referred to as a timer entry storage unit 30). ).

  The tag entry storage unit 20 and the timer entry storage unit 30 are connected to the control unit 1. The control unit 1 includes a request buffer 4 and a response buffer 5. The control unit 1 receives command information from the processor 100 and outputs it to the PCIe switch 120.

  The tag entry storage unit 20 will be described with reference to FIG. The tag entry storage unit 20 includes a tag entry number that is an identifier of command information sent from the processor 100 that is a higher-level device to the PCIe switch 120 that is the lower-level device 3, and a plurality of storage areas 20-0 to which the number is assigned. The storage device includes a storage area 20-n. The storage area includes a validity flag 20-n-1 indicating that the storage area 20-n is used and valid, and a request information unit 20-n-2 that stores request information instructed by the processor 100. , Including a TLP header section 20-n-3 for storing a header of the TLP created according to an instruction from the processor 100 and transmitted to the PCIe switch 120.

The timer entry storage unit 30 will be described with reference to FIG.
The timer entry storage unit 30 is a storage device that stores information for the control unit 1 to monitor a timeout of a response to a request to the PCIe switch 120. The timer entry storage unit 30 includes the above-described tag entry number and timer areas 30-0 to 30-n associated with the tag entry number. The timer entry storage unit 30 includes a validity flag 30-n-1 indicating whether or not a timer in the timer area 30-n is valid, and a timer count (referred to as a timer count value) 30-n-2.

  The control unit 1 receives response information from the PCIe switch 120 and outputs the response information to the processor 100.

  The PCIe switch 120 is used to connect the processor 100 via the failure processing apparatus 101 to a network (not shown), the external storage device 2000 connected to each of the PCIe card 143 from the PCIe card 140 and the external storage device 3000. Switch.

  The PCIe controller 101 is positioned between the processor 100 and the PCIe switch, and performs processing for a failure that occurs in packet communication between the processor 100 and the PCIe card 140 and the PCIe card 143.

  A failure processing apparatus (referred to as a PCIe controller) 102 connects a device 130 that performs a specific process that does not pass through the PCIe switch 120 and the processor 100, and processes a failure that occurs in packet communication between the apparatuses.

  In FIG. 20, an external storage device 2000 and an external storage device 3000 are a PCIe disk and a magnetic disk device connected to each, and store data, and write and read data based on commands from the processor 100.

  The PCIe card 140 to the PCIe card 143 convert a packet-based serial interface signal into an interface signal and a connector shape of each peripheral device to be connected.

  The PCIe controller 102 and the device 130 are connected by a PCIe_I / F 131. The PCIe controller 101 and the PCIe switch 120 are connected by a PCIe_I / F 121. The PCIe switch 120 and the device 130 are connected by a PCIe_I / F 122. The PCIe switch 120 and the PCIe card 140 are connected by a PCIe_I / F 123. The PCIe switch 120 and the PCIe card 141 are connected by a PCIe_I / F 124. The PCIe switch 120 and the PCIe card 142 are connected by a PCIe_I / F 125. The PCIe switch 120 and the PCIe card 143 are connected by a PCIe_I / F 126. The PCIe card 140 and the external storage device 2000 are connected by an interface 2001. The PCIe card 141 and the external storage device 2000 are connected through an interface 2002. The PCIe card 142 and the external storage device 3000 are connected by an interface 3001. The PCIe card 143 and the external storage device 2000 are connected by an interface 3002.

  A method of exchanging data with the input / output device will be described.

  When a command is output from the host device 2 to the external storage device 2000 or the external storage device 3000, the command is transmitted from the PCIe card 140 via one of the PCIe cards 143.

  The instruction from the processor 100 to the PCIe card 140 to the PCIe card 143 realizes the operation for the input / output device by handling the instruction for the processor 100 to access the input / output device in the same address space as the instruction for accessing the MEM 110. This method is called Memory_Mapped_Input_Output (hereinafter referred to as MMIO). Hereinafter, the operation of the present invention will be described on the premise of this MMIO.

  Here, the contents of the PCIe TLP header are shown in FIG. 16, FIG. 17, FIG. 18, and FIG.

  A command issued from one device to another device is a request. An output from another device in response to the command is used as a response. The format of the TLP differs depending on the request content and whether it is a request or a response. The details of the TLP header and the operation when the TLP is received are described in the PCIe specification, so only the relationship with the present invention will be described.

  16 and 17 are TLP headers mainly used for memory access requests. FIG. 16 shows a 64-bit address format and FIG. 17 shows a 32-bit address format. Fmt (format) and Type (type) shown in FIGS. 16, 17 and 18 indicate the request contents, and the address indicates the request destination. FIG. 18 shows a TLP header used in a configuration access request, and the request destination is specified by Bus_Number (bus number), Device_Number (device number), Function_Number (function number), and Register_Number (register number).

  A requester ID (IDentifier) 41 in FIG. 17, a requester ID 51 in FIG. 18, and a requester ID 61 in FIG. 19 indicate identifiers indicating request sources. A tag 42 in FIG. 17, a tag 52 in FIG. 18, and a tag 62 in FIG. 19 indicate tag entry numbers assigned to the packets. The requester ID and tag information are extracted to form the transaction ID 70 shown in FIGS. 17, 18, and 19 and used when the control unit 1 determines whether the response corresponds to the request. The

  The transaction ID 70 in this example is information obtained by combining the requester ID and the tag. The control unit 1 indexes and recognizes requester IDs and related tags included in various request TLPs and response TLPs. However, the control unit 1 may prepare a dedicated storage area for the transaction ID 70, extract and write necessary information from the request TLP or response TLP to the area, and use the information. .

  FIG. 19 is a diagram showing details of a TLP header in response to a memory read request or a configuration access request. The response TLP header refers to the request corresponding to the response by the control unit 1, the requester ID 61 and tag 62 for the control unit 1 to identify, the response ID indicating the response source, and the response status indicating the result of the request. have. The requester ID 61 and the tag 62 are information obtained by copying the requester ID 41, the requester ID 51, the tag 42, and the tag 52 stored in the TLP of the request corresponding to the response. The PCIe controller 101 determines whether a response to the request has been returned by comparing the transaction ID 70 between the request and the response.

  Next, the operation of the PCIe interface in the information processing apparatus 1000 will be described.

  First, the memory read operation from the PCIe card 140 to the PCIe card 143 will be described with reference to FIG.

  When the software 200 operating on the processor 100 reads the registers of the PCIe card 140 to the PCIe card 143, the read instruction of the processor 100 is designated by specifying an address indicating the register of the PCIe card 140 to the PCIe card 143, and a read command is issued. Execute (a-1).

When the read instruction is executed, the processor 100 instructs the PCIe controller 101 to transmit the TLP command for memory read by designating the address (a-2).
When the PCIe controller 101 is instructed to read the memory, the PCIe controller 101 acquires a tag number from the tag entry storage unit 20 (a-3), creates a read request TLP, and transmits a TLP command to the PCIe_I / F 121 (a-4). . At this time, a value for identifying the PCIe controller is stored in the requester ID, and the control unit 1 identifies a response to the request. Therefore, the request TLP including the transaction ID is stored in the tag entry number storage area of the tag entry storage unit 20. The request information of the processor 100 is held in the tag entry number storage area of the tag entry storage unit 20 in order to return a response to the requesting processor 100 when receiving the response.

  Next, the TLP command of the read request TLP transmitted to the PCIe_I / F 121 is transmitted to any one of the target PCIe card 140 to the PCIe card 143 via the PCIe switch 120 (a-5).

  Upon receiving the read request TLP, the PCIe card 140 to the PCIe card 143 perform corresponding processing, create a response TLP, attach the read data, and transmit the response TLP to the PCIe controller 101 (a-6). At this time, the transaction ID of the read request TLP is carried, and a value identifying which of the PCIe card 140 to the PCIe card 143 is stored in the response ID.

  When the PCIe controller 101 receives the response TLP from the PCIe card 140 to the PCIe card 143 via the PCIe switch 120, the PCIe controller 101 compares the stored transaction TLP with the transaction ID of the response TLP. If the above comparison results match, it is determined that the response is a response to the request. The PCIe controller 101 transmits the accompanying response data to the processor 100 (a-9), and releases the tag entry number used in the request (a-8). With this release process, the tag entry number in the tag entry storage unit 20 can be assigned to another process. In addition, the PCIe controller 101 erases the information in the storage area used for storing the request TLP. Upon receiving the response information from the PCIe controller 101, the processor 100 completes the read command and returns the read data to the software 200 (a-10).

  Next, the operation when the PCIe card 140 to the PCIe card 143 cannot return the response TLP to the read request TLP for some reason or the response becomes slow will be described with reference to FIG.

  The operation is the same as that shown in FIG. 8 until the software 200 executes a read command to read out the registers of the PCIe card 140 to the PCIe card 143 and the read request TLP is transmitted to the PCIe card 140 to the PCIe card 143 ( b-1 to b-5).

  Here, if the PCIe card 140 to the PCIe card 143 do not transmit a response TLP within a certain time, the PCIe controller 101 detects a timeout (b-10). Based on the request information from the processor 100 stored in the PCIe controller 101, error data is transmitted to the processor 100 (b-8), and the reserved tag entry number and the storage area associated with the tag entry number; The timer area is released (b-11). With this release process, the tag entry number in the tag entry storage unit 20 can be assigned to another process. At the same time, the information in the storage area associated with the tag entry number used for storing the request TLP or the like is deleted. When receiving error data from the PCIe controller 101, the processor 100 notifies the software 200 of the error data (b-9).

  Thereafter, when the PCIe card 140 to the PCIe card 143 return the response TLP with a delay (b-6, b-7), the PCIe controller 101 receives the response TLP. The PCIe controller 101 searches whether the tag entry number given to the response TLP exists in each storage area of the tag entry storage unit 20. However, since there is no tag entry number having a transaction ID corresponding to the tag entry number assigned to the response TLP, it is determined as an invalid TLP, and the response TLP received by the control unit 1 is discarded as an unexpected response. (B-12) is performed.

  The above is the operation when the response is output normally and data is exchanged regularly.

  Next, the operation when a read command is executed from the processor 100 will be described using the flowchart of FIG.

  When the processor 1 is instructed to read the memory from the processor 100, the controller 1 executes a read process (step 300).

  In the read process (step 300), the control unit 1 reads each of the storage areas 20-n from the tag entry storage unit 20 (step 301). The control unit 1 refers to the valid flag 20-n-1 of each tag entry 20-n to determine whether there is an unused storage area 20-n (step 302). The control unit 1 sets the valid flag 20-n-1 to secure the storage area 20-n (step 303).

  Then, the controller 1 creates a read request TLP according to the memory read request information from the processor 100 (step 304). At this time, the control unit 1 stores the number n of the storage area 20-n in the tag number of the transaction ID.

  After that, the control unit 1 stores the memory read request information from the processor 100 in the request information unit 20-n-2 of the storage area 20-n. The control unit 1 stores the TLP header of the created read request TLP in the TLP header unit 20-n-3 of the storage area 20-n (step 305).

  Further, the control unit 1 sets the valid flag 30-n-1 and the timer count value 30-n-2 of the timer area 30-n corresponding to the storage area 20-n. The control unit 1 starts a timer (step 306). The control unit 1 transmits the TLP command of the last created read request to the PCIe switch 120 and ends the process (steps 307 and 308).

  Thus, when the PCIe card 140 to the PCIe card 143 receive the read request TLP, the response TLP is transmitted to the PCIe controller 101 with the read data attached.

  Next, the response processing operation will be described with reference to the flowchart of FIG. When the control unit 1 of the PCIe controller 101 receives the response TLP, the response processing is executed.

  In the response process (step 400), the control unit 1 reads the response TLP received from the response buffer 5 (step 401), and the control unit 1 reads each tag entry 20-n (step 401). The control unit 1 determines whether there is a valid storage area 20-n having the same transaction ID as the response TLP (step 403).

  Here, if there is no storage area 20-n having the same transaction ID, the control unit 1 processes the response TLP as an unexpected response (step 408) and ends the processing (step 409).

  When there is a storage area 20-n (tag entry storage area) having the same transaction ID as that of the response TLP (step 403: YES), the processing is a response to the response to the request stored in the storage area 20-n. In this case, the control unit 1 clears the valid flag 30-n-1 of the timer area 30-n corresponding to the storage area 20-n, stops the timer (step 404), and requests information in the storage area 20-n. The data of the response TLP is transmitted to the processor 100 according to the unit 20-n-2 (step 405).

  Then, the control unit 1 clears the valid flag 20-n-1 of the storage area 20-n, releases the storage area 20-n (step 406), and ends the process (step 407).

  Next, an operation when a response time-out occurs due to a delay in the response from the PCIe card will be described using the flowchart of FIG.

  The response time-out is generated when the control unit 1 subtracts the value of the timer count value 30-n-2 in the valid timer area 30-n and the value becomes zero.

  In the timeout process (500), the control unit 1 clears the valid flag 30-n-1 of the corresponding timer area 30-n, stops and releases the timer (step 501), and corresponds to the timer area 30-n. The error data is transmitted to the processor 100 in accordance with the request information part 20-n-2 of the storage area 20-n (step 502). Thereafter, the control unit 1 clears the valid flag 20-n-1 of the storage area 20-n to release the tag entry number of the 20-n (Step 503), and ends the processing (Step 504).

  Next, a situation where a failure occurs in the information processing apparatus 1000 when the operation of the failure processing apparatus of the present invention is not performed will be described with reference to FIG. FIG. 10 shows an operation when an arbitrary memory read times out in response to a plurality of memory reads being performed on the PCIe card 140 to the PCIe card 143.

  The software 200 executes a read command to the processor 100 in order to perform memory read of the PCIe card 140 to the PCIe card 143 (c-1). The processor 100 transmits a command to the PCIe controller (c-2). The PCIe controller 101 transmits a TLP command of a read request to the PCIe switch 120 (c-3). The PCIe switch 120 transmits a TLP command to the PCIe card 140 to the PCIe card 143, and the PCIe card 140 to the PCIe card 143 receives it (c-4). However, if the response of the PCIe card 140 to the PCIe card 143 is delayed for some reason, the PCIe controller 101 detects a response timeout (c-17), releases the tag entry number (c-18), and sends the response to the processor 100. Error data (c-5) is returned. The software 200 receives the error data and knows that the reading has failed (c-6).

  However, after that, the software 200 may read the memory of the PCIe card 140 to the PCIe card 143. In this case, the PCIe controller 101 obtains the same tag entry number as the request that has timed out the response. After the read request TLP is issued to the PCIe card 140 to the PCIe card 143 (c-7 to c-10), the response TLP to the previous read request TLP is delayed and arrives at the PCIe controller 101 (c-11) , C-12) occurs. As a result, the transaction ID in the subsequent read request TLP matches the transaction ID of the response TLP that has timed out. Accordingly, in this case, the PCIe controller 101 erroneously processes the response TLP for the preceding read request TLP as the response TLP for the subsequent read request TLP. Then, the control unit 1 outputs wrong response data to the processor 100 (c-13), and passes wrong read data to the software 200 (c-14). This causes the control unit 1 to pass wrong data to the software 200, causing the software to malfunction.

  Next, with reference to FIGS. 15 and 11, an operation for operating the failure processing apparatus according to the present invention to prevent the software 200 from malfunctioning will be described. In this example, a case where a subsequent memory read is performed after the memory read of the PCIe card 140 to the PCIe card 143 has timed out in response will be described.

  First, in the control unit 1 of the PCIe controller 101 in FIG. 21, a timeout flag 20-n-4 (see FIG. 11) indicating that a response timeout has occurred is provided in the storage area 20-n.

  First, the software 200 performs a memory read of the PCIe card 140 to the PCIe card 143, and a response timeout occurs when the response of the PCIe card 140 to the PCIe card 143 is delayed. This situation is a state (d-1 to d-4, d-20) in FIG. This state is the same as the description of the states (c-1 to c-4, c-17) in FIG.

  Here, when the PCIe controller 101 detects a response timeout, the control unit 1 executes a timeout process (step 700).

  Referring to the flowchart of the timeout process in FIG. 13, in the timeout process (700), the control unit 1 stops the timer in the timer area 30-n. The controller 1 clears the valid flag 30-n-1 and releases the timer area 30-n (Step 701). The control unit 1 transmits error data to the processor 100 according to the request information in the request information unit 20-n-2 in the storage area 20-n corresponding to the timer area 30-n (step 702), and the state (d-5) ). Then, the control unit 1 sets the timeout flag 20-n-4 in the storage area 20-n and finishes the process (steps 703 and 704), and the state (d-20). As a result, the tag entry number used in the request TLP whose response timed out is kept, and the tag entry number is not released in response time out.

  Next, when the software 200 performs a subsequent memory read and the PCIe controller 101 receives the instruction, the control unit 1 executes the read process (300) of FIG. This is the operation in the state (d-7, d-8) in FIG.

  At this time, since the storage area 20-n used in the request TLP whose response has timed out remains secured, the control unit 1 selects the storage area 20-n other than the reserved tag entry number. This is a state (d-21). As a result, the transaction ID in the read request TLP of the subsequent memory read becomes different from that of the read request TLP in which the preceding response time-out has occurred. This is a state (d-9, d-10).

  Here, when the PCIe controller receives a response TLP to the preceding read request TLP, a response process (600) shown in the flowchart of FIG. 12 is executed. The control unit 1 takes out the response TLP received from the response buffer 5 (step 601). State (d-11, d-12). The control unit 1 reads each tag entry 20-n (602). The control unit 1 determines whether there is a tag entry 20-n having the same transaction ID as the response TLP (step 603).

  At this time, since the corresponding storage area 20-n remains secured, the transaction IDs match (step 603: Yes). The control unit 1 confirms that the timeout flag 20-n-4 of the storage area 20-n is set (step 604). The control unit 1 recognizes that the timeout flag 20-n-4 is set, and determines that the response TLP is an unexpected response (step 605: Yes). Then, processing for an unexpected response is performed (step 612). Thereafter, the process ends (step 613).

  As a result, the response TLP to the read request TLP whose response timed out is discarded as an unexpected response, and incorrect data is prevented from being transmitted to the program. State (d-22).

  Then, a response TLP to the subsequent read request TLP is transmitted from the PCIe card 140 to the PCIe card 143. This is state (d-13). When the PCIe controller 101 receives the information, the control unit 1 executes the response process (600) of FIG. 12 in the state (d-14). The control unit 1 extracts the response TLP from the response buffer 5 (step 601), and determines whether there is a tag entry 20-n having the same transaction ID from the tag entry storage unit 20 (step 603).

  At this time, since the corresponding storage area 20-n is secured, the control unit 1 checks the contents of the timeout flag 20-n-4 of the storage area 20-n (step 604).

The control unit 1 recognizes that the timeout flag 20-n-4 is not set, and determines that the response has not timed out (step 605: No). Then, the control unit 1 stops the timer in the timer area 30-n corresponding to the storage area 20-n. The control unit 1 clears the valid flag 30-n-1 to release the timer area 30-n (step 606), and in response to the request information of the request information section 20-n-3 in the storage area 20-n, the response TLP The response data is transmitted to the processor 100 (step 607). State (d-15)
Thereafter, the control unit 1 clears the valid flag 20-n-1 in the storage area 20-n, releases the tag entry 20-n, and ends the process (steps 608 and 609). State (d-23).

  The processor 100 that has received the response data from the PCIe controller 101 completes the read command and passes the received read data to the program. State (d-16). Thereby, the program 200 can receive data corresponding to the memory read of the PCIe card 140 to the PCIe card 143.

  Thereafter, the program 200 performs failure processing by resetting the PCIe card 140 to the PCIe card 143, and the transaction ID corresponding to the read request TLP whose response timed out from the PCIe card 140 to the PCIe card 143 is not used. Guarantee. Thereafter, the program 200 issues a write command in order to write to a specific register of the PCIe controller 101. Status (d-17) The processor 100 transmits to the PCIe controller 101 a release command for instructing the release of the storage area 20-n that has been held by the response timeout. State (d-18).

  The PCIe controller 101 transmits an instruction from the above-described software 200 to the control unit 1, and the control unit 1 performs a tag entry release process (800) shown in the flow of FIG.

  In the tag entry release process (800), the valid flag 20-n-1 and timeout flag 10-n-4 of all tag entry numbers for which the timeout flag 20-n-4 of the storage area 20 is set are cleared and released. (Step 801).

  By this operation, the tag entry that has been secured when the response timeout is turned ON can be used for the tag entry used for the subsequent packet generation work. State (d-24).

  As described above, according to the third embodiment of the present invention, when the response from the PCIe device times out and the transaction processing is not completed, the program of the information processing apparatus or the like affects the influence of erroneous data. It is possible to prevent the operation from becoming unstable. This is because the control unit 1 invalidates the tag entry number of the packet that has been typed out in the packet processing of PCIe so that it is not used, and validates it when the failure is resolved. This is because it is possible to prevent the command from being assigned by mistake.

DESCRIPTION OF SYMBOLS 1 Control part 2 High-order apparatus 3 Low-order apparatus 4 Request buffer 5 Response buffer 6 Control part 20 Identifier storage part 21 Identifier storage part 22 Identifier storage part 30 Elapsed time storage part 31 Elapsed time storage part 32 Elapsed time storage part 100 Processor 101 Failure process Device 102 Fault processing device 120 PCIe switch 121 PCIe_I / F
122 PCIe_I / F
123 PCIe_I / F
124 PCIe_I / F
125 PCIe_I / F
126 PCIe_I / F
130 device 131 PCIe_I / F
140 PCIe card 141 PCIe card 142 PCIe card 143 PCIe card 150 failure processing device 180 failure processing device 200 program 300 central processing device 1000 information processing device 2000 external storage device 2001 interface 2002 interface 3000 external storage device 3001 interface 3002 interface

Claims (7)

Identifier storage means for storing information indicating whether or not the identifier is in use in a first storage area associated with the identifier assigned to each command information in the command information group received from the host device; ,
In a second storage area associated with each identifier stored in the first storage area, an elapsed time starting from the time when the command information to which the identifier is assigned is transmitted to a lower-level device is stored. An elapsed time storage means;
If the identifier is not in use, permit the identifier to be assigned to the command information;
If the identifier is in use, it is prohibited to assign the identifier to the command information;
When the identifier is in use and the elapsed time associated with the identifier has not reached a predetermined threshold, a response to the transmission of the command information to which the identifier is assigned to the lower-level device is given. When received, the response is transmitted to the host device, and the first storage area associated with the identifier is reset,
When the identifier is in use and the elapsed time associated with the identifier has reached the threshold, a response to the transmission of the command information to which the identifier is assigned to the lower-level device is received A failure processing apparatus comprising: a control unit that discards the response and resets the first storage area associated with the identifier.   A response information buffer storage device that temporarily stores response information from a lower-level device in response to a command output by the higher-level device; and a request information buffer storage device that temporarily stores request information for the higher-level device output by the lower-level device, The failure processing apparatus according to claim 1, wherein a control unit sequentially reads the response information and the request information from the response information buffer storage device and the request information buffer storage device. The failure processing apparatus according to claim 1,
Information processing means for transmitting information using the PCIe standard, and a PCIe card for converting and connecting a PCIe standard signal to the interface of each peripheral device,
PCIe switching means for switching the connection destination with the PCIe card from the information processing means;
A fault processing system including peripheral devices connected to each PCIe card. Identifier storage means for storing information indicating whether or not the identifier is in use in a first storage area associated with the identifier assigned to each command information in the command information group received from the host device; ,
In a second storage area associated with each identifier stored in the first storage area, an elapsed time starting from the time when the command information to which the identifier is assigned is transmitted to a lower-level device is stored. A failure processing method in a failure processing apparatus having elapsed time storage means,
If the identifier is not in use, permit the identifier to be assigned to the command information;
If the identifier is in use, it is prohibited to assign the identifier to the command information;
If the identifier is in use and the elapsed time associated with the identifier has not reached a predetermined threshold, a response to the transmission of the command information to which the identifier is assigned to the lower-level device is given. When received, the response is transmitted to the host device, and the first storage area associated with the identifier is reset,
If the identifier is in use and the elapsed time associated with the identifier has reached the threshold, a response to the transmission of the command information assigned the identifier to the lower-level device has been received. Sometimes, a failure processing method for discarding the response and resetting the first storage area associated with the identifier.   Claims: Temporary storage of response information from a lower-level device with respect to a command output by a higher-level device; Temporary storage of request information for the higher-level device output by the lower-level device; 4. Fault handling method. Identifier storage means for storing information indicating whether or not the identifier is in use in a first storage area associated with the identifier assigned to each command information in the command information group received from the host device; ,
In a second storage area associated with each identifier stored in the first storage area, an elapsed time starting from the time when the command information to which the identifier is assigned is transmitted to a lower-level device is stored. A computer provided in a failure processing apparatus having elapsed time storage means,
If the identifier is not in use, permit the identifier to be assigned to the command information;
If the identifier is in use, it is prohibited to assign the identifier to the command information;
When the identifier is in use and the elapsed time associated with the identifier has not reached a predetermined threshold, a response to the transmission of the command information to which the identifier is assigned to the lower-level device is given. When received, the response is transmitted to the host device, and the first storage area associated with the identifier is reset,
When the identifier is in use and the elapsed time associated with the identifier has reached the threshold, a response to the transmission of the command information to which the identifier is assigned to the lower-level device is received when the discard of the response, and the first fault processing program to perform processing for resetting the storage region associated with the identifier. Processing for temporarily storing response information from a lower-level device for a command output by a higher-level device, temporarily storing request information for the higher-level device output by the lower-level device, and sequentially reading the stored response information and the request information The fault processing program according to claim 6, further executed by the computer.

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