JP6554942B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device including a boost converter and an insulated half bridge converter.

  As a DC-DC converter, a boost converter that boosts the DC input by turning on and off the switching element and a DC boosted by the boost converter by alternately turning on and off the two switching elements are converted into AC. A configuration including a half-bridge converter and a conversion unit that rectifies and smoothes the output of the half-bridge converter and outputs a direct current is proposed (see, for example, Patent Document 1). However, since this DC-DC converter uses two converters, the control circuit becomes complicated. Further, since the output voltage is controlled by the half bridge converter, there is a disadvantage that the utilization factor of the transformer is deteriorated and the conversion efficiency is lowered.

  Therefore, the DC-DC converter is composed of a boost converter and an isolated half-bridge converter, the isolated half-bridge converter is driven at a fixed on-duty ratio and a fixed switching frequency, and the voltage applied to the isolated half-bridge converter by the boost converter. A technique for adjusting the output voltage by controlling the above has been proposed (see, for example, Patent Document 2).

JP 2005-287195 A JP 2013-258860 A

  However, in the prior art described in Patent Document 2, the charge (energy) stored in the smoothing capacitor of the boost converter is output to the secondary side by the insulated half bridge converter. Therefore, the voltage of the smoothing capacitor of the boost converter varies depending on the load. In particular, in an insulated half-bridge converter, when operating at a duty of 50% in order to optimize the utilization factor of the transformer, the voltage of the smoothing capacitor is set high, and the smoothing capacitor is enlarged and switched. It was necessary to increase the breakdown voltage of the element.

  In view of the above problems, the object of the present invention is to reduce the smoothing capacitor of the boost converter and reduce the size of the switching element even when the isolated half-bridge converter provided in the subsequent stage of the boost converter is operated at 50% duty. An object of the present invention is to provide a switching power supply device capable of realizing a low breakdown voltage.

The switching power supply according to the present invention is configured as follows to achieve the above object.
The switching power supply device of the present invention includes a first arm configured by connecting a first switching element and a second switching element in series, one end connected to a DC input terminal, and the other end connected to the first arm. Reactor connected to the middle point, smoothing capacitor connected in parallel to the first arm, connected in parallel to the first arm, and configured by connecting a third switching element and a fourth switching element in series The second arm is connected between the midpoint of the first arm and the midpoint of the second arm, and a resonance capacitor, a resonance reactor, and a primary winding of the transformer are connected in series. A series circuit connected to the secondary winding of the transformer, a rectifying / smoothing circuit for rectifying and smoothing the voltage generated in the secondary winding to extract a DC output, the first switching element and the second switch. A first control circuit for alternately turning on and off the switching element, a second control circuit for alternately turning on and off the third switching element and the fourth switching element, and comparing the DC output with a predetermined reference voltage An error amplifier for generating an error signal obtained in this manner, a first triangular wave generator for generating a first sawtooth wave that fluctuates from a second voltage to a third voltage that is greater than the second voltage, and more than the second voltage. A second triangular wave generator that generates a second sawtooth wave having a frequency several times that of the first sawtooth wave, which varies from a small first voltage to the second voltage, and whose falling is synchronized, At the time of load, the first control circuit compares the error signal and the first sawtooth wave to alternately turn on and off the first switching element and the second switching element with a variable duty. The second control circuit alternately turns on and off the third switching element and the fourth switching element at a 50% duty, and the first control circuit sets the first switching element to zero at a light load. While controlling to a duty, the second control circuit alternately turns on and off the third switching element and the fourth switching element at a variable duty by comparing the error signal and the second sawtooth wave. It is characterized by.
Furthermore, in the switching power supply according to the present invention, the turn-on of the first switching element and the turn-on of the third switching element are synchronized at the time of steady load, and the turn-off of the second switching element and the fourth switching element are synchronized. A synchronization circuit that synchronizes the turn-off may be provided.
Furthermore, the switching power supply device according to the present invention may include a signal reduction circuit that reduces the error signal in accordance with a current output from the DC output during overload.
Furthermore, the switching power supply according to the present invention may include an adjustment circuit that adjusts the error signal according to a soft start signal at the time of startup.

  According to the present invention, even if the excitation energy of the resonance reactor is large and the energy increases the voltage of the smoothing capacitor, not only the charge (energy) is accumulated in the smoothing capacitor but also output through the transformer at the same time. Even if the voltage of the smoothing capacitor is suppressed, and the isolated half-bridge converter provided in the subsequent stage of the boost converter is operated at 50% duty, it is not necessary to increase the breakdown voltage of the switching element, and the smoothing capacitor can be reduced in size. There is an effect.

1 is a circuit diagram showing a configuration of a first embodiment of a switching power supply device according to the present invention. FIG. 2 is a circuit diagram showing a detailed configuration of a control circuit shown in FIG. 1. It is a wave form diagram which shows the signal waveform and operation | movement waveform of each part shown in FIG. It is a wave form diagram which shows the signal waveform and operation | movement waveform of each part shown in FIG. It is a circuit diagram which shows the detailed structure of the control circuit in 2nd Embodiment of the switching power supply device which concerns on this invention. FIG. 6 is a waveform diagram showing signal waveforms and operation waveforms of each unit shown in FIG. 5. It is a figure which shows the equivalent circuit at the time of light load in 2nd Embodiment of the switching power supply device which concerns on this invention. FIG. 6 is a waveform diagram showing signal waveforms and operation waveforms of each part shown in FIG. 1 when the control circuit shown in FIG. 5 is used. FIG. 6 is a waveform diagram showing signal waveforms and operation waveforms of each part shown in FIG. 1 when the control circuit shown in FIG. 5 is used. FIG. 6 is a waveform diagram showing signal waveforms and operation waveforms of each part shown in FIG. 1 when the control circuit shown in FIG. 5 is used. 3 is a graph showing duty D and input / output gain Vo / Vin characteristics of the first switch element shown in FIG. 1. 6 is a graph showing duty D ′ and input / output gain Vo / Vin characteristics of the fourth switch element shown in FIG. 1. It is a circuit diagram which shows the detailed structure of the control circuit in 3rd Embodiment of the switching power supply device which concerns on this invention.

  Next, embodiments of the present invention will be specifically described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and a part of the description is omitted.

(First embodiment)
Referring to FIG. 1, the switching power supply device 1 of the first embodiment includes a boost converter including a first arm in which a switching element Q1 and a switching element Q2 are connected in series, a switching element Q3, and a switching element Q4. And an insulating half bridge converter having a second arm connected in series, and a control circuit 10 for controlling the boost converter and the insulating half bridge converter.

  The boost converter is a synchronous rectification type booster circuit, and includes a reactor Lr1, a switching element Q1 that functions as a main control switch, a switching element Q2 that functions as a sub-control switch (synchronous rectification switch), a capacitor C1, and a switching element. The first control circuit 11 is configured to alternately turn on and off Q1 and the switching element Q2.

  A series circuit configured by connecting a reactor Lr1 and a switching element Q1 in series is connected to both ends of the DC power supply Vin. And the capacitor | condenser C1 is connected to the both ends of the 1st arm which connected the switching element Q1 and the switching element Q2 in series.

  The insulated half-bridge converter includes a switching element Q3 that functions as a main control switch, a switching element Q4 that functions as a sub-control switch, capacitors C2 and C3, a transformer T, diodes D1 and D2, reactors Lr2 and Lr3, The second control circuit 12 is configured to alternately turn on / off the switching element Q3 and the switching element Q4.

  A second arm in which the switching element Q3 and the switching element Q4 are connected in series is connected in parallel with the capacitor C1 at both ends of the first arm in which the switching element Q1 and the switching element Q2 are connected in series. The switching element Q3 is connected to the switching element Q2 side, and the switching element Q4 is connected to the switching element Q1 side.

  Switching elements Q1-Q4 are made of MOSFETs. A parallel circuit of diodes Da to Dd and capacitors Ca to Cd is connected between the drains and sources of the switching elements Q1 to Q4. The diodes Da to Dd are freewheeling diodes and may be parasitic diodes of the switching elements Q1 to Q4. The capacitors Ca to Cd are resonance capacitors and may be parasitic capacitors of the switching elements Q1 to Q4.

  Between the connection point of the switching element Q1 and the switching element Q2 (midpoint of the first arm) and the connection point of the switching element Q3 and the switching element Q4 (midpoint of the second arm), the capacitor C2 and the reactor A series circuit configured by connecting Lr2 and the primary winding P1 of the transformer T in series is connected. Note that the reactor Lr2 may be a leakage inductance between the primary winding P1 of the transformer T and the secondary windings S1 and S2. With this configuration, even when the switching elements Q1 and Q3 functioning as the main control switch are in the off period, a path through which a regenerative current always flows can be secured through the switching element switches Q2 and Q4 and the diodes Da and Dc. Can perform zero voltage switching (ZVS) operation.

  The secondary winding S1 and the secondary winding S2 of the transformer T are connected in series, one end of the secondary winding S1 is connected to the anode of the diode D1, and one end of the secondary winding S2 is connected to the anode of the diode D2. It is connected. The cathodes of the diodes D1 and D2 are connected to one end of the reactor Lr3, the other end of the reactor Lr3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the secondary winding S1 and the secondary winding S2. Connected to a point. An output voltage Vo is output from both ends of the capacitor C3. The diodes D1 and D2, the reactor Lr3, and the capacitor C3 constitute a rectifying and smoothing circuit.

  The control circuit 10 includes a first control circuit 11, a second control circuit 12, and a synchronization circuit 13. Referring to FIG. 2, the first control circuit 11 includes an error amplifier AMP1, a triangular wave generator 14, a comparator CMP1, a buffer circuit BUF1, an inverter INV1, and a dead time generation circuit 15a. The second control circuit 12 includes a buffer circuit BUF2, an inverter INV2, and a dead time generation circuit 15b.

  The synchronization circuit 13 is a circuit that synchronizes the operation timing of the first control circuit 11 and the operation timing of the second control circuit 12, and converts the rectangular wave signal Tsq shown in FIG. 2 Output to the control circuit 12.

  In the first control circuit 11, the error amplifier AMP1 amplifies the error voltage between the output voltage + Vo from the capacitor C3 and the reference voltage Vref1, and outputs this error amplification signal EAS to the non-inverting input terminal (+) of the comparator CMP1. To do.

  The triangular wave generator 14 generates the sawtooth wave signal Tria shown in FIG. 3B based on the rectangular wave signal Tsq from the synchronization circuit 13, and outputs the sawtooth wave signal Tria to the inverting input terminal (−) of the comparator CMP1. . The sawtooth wave signal Tria is a signal having the same period T synchronized with the rectangular wave signal Tsq.

  As shown in FIG. 3C, the error CMP signal EAS is input from the error amplifier AMP1 and the sawtooth wave signal Tria from the triangular wave generator 14 is input to the input CMP1in of the comparator CMP1. The comparator CMP1 outputs an H level from the comparator CMP1 to the buffer circuit BUF1 and the inverter INV1 when the error amplification signal EAS is equal to or higher than the sawtooth wave signal Tria. When the error amplification signal EAS is less than the sawtooth wave signal Tria, the comparator CMP1 Is output to the buffer circuit BUF1 and the inverter INV1.

  The buffer circuit BUF1 outputs the output of the comparator CMP1 to the dead time generation circuit 15a. The inverter INV1 inverts the output of the comparator CMP1 and outputs it to the dead time generation circuit 15a. The dead time generation circuit 15a is a circuit that delays rising of signals from the buffer circuit BUF1 and the inverter INV1 by a predetermined time (td). The dead time generation circuit 15a delays the rise of the signal from the buffer circuit BUF1 by a predetermined time (td), and outputs a gate signal Q1g applied to the gate of the switching element Q1 shown in FIG. The dead time generation circuit 15a delays the rising of the signal from the inverter INV1 by a predetermined time (td), and outputs a gate signal Q2g applied to the gate of the switching element Q2 shown in FIG. With this configuration, the ON period of the switching element Q1 is controlled according to the output voltage + Vo, and the energy transmitted to the secondary side is controlled in the boost converter.

  In the second control circuit 12, the buffer circuit BUF2 outputs the rectangular wave signal Tsq from the synchronization circuit 13 to the dead time generation circuit 15b. The inverter INV1 inverts the rectangular wave signal Tsq from the synchronization circuit 13 and outputs it to the dead time generation circuit 15b. The dead time generation circuit 15b is a circuit that delays the rising edges of the signals from the buffer circuit BUF2 and the inverter INV2 by a predetermined time (td), like the dead time generation circuit 15a. The dead time generation circuit 15b delays the rise of the signal from the buffer circuit BUF2 by a predetermined time (td), and outputs a gate signal Q3g applied to the gate of the switching element Q3 shown in FIG. The dead time generation circuit 15b delays the rise of the signal from the inverter INV2 by a predetermined time (td) and outputs a gate signal Q4g to be applied to the gate of the switching element Q4 shown in FIG. With this configuration, the switching element Q3 and the switching element Q4 are turned on and off by the rectangular wave signal Tsq, so the on period of the switching element Q3 and the on period of the switching element Q4 are equal, and the insulation half-bridge converter is 50% Driven by duty.

  With this configuration, the gate signal Q2g falls at the rising edge of the rectangular wave signal Tsq, and the sawtooth wave signal Tria suddenly falls below the error amplification signal EAS, and the gate signal Q4g falls. Thereby, the falling edge (turn-off) of the gate signal Q2g of the switching element Q2 and the falling edge (turn-off) of the gate signal Q4g of the switching element Q4 are synchronized. Further, the gate signal Q1g rises after a predetermined time (td) from the rising of the rectangular wave signal Tsq, and the sawtooth wave signal Tria suddenly drops and becomes equal to or less than the error amplification signal EAS. After a predetermined time (td), the gate signal Q3g Fall down. Thereby, the rising edge (turn-on) of the gate signal Q1g of the switching element Q1 and the rising edge (turn-on) of the gate signal Q3g of the switching element Q3 are synchronized.

Next, the operation of the switching power supply device 1 according to the first embodiment will be described in detail with reference to FIG. 4. FIG. 4 shows signal waveforms and operation waveforms of each part shown in FIG. ) Is a current Id1 flowing through the switching element Q1, (b) is a drain-source voltage Vds1 of the switching element Q1, (c) is a current Id2 flowing through the switching element Q2, and (d) is a drain-source voltage Vds2 of the switching element Q2. (E) is a current Id3 flowing through the switching element Q3, (f) is a drain-source voltage Vds3 of the switching element Q3, (g) is a current Id4 flowing through the switching element Q4, and (h) is a drain-source voltage of the switching element Q4. Vds4 and (i) indicate currents Ia1 and Ia2 flowing through the diodes D1 and D2, respectively. In FIG. 4, the diodes Da to Dd are parasitic diodes of the switching elements Q1 to Q4, and the currents flowing through the diodes Da to Dd are also shown as currents Id1 to Id4 flowing through the switching elements Q1 to Q4.

In the period t1 shown in FIG. 4, the switching element Q1 and the switching element Q3 are on periods, and the switching element Q2 and the switching element Q4 are off periods.
In the period t1, due to the ON period of the switching element Q1, a current flows from the DC power source Vin through the reactor Lr1 to the switching element Q1, and the reactor Lr1 is excited. Due to the ON period of the switching element Q3, the current 1d3 flows from the capacitor C1 through the path of the capacitor C1, the switching element Q3, the primary winding P1 of the transformer T, the reactor Lr2, the capacitor C2, the switching element Q1, and the capacitor C1, and the reactor Lr2 Excited in this direction. Therefore, the current Id1 flowing through the switching element Q1 is a total current of the exciting current of the reactor Lr1 and the current Id3 of the switching element Q3.

  Next, during the dead time (td) until the switching element Q1 is turned off and the switching element Q2 is turned on while the switching element Q3 is on, the discharge energy of the reactor Lr1 and the reactor Lr2 is changed to the capacitor of the switching element Q2. Begins extracting the charge of Cb. As a result, a current flows through the path of DC power supply Vin → reactor Lr1 → capacitor Cb of switching element Q2 → capacitor C1 → DC power supply Vin. The current 1d3 also flows through the path of the reactor Lr2, the capacitor C2, the capacitor Cb of the switching element Q2, the switching element Q3, the primary winding P1 of the transformer T, and the reactor Lr2. Then, when the electric charge of the capacitor Cb of the switching element Q2 is extracted and becomes a negative potential and reaches the forward voltage of the diode Db of the switching element Q2, the DC power source Vin → the reactor Lr1 → the diode Db of the switching element Q2 → the capacitor C1. → Current flows through the path of the DC power supply Vin. The current 1d3 also flows through the path of the reactor Lr2, the capacitor C2, the diode Db of the switching element Q2, the switching element Q3, the primary winding P1 of the transformer T, and the reactor Lr2.

  Thereby, when the switching element Q2 is turned on, the drain-source voltage Vds2 of the switching element Q2 falls, and zero voltage switching (ZVS) of the switching element Q2 can be realized.

In a period t2 shown in FIG. 4, the switching element Q2 and the switching element Q3 are on periods, and the switching element Q1 and the switching element Q4 are off periods.
In the period t2, the energy accumulated in the reactor Lr1 in the period t1 is released through the path of the reactor Lr1, the switching element Q2, the capacitor C1, the DC power source Vin, and the reactor Lr1, and charges the capacitor C1. At the same time, current also flows through the path of the switching element Q3 in parallel with the capacitor C1, the primary winding P1 of the transformer T, the reactor Lr2, the capacitor C2, and the switching element Q2, and transmits energy to the secondary side.

  Next, during the dead time (td) until the switching element Q3 is turned off and the switching element Q4 is turned on while the switching element Q2 is on, the reactor Lr2 → the capacitor C2 → the switching element due to the discharge energy of the reactor Lr2. A current flows through a path of Q2 → capacitor C1 → capacitor Cd of the switching element Q4 → primary winding P1 of the transformer T → reactor Lr2, and starts to extract the charge of the capacitor Cd of the switching element Q4. Then, when the charge of the capacitor Cd of the switching element Q4 is extracted and becomes a negative potential and reaches the forward voltage of the diode Dd of the switching element Q4, the reactor Lr2, the capacitor C2, the switching element Q2, the capacitor C1, and the switching element Q4. Current 1d4 flows through the path of the diode Db → the primary winding P1 of the transformer T → the reactor Lr2. Note that charging of the capacitor C1 by the energy accumulated in the reactor Lr1 is continued.

  Thereby, when the switching element Q4 is turned on, the drain-source voltage Vds4 of the switching element Q4 falls, and zero voltage switching (ZVS) of the switching element Q4 can be realized.

In the period t3 and the period t4 shown in FIG. 4, the switching element Q2 and the switching element Q4 are on periods, and the switching element Q1 and the switching element Q3 are off periods.
In the period t3, the switching element Q3 is in the off period and the switching element Q4 is in the on period, so that the current flowing through the primary winding P1 of the transformer T is the primary winding P1 of the transformer T → reactor Lr2 → capacitor C2 → switching element Q2. → Capacitor C1 → Switching element Q4 → Change to the path of the primary winding P1 of the transformer T. This current decreases due to the resonance operation of the primary winding P1, the reactor Lr2, and the capacitor C2 of the transformer T, and then inverts until the period t4.

  In the period t4, a current flows through the path of the primary winding P1 of the transformer T → the switching element Q4 → the capacitor C1 → the switching element Q2 → the capacitor C2 → the reactor Lr2 → the primary winding P1 of the transformer T, and the secondary side of the transformer T Energy is transmitted. At this time, since the capacitor C1 is in the discharge mode, the capacitor C1 does not become a high voltage.

  Next, in the dead time (td) until the switching element Q2 and the switching element Q4 are turned off and the switching element Q1 and the switching element Q3 are turned on, the primary winding of the reactor Lr2 → the transformer T due to the discharge energy of the reactor Lr2. A current flows through the path of line P1 → capacitor Cc of switching element Q3 → capacitor C1 → capacitor Ca of switching element Q1 → capacitor C2 → reactor Lr2, and the charge of capacitor Ca of switching element Q1 and the charge of capacitor Cc of switching element Q3 Start pulling out. Then, when the charge of the capacitor Ca of the switching element Q1 and the charge of the capacitor Cc of the switching element Q3 are pulled out and become negative potential, the forward voltage of the diode Da of the switching element Q1 and the diode Dc of the switching element Q3 is reached. Current flows in the path of reactor Lr2 → primary winding P1 of transformer T → diode Dc of switching element Q3 → capacitor C1 → diode Da of switching element Q1 → capacitor C2 → reactor Lr2.

  Thereby, when the switching element Q1 and the switching element Q3 are turned on, the drain-source voltage Vds1 of the switching element Q1 and the drain-source voltage Vds3 of the switching element Q3 fall, and zero voltage switching of the switching element Q1 and the switching element Q3 ( ZVS) can be realized.

  The period t1 in which the switching element Q1 is on and the period t2 + period t3 + period t4 in which the switching element Q2 is on are the on-duty and off-duty of the boost converter and are driven with a variable duty. That is, the energy transmitted to the secondary side is controlled by controlling the on-duty period t1 based on the output voltage + Vo, and the output voltage + Vo is controlled. In addition, the period t1 + period t2 in which the switching element Q3 is on and the period t3 + period t4 in which the switching element Q4 is on are the on-duty and off-duty of the insulated half-bridge converter, that is, 50% duty, Driven at the same time. For this reason, the utilization factor of the transformer T is high, and highly efficient conversion becomes possible. Further, since the duty is 50%, the capacitor C2 is not DC-charged, and the voltage can be effectively supplied to the primary winding P1 of the transformer T.

  The heavier load increases the charge amount of the capacitor C2 and the voltage drop of the reactor Lr2 also increases. The voltage of the capacitor C1 tends to increase. However, in the case of dynamic such as heavy load-light load, the switching element Q1 The duty is reduced, the duty of the switching element Q2 that is a synchronous switch is increased, and the charge of the capacitor C1 is regenerated on the input side. That is, it becomes a step-down chopper that receives the voltage of the capacitor C1, and immediately reduces the charge of the switching element C1 to maintain the output voltage.

  Furthermore, at a small power output, the excitation energy of reactor Lr1 is also small, and the voltage of capacitor C1 does not increase. Even if the power output is large or the excitation energy of the reactor Lr1 is large enough to increase the voltage of the capacitor C1, not only the charge (energy) is accumulated in the capacitor C1, but also output through the transformer T at the same time. Therefore, the voltage of the capacitor C1 is suppressed. Accordingly, the capacitor C1 has a voltage with a small and substantially constant fluctuation depending on the input level and the load weight. Since the voltage fluctuation of the capacitor C1 is small, the diodes D1 and D2 as the secondary side switches are always applied with a substantially constant voltage, so that a switch with a low withstand voltage and a small conduction loss can be selected.

  In the first embodiment, the first control circuit 11 is configured to control the ON period of the switching element Q1 according to the output voltage + Vo. However, the current Id1 flowing through the switching element Q1 is detected. A current detection resistor may be provided so that the ON period of the switching element Q1 is controlled according to the current Id1.

As described above, in the first embodiment, the first arm configured by connecting the switching element Q1 and the switching element Q2 in series, and one end thereof is connected to the DC input terminal (DC power supply Vin). The other end of the reactor Lr1 is connected to the midpoint of the first arm, the capacitor C1 is connected in parallel to the first arm, and the switching element Q3 and switching element Q4 are connected in series to the first arm. A second arm configured to be connected to the center, and a middle point of the first arm and a middle point of the second arm, and a capacitor C2, a reactor Lr2, and a primary winding P1 of the transformer T connected in series. A series circuit constructed by connecting, and a rectifying and smoothing circuit (diode) connected to the secondary windings S1 and S2 of the transformer T and rectifying and smoothing the voltage generated in the secondary windings S1 and S2 to extract a DC output D1, D2, reactor Lr3, capacitor C3), switching element Q1 and switching element Q2 are alternately turned on and off at a variable duty, and the first control circuit 11 for controlling the DC output, the third switching element Q3 and the switching element The second control circuit 12 that alternately turns on and off Q4 at a 50% duty, synchronizes the turn-on of the switching element Q1 and the turn-on of the switching element Q3, and synchronizes the turn-off of the switching element Q2 and the turn-off of the switching element Q4. And a synchronizing circuit 13.
With this configuration, even if the excitation power of the reactor Lr1 is large and the energy of the capacitor C1 is increased, the capacitor C1 not only accumulates charges (energy) but also outputs via the transformer T at the same time. Therefore, the voltage of the capacitor C1 is suppressed. That is, the capacitor C1 has a function as a clamp capacitor in addition to a function as a smoothing capacitor. Accordingly, the capacitor C1 has a voltage with almost constant fluctuations depending on the level of input and the weight of the load, so that the capacitor C1 can be reduced in size and can be several tens of nF to several uF. The breakdown voltage of the elements Q1 to Q4 can be reduced. For this reason, it is optimal for a power source that uses a DC power source with a large fluctuation as an input and a large capacity power source.

  Furthermore, in the first embodiment, the resonant reactor Lr2 is configured by the leakage inductance of the transformer T.

Furthermore, in the first embodiment, the first control circuit 11 provides a dead time for lowering the voltage across the switching element Q1 or the switching element Q2 by the discharge energy of the reactor Lr2, so that the switching element Q1 and the switching element Q2 Are alternately turned on and off, and the second control circuit 12 alternately turns on and off the switching elements Q3 and Q4 by providing a dead time for dropping the voltage across the switching element Q3 or the switching element Q4 by the discharge energy of the reactor Lr2. Let
With this configuration, the switching elements Q1 to Q4 can be operated with zero voltage switching (ZVS).

(Second Embodiment)
The switching power supply according to the second embodiment controls the boost converter (switching elements Q1, Q2) and the insulated half-bridge converter (switching elements Q3, Q4) shown in FIG. 1 by a control circuit 10a shown in FIG.

  Referring to FIG. 5, the control circuit 10a includes a first control circuit 11a, a second control circuit 12a, a synchronization circuit 13a, and an error amplifier AMP1. The first control circuit 11a includes a comparator CMP1, an inverter INV1, AND circuits AND1 and AND2, and a dead time generation circuit 15a. The second control circuit 12a includes a comparator CMP1, an inverter INV2, an AND circuit AND3, and a dead time generation circuit 15b. The synchronous circuit 13a includes an oscillator 16a, a synchronous oscillator 16b, a D flip-flop FF1, a T flip-flop FF2, an AND circuit AND4, a NAND circuit NAND1, a first triangular wave generator 14a, and a second triangular wave. And the generator 14b. The configuration of the control circuit 10a shown in FIG. 5 is a circuit configuration for simplifying the description, and includes a case where the control circuit 10a is to be realized with a similar function.

FIG. 6A shows an output waveform of the oscillator 16a. The oscillator 16a outputs a pulse having a frequency f. The pulse output from the oscillator 16a is input to the CK terminal of the flip-flop FF1, the T terminal of the flip-flop FF1, and the second triangular wave generator 14b.
FIG. 6B shows a waveform FF1out of the output Q of the flip-flop FF1. Inverting output Q of the flip-flop FF1 ^- is input to its D terminal, the flip-flop FF1 by the rising edge of the oscillator 16a generates a square wave of half the frequency. The output Q of the flip-flop FF1 is input to one input terminal of the AND circuit AND4 and the NAND circuit NAND1.
FIG. 6C shows a waveform FF2out of the output Q of the flip-flop FF2. The flip-flop FF2 generates a ½ frequency rectangular wave at the falling edge of the oscillator 16a. The output Q of the flip-flop FF2 is input to the other input terminals of the AND circuit AND4 and the NAND circuit NAND1, and is also input to one input terminal of the AND circuit AND3 in the second control circuit 12a.
FIG. 6D shows the output AND4out of the AND circuit AND4. Since the output of the oscillator 16a has a certain pulse width, the period between the rising edge of the output Q of the flip-flop FF1 and the falling edge of the output Q of the flip-flop FF2, or the falling edge of the output Q of the FF1 and FF2 The period from the rising edge of the output Q has the same width as the pulse width of the oscillator 16a. As a result, the output AND4out of the AND circuit AND4 becomes an oscillator of f / 2 frequency while being synchronized with the oscillator 16a. The output AND4out of the AND circuit AND4 is input to the synchronous oscillator 16b.
FIG. 6E shows the output NAND1out of the NAND circuit NAND1. The output NAND1out of the NAND circuit NAND1 is an inverted signal of the output AND4out of the AND circuit AND4. The output NAND1out of the NAND circuit NAND1 is input to one input terminal of the AND circuit AND1 and the AND circuit AND2 in the first control circuit 11a.
FIG. 6F shows an input CMP1in of the comparator CMP1, which receives the first sawtooth wave Tria1 output from the first triangular wave generator 14a and the error amplification signal EAS from the error amplifier AMP1. The first sawtooth wave Tria1 is generated as a triangular wave (sawtooth wave) having an amplitude of Vc (Vb <Vc) from the voltage Vb by the synchronous oscillator 16b and the first triangular wave generator 14a using the output AND4out of the AND circuit AND4 as a trigger. . The first sawtooth wave Tria1 is input to the inverting input terminal (−) of the comparator CMP1 in the first control circuit 11a.
FIG. 6G shows the input CMP2in of the comparator CMP1, which receives the second sawtooth wave Tria2 output from the second triangular wave generator 14b and the error amplification signal EAS from the error amplifier AMP1. The second sawtooth wave Tria2 is generated as a triangular wave (sawtooth wave) having an amplitude from the voltage Va to Vb (Va <Vb) by the output of the oscillator 16a. The second sawtooth wave Tria2 is input to the inverting input terminal (−) of the comparator CMP2 in the second control circuit 12a. Note that the first sawtooth wave Tria1 and the second sawtooth wave Tria2 are synchronized, and the period of the first sawtooth wave Tria1 is set to be twice that of the second sawtooth wave Tria2.
FIG. 6H shows the output CMP1out of the comparator CMP1. The error amplifier AMP1 amplifies the error voltage between the output voltage + Vo from the capacitor C3 and the reference voltage Vref1, and this error amplified signal EAS is connected to the non-inverting input terminal (+) of the comparator CMP1 in the first control circuit 11a and the first voltage. 2 is output to the non-inverting input terminal (+) of the comparator CMP2 in the control circuit 12a. The comparator CMP1 compares the first sawtooth wave Tria1 with the error amplification signal EAS. When the error amplification signal EAS is larger than the first sawtooth wave Tria1, the output CMP1out outputs a Hi voltage. The output CMP1out of the comparator CMP1 is input to the other input terminal of the AND circuit AND1, and is also input to the other input terminal of the AND circuit AND2 via the inverter INV1.
FIG. 6I shows the output CMP2out of the comparator CMP2. The comparator CMP2 compares the second sawtooth wave Tria2 with the error amplification signal EAS. When the error amplification signal EAS is larger than the second sawtooth wave Tria2, the output CMP2out outputs a Hi voltage. The output CMP2out of the comparator CMP2 is input to the other input terminal of the AND circuit AND3 and also input to the dead time generation circuit 15b via the inverter INV1.
FIG. 6J shows a control signal Q1g for the switch element Q1. The control signal Q1g is obtained by delaying the logical product of the output NAND1out of the NAND circuit NAND1 and the output CMP1out of the comparator CMP1 by a dead time generator 15a by a predetermined time (td).
FIG. 6K shows a control signal Q2g for the switch element Q2. The control signal Q2g is obtained by delaying the logical product of the output NAND1out of the NAND circuit NAND1 and the output INV1out of the inverter INV1 by a dead time generator 15a by a predetermined time (td).
FIG. 6 (l) shows a control signal Q3g for the switch element Q3. The control signal Q3g is obtained by delaying the output of the inverter INV2 obtained by inverting the output CMP2out of the comparator CMP2 by a dead time generator 15b by a predetermined time (td).
FIG. 6 (m) shows a control signal Q4g for the switch element Q4. The control signal Q4g is obtained by delaying a logical product of the output Q (waveform FF2out) of the flip-flop FF2 and the output CMP1out of the comparator CMP2 by a dead time generator 15b by a predetermined time (td). As a result, the rise of the control signal Q1g and the rise of the control signal Q3g are synchronized, and the fall of the control signal Q2g and the fall of the control signal Q4g are synchronized.

  The error amplification signal EAS from the error amplifier AMP1 increases as the output voltage + Vo increases, and is set to be positioned between the voltages Vb and Vc at the time of steady load. That is, at heavy load, the error amplification signal EAS is controlled by comparison with the first sawtooth wave Tria1, the switch elements Q1 and Q2 are adjusted in on-time according to the error amplification signal EAS, and the switch elements Q3 and Q4 are duty cycles. Operates at 50%.

  Further, at the time of light load, the error amplification signal EAS is reduced from the error amplifier AMP1, and the error amplification signal EAS exists between the voltages Va and Vb. As a result, the control signal Q1g is turned off because the pulse width is narrowed, but the error amplification signal EAS is controlled by comparison with the second sawtooth wave Tria2, and the switch elements Q3 and Q4 are turned on according to the error amplification signal EAS. And the isolated half-bridge converter switches from 50% duty operation to variable duty control.

  It is necessary to suppress the output when the input voltage rises, the output droops, or at the time of startup. In this case, if the on-time of the switch elements Q1 and Q2 is adjusted according to the error amplification signal EAS and the switch elements Q3 and Q4 are operated at a duty of 50%, the output cannot be sufficiently suppressed. That is, the switch elements Q1 and Q2 operate as a boost chopper and do not drop below the input voltage. For this reason, the output cannot be sufficiently suppressed.

  In the second embodiment, when the output needs to be suppressed, the error amplification signal EAS is set to decrease to Vb or less. Then, as described above, the switch element Q1 is turned off, and the on-time of the switch elements Q3 and Q4 is adjusted according to the error amplification signal EAS, so that the output of the insulated half bridge converter is suppressed according to the error amplification signal EAS. can do. At this time, since the switching element Q1 is off and the switching element Q2 is almost on, the switching power supply according to the second embodiment has an equivalent circuit shown in FIG. 7, that is, a high-frequency input to the reactor Lr1 and the capacitor C1. It becomes an insulated half-bridge converter as a filter. As a result, even during the variable duty control of the insulated half bridge converter, the input current becomes a direct current as in the step-up operation by switching of the switch elements Q1 and Q2. In FIG. 7, the capacitors Ca to Cd are not shown in order to simplify the description.

In this way, in the second embodiment, the differential amplification signal EAS can freely pass between two sawtooth waves (first sawtooth wave Tria1 and second sawtooth wave Tria2), so that it is appropriate under any input / output conditions. The operation can be performed.

  8 to 10 show signal waveforms and operation waveforms of the respective parts shown in FIG. 1 when the control circuit 10a of the second embodiment is used. (A) is a control signal Q1g, (b). Is a control signal Q2g, (c) is a control signal Q3g, (d) is a control signal Q4g, (e) is a current Id1 flowing through the switching element Q1, (f) is a drain-source voltage Vds1 of the switching element Q1, (g) Is the current Id2 flowing through the switching element Q2, (h) is the drain-source voltage Vds2 of the switching element Q2, (i) is the current Id3 flowing through the switching element Q3, (j) is the drain-source voltage Vds3 of the switching element Q3, ( k) is a current Id4 flowing through the switching element Q4, (l) is a drain-source voltage Vds4 of the switching element Q4, and (m) is a diode D1. Each of the current Ia1 flows shows (n) is the respective currents Ia2 flowing through the diode D2, respectively. 8 to 10, the diodes Da to Dd are parasitic diodes of the switching elements Q1 to Q4, and currents flowing through the diodes Da to Dd are also shown as currents Id1 to Id4 flowing through the switching elements Q1 to Q4.

  8 and 9 show signal waveforms and operation waveforms of the respective parts in a state where the insulated half bridge converter operates at 50% duty and the switch elements Q1 and Q2 perform variable duty control, and FIG. 8 shows 0%. <Duty of switch element Q1 ≦ 50% FIG. 9 shows 50% ≦ duty of switch element Q1. Further, FIG. 10 shows signal waveforms and operation waveforms of respective parts in a state where the duty of the switching element Q1 = 0 and the insulated half bridge converter is subjected to variable duty control. In the following description of the input / output characteristics of FIGS. 8 to 10, the duty cycles of the switch elements Q1 and Q2 in FIGS. 8 and 9 are D and 1-D, respectively, and the switch elements Q3 and Q4 in FIG. The duty cycles are D ′ and 1−D ′, respectively. Further, the voltages of the capacitors C1 and C2 are Vc1 and Vc2, respectively, the turns ratio of the primary winding P1 of the transformer T1 and the secondary windings S1 and S2 is N: 1: 1, and the primary side excitation of the transformer T1 is excited. The inductance component is Lp, the input voltage is Vin, and the output voltage at the output terminals + Vo and −Vo is Vo. However, in the subsequent analysis, the dead time td of the control signals Q1g and Q2g, the dead time td of the control signals Q3g and Q4g, and the voltage drop when the switch elements Q1 to Q4 and the diodes D1 and D2 are turned on are very small. Ignore as. For the sake of convenience, the direction in which the current flowing through the primary winding P1 of the transformer T1 flows from the direction without dot display to the direction with dot display is positive with respect to the dot display indicating the start of winding.

First, the input / output characteristics of FIG. 8 will be described.
The insulated half bridge converter has a 50% duty, the boost converter has a variable duty control, and the duty of the switch element Q1 is 50% or less (D ≦ 0.5). First, the following formula is established in the boost converter.

  When the boost converter is operating stably, the amount of excitation of the core of the transformer T1 during one cycle is equal to the amount reset, so that the total exciting current flowing through the inductance component Lp becomes zero during one cycle. Become. That is, the sum of the excitation currents is given by the following equation.

  The following equation is derived from [Equation 1] and [Equation 2].

  The voltage applied to the primary winding P1 of the transformer T1 is multiplied by 1 / N and output to the secondary windings S1 and S2. Here, the output voltage Vo at the output terminals + Vo and -Vo is obtained by averaging the voltages of the secondary windings S1 and S2 of the transformer T1 with an output filter including a reactor Lr3 and a capacitor C3 over one period T. From the following, the following equation holds.

  From [Equation 1], [Equation 3], and [Equation 4], the following equation showing the input / output characteristics at D ≦ 0.5 is derived.

  The voltages of the secondary windings S1 and S2 of the transformer T1 are obtained individually. The signal is output from the two-time winding S2 during the t1 and t2 periods, and is output from the secondary winding S1 during the t3 period. The secondary winding voltage in each period is derived from [Equation 1], [Equation 2] and the turn ratio N as follows.

  Here, the t3 period is output from S1 as described above, and the S1 voltage is equal to [Equation 5]. Since the transformer output and the voltage Vo between the output terminals + Vo and −Vo are equal, it can be said that the output is constant current during the period t3. The T3 period is 50% duty, that is, the half cycle is a constant current output, and the output current ripple is reduced. This is indicated by the fact that the current Ia1 of the diode D1 shown in FIG.

Next, the input / output characteristics of FIG. 9 will be described.
The insulated half bridge converter has 50% duty, the boost converter unit has variable duty control, and the switching element Q1 duty is 50% or more (D ≧ 0.5). The boost converter is the same as [Equation 1]. At this time, the sum total of the excitation current of the transformer T1 during one period is given by the following equation.

  The following equation is derived from [Equation 1] and [Equation 7].

  For the output voltage Vo at the output terminals + Vo and −Vo, the following equation is established.

  From [Equation 1], [Equation 8], and [Equation 9], the following equation showing the input / output characteristics at D ≧ 0.5 is derived.

  The voltages of the secondary windings S1 and S2 of the transformer T1 are obtained individually. It is output from the secondary winding S2 during the t1 period, and is output from the secondary winding S1 during the t2 and t3 periods. The secondary winding voltage in each period is derived from [Equation 1], [Equation 8] and the turn ratio N as follows.

  Here, the t1 period is output from the secondary winding S2 as described above, and the voltage of the secondary winding S2 is equal to [Equation 10]. Since the output of the transformer T is equal to the voltage Vo between the output terminals + Vo and −Vo, it can be said that the output is constant current during the period t1. The t1 period is 50% duty, that is, the half cycle is a constant current output, and the output current ripple is reduced. This is shown by the fact that the current Ia2 flowing through the diode D2 has a trapezoidal waveform as shown in FIG.

  As described above, when the duty cycle D of the switch element Q1 is <D ≦ 0.5, the t3 period which is the latter half 50% duty is a constant current output, and the duty cycle D of the switch element Q1 is 0.5 ≦ D. Similarly, the t1 period which is the 50% duty period of the first half is constant current operation. Thus, a constant current output is always performed in a half cycle, and an effect that the output current ripple can be reduced is obtained. Furthermore, if D = 0.5, that is, if all the switches operate at a duty of 50%, the t2 period disappears and only the t1 and t3 periods exist, and D = 0.5, and [Equation 5], [Equation 6], [Equation 6] [Equation 10] and [Equation 11] are all equal to the following equation. That is, the voltage of the secondary windings S1 and S2 of the transformer T1 and the output terminal + Vo. The constant current output becomes equal to the output voltage Vo between −Vo, and the ripple current becomes zero.

  That is, in the vicinity of D = 0.5, the ripple current is completely canceled or very small. Here, the duty D and the input / output gain Vo / Vin characteristics are represented by the graph shown in FIG. 11 from [Equation 5] and [Equation 10] when the turn ratio N = 1 for simplicity. According to the duty D and input / output gain Vo / Vin characteristics shown in FIG. 11, the input / output gain Vo / Vin = 0.5 when D = 0, and the output is obtained even when the duty of the switch element Q1 is reduced to zero. It is proved that cannot be reduced to zero. The input / output relationship at this time is obtained by substituting D = 0 into [Equation 5].

In the control circuit 10a of the second embodiment, the output can be suppressed when the duty of the switch element Q1 = 0 and the insulated half bridge converter performs variable duty control. That is, as shown in FIG. 10, the switching element Q4 of the insulated half bridge converter is subjected to variable duty control, and the switching element Q3 is inverted and synchronously switched.
The input / output characteristics of FIG. 10 will be described.
When the converter is operating stably, the direction of the current flowing through the transformer T1 is equal to the amount that the core of the transformer T1 is excited in one cycle is equal to the reset amount. The sum is zero during one cycle. Therefore, the sum of the excitation currents is given by the following equation.

  The following equation is derived from [Equation 14].

  For the output voltage Vo at the output terminals + Vo and −Vo, the following equation is established.

  From [Equation 15] and [Equation 16], the following equation indicating the input / output characteristics of the insulated half-bridge converter is derived.

  The following equation is obtained by substituting D ′ = 0.5 into [Equation 17], and is the same equation as [Equation 13] in which D = 0 is substituted into [Equation 5].

  It is proved that the operation of the isolated half bridge converter with 50% duty and the boost converter with variable duty control and that with the isolated half bridge converter with variable duty control are switched when the input / output relationship of [Equation 18] is satisfied. The The duty D ′ and the input / output gain Vo / Vin characteristics are represented by the graph shown in FIG. 12 from [Equation 17] when the turns ratio N = 1 for simplicity. According to the duty D ′ and the input / output gain Vo / Vin characteristics shown in FIG. 12, when the duty of the switch element Q3 is reduced to zero, the output becomes zero, which causes the output when the input current increases or when the output droops. Can be suppressed. It should be noted that [Equation 17] is a quadratic equation of the duty D ′, and the duty D ′ can obtain two solutions, but the duty D ′ is 0. Since it is 5, the following solution can be obtained.

As described above, in the second embodiment, the first arm configured by connecting the switching element Q1 and the switching element Q2 in series and one end thereof are connected to the DC input terminal (DC power supply Vin). The other end of the reactor Lr1 is connected to the midpoint of the first arm, the capacitor C1 is connected in parallel to the first arm, and the switching element Q3 and switching element Q4 are connected in series to the first arm. A second arm configured to be connected to the center, and a middle point of the first arm and a middle point of the second arm, and a capacitor C2, a reactor Lr2, and a primary winding P1 of the transformer T connected in series. A series circuit constructed by connecting, and a rectifying and smoothing circuit (diode) connected to the secondary windings S1 and S2 of the transformer T and rectifying and smoothing the voltage generated in the secondary windings S1 and S2 to extract a DC output D1, D2, reactor Lr3, capacitor C3), first control circuit 11a for alternately switching on and off switching element Q1 and switching element Q2, and on and off of third switching element and fourth switching element alternately The first control circuit 11a alternately turns on and off the switching element Q1 and the switching element Q2 with a variable duty during a steady load, and the second control circuit 12a 3 The switching element Q3 and the switching element Q4 are alternately turned on and off at 50% duty, and at the time of light load, the first control circuit 11a controls the first switching element Q1 to zero duty, and the second control circuit 12a The third switching element Q3 and the switching element Q4 are connected to a variable duty. To be alternately turned on and off at tea.
With this configuration, the switch element Q1 is turned off, and the on-time of the switch elements Q3 and Q4 is adjusted according to the error amplification signal EAS, so that the output of the insulated half bridge converter can be suppressed according to the error amplification signal EAS. it can. Also during the variable duty control of the insulated half bridge converter, the input current becomes a direct current as in the step-up operation by switching of the switch elements Q1 and Q2.

Further, in the second embodiment, a synchronization circuit 13a is provided that synchronizes the turn-on of the switching element Q1 and the turn-on of the switching element Q3, and synchronizes the turn-off of the switching element Q2 and the turn-off of the switching element Q4.
With this configuration, even if the excitation power of the reactor Lr1 is large and the energy of the capacitor C1 is increased, the capacitor C1 not only accumulates charges (energy) but also outputs via the transformer T at the same time. Therefore, the voltage of the capacitor C1 is suppressed.

Further, in the second embodiment, an error amplifier AMP1 that generates an error amplification signal EAS obtained by comparing a direct current output with a predetermined reference voltage Vref1, and a first saw that varies from Vb to Vc (Vb <Vc). A first triangular wave generator 14a for generating a wave Tria1, and a second sawtooth wave Tria2 having a frequency twice as high as that of the first sawtooth wave Tria1 varying from Va to Vb (Va <Vb) and synchronized in falling. The first control circuit 11a compares the error amplification signal EAS with the first sawtooth wave Tria1 at the time of steady load, thereby generating a first switching element Q1 and a second switching element. Q2 is alternately turned on and off at a variable duty, and at light load, the second control circuit 12a performs error amplification signal EAS and second sawtooth wave Tr. By comparing the a2, it is off and the third switching element Q3 and the fourth switching element Q4 are alternately variable duty.
With this configuration, the differential amplification signal EAS can freely travel between the two sawtooth waves (the first sawtooth wave Tria1 and the second sawtooth wave Tria2), so that an appropriate operation can be performed under any input / output conditions. .

(Third embodiment)
The switching power supply according to the third embodiment controls the boost converter (switching elements Q1, Q2) and the insulated half-bridge converter (switching elements Q3, Q4) shown in FIG. 1 by a control circuit 10b shown in FIG. Referring to FIG. 13, the control circuit 10b includes a first control circuit 11b, a second control circuit 12b, a synchronization circuit 13a, an error amplifier AMP1, and an error amplifier AMP2.

  The first control circuit 11b is provided with a comparator CMP3 and an AND circuit AND5 in addition to the first control circuit 11a of the second embodiment. The first sawtooth wave Tria1 output from the first triangular wave generator 14a is input to the inverting input terminal (−) of the comparator CMP3. Further, a resistor R4 and a capacitor C4 are connected in series between a reference voltage Vref2 greater than Vc (the maximum voltage of the first sawtooth wave Tria1) and the ground terminal, and the resistor R4 and the capacitor C4 are connected. The voltage at the point is input as the soft start signal SS to the non-inverting input terminal (−) of the comparator CMP3. The output CMP1out of the comparator CMP1 and the output CMP3out of the comparator CMP3 are input to the respective input terminals of the AND circuit AND5. The output of the AND circuit AND5 is input to the other input terminal of the AND circuit AND1, and via the inverter INV1. Are input to the other input terminal of the AND circuit AND2.

  In addition to the second control circuit 12a of the second embodiment, the second control circuit 12b is provided with a comparator CMP4 and an AND circuit AND6. The second sawtooth wave Tria2 output from the second triangular wave generator 14b is input to the inverting input terminal (−) of the comparator CMP4. Further, a resistor R4 and a capacitor C4 are connected in series between a reference voltage Vref2 larger than Vc (the maximum voltage of the first sawtooth wave Tria1) and the snow dust terminal, and the resistor R4 and the capacitor C4 are connected. The voltage at the point is input as the soft start signal SS to the non-inverting input terminal (−) of the comparator CMP4. The output CMP2out of the comparator CMP2 and the output CMP4out of the comparator CMP4 are input to the respective input terminals of the AND circuit AND6, the output of the AND circuit AND6 is input to the other input terminal of the AND circuit AND3, and via the inverter INV1. And input to the dead time generation circuit 15b.

  With this configuration, at the time of startup, the capacitor C4 is started by the reference voltage Vref2, the soft start signal SS and the first sawtooth wave Tria1 that gradually increase from 0V are gradually increased from 0V in the comparator CMP3, and are gradually increased from 0V in the comparator CMP4. The soft start signal SS and the second sawtooth wave Tria2 are respectively compared. Therefore, when the soft start signal SS <Vb, the duty of the switching element Q1 = 0, and the insulated half bridge converter is variable duty controlled according to the smaller value of the soft start signal SS or the error amplification signal EAS. When Vb ≦ soft start signal SS ≦ Vc and error amplification signal EAS <Vb, the duty of switch element Q1 = 0, and the insulated half-bridge converter is subjected to variable duty control according to error amplification signal EAS. When Vb ≦ soft start signal SS ≦ Vc and Vb ≦ error amplification signal EAS ≦ Vc, the insulated half-bridge converter operates at 50% duty, and the switch elements Q1 and Q2 are connected to the soft start signal SS or the error amplification signal EAS. Variable duty control is performed according to the smaller value.

  As described above, the comparator CMP3 and the AND circuit AND5 of the first control circuit 11b and the comparator CMP4 and the AND circuit AND6 of the second control circuit 12b are adjusted to adjust the error signal according to the soft start signal SS at the time of activation. Functions as a circuit.

  The error amplifier AMP2 is provided for overload detection. The error amplifier AMP2 amplifies an error voltage between the voltage proportional to the output current (which may be the drain current of the switch elements Q1 to Q4, preferably the drain current of the switch element Q4) and the reference voltage Vre3, and this error amplification signal EAS Are output to the non-inverting input terminal (+) of the comparator CMP1 in the first control circuit 11a and the non-inverting input terminal (+) of the comparator CMP2 in the second control circuit 12a. The output terminals of the error amplifier AMP1 and the error amplifier AMP2 are connected to the reference voltage Vre via a backflow prevention diode and a resistor R5, respectively. Thereby, at the time of load, the voltage generated in the secondary winding lines S1 and S2 can be rectified and smoothed to reduce the error amplification signal EAS according to the current output from the DC output, thereby suppressing the output. That is, the error amplifier AMP2 functions as a signal lowering circuit that lowers the error amplification signal EAS according to the current output from the DC output during overload.

As described above, the third embodiment includes the signal reduction circuit (error amplifier AMP2) that reduces the error amplification signal EAS according to the current output from the DC output during overload.
With this configuration, it is possible to suppress the output of the insulated half-bridge converter according to the error amplification signal EAS during overload.

Furthermore, in the third embodiment, an adjustment circuit (the comparator CMP3 and AND circuit AND5 of the first control circuit 11b and the second control circuit 12b) that adjusts the error amplification signal EAS according to the soft start signal SS at the time of startup. Comparator CMP4 and AND circuit AND6) are provided.
With this configuration, it is possible to suppress the output of the insulated half bridge converter according to the error amplification signal EAS at the time of startup.

  The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented, and numerical values and compositions (materials) of the respective components. Is merely an example. Therefore, the present invention is not limited to the described embodiments, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.

AND1 to AND6 AND circuits AMP1, AMP2 Error amplifiers BUF1, BUF2 Buffer circuits C1-C4 Capacitors Ca-Cd Capacitors CMP1-CMP4 Comparators D1-D4 Diode Da-Dd Diode FF1, FF2 Flip-flop INV1, INV2 Inverter NAND1 NAND circuit Lr1, Lr2 , Lr3 Reactor P1 Primary windings Q1-Q4 Switching elements R1-R5 Resistors S1, S2 Secondary winding T Transformer Vin DC power supply 1 Switching power supply device 10, 10a Control circuits 11, 11a, 11b First control circuits 12, 12a, 12b Second control circuit 13, 13a Synchronous circuit 14 Triangular wave generator 14a First triangular wave generator 14b Second triangular wave generators 15a, 15b Dead time generating circuit 16a Oscillator 16b Synchronous oscillation

Claims (4)

A first arm configured by connecting a first switching element and a second switching element in series;
A reactor having one end connected to a DC input terminal and the other end connected to the midpoint of the first arm;
A smoothing capacitor connected in parallel to the first arm;
A second arm connected in parallel to the first arm and configured by connecting a third switching element and a fourth switching element in series;
A series circuit connected between a midpoint of the first arm and a midpoint of the second arm, and configured by connecting a resonant capacitor, a resonant reactor, and a primary winding of a transformer in series;
A rectifying and smoothing circuit connected to the secondary winding of the transformer and rectifying and smoothing a voltage generated in the secondary winding to extract a DC output;
A first control circuit for alternately turning on and off the first switching element and the second switching element;
A second control circuit that alternately controls on and off of the third switching element and the fourth switching element;
An error amplifier for generating an error signal obtained by comparing the DC output with a predetermined reference voltage;
A first triangular wave generator that generates a first sawtooth wave that varies from a second voltage to a third voltage that is greater than the second voltage;
A second triangular wave generator for generating a second sawtooth wave having a frequency several times that of the first sawtooth wave, which fluctuates from the first voltage smaller than the second voltage to the second voltage, and whose falling edge is synchronized. And
At the time of steady load, the first control circuit compares the error signal with the first sawtooth wave to alternately turn on and off the first switching element and the second switching element with a variable duty, and The second control circuit alternately turns on and off the third switching element and the fourth switching element with a 50% duty,
At the time of light load, the first control circuit controls the first switching element to zero duty, and the second control circuit compares the error signal with the second sawtooth wave to thereby calculate the third switching element. A switching power supply device, wherein the switching element and the fourth switching element are alternately turned on and off at a variable duty. A synchronization circuit that synchronizes the turn-on of the first switching element and the turn-on of the third switching element and the turn-off of the second switching element and the turn-off of the fourth switching element during a steady load; The switching power supply device according to claim 1 . 3. The switching power supply device according to claim 1, further comprising a signal reduction circuit that reduces the error signal in accordance with a current output from the DC output during overload. At startup, the switching power supply device according to any of claims 1 to 3, characterized in that it comprises an adjusting circuit for adjusting said error signal in response to the soft start signal.

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