JP6540650B2 - 半導体装置およびその製造方法 - Google Patents
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- JP6540650B2 JP6540650B2 JP2016205225A JP2016205225A JP6540650B2 JP 6540650 B2 JP6540650 B2 JP 6540650B2 JP 2016205225 A JP2016205225 A JP 2016205225A JP 2016205225 A JP2016205225 A JP 2016205225A JP 6540650 B2 JP6540650 B2 JP 6540650B2
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H01L23/562—Protection against mechanical damage
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- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Chemical Vapour Deposition (AREA)
Description
また、パッシベーション膜は、絶縁膜層、有機物層および金属層を覆って半導体基板に形成される。このため、半導体基板、絶縁膜層、有機物層および金属層が、互いの熱膨張係数差に起因して圧縮応力を発生させるときでも、引張応力を発生させるパッシベーション膜によって、これらの圧縮応力を緩和することができる。
以下、本発明の実施の形態による半導体装置について、添付図面を参照しつつ詳細に説明する。本発明の半導体装置は、例えばMHz帯またはGHz帯のような高周波信号を増幅する電力増幅器に適用されるものである。
2 半導体基板
2A 表面
2B 半導体層
3 半導体素子
4 金属層
11,32,46 パッシベーション膜
12,33,47 第1絶縁膜
13,34,48 第2絶縁膜
42 第1金属層(金属層)
43 絶縁膜層
44 有機物層
45 第2金属層(金属層)
Claims (4)
- 半導体基板と、
前記半導体基板に形成された半導体素子と、
前記半導体素子を覆って前記半導体基板の表面に形成された無機材料からなる絶縁膜層と、
前記絶縁膜層を覆って前記絶縁膜層の表面に形成された有機材料からなる有機物層と、
前記有機物層の表面に形成された金属層と、
前記絶縁膜層、前記有機物層および前記金属層を覆って前記半導体基板に形成され前記半導体素子を保護するパッシベーション膜と、を備え、
前記パッシベーション膜は、引張応力が大きい第1絶縁膜と、引張応力が小さい第2絶縁膜とを交互に積み重ねて形成され、全体として引張応力を発生させ、
前記有機物層は、平面視において、前記半導体基板の表面全体のうち一部の領域に形成され、かつ前記有機物層の側面部を、前記パッシベーション膜が覆っており、
前記パッシベーション膜の一部は、前記半導体基板の表面に接していることを特徴とする半導体装置。 - 前記第2絶縁膜は、圧縮応力を発生させてなる請求項1に記載の半導体装置。
- 半導体基板に半導体素子を形成する工程と、
前記半導体素子を覆って前記半導体基板の表面に無機材料からなる絶縁膜層を形成する工程と、
前記絶縁膜層を覆って前記絶縁膜層の表面に有機材料からなる有機物層を形成する工程と、
前記有機物層の表面に金属層を形成する工程と、
前記絶縁膜層、前記有機物層および前記金属層を覆って前記半導体基板上に、引張応力が大きい第1絶縁膜と、引張応力が小さい第2絶縁膜とを交互に積み重ねて形成し、全体として引張応力を発生させるパッシベーション膜を形成する工程とを有し、
前記有機物層は、平面視において、前記半導体基板の表面全体のうち一部の領域に形成され、
前記パッシベーション膜は、前記有機物層の側面部を覆い、その一部が前記半導体基板の表面に接していることを特徴とする半導体装置の製造方法。 - 前記金属層は、蒸着またはめっきによって形成してなる請求項3に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2016205225A JP6540650B2 (ja) | 2016-10-19 | 2016-10-19 | 半導体装置およびその製造方法 |
US15/784,709 US10163749B2 (en) | 2016-10-19 | 2017-10-16 | Semiconductor device and method of manufacturing the same |
CN201710963260.2A CN107968035B (zh) | 2016-10-19 | 2017-10-16 | 半导体装置及其制造方法 |
TW106135826A TWI673838B (zh) | 2016-10-19 | 2017-10-19 | 半導體裝置及其製造方法 |
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JP2016205225A JP6540650B2 (ja) | 2016-10-19 | 2016-10-19 | 半導体装置およびその製造方法 |
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JP2018067633A JP2018067633A (ja) | 2018-04-26 |
JP6540650B2 true JP6540650B2 (ja) | 2019-07-10 |
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JP (1) | JP6540650B2 (ja) |
CN (1) | CN107968035B (ja) |
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US11145564B2 (en) * | 2018-06-29 | 2021-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-layer passivation structure and method |
JP7076490B2 (ja) | 2020-03-24 | 2022-05-27 | 株式会社Kokusai Electric | 基板処理方法、半導体装置の製造方法、基板処理装置、およびプログラム |
JP7268630B2 (ja) * | 2020-03-30 | 2023-05-08 | 三菱電機株式会社 | 半導体圧力センサ及びその製造方法 |
US20210366792A1 (en) * | 2020-05-22 | 2021-11-25 | Tokyo Electron Limited | Backside deposition tuning of stress to control wafer bow in semiconductor processing |
US20240030331A1 (en) * | 2021-08-06 | 2024-01-25 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device and method for manufacturing the same |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS62293726A (ja) * | 1986-06-13 | 1987-12-21 | Nec Corp | 半導体装置 |
JPS63244628A (ja) * | 1987-03-30 | 1988-10-12 | Mitsubishi Electric Corp | 表面保護膜 |
JPH01241134A (ja) * | 1988-03-23 | 1989-09-26 | Seiko Epson Corp | 半導体装置 |
JP3033376B2 (ja) * | 1993-01-22 | 2000-04-17 | 株式会社デンソー | 半導体装置の製造方法 |
US5756404A (en) * | 1995-12-07 | 1998-05-26 | Micron Technologies, Inc. | Two-step nitride deposition |
TW396454B (en) * | 1997-06-24 | 2000-07-01 | Matsushita Electrics Corporati | Semiconductor device and method for fabricating the same |
JP4460669B2 (ja) * | 1999-03-19 | 2010-05-12 | 株式会社東芝 | 半導体装置 |
US6939814B2 (en) * | 2003-10-30 | 2005-09-06 | International Business Machines Corporation | Increasing carrier mobility in NFET and PFET transistors on a common wafer |
US7381619B2 (en) * | 2004-04-27 | 2008-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual work-function metal gates |
US7585704B2 (en) * | 2005-04-01 | 2009-09-08 | International Business Machines Corporation | Method of producing highly strained PECVD silicon nitride thin films at low temperature |
US20080173908A1 (en) * | 2007-01-19 | 2008-07-24 | Freescale Semiconductor, Inc. | Multilayer silicon nitride deposition for a semiconductor device |
CN101286478A (zh) * | 2007-04-11 | 2008-10-15 | 联华电子股份有限公司 | 互补式金属氧化物半导体晶体管及其制造方法 |
JP2008300678A (ja) * | 2007-05-31 | 2008-12-11 | Oki Electric Ind Co Ltd | 半導体素子の製造方法、及び半導体素子 |
KR20110009762A (ko) * | 2009-07-23 | 2011-01-31 | 삼성전자주식회사 | 트랜지스터 및 그 제조 방법 |
KR20120023968A (ko) * | 2010-09-03 | 2012-03-14 | 삼성전자주식회사 | 트랜지스터 형성 방법, 상보형 트랜지스터 형성 방법 및 이를 이용한 반도체 소자 제조 방법 |
US8941218B1 (en) * | 2013-08-13 | 2015-01-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Passivation for group III-V semiconductor devices having a plated metal layer over an interlayer dielectric layer |
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- 2016-10-19 JP JP2016205225A patent/JP6540650B2/ja active Active
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- 2017-10-16 US US15/784,709 patent/US10163749B2/en active Active
- 2017-10-16 CN CN201710963260.2A patent/CN107968035B/zh active Active
- 2017-10-19 TW TW106135826A patent/TWI673838B/zh active
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CN107968035A (zh) | 2018-04-27 |
JP2018067633A (ja) | 2018-04-26 |
CN107968035B (zh) | 2022-02-25 |
TWI673838B (zh) | 2019-10-01 |
US20180108588A1 (en) | 2018-04-19 |
TW201830603A (zh) | 2018-08-16 |
US10163749B2 (en) | 2018-12-25 |
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