JP6538987B2 - Memoryless, common mode, low sensitivity and low pulling VCO - Google Patents

Description

Cross-reference to related applications
[0001] The present application relates to ACTIVE DEVICE WHICH HAS A HIGH BREAK DOWN, IS MEMORY-LESS, TRAPS EVEN HARMONIC SIGNALS AND CIRCUITS USED THEREWITH (High breakdown voltage and memoryless, filed on June 19, 2015. U.S. patent application Ser. No. 14 / 745,261, entitled "Active Device for Capturing Even Harmonic Signals and Circuits Used With It", filed on Jan. 6, 2015. VERY LOW PHASE NOISE, MEMORYLESS COMMON-MODE INSENSITIVE, AND LOW PULLING VCO WITH CAPACITOR BANKS AS TUNING Ultra-low phase noise, memoryless, common mode, low sensitivity and low pulling VCOs) using capacitor banks as in US Patent Law Article 119 (e) of US Provisional Patent Application No. 62 / 100,397 Claims the benefits of which are both incorporated herein by reference in their entirety.

  FIELD [0002] The present invention relates generally to wireless devices, and more particularly to voltage controlled oscillators utilized in such devices.

  Wireless products are utilized in various environments such as mobile (eg, cellular and Wi-Fi for handsets) or non-mobile (eg, Wi-Fi for access points and routers). A voltage controlled oscillator or VCO is an electronic oscillator whose oscillation frequency is controlled by a voltage input. The applied input voltage determines the instantaneous oscillation frequency. Thus, modulating the applied signal to control the input may result in frequency modulation (FM) or phase modulation (PM). The VCO may also be part of a phase locked loop. The VCO may be utilized in amplifiers in such products to amplify signals received or transmitted therefrom. As the market for wireless products evolves, the need for more bandwidth and more data across mobile and non-mobile networks is further increasing, with more demand for higher efficiency and linearity. Thus, the communication of such data through these networks is becoming increasingly difficult. For example, as bandwidth increases as the network evolves, at the same time, the signal constellation becomes more dense like the 802.11ax standard for WiFi applications. As a result, the in-band and out-of-band noise of the VCO becomes very important. VCO pulling is also a major issue. This case is more important in the presence of high power amplifiers for integration. Furthermore, conventional VCO architectures rely on buffers to center the output of the core VCO and then drive the inverter chain following the core. This buffer consumes a great deal of power and is another source of noise and jamming problems.

[0004] VCO tuning range is another issue. The VCO tuning range is limited by the noise of the capacitor bank and its parasitics.
[0005] Devices and circuits according to the present invention address such needs.

  One embodiment of the present invention relates, for example, to memoryless, common mode, low sensitivity and low pulling VCOs.

  [0006] A voltage controlled oscillator (VCO) and circuitry utilized therewith are disclosed. In a first aspect, the VCO comprises an active device. The VCO comprises an active device, which further comprises an n-type transistor having a drain, a gate and a bulk and a p-type transistor having a drain, a gate and a bulk. The n-type transistor and the p-type transistor share a common source.

  The active device comprises a first capacitor coupled between a gate of an n-type transistor and a gate of a p-type transistor, and a first capacitor coupled between a drain of the n-type transistor and a drain of the p-type transistor. And a third capacitor coupled between the bulk of the n-type transistor and the bulk of the p-type transistor.

  [0008] A differential voltage controlled oscillator (VCO) is also disclosed. The differential VCO includes a first active device and a second active device. Each of the first and second active devices further includes an n-type transistor having a drain, a gate, and a bulk. Each of the first and second active devices also includes a p-type transistor having a drain, a gate and a bulk. The n-type transistor and the p-type transistor share a common source. Each of the first active device and the second active device also includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor. Each of the first active device and the second active device also includes a second capacitor coupled between the drain of the n-type transistor and the drain of the p-type transistor. Each of the first active device and the second active device further includes a third capacitor coupled between the bulk of the n-type transistor and the bulk of the p-type transistor. The differential VCO also includes a fourth capacitor coupled between the bulk of the n-type transistor of the first active device and the shared source of the second active device. The differential VCO also includes a fifth capacitor coupled between the bulk of the p-type transistor of the first active device and the shard source of the second active device. The tile differential VCO also includes a sixth capacitor coupled between the bulk n-type transistor of the second active device and the shared source of the first active device. The differential VCO also includes a seventh capacitor coupled between the bulk of the p-type transistor of the second active device and the shared source of the first active device. The differential VCO also includes a tuning block coupled to the common source to form a common gate amplifier. The differential VCO also includes at least one first tuning device coupled between the drain of the n-type transistor of the first active device and the drain of the n-type transistor of the second active device. The differential VCO is coupled between the sources of the n-type and p-type transistors of the first active device and the sources of the n-type and p-type transistors of the second active device. Also includes tuning devices. Finally, the differential VCO is coupled between the drain of the p-type transistor of the first active device and the drain of the p-type transistor of the second first active device, at least one third tuning device , The differential VCO has a high breakdown voltage, is memoryless, is very close in and far phase noise, is extremely Pull and capture even harmonic signals.

  [0009] The VCO includes a tuning block coupled to the common source to form a common gate amplifier, and at least one tuning element coupled to the active device to change the overall capacitance of the VCO. The VCO has high breakdown voltage, is memoryless, is very low near distal phase noise, is very low sensitivity to power and ground disturbances and thus low pulling, and captures even harmonic signals.

  [0010] The VCO has a high breakdown voltage since the n-type device and the p-type device respectively receive a portion of the total power supply voltage, and the gate capacitance and n coupled between the n-type gate and the p-type gate The bulk capacitor, which combines the bulk of the shape and the p-type, captures a common mode signal coupled to the key node of the device, so it is memoryless and captures even harmonic signals. Also, this combination of n-type and p-type distinguishes between even and odd signals generated during Class AB or Class B or Class C operation.

  [0011] Systems and methods according to the present invention provide amplifier circuits that can be combined with transformers to obtain increased gain and positive feedback for voltage controlled oscillator (VCO) applications. The resulting device does not require a buffer or memory, since the output signal can be taken from each common source centered on the power supply, and thus is smaller in size and uses less power than a conventional VCO.

[0012] FIG. 1 is a schematic diagram of an active device utilized in a voltage controlled oscillator according to the present invention. [0013] FIG. 1B is a block diagram of the active device shown in FIG. 1A. [0014] FIG. 5 is a schematic diagram of a differential active device utilized in a voltage controlled oscillator according to the present invention. [0015] FIG. 5 is a schematic view of a differential active device including a capacitive tuning element utilized in a voltage controlled oscillator according to the invention. [0016] FIG. 5 is a block diagram of the differential active device shown in FIG. 1D. [0017] FIG. 2A is a first embodiment of a tuning block according to the present invention. [0018] FIG. 28 is a second embodiment of a tuning block according to the present invention. [0019] FIG. 2C is a third embodiment of a tuning block according to the present invention. [0020] FIG. 3A is a block diagram of a common gate amplifier according to the present invention. [0021] FIG. 38 is a block diagram of a combined common gate and common source amplifier according to the present invention. [0022] FIG. 1 is a block diagram of a first embodiment of a differential common gate amplifier according to the present invention. [0023] FIG. 7 is a block diagram of a second embodiment of a differential common gate amplifier according to the present invention. [0024] FIG. 7 is a block diagram of an embodiment of a differential combination common gate and common source amplifier according to the invention. [0025] FIG. 7 is a block diagram of an embodiment of a single ended voltage controlled oscillator (VCO) according to the present invention. [0026] FIG. 6 is a block diagram of an embodiment of a differential VCO arranged in the form of a common gate, common source according to the present invention. [0027] FIG. 7 is a block diagram of an embodiment of a cascade VCO of CG-CS according to the present invention. [0028] FIG. 7 is a block diagram of an embodiment of a differential VCO arranged in the form of a common gate according to the invention. [0029] FIG. 7 is a block diagram of an embodiment of a cascaded VCO of CG according to the present invention. [0030] FIG. 7 is a block diagram of an embodiment of a cascaded VCO with CG and CG-CS combination. [0031] FIG. 7 is a diagram of two differential common gate active devices coupled to a coupled inductive differential tuning block in accordance with the present invention. [0032] FIG. 6 is a diagram of three common gate differential active devices coupled to a coupled inductive differential tuning block in accordance with the present invention. [0033] FIG. 7 is a diagram of four differential common gate active devices coupled to an inductive differential tuning block in accordance with the present invention. [0034] FIG. 7 illustrates the addition of drain current before the loop in the VCO according to the present invention. [0035] FIG. 5 illustrates the addition of drain current after the loop in the VCO, according to the present invention.

  The present invention relates generally to wireless devices, and more particularly to voltage controlled oscillators utilized in such devices. The following description is presented to enable any person skilled in the art to make and use the present invention, and is given in the context of patent applications and their requirements. Various modifications to the preferred embodiments and the general principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

  [0037] FIG. 1A is a schematic diagram of an active device 100 utilized in a voltage controlled oscillator according to the present invention. Active Devices and Use of Active Devices in Amplifier Circuits are owned by the assignee of the present application, ACTIVE DEVICE WHICH HAS A HIGH BREAK DOWN, filed on June 19, 2015, IS MEMORY-LESS, TRAPS EVEN HARMONIC SIGNALS And described in detail in the co-pending US application entitled AND CIRCUITS USED THEREWITH (Active Device with High Breakdown Voltage, Memoryless, and Active Device for Capturing Even Harmonic Signals and Circuits Used With It) There is. Active device 100 includes an n-type transistor 102 including a gate (gn), a drain (dn) and a bulk (bn), and a p-type transistor 104 including a gate (gp), a drain (dp) and a bulk (bp). . The n-type transistor 102 and the p-type transistor 104 share one or more common sources. Active device 100 includes a first capacitor 106 coupled between gn and gp, a second capacitor 108 coupled between dn and dp, and a second capacitor coupled between bn and bp. And three capacitors 110. Active device 100, when used with some amplifiers such as class AB amplifiers, has high breakdown voltages due to four terminals (gate, drain, bulk and source), is memoryless and has even harmonics Capture

  [0038] FIG. 1B is a block diagram of the active device 100 shown in FIG. 1A. The n-type transistor 102 can be an NPN bipolar or any other active element from GaAs. P-type transistor 104 may be PNP bipolar or any other active complement from GaAs. The n-type transistor 102 may be further protected by a cascaded NMOS circuit. The p-type transistor 104 may be a variable capacitor, which may be further protected by a cascaded PMOS circuit, which may comprise a series resistor and / or a series inductor, all of which are variable. Capacitor 106 may be further divided into N capacitors with any series element. The capacitor 108 may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. Capacitor 108 can be further divided into N capacitors with any series element. Capacitor 110 may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. Capacitor 110 can be further divided into N capacitors with any series element.

  [0039] More capacitors may be coupled from dn to gn, from dn to gp, from dp to gp, from dp to gn (parasitic or non-parasitic). These capacitors are variable and / or may have series passive or active elements such as inductors, resistors, transformers and the like. Node gp can be connected to a bias network. The bias network can include any passive, such as resistors, capacitors, inductors, transformers, and any combination thereof. The bias can also include any active element.

  [0040] When using cascaded transistors for n-type and / or p-type, an additional capacitor is required to connect the cascade n-type drain to the cascade p-type drain as well as capacitor 110. May be required. Also, the capacitor that couples the cascade n-type bulk to the cascade p-type bulk may be similar to the capacitor 108. Furthermore, capacitors may be connected from the cascade n-type gate to the cascade p-type gate, similar to the capacitor 106.

  [0041] FIG. 1C is a schematic diagram of a differential active device 150 utilized in a voltage controlled oscillator according to the present invention. Differential active device 150 includes a first active device 100 and a second active device 100 coupled in a differential manner. The differential active devices include capacitors 190 and 192 in both active devices 100 coupled from the bulk to the source of the respective transistors 102 and 104. Capacitors 190 and 192 improve the high frequency linearity, stability and self gain of common gate active device 150. Capacitor 106, which connects the common gate of an n-type device to the common gate of a p-type device, is a power supply, ground and (class AB, class B, C, etc. Common mode signals can be captured from self-generated even harmonics (by VCOs or amplifiers that input class ... mode).

  [0042] A capacitor 108 connecting the bulk of the n-type device to the bulk of the p-type device is a class AB, class B, class C,. . . Provides a path for even harmonics generated by the action. Also, bulk nodes are filtered from power or ground noise to ameliorate the problems associated with VCO pulling or memory effects.

  [0043] FIG. 1D is a schematic diagram of a differential active device 151 including capacitive tuning elements 194a, 194b and 196 utilized in a voltage controlled oscillator according to the present invention. Differential active device 151 is similar to the differential active device of FIG. 1C. Tuning elements 194 a and 194 b are coupled between the drains of active device 100 to provide coarse tuning adjustment of device 151. The tuning element 196 is coupled between the sources of the active device 100 to provide fine tuning adjustment of the device 151. The tuning elements 194a, 194b and 196 are utilized to change the effective capacitance (not shown but possibly apparent, including parasitic capacitances) of the device 151. This can change the center frequency of the entire VCO structure. The tuning element 194a may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. The tuning element 194a can be further divided into N capacitors with any series element. The tuning element 194b may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. The tuning element 194b can be further divided into N capacitors with any series element. Capacitor 110 may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. Capacitor 110 can be further divided into N capacitors with any series element.

  [0044] FIG. 1E is a block diagram of the differential active device shown in FIG. 1D. Similar to FIG. 1A, in each of the active devices, n-type transistor 102 may be an NPN bipolar or any other active element from GaAs. P-type transistor 104 may be PNP bipolar or any other active complement from GaAs. The n-type transistor 102 can be further protected by a cascaded NMOS or NPN circuit. The p-type transistor 104 may be further protected by a cascaded PMOS or PNP circuit. The capacitor 106 may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. Capacitor 106 may be further divided into N capacitors with any series element. The capacitor 108 may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. Capacitor 108 can be further divided into N capacitors with any series element. Capacitor 110 may be a variable capacitor, which may have a series resistor and / or a series inductor, all of which are variable. Capacitor 110 can be further divided into N capacitors with any series element.

  [0045] More capacitors may be coupled from dn to gn, from dn to gp, from dp to gp, from dp to gn (parasitic or non-parasitic). These capacitors are variable and / or may have series passive or active elements such as inductors, resistors, transformers and the like. Node gp can be connected to a bias network. The bias network can include any passive, such as resistors, capacitors, inductors, transformers, and any combination thereof. The bias can also include any active element.

  [0046] When using cascaded transistors for n-type and / or p-type, an additional capacitor is needed to connect the cascade n-type drain to the cascade p-type drain as well as capacitor 110. May be required. Also, the capacitor that couples the cascade n-type bulk to the cascade p-type bulk may be similar to the capacitor 108. Furthermore, capacitors may be connected from the cascade n-type gate to the cascade p-type gate, similar to the capacitor 106.

  [0047] Active device 100 in FIG. 1A or differential active device 150 or differential active device 151 in FIGS. 1C and 1D are any other than class AB or class B or class C or class D or class A, respectively. Active device 151 generates even and odd harmonic output currents flowing through the dn and dp nodes. Active device 151 distinguishes between even and odd harmonics by generating current flow in similar directions at node dn and node dp for odd signals such as the main signal or third harmonic. be able to. However, active device 100 will generate currents in opposite directions at node dn and node dp for the second, fourth, fifth, etc. even harmonics. Also, the filtering action produced by capacitors 110, 108 and 106 will affect the magnitude of the even harmonics flowing through the dn and dp nodes.

  [0048] FIG. 2A is a first embodiment of a tuning block 200 according to the present invention. Single-ended tuning block 200 includes two inputs, dn and dp, one output, s, voltage supply (vdd) and ground (gnd). Input signals in the form of current may be provided to node dn and node dp as l_in_n and l_in_p, respectively. The tuning block 200, which can include all or some combination of passive, inductor, capacitor, resistor and transformer, but not limited to either, l_in_n and l_in_n and l_in_n + l_in_p if It has a function of receiving l_in_p and providing an output current at the node S, l_s. The tuning block 200 is utilized to provide a linear output signal regardless of power. The combination of tuning block 200 and active device 100 forms a common gate amplifier.

  [0049] FIG. 3A is a block diagram of a single ended common gate amplifier according to the present invention. The common gate amplifier comprises an active device 100 coupled to a tuning block 200. In this embodiment, the current l_s from the tuning block 200 is provided to the source connection, S, of the active device 100. The common gating action of the device 100 causes the current l_s to split, part of which is directed to dn as the output current l_out_n and the other part to dp as the output current l_out_p. The gate gn and gate gp of the active device 100 are coupled to the bias line. (Signal not applied to gn and gp). Bulk node bn and bulk node bp are also coupled to their respective bias lines.

  When the active device 100 is operating in class AB, class B, C, class D and class F modes, other even and odd harmonic currents are generated inside the active device 100. These currents are directed towards dn and dp. For even harmonics, such as AM (amplitude modulated) current and second harmonic, the direction of current flow through dn and the direction of current flow through dp are opposite. However, for odd harmonics, such as the main signal current and the third harmonic, the direction of the output current through dn and the direction of the output current through dp are the same.

  [0051] FIG. 28 is a second embodiment of a tuning block 200 'in accordance with the present invention. Single-ended tuning block 200 'includes two inputs, dn and dp, and three outputs, s, gn and gp. The single-ended tuning block 200 'has a power supply (vdd) and a ground (gnd). An input signal in the form of a current is inserted into node dn and node dp using l_in_n and l_in_p respectively. A tuning block 200 'that can include all or some combination of passive, inductor, capacitor, resistor and transformer, but not limited to any, where the following conditions, ie, l_s> l_in_n + l_in_p It has a function of receiving l_in_n and l_in_p and providing an output current at the node S, l_s. The outputs gp and gn are voltages that will drive the gn and gp nodes of the active device 100. As shown in FIG. 38, combining tuning block 200 'with active device 100 forms a common gate / common source amplifier action.

  [0052] Further, tuning block 200 'may send only gating information gn and gp and not sending information at S nodes. In this case, the S node may be grounded or coupled to passive devices such as resistors, capacitors, inductors, transformers, or active devices, or all. The combination of tuning block 200 'and active device 100 forms a common source amplifier in this particular case.

  [0053] FIG. 38 is a block diagram of a combined common gate and common source amplifier in single-ended form according to the present invention. The common gate and common source amplifier comprises an active device 100 coupled to the tuning block 200 '. In this embodiment, the current l_s from the tuning block 200 ′ is provided to the source connection, S, of the active device 100. The common gating action of the device for the current entering node s causes the current l_s to split up, part of it being directed to dn as output current l_out_n and the other part being directed to dp as output current l_out_p. Gate gn and gate gp of active device 100 are coupled to the bias line and are driven by output nodes gn and gp of the tuning block. Bulk node bn and bulk node bp are also coupled to their respective bias lines. Node gn and node gp may be further connected to their respective biases isolated from the main signal.

  [0054] FIG. 4A is a block diagram of a first embodiment of a differential common gate amplifier 400 according to the present invention. Amplifier 400 comprises a differential tuning block 200 coupled to a first active device 151 and a second active device 151. The differential tuning block 200 comprises four inputs, dn_in +, dp_in + and dn_in-, dp_in-, and two outputs, ss + and s-. Power (vdd) and ground (gnd) are provided. Input signals in the form of current are inserted as l_in_n +, l_in_p- and l_in_n- and l_in_p- to node dn_in +, node dp_in + and node dn_in-, node dp_in- respectively. The tuning block 200, which can include all or some combination of passive, inductor, capacitor, resistor and transformer, but not limited to any of the following conditions: l_s +> (l_in_n +) + (l_in_p +) And l_s-> (l_in_n-) + (l_in_p-), receive l_in_n +, l_in_p + and l_in_n-, l_in_p- and treat them as output currents l_s + and l_s- at node S + and node S- respectively It has a function.

  [0055] In this embodiment, the current l_s from the tuning block 200 is provided to the source connection, S, of the active device +151. The common gate action of device 151+ causes current l_s to split, part of which is directed to dn as output current l_out_n and the other part is directed to dp as output current l_out_p. The gate gn and gate gp of the active device are coupled to the bias line. (Signal not applied to gn and gp). Bulk node bn and bulk node bp are also coupled to their respective bias lines.

  Similarly, in this embodiment, the current l_s from the tuning block 200 is provided to the source connection, S, of the active device 151−. The common gate action of device 151-causes current l_s to split, part of which is directed to dn as output current l_out_n and the other part is directed to dp as output current l_out_p. The gate gn and gate gp of the active device are coupled to the bias line. (Signal not applied to gn and gp). Bulk node bn and bulk node bp are also coupled to their respective bias lines.

  [0057] Any number of capacitors or variable capacitors may be coupled between the + and-nodes of the input of tuning block 200. Similarly, any number of capacitors or variable capacitors can be connected between the inputs to the inputs and outputs of active device + 151 and active device 151-output, gate, bulk + and-nodes. For example, mutual capacitors or variable capacitors may be coupled between dn + and dn−, between dp + and dp−, between dn− and dp +, between dn + and dp−, and / or any combination thereof It can be done. Also, these capacitors or variable capacitors can include series resistors or series inductances or parallel resistors or parallel inductors that do not affect or modify the present invention.

  [0058] FIG. 48 is a block diagram of a second embodiment of a differential common gate amplifier according to the present invention. Amplifier 400 comprises a differential tuning block 200 coupled to a first active device 151 and a second active device 151. The differential tuning block 200 comprises four inputs, dn_in +, dp_in + and dn_in-, dp_in-, and two outputs, ss + and s-. Power (vdd) and ground (gnd) are provided. Input signals in the form of current are inserted as l_in_n +, l_in_p- and l_in_n- and l_in_p- to node dn_in +, node dp_in + and node dn_in-, node dp_in- respectively. Power supply vdd on the left, and gnd on the right. The tuning block 200, which can include all or some combination of passive, inductor, capacitor, resistor and transformer, but not limited to any of the following conditions: l_s +> (l_in_n +) + (l_in_p +) And l_s-> (l_in_n-) + (l_in_p-), receive l_in_n +, l_in_p + and l_in_n-, l_in_p- and treat them as output currents l_s + and l_s- at node S + and node S- respectively It has a function.

  [0059] In this embodiment, the current l_s from the tuning block 200 is provided to the source connection, S, of the active device +151. The common gate action of device 151+ causes current l_s to split, part of which is directed to dn as output current l_out_n and the other part is directed to dp as output current l_out_p. The gate gn and gate gp of the active device are coupled to a bias line which forms a virtual ground between the positive and negative sides (signal differential signals are not applied to gn and gp). Bulk node bn and bulk node bp are also coupled to their respective bias lines.

  [0060] Similarly, in this embodiment, the current l_s from the tuning block 200 is provided to the source connection, S, of the active device 151-. The common gate action of the device 151-causes the current l_s to split up, part of which is directed to dn as the output current l_out_n and the other part to dp as the output current l_out_p. Are coupled to gate gn + to form a common bias voltage, vbias_n. Similarly, gp- and gp + are coupled together to form a virtual ground, which share a common bias voltage, bias_p. Bulk node bn- and bulk node bp- are also coupled to their respective bias lines.

  [0061] Any number of capacitors or variable capacitors may be coupled between the + and-nodes of the input and output of tuning block 200. Similarly, any number of capacitors or variable capacitors can be connected between the + and-nodes of the input and output, gate, bulk and source of active device + 151 and active device 151. For example, mutual capacitors or variable capacitors may be coupled between dn + and dn−, between dp + and dp−, between dn− and dp +, between dn + and dp−, or any combination thereof obtain. Also, these capacitors or variable capacitors can include series resistors or series inductances or parallel resistors or parallel inductors that do not affect or modify the present invention.

  [0062] FIG. 4C is a block diagram of an embodiment of a differential combination common gate and common source amplifier according to the present invention. Amplifier 400 comprises a differential tuning block 200 coupled to a first active device 151 and a second active device 151. The differential tuning block 200 comprises four inputs, n +, p + and n-, d-, and six outputs, S +, s-, gn +, gn-, gp +, gp-. Also, power supplies vdd and gnd are provided for the required biasing of the active devices feeding nodes dn +, dn−, dp + and dp−.

  [0063] The input signal is in the form of a current and is applied to node n +, node p + and node n-, node p- as l_in_n +, l_in_p- and l_in_n- and l_in_p- respectively. The tuning block 200, which can include all or some combination of passive devices such as, but not limited to, inductors, capacitors, resistors and transformers, has the following conditions: l_s +> (l_in_n +) + (l_in_p +) And l_s-> (l_in_n-) + (l_in_p-), receive l_in_n +, l_in_p + and l_in_n-, l_in_p- and treat them as output currents l_s + and l_s- at node S + and node S- respectively It has a function.

  [0064] The other four output nodes of tuning block 200 are positive n-type and p-type gates and negative of active device + 151 and active device 151, respectively, to form a differential common gate-common source amplifier. Connect to n-type and p-type gates.

  [0065] A current l_s + is provided to the active device + 151 source connection, S. The common gate action of this device causes the current l_s + to split, part of which is directed to dn + as the output current l_out_n +, and the other part to dp + as the output current l_out_p +. Gate gn + and gate gp− of active device 151 are coupled to the bias line. (Signal is not applied to gn + and gp +). Bulk node bn + and bulk node bp + are also coupled to their respective bias lines.

  [0066] Similarly, the current l_s- is in the source connection, S, of the active device-151. The common gating action of the active device 151 causes the current l_s- to split up, part of which is directed to dn- as the output current l_out_n- and the other part to dp- as the output current l_out_p-.

  [0067] Any number of capacitors or variable capacitors can be coupled between the + and-nodes of the input and output, gate and bulk and source of tuning block 200. Similarly, any number of capacitors or variable capacitors can be connected between the + and-nodes of the input and output of active device + 151 and active device 151. For example, mutual capacitors or variable capacitors may be connected between dn + and dn-, between dp + and dp-, between dn- and dp +, between dn + and dp- and any combination thereof Can. Also, these capacitors or variable capacitors can include series resistors or series inductances or parallel resistors or parallel inductors that do not affect or modify the present invention.

  [0068] FIG. 40 is a block diagram of an embodiment of a single ended voltage controlled oscillator (VCO) 400 according to the present invention. As shown, the active device 100 is coupled to the tuning block 200 in a feedback relationship directly through the source and through the drain.

  [0069] FIG. 4E is a block diagram of an embodiment of a differential VCO 400 'according to the present invention. As shown, the active device 151 is coupled to the tuning block 200 in a feedback relationship directly through the source and gate and through the drain.

  [0070] FIG. 4F is a block diagram of an embodiment of cascaded VCO 400 '' according to the present invention. FIG. 4F shows a cascade of common source tuning and active devices. However, common gate or common gate according to the present invention, Common sources or even mixing and matching of common sources may be implemented.

  [0071] FIG. 4G is a block diagram of an embodiment of a differential VCO 410, in accordance with the present invention. As shown, the active device 151 is coupled to the tuning block 200 in a feedback relationship directly through the source and through the drain. The effective loop feedback has a positive sign to ensure oscillation.

  [0072] FIG. 4H is a block diagram of an embodiment of a cascaded VCO 410 'according to the present invention. FIG. 4H shows a cascade of common gate tuning and active devices. However, common gates or common gates, common source or even common source mixing and matching according to the present invention may be implemented. Dotted lines mean that many of these blocks may be present.

  [0073] FIG. 4I is a block diagram of an embodiment of a cascaded VCO 420 according to the present invention. FIG. 4I shows a cascade of common gate tuning and active devices using common gate tuning and active devices. The dotted lines mean that there may be many combinations of common gate active and tuning devices, or common gate, common source active and tuning devices.

  [0074] FIG. 5 is a diagram of two differential active devices coupled to an inductive tuning block to form a VCO 500, in accordance with the present invention. FIG. 5 shows how to achieve a positive feedback loop with a gain greater than 1 and approaching a gain of 2 using passive inductance in combination with a common gate amplifier. Clusters 200 of inductors are coupled together. This satisfies the condition that the source current is greater than each drain current specified using the tuning block function. Although not shown, in the case of FIG. 5, the same polarity sources can be connected together, and the same polarity dn or dp can be connected to one another without altering their function. For example, the S + of each active device 151 can be connected together. Or, S- of each active device can be connected together.

  [0075] FIG. 6 is a diagram of three differential active devices coupled to an inductive tuning block to form a VCO 600, in accordance with the present invention. FIG. 6 shows how to use a passive inductance in combination with a common gate amplifier to achieve a positive feedback loop with a gain greater than 1 and approaching a gain of 3. Clusters 200 of inductors are coupled together. This satisfies the condition that the source current is greater than each drain current specified using the tuning block function. Although not shown, in the case of FIG. 6 the same polarity sources can be connected together, and the same polarity dn or dp can be connected to one another without altering their function. For example, the S + of each active device 151 can be connected together. Or, S- of each active device can be connected together.

  [0076] FIG. 7 is a diagram of four differential active devices coupled to an inductive tuning block in accordance with the present invention. FIG. 7 shows that the gain can be a gain approaching 4 more than 1 by this positive feedback. All grouped inductors in the dotted oval are coupled together. The same polarity source nodes of each active device can be connected together without modifying the present invention. Also, the same polarity dn and dp nodes of each active device can be connected together without modifying the present invention.

  [0077] FIG. 8 is a diagram illustrating where the drain current of two active devices is added before the loop in VCO 800, according to the present invention. In doing so, the drain currents of the two devices are added first, and the drain is coupled to the source in a positive feedback manner. Similarly, all or several similar polarity source nodes from each differential active device to another differential active device can be connected together without modifying the present invention.

  [0078] FIG. 9 is a diagram showing where a drain current is added before the loop in VCO 900 according to the present invention. In doing so, drain current is added first, and the three drains are coupled to the source in a positive feedback manner. Similarly, all or several similar polarity source nodes from each differential active device to another differential active device can be connected together without modifying the present invention.

  [0079] The systems and methods according to the present invention provide an amplifier circuit that can be combined with a transformer to obtain increased gain and positive feedback for voltage controlled oscillator (VCO) applications. The resulting device does not require buffers or memory, and thus is smaller in size and consumes less power than conventional VCOs.

  Although the present invention has been described according to the illustrated embodiments, those skilled in the art can easily recognize that there may be variations on the embodiments, and those variations are within the spirit and scope of the present invention. It will be done. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the present invention.

Claims (7)

A voltage controlled oscillator (VCO),
An active device, the active device further comprising an n-type transistor having a drain, a gate and a bulk, and a p-type transistor having a drain, a gate and a bulk, the n-type transistor and the p-type transistor being common Share the source,
The active device is coupled between a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, and between the drain of the n-type transistor and the drain of the p-type transistor. a second capacitor, further comprising a third capacitor coupled between the bulk of the bulk and p-type transistors of the n-type transistor, and the active device,
A tuning block coupled to the common source to form a common gate amplifier;
And at least one tuning element coupled to the active device in order to change the overall capacitance of the VCO, the VCO is a memoryless (memory less), to capture the even harmonic signal, at least Voltage controlled oscillator (VCO) comprising one tuning element.   Each of the first capacitor, the second capacitor and the third capacitor is coupled in series with a variable capacitor, a capacitor coupled in series with a resistor, a capacitor coupled in parallel with a resistor, and an inductor The VCO according to claim 1, comprising either a capacitor or a capacitor coupled in parallel with the inductor.   The VCO according to claim 1, wherein the at least tuning element comprises any of an inductor, a capacitor, a resistor, and a transformer, comprising two inputs and one output. A differential voltage controlled oscillator (VCO),
First active device and second active device, wherein each of the first active device and the second active device is an n-type transistor having a drain, a gate and a bulk, and a drain, a gate and a bulk Further comprising a p-type transistor having the n-type transistor and the p-type transistor share a common source, and each of the first active device and the second active device is connected to the gate of the n-type transistor a first capacitor coupled between the gate of the p-type transistor and a second capacitor coupled between the drain of the n-type transistor and the drain of the p-type transistor; further comprising a third capacitor coupled between the bulk of the bulk and p-type transistors, Coupled between the first active device and the second active device and the bulk of the n-type transistor of the first active device to the shared source of the second active device, and a fourth capacitor,
A fifth capacitor coupled between the bulk of the p-type transistor of the first active device and the common source of the second active device;
A sixth capacitor coupled between the bulk of the n-type transistor of the second active device and the shared source of the first active device;
A seventh capacitor coupled between the bulk of the p-type transistor of the second active device and the shared source of the first active device;
A tuning block coupled to the common source to form a common gate amplifier;
At least one first tuning device coupled between the drain of the n-type transistor of the first active device and the drain of the n-type transistor of the second active device;
At least one coupled between the source of the n-type transistor of the first active device and the source of the p-type transistor and the source of the n-type transistor of the second active device and the source of the p-type transistor A second tuning device,
At least one third tuning device coupled between the drain of the p-type transistor of the first active device and the drain of the p-type transistor of the second active device; A differential voltage controlled oscillator (VCO) comprising: at least one third tuning device, wherein the differential VCO is memoryless and captures even harmonic signals.   Each of the first capacitor, the second capacitor and the third capacitor is coupled in series with a variable capacitor, a capacitor coupled in series with a resistor, a capacitor coupled in parallel with a resistor, and an inductor 5. The differential VCO according to claim 4, comprising either a capacitor or a capacitor coupled in parallel with the inductor. 5. The method of claim 4, wherein each of the first tuning device , the second tuning device and the third tuning device comprises any of an inductor, a capacitor, a resistor, and a transformer, comprising two inputs and one output. Differential VCO described in. 5. The method of claim 4, wherein the first tuning device and the second tuning device are utilized for coarse tuning of the VCO, and the second tuning device is utilized for fine tuning of the VCO. Differential VCO described.

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