JP6530288B2 - Semiconductor device and test method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a test method of the semiconductor device.

  The following techniques are known as techniques for reducing the test time of semiconductor devices. For example, in Patent Document 1, a bypass line is selected based on a test control signal output from a test mode selection circuit, and the output side of the input buffer circuit and the input side of the output buffer circuit are connected by a bypass line. Thus, a test apparatus is described which is configured to directly evaluate the characteristics of the input buffer circuit and the output buffer circuit without passing through the internal circuit.

JP, 2006-337298, A

  In a semiconductor device including a memory circuit such as a flip flop or the like that updates data in synchronization with a clock signal as a component of the interface circuit, a plurality of data output terminals are connected to the data output terminal of the memory circuit. Data output from the memory circuit can be taken out from each of the data output external terminals, and by connecting a plurality of clock output external terminals to the clock input terminal of the memory circuit There is one configured to be able to extract a clock signal from each of the terminals.

  In the semiconductor device having such a configuration, a delay in update timing of data output from each of the plurality of data output external terminals with respect to the transition timing of the clock signal output from each of the plurality of clock output external terminals It is tested whether or not the output delay time is within the standard. The test of output delay time is performed, for example, as follows. First, the transition timing of the clock signal output from each of the plurality of clock output external terminals is measured for each terminal (first step). Next, the update timing of the data output from each of the plurality of data output external terminals is measured for each terminal (second step). Next, based on the values measured in the first step and the second step, the output delay time is calculated for each pair of the clock output external terminal and the data output external terminal, and the calculated value is standardized. It is determined whether the condition is satisfied (third step).

  Here, the transition timing of the clock signal measured in the first step and the second step and the update timing of data are measured using a search measurement technique such as binary search or shmoo. In the measurement of the transition timing of the clock signal by the search measurement method, the transition timing of the clock signal is searched while sequentially moving the search points on the time axis. Similarly, in the measurement of the data update timing by the search measurement method, the data update timing is searched while sequentially moving the search points on the time axis. Therefore, the measurement of the transition timing of the clock signal and the measurement of the update timing of the data by the search measurement method take a relatively long time. In addition, when the search measurement is performed for each of the plurality of data output external terminals and each of the plurality of clock output external terminals, the test time becomes enormous.

  In recent years, with the reduction in size of semiconductor devices, the proportion of the test cost of semiconductor devices is increasing, and shortening of test time is required. The present invention has been made in view of the above-described points, and an object of the present invention is to provide a semiconductor device and a test method of the semiconductor device capable of shortening a test time.

  A semiconductor device according to a first aspect of the present invention updates a stored data in synchronization with a clock signal input to a clock input terminal, and outputs the stored data from a data output terminal, and the data output terminal And a plurality of clock output external terminals connected to the plurality of data output external terminals connected to the clock input terminal and corresponding to the plurality of data output external terminals, and the plurality of data output terminals First delay means for delaying each of the data output from each of the predetermined data output external terminals among the external terminals, and delay by the first delay means of the plurality of clock output external terminals And second delay means for delaying the clock signal output from the specific clock output external terminal corresponding to the specific data output external terminal that is not connected.

  A semiconductor device according to a second aspect of the present invention updates a stored data in synchronization with a clock signal input to a clock input terminal, and outputs the stored data from a data output terminal, and the data output terminal A plurality of data output external terminals connected to the plurality of clock output external terminals connected to the clock input terminal and corresponding to the plurality of data output external terminals, and the plurality of data output externals A first delay means for delaying data output from a specific data output external terminal of the terminals, and an external for data output not delayed by the first delay means of the plurality of clock output external terminals And second delay means for delaying each of the clock signals output from each of the clock output external terminals corresponding to each of the terminals.

  According to a third aspect of the present invention, there is provided a semiconductor device comprising: a memory circuit for holding data inputted from a data input terminal in synchronization with a clock signal inputted to a clock input terminal; and data inputted to the memory circuit. A data generation circuit to be generated, an external terminal for data input that receives an external input of data input to the memory circuit, data generated by the data generation circuit, and an external input via the data input external terminal And a first selector selectively supplying the data to the data input terminal.

  A test method of a semiconductor device according to a fourth aspect of the present invention includes: a storage circuit that updates stored data in synchronization with a clock signal input to a clock input terminal and outputs the stored data from a data output terminal; Semiconductor device including: a plurality of data output external terminals connected to a data output terminal; and a plurality of clock output external terminals connected to the clock input terminal and corresponding to the plurality of data output external terminals A test method for updating data output from a specific data output external terminal among the plurality of data output external terminals, and the specific data among the plurality of clock output external terminals The transition timing of the clock signal output from the specific clock output external terminal corresponding to the output external terminal is the worst case The semiconductor device is configured such that the transition timing of the clock signal output from the specific clock output external terminal is acquired as a first measurement value, and the data output from the specific data output external terminal The clock signal output from each of a plurality of clock output terminals other than the specific clock output external terminal among the plurality of clock output external terminals is acquired as a second measured value of the update timing of It is determined whether or not the level is a predetermined level at a timing corresponding to the first measured value, and other than the specific data output external terminal among the plurality of data output external terminals. It is determined whether or not the value of the data output from each of the plurality of data output external terminals is a predetermined value at the timing corresponding to the second measured value. Including the Rukoto.

  According to the present invention, a semiconductor device and a test method of the semiconductor device capable of shortening the test time are provided.

It is a figure showing composition of a semiconductor device concerning a comparative example. 5 is a timing chart of data and clock signals in a semiconductor device according to a comparative example. It is a figure showing composition of a semiconductor device concerning an embodiment of the present invention. 5 is a timing chart of data and clock signals in the semiconductor device according to the embodiment of the present invention. It is a flowchart which shows the test method in the semiconductor device which concerns on embodiment of this invention. It is a figure showing composition of a semiconductor device concerning an embodiment of the present invention. It is a figure showing composition of a semiconductor device concerning an embodiment of the present invention. 5 is a timing chart of data and clock signals in the semiconductor device according to the embodiment of the present invention. It is a flowchart which shows the test method in the semiconductor device which concerns on embodiment of this invention. It is a figure showing composition of a semiconductor device concerning an embodiment of the present invention. It is a figure showing composition of a semiconductor device concerning an embodiment of the present invention.

[Comparative example]
FIG. 1 is a diagram showing the configuration of a semiconductor device 100X according to a comparative example. The semiconductor device 100X according to the comparative example is configured to include the flip flop 10 that configures the interface device. Data signals from other circuits (not shown) such as a CPU (Central Processing Unit) provided in the semiconductor device 100X are input to the data input terminal D of the flip flop 10 through an arbitrary logic circuit 21. Ru. A clock signal from a clock generation circuit (not shown) provided in the semiconductor device 100X is input to the clock input terminal C of the flip flop 10 via an arbitrary logic circuit 22. Flip-flop 10 holds data included in the data signal input to data input terminal D in synchronization with the clock signal input to clock input terminal C, and outputs the held data from data output terminal Q Do. That is, the flip-flop 10 updates the data output from the data output terminal in synchronization with the clock signal input to the clock input terminal C.

  The data output terminal Q of the flip flop 10 is connected to data output external terminals 30A, 30B, 30C, 30D and 30E. Data output from the data output terminal Q of the flip flop 10 can be taken out of the semiconductor device 100X from the data output external terminals 30A, 30B, 30C, 30D, and 30E. Arbitrary logic circuits 23 may be provided between the data output external terminals 30A, 30B, 30C, 30D, and 30E and the data output terminal Q of the flip flop 10, respectively.

  The clock output external terminals 31A, 31B, 31C, 31D and 31E are connected to the clock input terminal C of the flip flop 10. The clock signal input to the clock input terminal C of the flip flop 10 can be taken out of the semiconductor device 100X from the clock output external terminals 31A, 31B, 31C, 31D and 31E. Arbitrary logic circuits 24 may be provided between the clock output external terminals 31 A, 31 B, 31 C, 31 D and 31 E and the clock input terminal C of the flip flop 10 respectively.

  FIG. 2 is a timing chart of data and clock signals output from the data output external terminals 30A to 30E and the clock output external terminals 31A to 31E, respectively. Here, the data output external terminal 30A and the clock output external terminal 31A form a pair, the data output external terminal 30B and the clock output external terminal 31B form a pair, and the data output external terminal 30C and the clock output In which the data output external terminal 30D and the clock output external terminal 31D form a pair and the data output external terminal 30E and the clock output external terminal 31E form a pair I assume. The clock signals output from the clock output external terminals 31A, 31B, 31C, 31D and 31E are denoted as clk_A, clk_B, clk_C, clk_D and clk_E, respectively, and the data output external terminals 30A, 30B, 30C. , 30D and 30E are respectively denoted as data_A, data_B, data_C, data_D and data_E.

  In the test of the semiconductor device 100X, the update timing delay of the data data_A, data_B, data_C, data_D, and data_E with respect to the transition timing of the clock signals clk_A, clk_B, clk_C, clk_D, and clk_E (for example, timing at which a rising edge occurs) The output delay time Td is measured, and it is determined whether the measured output delay time Td is within the standard. The output delay time Td is measured between data output from the paired data output external terminal and the clock output external terminal and the clock signal. As shown in FIG. 2, the transition timings of the clock signals are different among the clock signals clk_A to clk_E. Similarly, data update timings differ among the data data_A to data_E.

  The test of the output delay time Td is performed, for example, as follows. First, the clock signals clk_A, clk_B, clk_C, clk_D and clk_E outputted from the clock output external terminals 31A, 31B, 31C and 31E, respectively, are measured by a search measurement method such as binary search or shmoo (first example) Step). Next, measure the data data_A, data_B, data_C, data_D and data_E outputted from the data output external terminals 30A, 30B, 30C, 30D and 30E, respectively, by a search measurement method such as binary search or shmoo (second step ). Next, based on the values measured in the first step and the second step, the output delay time Td is calculated for each pair of the clock output external terminal and the data output external terminal, and the output delay time Td is It is determined whether the standard is satisfied (third step).

  In the measurement of the transition timing of the clock signal by the search measurement method, the transition timing of the clock signal is searched while sequentially moving the search points on the time axis. Similarly, in the measurement of the data update timing by the search measurement method, the data update timing is searched while sequentially moving the search points on the time axis. Therefore, the measurement of the transition timing of the clock signal and the measurement of the update timing of the data by the search measurement method take a relatively long time. In addition, when measurement is performed on each of the data output external terminals 30A to 30E and each of the clock output external terminals 31A to 31E, the test time becomes enormous.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding components and portions are denoted by the same reference numerals. The same or corresponding components as or to the components of the semiconductor device 100X according to the comparative example are given the same reference numerals as the reference numerals attached to the components of the semiconductor device 100X.

First Embodiment
FIG. 3 is a diagram showing the configuration of the semiconductor device 100 according to the embodiment of the present invention. The semiconductor device 100 has a configuration where the lower limit standard is defined for the output delay time Td. That is, the output delay time Td is required to be larger than the lower limit standard.

  The semiconductor device 100 is configured to include a flip flop 10 that constitutes an interface device. Data signals from other circuits (not shown) such as a CPU (Central Processing Unit) provided in the semiconductor device 100 are input to the data input terminal D of the flip flop 10 through an arbitrary logic circuit 21. Ru. A clock signal from a clock generation circuit (not shown) is input to a clock input terminal C of the flip flop 10 via an arbitrary logic circuit 22. Flip-flop 10 holds data included in the data signal input to data input terminal D in synchronization with the clock signal input to clock input terminal C, and outputs the held data from data output terminal Q Do. That is, the flip-flop 10 updates the data output from the data output terminal in synchronization with the clock signal input to the clock input terminal C.

  The data output terminal Q of the flip flop 10 is connected to data output external terminals 30A, 30B, 30C, 30D and 30E. Data output from the data output terminal Q of the flip flop 10 can be taken out of the semiconductor device 100 from the data output external terminals 30A, 30B, 30C, 30D, and 30E. Arbitrary logic circuits 23 may be provided between the data output external terminals 30A, 30B, 30C, 30D, and 30E and the data output terminal Q of the flip flop 10, respectively.

  The clock output external terminals 31A, 31B, 31C, 31D and 31E are connected to the clock input terminal C of the flip flop 10. The clock signal input to the clock input terminal C of the flip flop 10 can be taken out of the semiconductor device 100 from the clock output external terminals 31A, 31B, 31C, 31D and 31E. Arbitrary logic circuits 24 may be provided between the clock output external terminals 31 A, 31 B, 31 C, 31 D and 31 E and the clock input terminal C of the flip flop 10 respectively.

  In the semiconductor device 100, delay elements 40 are provided between the data output external terminals 30B, 30C, 30D and 30E and the data output terminal Q of the flip flop 10, respectively. On the other hand, no delay element is provided between the data output external terminal 30A and the data output terminal Q of the flip flop 10. That is, data output from the data output terminal Q of the flip flop 10 is given a delay time by the delay element 40 and output as data data_B to data_E from the data output external terminals 30B to 30E. On the other hand, the data output from the data output terminal Q of the flip flop 10 is output as data data_A from the data output external terminal 30A without delay time being applied.

  In the semiconductor device 100, a delay element 41 is provided between the clock output external terminal 31A and the clock input terminal C of the flip flop 10. On the other hand, no delay element is provided between the clock output external terminals 31 B to 31 E and the clock input terminal C of the flip flop 10. That is, a delay time is given by the delay element 41 and the clock signal input to the clock input terminal C of the flip flop 10 is output as the clock signal clk_A from the clock output external terminal 31A. On the other hand, the clock signal input to the clock input terminal C of the flip flop 10 is output as the clock signals clk_B to clk_E from the clock output external terminals 31B to 31E without delay time being applied.

  FIG. 4 is a timing chart of data data_A to data_E output from the data output external terminals 30A to 30E and clock signals clk_A to clk_E output from the clock output external terminals 31A to 31E, respectively. Here, the data output external terminal 30A and the clock output external terminal 31A form a pair, the data output external terminal 30B and the clock output external terminal 31B form a pair, and the data output external terminal 30C and the clock output In which the data output external terminal 30D and the clock output external terminal 31D form a pair and the data output external terminal 30E and the clock output external terminal 31E form a pair I assume.

  According to the configuration of the semiconductor device 100 according to the present embodiment, the update timing of the data data_A output from the data output external terminal 30A is the same as that of the data data_B to data_E output from the other data output external terminals 30B to 30E. Since it precedes the update timing, the output delay time Td is the worst case under the condition where the lower limit standard is defined. Further, the transition timing of the clock signal clk_A output from the clock output external terminal 31A is delayed from the transition timing of the clock signals clk_B to clk_E output from the other clock output external terminals 31B to 31E, so the output delay time This is the worst case under the condition where the lower limit standard is defined in Td. That is, in the semiconductor device 100 according to the present embodiment, by providing the delay elements 40 and 41, the data data_A output from the data output external terminal 30A and the clock signal clk_A output from the clock output external terminal 31A. Pair is the worst case with respect to the output delay time Td for which the lower limit standard is defined.

  FIG. 5 is a flowchart showing an example of a test method of the output delay time Td of the semiconductor device 100.

  In step S1, the transition timing of the clock signal clk_A output from the clock output external terminal 31A corresponding to the worst case is acquired as a first measurement value M1. The transition timing of the clock signal clk_A is measured by a search measurement method such as binary search or shmoo. The first measurement value M1 is a time width from a predetermined reference time to a transition time of the clock signal clk_A.

  In step S2, the update timing of the data data_A output from the data output external terminal 30A corresponding to the worst case is acquired as a second measurement value M2. The update timing of the data data_A is measured by a search measurement method such as binary search or shmoo. The second measurement value M2 is a time width from the predetermined reference time to the update time of the data data_A.

  In step S3, based on the first measurement value M1 and the second measurement value M2, the output delay time Td_worst for the pair consisting of the data data_A corresponding to the worst case and the clock signal clk_A is calculated. Specifically, the output delay time Td_worst can be obtained by subtracting the first measurement value M1 from the second measurement value M2.

  In step S4, it is determined whether the calculated output delay time Td_worst is larger than the lower limit standard Td_l for the output delay time. If the output delay time Td_worst is smaller than the lower limit standard Td_l, it is judged as a fail. If the output delay time Td_worst is larger than the lower limit standard Td_1 for the output delay time, the process proceeds to the next step S5.

  In step S5, it is determined whether the clock signals clk_B to clk_E have already shifted to the high level at the timing corresponding to the first measurement value M1 corresponding to the worst case. If it is determined that one of the clock signals clk_B to clk_E has not transitioned to the high level at the timing corresponding to the first measurement value M1, a fail determination is made. If the clock signals clk_B to clk_E transition to the high level at the timing corresponding to the first measurement value M1, the process proceeds to the next step S6.

  In step S6, it is determined whether the values of the data data_B to data_E are still values before data update at the timing corresponding to the second measurement value M2 corresponding to the worst case. If it is determined that the values of the data data_B to data_E are not values before the data update at the timing corresponding to the second measurement value M2, a fail determination is made. If all the determinations in steps S4 to S6 are positive, the output delay time Td of the semiconductor device 100 is a path determination.

  As described above, according to the semiconductor device 100 according to this embodiment, only the transition timing of the clock signal clk_A corresponding to the worst case and the update timing of the data data_A are measured using the search measurement method. Then, with respect to transition timings of the clock signals clk_B to clk_E other than the worst case, whether or not the levels of the clock signals clk_B to clk_E are high level at the timing indicated by the first measurement value M1 corresponding to the worst case. Good or bad judgment is made by a so-called function test which judges. Similarly, with respect to the update timing of the data data_B to data_E other than the worst case, whether or not the values of the data data_B to data_E are values before the update at the timing indicated by the second measurement value M2 corresponding to the worst case Good or bad judgment is made by a so-called function test which judges.

  Thus, in the test of output delay time Td, measurement using the search measurement method is limited to the specific data and clock signal which is the worst case, and the remaining data and clock signal are measured in the worst case. By performing the used function test, the test time can be significantly reduced.

  The flip flop 10 is an example of the memory circuit in the present invention. The data output external terminals 30A to 30E are examples of data output external terminals in the present invention. The clock output external terminals 31A to 31E are examples of clock output external terminals in the present invention. The delay element 40 is an example of the first delay means and the first delay element in the present invention. The delay element 41 is an example of the second delay means and the second delay element in the present invention.

Second Embodiment
FIG. 6 is a view showing the configuration of a semiconductor device 100A according to the second embodiment of the present invention. In the semiconductor device 100A, the bypass wire 42 provided between the clock input terminal C of the flip flop 10 and the clock output external terminal 31A, the input end of the delay element 41 and one end of the bypass wire 42 are selectively flipped 10 further includes a switch 43 connected to the clock input terminal C of 10, and a switch 44 selectively connecting the output end of the delay element 41 and the other end of the bypass wire 42 to the clock output external terminal 31A. This differs from the semiconductor device 100 according to the first embodiment.

  The switches 43 and 44 are connected to the delay element 41 when testing the output delay time Td of the semiconductor device 100A. That is, at the time of testing the output delay time Td of the semiconductor device 100A, the clock signal is output from the clock output external terminal 31A via the delay element 41. On the other hand, the switches 43 and 44 are connected to the bypass wiring 42 in the normal operation of the semiconductor device 100A. That is, in the normal operation of the semiconductor device 100A, the clock signal is output from the clock output external terminal 31A via the bypass wiring 42 bypassing the delay element 41.

  The delay element 41 is provided to make the transition timing of the clock signal clk_A output from the clock output external terminal 31A the worst case in the test of the output delay time Td, and is not necessary in the normal operation. is there. According to the semiconductor device 100A according to the present embodiment, it is possible to output the clock signal from the clock output external terminal 31A via the bypass wiring 42 bypassing the delay element 41 in the normal operation.

  The bypass wiring 42 is an example of the bypass wiring in the present invention. The switches 43 and 44 are an example of switches in the present invention.

Third Embodiment
FIG. 7 is a view showing the configuration of a semiconductor device 100B according to the third embodiment of the present invention. The semiconductor device 100B has a configuration in which the upper limit standard is defined for the output delay time Td. That is, the output delay time Td is required to be smaller than the upper limit standard.

  In the semiconductor device 100B, a delay element 40 is provided between the data output external terminal 30A and the data output terminal Q of the flip flop 10. On the other hand, no delay element is provided between the data output external terminals 30 B to 30 E and the data output terminal Q of the flip flop 10. That is, data output from the data output terminal Q of the flip flop 10 is given a delay time by the delay element 40 and output as data data_A from the data output external terminal 30A. On the other hand, the data output from the data output terminal Q of the flip flop 10 is output as data data_B to data_E from the data output external terminals 30B to 30E, respectively, without delay time being applied.

  In the semiconductor device 100B, delay elements 41 are provided between the clock output external terminals 31B to 31E and the clock input terminal C of the flip flop 10, respectively. On the other hand, the delay element 41 is not provided between the clock output external terminal 31A and the clock input terminal C of the flip flop 10. That is, the delay time is given by the delay element 41 and the clock signal is output as the clock signals clk_B to clk_E from the clock output external terminals 31B to 31E. On the other hand, the clock signal is output as the clock signal clk_A from the clock output external terminal 31A without delay time being applied.

  FIG. 8 is a timing chart of data data_A to data_E output from the data output external terminals 30A to 30E and clock signals clk_A to clk_E output from the clock output external terminals 31A to 31E, respectively.

  According to the configuration of the semiconductor device 100B according to the present embodiment, the update timing of the data data_A output from the data output external terminal 30A is the same as that of the data data_B to data_E output from the other data output external terminals 30B to 30E. Since it is delayed from the update timing, the output delay time Td is the worst case under the condition where the upper limit standard is defined. In addition, the transition timing of the clock signal clk_A output from the clock output external terminal 31A precedes the transition timing of the clock signals clk_B to clk_E output from the other clock output external terminals 31B to 31E, so the output Under the situation where the upper limit standard is defined in the delay time Td, it is the worst case. That is, in the semiconductor device 100B according to the present embodiment, by providing the delay elements 40 and 41, the data data_A output from the data output external terminal 30A and the clock signal clk_A output from the clock output external terminal 31A. Pair is the worst case with respect to the output delay time Td for which the upper limit standard is defined.

  FIG. 9 is a flowchart showing an example of a test method of the output delay time Td of the semiconductor device 100B.

  In step S11, the transition timing of the clock signal clk_A output from the clock output external terminal 31A corresponding to the worst case is acquired as the first measurement value M1. The transition timing of the clock signal clk_A is measured by a search measurement method such as binary search or shmoo. The first measurement value M1 is a time width from a predetermined reference time to a transition time of the clock signal clk_A.

  In step S12, the update timing of the data data_A output from the data output external terminal 30A corresponding to the worst case is acquired as the second measurement value M2. The update timing of the data data_A is measured by a search measurement method such as binary search or shmoo. The second measurement value M2 is a time width from the predetermined reference time to the update time of the data data_A.

  In step S13, based on the first measurement value M1 and the second measurement value M2, the output delay time Td_worst for the pair consisting of the data data_A corresponding to the worst case and the clock signal clk_A is calculated. Specifically, the output delay time Td_worst can be obtained by subtracting the first measurement value M1 from the second measurement value M2.

  In step S14, it is determined whether the calculated output delay time Td_worst is smaller than the upper limit standard Td_u for the output delay time. If the output delay time Td_worst is larger than the upper limit standard Td_u, it is judged as a fail. If the output delay time Td_worst is smaller than the upper limit standard Td_u for the output delay time, the process proceeds to the next step S15.

  In step S15, it is determined whether the clock signals clk_B to clk_E are still at the low level at the timing corresponding to the first measurement value M1 corresponding to the worst case. If it is determined that any of the clock signals clk_B to clk_E does not maintain the low level at the timing corresponding to the first measurement value M1, a fail determination is made. When the clock signals clk_B to clk_E maintain the low level at the timing corresponding to the first measurement value M1, the process proceeds to the next step S16.

  In step S16, it is determined whether the values of the data data_B to data_E are values after data update at the timing corresponding to the second measurement value M2 corresponding to the worst case. If it is determined that the values of the data data_B to data_E are not values after data update at the timing corresponding to the second measurement value M2, a fail determination is made. If all the determinations in steps S14 to S16 are positive, the path determination is performed for the output delay time Td of the semiconductor device 100B.

  As described above, according to the semiconductor device 100B according to the present embodiment, only the transition timing of the clock signal clk_A corresponding to the worst case and the update timing of the data data_A are measured using the search measurement method. Then, with respect to transition timings of the clock signals clk_B to clk_E other than the worst case, whether or not the clock signals clk_B to clk_E still maintain the low level at the timing indicated by the first measurement value M1 corresponding to the worst case. Good or bad judgment is made by a so-called function test which judges. Similarly, with respect to the update timing of the data data_B to data_E other than the worst case, whether or not the values of the data data_B to data_E are values after the update at the timing indicated by the second measurement value M2 corresponding to the worst case Good or bad judgment is made by a so-called function test which judges.

  Thus, in the test of output delay time Td, measurement using the search measurement method is limited to the specific data and clock signal which is the worst case, and the remaining data and clock signal are measured in the worst case. By performing the used function test, the test time can be significantly reduced.

  The flip flop 10 is an example of the memory circuit in the present invention. The data output external terminals 30A to 30E are examples of data output external terminals in the present invention. The clock output external terminals 31A to 31E are examples of clock output external terminals in the present invention. The delay element 40 is an example of the first delay means and the first delay element in the present invention. The delay element 41 is an example of the second delay means and the second delay element in the present invention.

Fourth Embodiment
FIG. 10 is a view showing the configuration of a semiconductor device 100C according to the fourth embodiment of the present invention. In the semiconductor device 100C, the bypass wire 45 provided between the data output terminal Q of the flip flop 10 and the data output external terminal 30A, the input end of the delay element 40 and one end of the bypass wire 45 are selectively flipped 10 in that it further includes a switch 46 connected to the data output terminal Q of 10, and a switch 47 selectively connecting the output end of the delay element 40 and the other end of the bypass wire 45 to the data output external terminal 30A. It differs from the semiconductor device 100B according to the third embodiment.

  The switches 46 and 47 are connected to the delay element 40 when testing the output delay time Td of the semiconductor device 100C. That is, at the time of testing the output delay time Td of the semiconductor device 100C, data output from the data output terminal Q of the flip flop 10 is output from the data output external terminal 30A via the delay element 40. On the other hand, the switches 46 and 47 are connected to the bypass wiring 45 side in the normal operation of the semiconductor device 100C. That is, during the normal operation of the semiconductor device 100C, data output from the data output terminal Q of the flip flop 10 is output from the data output external terminal 30A via the bypass wiring 45 bypassing the delay element 40.

  The delay element 40 is provided to make the update timing of the data data_A output from the data output external terminal 30A worst case in the test of the output delay time Td, and is not necessary in the normal operation. . According to the semiconductor device 100C according to the present embodiment, during normal operation, data can be output from the data output external terminal 30A via the bypass wiring 45 bypassing the delay element 40.

  The bypass wiring 45 is an example of the bypass wiring in the present invention. The switches 46 and 47 are an example of switches in the present invention.

  In the semiconductor devices according to the first to fourth embodiments described above, the delay elements 40 and 41 are used to make the transition timing of the clock signal clk_A and the update timing of the data data_A the worst case. It is not limited. For example, the worst case may be created by elements other than delay elements, layout, wiring lengths and timing designs.

Fifth Embodiment
FIG. 11 is a view showing the configuration of a semiconductor device 100D according to the fifth embodiment of the present invention. The semiconductor device 100D includes a first selector 51, a second selector 52, a test data input external terminal 61, a selector control external terminal 62, a test clock input external terminal 63, a CPU 70, and a clock generation circuit 71.

  The CPU 70 is connected to the input terminal J of the first selector 51 via an arbitrary logic circuit 21. The test data input external terminal 61 is connected to the input terminal K of the first selector 51. The clock generation circuit 71 is connected to the input terminal U of the second selector 52 via an arbitrary logic circuit 22. The test clock input external terminal 63 is connected to the input terminal V of the second selector 52. The selector control external terminal 62 is connected to the control terminal M of the first selector 51 and the control terminal X of the second selector 52. The output terminal L of the first selector 51 is connected to the data input terminal D of the flip flop 10. The output terminal W of the second selector 52 is connected to the clock input terminal C of the flip flop 10, and is connected to the clock output external terminals 31A to 31E through an arbitrary logic circuit 24.

  The CPU 70 generates a data signal to be supplied to the flip flop 10. The clock generation circuit 71 generates a clock signal to be supplied to the flip flop 10. The first selector 51 receives either the signal input to the input terminal J or the signal input to the input terminal K based on the selector control signal sel input to the control terminal M via the selector control external terminal 62. One or the other is selected and output to the output terminal L. Similarly, the second selector 52 is input to the signal input to the input terminal U and to the input terminal V based on the selector control signal sel input to the control terminal X via the selector control external terminal 62. One of the signals is selected and output to the output terminal W.

  The test data input external terminal 61 receives an input of test data data_T used to test the output delay time Td from the outside of the semiconductor device 100D. The test clock input external terminal 63 receives an input of the test clock signal clk_T used for testing the output delay time Td from the outside of the semiconductor device 100D. The selector control external terminal 62 receives an input of a selector control signal sel that controls selection operation in the first selector 51 and the second selector 52 from the outside of the semiconductor device 100D.

  In the normal operation of the semiconductor device 100D, the first selector 51 selects the data signal from the CPU 70 input to the input terminal J based on the selector control signal sel input to the control terminal M, This signal is supplied to the data input terminal D of the channel 10. Further, in the normal operation of the semiconductor device 100D, the second selector 52 selects the clock signal from the clock generation circuit 71 input to the input terminal U based on the selector control signal sel input to the control terminal X. To the clock input terminal C of the flip flop 10.

  On the other hand, at the time of the test of the output delay time Td, the first selector 51 is supplied from the outside of the semiconductor device 100D through the test data input external terminal 61 based on the selector control signal sel input to the control terminal M. To select the test data data_T to be input to the input terminal K, and supply it to the data input terminal D of the flip flop 10. Further, at the time of the test of the output delay time Td, the second selector 52 is supplied from the outside of the semiconductor device 100D through the test clock input external terminal 63 based on the selector control signal sel input to the control terminal X. , And selects the test clock signal clk_T input to the input terminal V and supplies it to the clock input terminal C of the flip flop 10.

  As described above, in the normal operation, the semiconductor device 100D operates based on the data signal supplied from the internal CPU 70 and the clock signal supplied from the internal clock generation circuit 71. On the other hand, when testing the output delay time Td, the semiconductor device 100D performs a test using test data data_T and a test clock signal clk_T supplied from the outside of the semiconductor device 100D. As described above, by providing a test path for external input separately from the signal path in the normal operation, it is possible to reduce the test time.

  If the test path is not provided by the external input, the CPU 70 creates test data (test pattern). However, since it takes a certain amount of time to create the test data, the test time becomes long. Moreover, since the transmission rate of test data is limited by the ability of the CPU 70, it is difficult to shorten the test time.

  On the other hand, according to the semiconductor device 100D, since there is a test path for external input, it is possible to test the semiconductor device 100D using test data data_T stored in advance in an external tester. Therefore, the test time can be reduced as compared with the case where the CPU 70 creates test data. Further, since the transmission rate of the test data data_T does not depend on the capability of the CPU 70, the test time can be easily shortened.

  The first selector 51 is an example of the first selector in the present invention. The second selector 52 is an example of a second selector in the present invention. The CPU 70 is an example of a data generation circuit in the present invention. The clock generation circuit 71 is an example of the clock generation circuit in the present invention. The test data input external terminal 61 is an example of the data input external terminal in the present invention. The test clock input external terminal 63 is an example of the clock input external terminal in the present invention.

10 flip flops 30A, 30B, 30C, 30D, 30E data output external terminals 31A, 31B, 31C, 31D, 31E clock output external terminals 40, 41 delay elements 42, 45 bypass wires 43, 44, 46, 47 switches 51 First selector 52 Second selector 61 Test data input external terminal 62 Selector control external terminal 63 Test clock input external terminal 70 CPU
71 Clock generation circuit D Data input terminal C Clock input terminal Q Data output terminal

Claims (9)

A storage circuit that updates stored data in synchronization with a clock signal input to a clock input terminal and outputs the stored data from the data output terminal;
A plurality of data output external terminals connected to the data output terminal;
A plurality of clock output external terminals connected to the clock input terminal and corresponding to each of the plurality of data output external terminals;
First delay means for delaying each of the data output from each of the predetermined data output external terminals among the plurality of data output external terminals;
A second delay for delaying a clock signal output from a specific clock output external terminal corresponding to a specific data output external terminal not delayed by the first delay means among the plurality of clock output external terminals Means,
Semiconductor devices. The first delay means is configured to transmit each of data output from each of a plurality of data output external terminals other than the specific data output external terminal among the plurality of data output external terminals. Delay the data output from the specific data output external terminal,
The second delay means is configured to output a clock signal output from the specific clock output external terminal to a plurality of clocks other than the specific clock output external terminal among the plurality of clock output external terminals. The semiconductor device according to claim 1, wherein each of the clock signals output from each of the output external terminals is delayed. The first delay means is disposed between each of the plurality of data output external terminals other than the specific data output external terminal among the plurality of data output external terminals and the data output terminal. Including a first delay element provided;
The semiconductor device according to claim 2, wherein the second delay means includes a second delay element provided between the specific clock output external terminal and the clock input terminal. A bypass line provided between the clock input terminal and the specific clock output external terminal;
A path from the clock signal to the specific clock output external terminal via the second delay element, and a path from the clock signal to the specific clock output external terminal via the bypass line , Switches, and
The semiconductor device according to claim 3, further comprising A storage circuit that updates stored data in synchronization with a clock signal input to a clock input terminal and outputs the stored data from the data output terminal;
A plurality of data output external terminals connected to the data output terminal;
A plurality of clock output external terminals connected to the clock input terminal and corresponding to each of the plurality of data output external terminals;
First delay means for delaying data output from a specific data output external terminal among the plurality of data output external terminals;
A second delaying each of the clock signals output from each of the clock output external terminals corresponding to each of the data output external terminals not delayed by the first delay means among the plurality of clock output external terminals Delay means, and
Semiconductor devices. The first delay means outputs data from the specific data output external terminal, and outputs a plurality of data other than the specific data output external terminal among the plurality of data output external terminals. Delay each of the data output from each of the
The second delay means includes a plurality of clock output external terminals other than the specific clock output external terminal corresponding to the specific data output external terminal among the plurality of clock output external terminals. The semiconductor device according to claim 5, wherein each of the clock signals output from the delay circuit is delayed with respect to the clock signal output from the specific clock output external terminal. The first delay means includes a first delay element provided between the specific data output external terminal and the data output terminal.
The second delay means is provided between each of a plurality of clock output external terminals other than the specific clock output external terminal among the plurality of clock output external terminals and the clock input terminal. The semiconductor device according to claim 6, further comprising a second delay element provided. A bypass line provided between the data output terminal and the specific data output external terminal;
A path from the data to the specific data output external terminal via the first delay element, and a path from the data to the specific data output external terminal via the bypass wiring; Switch to switch,
The semiconductor device according to claim 7, further comprising A storage circuit that updates stored data in synchronization with a clock signal input to a clock input terminal and outputs the stored data from the data output terminal; and a plurality of data output external terminals connected to the data output terminal; A test method of a semiconductor device including: a plurality of clock output external terminals connected to the clock input terminal and corresponding to each of the plurality of data output external terminals;
It corresponds to the update timing of the data output from the specific data output external terminal among the plurality of data output external terminals, and the specific data output external terminal among the plurality of clock output external terminals. The semiconductor device is configured such that transition timings of clock signals output from specific clock output external terminals are respectively in the worst case;
The transition timing of the clock signal output from the specific clock output external terminal is acquired as a first measurement value,
The update timing of the data output from the specific data output external terminal is acquired as a second measurement value,
The level of the clock signal output from each of a plurality of other clock output terminals other than the specific clock output external terminal among the plurality of clock output external terminals corresponds to the first measurement value It is determined whether or not the timing is a predetermined level,
Values of data output from each of a plurality of data output external terminals other than the specific data output external terminal among the plurality of data output external terminals correspond to the second measured value. A test method that determines whether or not the timing is a predetermined value.

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