JP6527194B2 - Display device - Google Patents

Description

The present technology relates to a display device .

  Patent Document 1 discloses a display device which drives each LED (Light Emitting Diode) provided at an intersection of a signal line and a scanning line by turning on and off signal lines and scanning lines arranged in a lattice. ing. In this driving method, since image display is performed by sequential scanning of the scanning lines, it is not easy to increase the display luminance. Therefore, for example, as described in Patent Document 2, it is conceivable to provide an LED and a drive IC for each pixel and to actively drive each LED.

JP, 2009-37164, A Japanese Patent Application Publication No. 2003-115613

  In the method described in Patent Document 2, it is necessary to provide many wirings connected to the drive IC on the surface (mounting surface) of the wiring layer on the wiring substrate, so the wiring pitch on the mounting surface becomes narrow. However, since the wiring substrate is a laminated substrate using via bonding, it is not easy to narrow the wiring pitch of the wiring substrate according to the wiring pitch of the mounting surface from the technical side or the cost side. Therefore, when the wiring pitch of the mounting surface and the wiring pitch of the wiring substrate are separated, for example, the wiring layer is formed in multiple layers, and the wiring having an intermediate value between the wiring pitch of the mounting surface and the wiring pitch of the wiring substrate It is conceivable to provide a layer of pitch. However, in such a case, the cost increases as the number of wiring layers is increased.

  Such a problem may occur not only in the field of display devices, but also in fields where the wiring pitch of the wiring substrate and the wiring pitch of the wiring layer on the wiring substrate are different.

The present technology has been made in view of such problems, and an object thereof is to provide a display device capable of narrowing the wiring pitch on the mounting surface without forming the wiring layers on the wiring substrate in multiple layers. is there.

The display device of the present technology includes a plurality of unit substrates. Each unit substrate is connected to a wiring substrate including a plurality of first wires and a plurality of vias , a plurality of second wires provided on the wiring substrate, and a plurality of second wires, and a light emitting element and a light emitting element And a plurality of pixels including a driving IC to be driven . A plurality of vias electrically connects a plurality of first wirings and the plurality of second wires. A plurality of pixels, through one or more second wires, are connected to one common multiple vias. The L / S of the plurality of second wires is smaller than the L / S of the plurality of first wires.

It is a figure showing an example of the perspective view composition of the display concerning a 1st embodiment of this art. It is a figure showing an example of the perspective view structure of the mounted substrate of FIG. It is a figure showing an example of the perspective view structure of the unit substrate of FIG. It is a figure showing an example of the circuit structure in the cell of FIG. It is a figure showing an example of the planar structure of the light emitting element of FIG. FIG. 5 is a diagram illustrating an example of a planar configuration of a drive IC of FIG. 4. It is a figure showing an example of the cross-sectional structure of the cell of FIG. It is a figure showing an example of the wiring layout of the cell of FIG. It is a figure showing an example of the manufacturing method of the cell of FIG. It is a figure showing an example of the process of following FIG. It is a figure showing an example of the process of following FIG. It is a figure showing an example of the process of following FIG. It is a figure showing an example of the process of following FIG. FIG. 14 is a diagram illustrating a modification of the wiring layout of the cell of FIG. 3; It is a figure showing an example of the perspective view composition of the lighting installation concerning a 2nd embodiment of this art. It is a figure showing an example of the perspective view composition of the light sensing device concerning a 3rd embodiment of this art. It is a figure showing one modification of the perspective view composition of the display of FIG. It is a figure showing one modification of the perspective view structure of the illuminating device of FIG. It is a figure showing one modification of the perspective view structure of the light-receiving device of FIG.

Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. The description will be made in the following order.

1. First Embodiment (Display Device)
2. Modified example (display device)
3. Second Embodiment (Lighting Device)
4. Modified example (lighting device)
5. Third embodiment (light receiving device)
6. Modification common to each embodiment

<1. First embodiment>
[Constitution]
FIG. 1 illustrates an example of a perspective configuration of a display device 1 according to a first embodiment of the present technology. The display device 1 is a so-called LED display, and an LED is used as a display pixel. For example, as shown in FIG. 1, the display device 1 includes a display panel 10 and a control circuit 20 that controls the display panel 10 (specifically, a cell 10E described later).

(Display panel 10)
The display panel 10 is a combination of the mounting substrate 10A and the counter substrate 10B. The surface of the opposing substrate 10B is an image display surface, and has a display area in the center portion, and a frame area which is a non-display area around the display area. The opposing substrate 10B is disposed, for example, at a position facing the mounting substrate 10A via a predetermined gap. The counter substrate 10B may be in contact with the upper surface of the mounting substrate 10A. The opposing substrate 10B includes, for example, a light transmitting substrate that transmits visible light, and includes, for example, a glass substrate, a transparent resin substrate, or a transparent resin film.

(Mounting substrate 10A)
FIG. 2 shows an example of a perspective view of the mounting substrate 10A. For example, as shown in FIG. 2, the mounting substrate 10A is configured of a plurality of unit substrates 10C arranged in a tile shape. FIG. 3 shows an example of a perspective view of the unit substrate 10C. The unit substrate 12C includes, for example, a plurality of cells 10E arranged in a tile shape, and a support substrate 10D for supporting the cells 10E. Each unit substrate 10C further includes a control substrate (not shown). The control substrate is electrically connected to each cell 10E, for example, via each electrode pad 34 described later. The support substrate 10D is configured of, for example, a metal frame or a wiring substrate. When the support substrate 10D is formed of a wiring substrate, it can also serve as a control substrate. At this time, at least one of the support substrate 10D and the control substrate is electrically connected to each cell 10E (or a wiring substrate 30 described later) via each electrode pad 34. Support substrate 10D is equivalent to one example of a "support substrate" of this art. The electrode pad 34 corresponds to one specific example of the “electrode pad” of the present technology.

(Circuit configuration of cell 10E)
FIG. 4 shows an example of a circuit configuration in the cell 10E. The cell 10E extends in a predetermined direction (more specifically, a row direction) with a plurality of data lines Sig extending in a predetermined direction (more specifically, a column direction) in the area facing the above-described display area. And a plurality of gate lines Gate. The data line Sig and the gate line Gate are formed of, for example, copper . Cell Le 10E further in the area facing the above-mentioned display area has a plurality of pixels 11 arranged in a matrix. Each pixel 11 includes a light emitting element 12 and a drive IC 13 for driving the light emitting element 12. The light emitting element 12 corresponds to one specific example of the “light emitting element” of the present technology. The drive IC 13 corresponds to one specific example of the “drive circuit” of the present technology.

  The cell 10E further includes, for example, a plurality of saw voltage lines Saw, a plurality of power supply lines VDD1 and VDD2, a plurality of reference voltage lines Ref1 and Ref2, and a plurality of ground lines GND in a region facing the display region described above. And. Each saw voltage line Saw extends, for example, in a predetermined direction (specifically, in the row direction). Each power supply line VDD1, each power supply line VDD2, each reference voltage line Ref1, each reference voltage line Ref2, and each ground line GND extend, for example, in a predetermined direction (specifically, the column direction). At least one of saw voltage line Saw, power supply lines VDD1 and VDD2, reference voltage lines Ref1 and Ref2, and ground line GND may be omitted depending on the drive system. Saw voltage line Saw, power supply lines VDD1 and VDD2, reference voltage lines Ref1 and Ref2, and ground line GND are formed of, for example, copper. In the following, column wiring is used as a generic term for the data line Sig, the power supply line VDD1, the power supply line VDD2, the reference voltage line Ref1, the reference voltage line Ref2 and the ground line GND. Also, in the following, row wiring is used as a generic term for the gate line Gate and the saw voltage line Saw.

  Each data line Sig is a wiring through which a signal corresponding to the video signal is input by the control circuit 20. The signal corresponding to the video signal is, for example, a signal for controlling the light emission luminance of the light emitting element 12. The plurality of data lines Sig are made of, for example, a wire of a type corresponding to the number of light emitting colors of the light emitting element 12. When the light emitting element 12 has three light emission colors, the plurality of data lines Sig include, for example, a plurality of data lines SigR, a plurality of data lines SigG, and a plurality of data lines SigB. Each data line SigR is a wiring through which a signal corresponding to the red video signal is input by the control circuit 20. Each data line SigG is a wiring through which a signal corresponding to a green video signal is input by the control circuit 20. Each data line SigB is a wiring through which a signal corresponding to a blue video signal is input by the control circuit 20.

  The light emission color of the light emitting element 12 is not limited to three colors, and may be four or more colors. When the plurality of data lines Sig include the plurality of data lines SigR, the plurality of data lines SigG, and the plurality of data lines SigB, one data line SigR, one data line SigG and one data line SigR One set of data lines Sig is assigned, for example, for each pixel column. Depending on the driving method, the set of data lines Sig is allocated for each of a plurality of pixel columns. In addition, depending on the driving method, the set of data lines Sig can be replaced with a single data line Sig.

  Each gate line Gate is a wiring through which a signal for selecting the light emitting element 12 is input by the control circuit 20. The signal for selecting the light emitting element 12 is, for example, a signal for starting sampling of the signal input to the data line Sig, and inputting the sampled signal to the light emitting element 12 to start light emission of the light emitting element 12. One gate line Gate is assigned, for example, for each pixel row. Each saw voltage line Saw is, for example, a wiring through which a signal having a sawtooth waveform is input by the control circuit 20. A signal having a sawtooth waveform is contrasted with the sampled signal, eg, sampled for a period during which the peak value of the signal having the sawtooth waveform is higher than the peak value of the sampled signal. A signal is input to the light emitting element 12. One sawtooth voltage line Saw is assigned, for example, every two pixel rows. Each power supply line VDD2 is a wiring through which a drive current supplied to the light emitting element 12 is input by the control circuit 20. One power supply line VDD2 is allocated, for example, every two pixel columns. Each power supply line VDD 1, each reference voltage line Ref 1, each reference voltage line Ref 2, and each ground line GND are wirings through which a fixed voltage is input by the control circuit 20. A ground potential is input to each ground line GND. One power supply line VDD1 is allocated, for example, every two pixel columns. One reference voltage line Ref1 is assigned, for example, every two pixel columns. One reference voltage line Ref2 is assigned, for example, every two pixel columns. One ground line GND is allocated, for example, every two pixel columns.

  FIG. 5 shows an example of a planar configuration of the light emitting element 12. The symbol enclosed by a square in FIG. 5 indicates that the terminal adjacent to the symbol is electrically connected to the terminal adjacent to the same symbol described in FIG. 6 described later. The light emitting element 12 is a chip-like component that emits light of a plurality of colors. When the light emitting elements 12 emit light in three colors, the light emitting elements 12 include, for example, a light emitting element 12R that emits red light, a light emitting element 12G that emits green light, and a light emitting element 12B that emits blue light. The light emitting elements 12R, 12G, 12B are covered with a protective body 12i made of, for example, a resin.

  The light emitting elements 12R, 12G, 12B are, for example, LED chips. Here, the above-mentioned LED chip has a chip size of micrometer order, for example, several tens of μm square. The LED chip has, for example, a semiconductor layer including a laminated structure in which active layers are sandwiched by semiconductor layers different in conductivity type, and two electrodes disposed on a common surface (the same surface) of the semiconductor layers. There is. The light emitting elements 12R, 12G, and 12B may be separate chips from each other, or may be a single common chip.

  The light emitting element 12 has, for example, six electrode pads 12a to 12f. In the light emitting element 12G, one electrode is electrically connected to the electrode pad 13m of the drive IC 13 via the electrode pad 12a and the wiring 16 (see FIG. 4), and the other electrode is the electrode pad 12b and the wiring 16 Are electrically connected to the ground line GND. In the light emitting element 12R, one electrode is electrically connected to the electrode pad 13o of the drive IC 13 via the electrode pad 12c and the wiring 16, and the other electrode is a ground line via the electrode pad 12d and the wiring 16. It is electrically connected to GND. In the light emitting element 12 B, one electrode is electrically connected to the electrode pad 13 p of the drive IC 13 via the electrode pad 12 e and the wiring 16, and the other electrode is a ground line via the electrode pad 12 f and the wiring 16. It is electrically connected to GND.

  For example, the wiring 16 electrically connects the pixel 11 and the data line Sig, the gate line Gate, the power supply line VDD1, the power supply line VDD2, the reference voltage line Ref1, the reference voltage line Ref2, the saw voltage line Saw, or the ground line GND. It is a wire connected to The wiring 16 is also a wiring that electrically connects the light emitting element 12 and the driving IC 13 to each other in the pixel 11, for example. The wiring 16 is formed by, for example, sputtering or plating. A part of the wirings 16 in the plurality of wirings 16 directly connects the pixels 11 with the various row wirings and the various column wirings. The other wirings 16 among the plurality of wirings 16 are composed of a plurality of partial wirings formed intermittently. In each wiring 16 composed of a plurality of partial wirings, each partial electrode is connected, for example, via one or more relay wirings 15 formed on the upper surface (for example, the wiring layer 32E described later) of the wiring substrate 30 described later There is. The relay wiring 15 is formed of, for example, copper.

  FIG. 6 shows an example of a planar configuration of the drive IC 13. The wiring name enclosed by a square in FIG. 6 indicates the name of the wiring electrically connected to the terminal adjacent to the wiring name. The drive IC 13 controls the light emission of the light emitting element 12. The drive IC 13 has, for example, fourteen electrode pads 13a, 13b, 13c, 13d, 13e, 13f, 13g, 13h, 13i, 13k, 13m, 13n, 13o, 13p.

  The electrode pads 13a, 13b, 13c are electrically connected to the data lines SigG, SigR, SigB through the wiring 16. The electrode pads 13 d and 13 e are electrically connected to the power supply lines VDD 1 and VDD 2 through the wiring 16. The electrode pads 13 f and 13 g are electrically connected to the reference potential lines Ref 1 and Ref 2 through the wiring 16. The electrode pad 13 h is electrically connected to the ground line GND via the wiring 16. The electrode pad 13 i is electrically connected to the gate line Gate via the wiring 16. The electrode pad 13 k is electrically connected to the saw voltage line Saw via the wiring 16. The electrode pads 13 m, 13 o and 13 n are electrically connected to the electrode pads 12 a, 12 c and 12 e of the light emitting element 12 through the wiring 16. The electrode pad 13 p is not connected to the wiring 16.

(Structure of cell 10E)
FIG. 7 shows an example of the cross-sectional configuration of the cell 10E. FIG. 7 shows an example of the cross-sectional configuration of the portion where the light emitting element 12, the drive IC 13, the data line SigB1 and the gate line Gate2 are formed in the cell 10E. FIG. 8 shows an example of the wiring layout of the cell 10E. FIG. 8 shows an example of a wiring layout such as the wiring 16 connected to four pixels 11 corresponding to the 2 × 2 matrix. The wiring layout of each cell 10E is, for example, a layout in which the layout shown in FIG. 8 is repeatedly arranged in the row direction and the column direction. The wiring name enclosed by a square in FIG. 8 indicates the name of the wiring electrically connected to the via 14 (described later) adjacent to the wiring name.

  The cell 10E includes the wiring substrate 30, the fine L / S layer 40 formed in contact with the upper surface of the wiring substrate 30, and the plurality of pixels 11 arranged in a matrix on the upper surface of the fine L / S layer 40. doing. The wiring substrate 30 has a role as an intermediate substrate in relation to the wiring substrate 10D. The wiring substrate 30 corresponds to one specific example of the “wiring substrate” of the present technology. The fine L / S layer 40 corresponds to one specific example of the “fine L / S layer” of the present technology. The pixel 11 corresponds to one specific example of the “element” of the present technology.

  The cell 10E further includes, for example, a buried layer 44 covering the surface including the respective pixels 11, a light shielding layer 45 formed in contact with the buried layer 44, and an insulating layer 50 formed in contact with the back surface of the wiring substrate 30. And. The buried layer 44 is made of a light transmissive material that transmits visible light. The light shielding layer 45 includes a material that absorbs visible light. The insulating layer 50 is formed of, for example, an ultraviolet curing resin or a thermosetting resin.

  The light shielding layer 45 has an opening 45 </ b> A at a position facing the light emitting elements 12. The light emitted from each light emitting element 12 is emitted to the outside through each opening 45A. The insulating layer 50 has openings 50A at locations facing the respective electrode pads 34 as external connection terminals of the cell 10E. Therefore, each electrode pad 34 is exposed to the back surface of the cell 10E (wiring substrate 30) through the opening 50A. For example, the electrode pad 34 and the wiring substrate 10D are electrically connected to each other through a metal bump or a solder bump provided in the opening 50A.

(Wiring board 30)
The wiring substrate 30 is, for example, a laminated substrate in which electrical connection between layers is made by vias. The wiring substrate 30 has a plurality of electrode pads 34 as external connection terminals on the back surface of the wiring substrate 30. The plurality of electrode pads 34 are formed, for example, for each of data line SigR1, data line SigG1, data line SigB1, gate line Gate1, gate line Gate2, power supply line VDD1, reference voltage line Ref1, reference voltage line Ref2 and saw voltage line Saw. One or more are provided.

  The wiring substrate 30 electrically connects the plurality of wirings 16 drawn around in the fine L / S layer 40 and the plurality of electrode pads 34. The wiring substrate 30 has a plurality of through wires 17 that electrically connect the plurality of wires 16 and the plurality of electrode pads 34. Each through wiring 17 is a wiring which penetrates the wiring substrate 30 in the thickness direction. A through wiring 17 includes a data line Sig extending in the column direction in a layer, and a plurality of vias 14 formed on (or above) data line Sig and exposed on the upper surface of wiring substrate 30. It is. A through wiring 17 includes a gate line Gate extending in the row direction in a layer, and a plurality of vias 14 formed on (or above) the gate line Gate and exposed on the upper surface of the wiring substrate 30. It is.

  A through wiring 17 includes power supply line VDD1 extending in the column direction in a certain layer, and a plurality of vias 14 formed on (or above) power supply line VDD1 and exposed on the upper surface of wiring substrate 30. It is. A through wiring 17 has a reference voltage line Ref1 extending in the column direction in a layer, and a plurality of vias 14 formed on (or above) the reference voltage line Ref1 and exposed on the upper surface of the wiring substrate 30. Contains. A through wiring 17 has a reference voltage line Ref2 extending in the column direction in a certain layer, and a plurality of vias 14 formed on (or above) the reference voltage line Ref2 and exposed on the upper surface of the wiring substrate 30. Contains. A through wiring 17 is formed in a certain layer with a saw voltage line Saw extending in the column direction, and a plurality of vias 14 formed on (or above) the saw voltage line Saw and exposed on the top surface of the wiring substrate 30. Contains.

  That is, in the wiring substrate 30, the plurality of vias 14 are the data line SigR1, the data line SigG1, the data line SigB1, the gate line Gate1, the gate line Gate2, the power line VDD1, the reference voltage line Ref1, the reference voltage line Ref2, and the saw voltage line A plurality is provided for each Saw.

  The vias 14 are provided in the openings of the insulating layer (for example, an insulating layer 32D described later). The vias 14 are a wiring (for example, the wiring 16) on the upper surface of the insulating layer (for example, the insulating layer 32D described later) and a wiring (for example, the data line Sig or the gate line Gate) on the back surface of the insulating layer (for example, the insulating layer 32D described later) And are connected to each other electrically. The vias 14 are, for example, conformal vias or filled vias.

  The plurality of vias 14 are arranged in a cycle that is an integral multiple of the arrangement cycle of the plurality of pixels 11. Specifically, the plurality of vias 14 formed on (or above) the data line Sig have a cycle of an integral multiple of the arrangement cycle of the extension direction (column direction) of the data line Sig in the plurality of pixels 11. It is arranged. Similarly, the plurality of vias 14 formed on (or above) the gate line Gate are arranged at a cycle that is an integral multiple of the arrangement cycle of the extending direction (row direction) of the gate lines Gate in the plurality of pixels 11. ing. The plurality of vias 14 formed above (or above) the power supply line VDD1 are arranged at a cycle that is an integral multiple of the arrangement cycle of the power supply lines VDD1 in the extending direction (column direction) of the plurality of pixels 11. The plurality of vias 14 formed on (or above) the reference voltage line Ref 1 are arranged in a cycle of an integral multiple of the arrangement cycle of the extension direction (column direction) of the reference voltage line Ref 1 in the plurality of pixels 11 There is. The plurality of vias 14 formed on (or above) the reference voltage line Ref2 are arranged at a period that is an integral multiple of the arrangement period of the extension direction (column direction) of the reference voltage line Ref2 in the plurality of pixels 11. There is. The plurality of vias 14 formed on (or above) the sawtooth voltage line Saw are arranged at a cycle that is an integral multiple of the arrangement cycle of the sawtooth voltage lines Saw extending direction (row direction) in the plurality of pixels 11. There is.

  Adjacent pixels 11 are electrically connected to one common via 14 via one or more wirings 16. Specifically, a plurality of pixels 11 arranged in the extending direction (column direction) of the data line Sig are formed on (or above) the data line Sig via one or more wirings 16. It is electrically connected to one via. Similarly, a plurality of pixels 11 arranged in the extending direction (row direction) of the gate line Gate is formed in common on one side (or upper side) of the gate line Gate via one or more wirings 16. It is electrically connected to the via. A plurality of pixels 11 arranged in the extending direction (column direction) of the power supply line VDD1 are electrically connected to one common via formed on (or above) the power supply line VDD1 via the one or more wirings 16 Connected. Common vias formed on (or above) the reference voltage line Ref1 with the plurality of pixels 11 arranged in the extension direction (column direction) of the reference voltage line Ref1 via the one or more wirings 16 Are connected electrically. Common vias formed on (or above) the reference voltage line Ref2 via the one or more wirings 16 and a plurality of pixels 11 arranged in the extending direction (column direction) of the reference voltage line Ref2 Are connected electrically. A plurality of pixels 11 arranged in the extending direction (row direction) of the sawtooth voltage line Saw are formed via the one or plural wirings 16 on a common one via on (or above) the sawtooth voltage line Saw. Are connected electrically.

  In FIG. 8, the vias 14 are shared in two pixels 11 arranged in the row direction, two pixels 11 arranged in the column direction, and four pixels 11 corresponding to the 2 × 2 matrix. For example, two pixels 11 arranged in the column direction are electrically connected to one common via 14 electrically connected to the data line SigB1 via one or more wirings 16. At this time, the plurality of vias 14 electrically connected to the data line SigB1 are arranged in a cycle twice as long as the arrangement cycle of the plurality of pixels 11 in the column direction. For example, two pixels 11 arranged in the row direction are electrically connected to one common via 14 electrically connected to the gate line Gate1 through one or more wirings 16. At this time, the plurality of vias 14 electrically connected to the gate line Gate 1 are arranged in a cycle twice as long as the arrangement cycle of the plurality of pixels 11 in the row direction. For example, four pixels 11 corresponding to 2 × 2 are electrically connected to one common via 14 electrically connected to the reference voltage line Ref 1 through one or more wirings 16. At this time, the plurality of vias 14 electrically connected to the reference voltage line Ref 1 are arranged in a cycle twice as long as the arrangement cycle of the plurality of pixels 11 in the column direction.

  Comparing the wiring layout shown in FIG. 8 (wiring layout of the embodiment) with the wiring layout of the following comparative example, the number of vias 14 required in the four pixels 11 corresponding to 2 × 2 is as follows: Become. In the comparative example, in each pixel 11, each of data line SigR1, data line SigG1, data line SigB1, gate line Gate1, gate line Gate2, power line VDD1, reference voltage line Ref1, reference voltage line Ref2, and saw voltage line Saw , Vias 14 are provided one by one.

Example Comparative Example SigR1 2 2
SigG1 1 2
SigB1 1 2
SigR2 1 2
SigG2 1 2
SigB2 1 2
VDD1 1 4
Ref1 1 4
Ref2 1 4
Gate1 1 2
Gate2 1 2
Saw 2 4
Total 14 32

  From the above, by sharing the vias 14 by a plurality of adjacent pixels 11, the number of vias 14 required for one pixel 11 is reduced compared to the case where the vias 14 are provided for each pixel 11. I understand that.

  By the way, as described above, the wiring layout of each cell 10E is, for example, a layout in which the layout shown in FIG. 8 is repeatedly arranged in the row direction and the column direction. At this time, it is preferable that the pitch of the pixels 11 be equal not only in each cell 10E but also between two adjacent cells 10E. In each cell 10E, a plurality of electrode pads 34 as external connection terminals of each cell 10E are provided on the back surface of the cell 10E. Therefore, it is possible to omit or minimize the frame area which can not be used for the arrangement of the pixels 11 as in the case where the external connection terminal is provided on the outer edge of the upper surface of the mounting surface. Therefore, in each cell 10E, such a frame area is omitted, or in the case where such a frame area in each cell 10E is minimized, even between two adjacent cells 10E. The pitch of the pixels 11 can be equal.

  The wiring substrate 30 is, for example, a buildup substrate, and the core substrate 31, the buildup layer 32 formed in contact with the upper surface of the core substrate 31, and the buildup layer 33 formed in contact with the back surface of the core substrate 31. And. The wiring substrate 30 corresponds to one specific example of the “build up substrate” of the present technology. The buildup layers 32 and 33 correspond to one specific example of the “buildup layer” of the present technology.

  The core substrate 31 secures the rigidity of the cell 10E, and is, for example, a glass epoxy substrate. The buildup layer 32 has one or more wiring layers. For example, as shown in FIG. 7, the buildup layer 32 includes the wiring layer 32A, the insulating layer 32B, the wiring layer 32C, the insulating layer 32D, and the wiring layer 32E in this order from the upper surface side of the core substrate 31. . The buildup layer 33 has one or more wiring layers. For example, as shown in FIG. 7, the buildup layer 33 includes the wiring layer 33A, the insulating layer 33B, the wiring layer 33C, the insulating layer 33D, and the wiring layer 33E in this order from the back surface side of the core substrate 31. . The wiring layers 32A, 32C, 32E, 33A, 33C, and 33E are formed of, for example, copper. The insulating layers 32B, 32D, 33B, and 33D are formed of, for example, an ultraviolet curable resin or a thermosetting resin.

  Each data line Sig is formed, for example, in the wiring layer 32C. FIG. 7 exemplifies how the data line SigB1 is formed in the wiring layer 32C. Each gate line Gate is formed in a layer different from the data line Sig, and is formed, for example, in the wiring layer 32A. FIG. 7 illustrates how the gate line Gate2 is formed in the wiring layer 32A. Each power supply line VDD2 and each ground line GND are formed, for example, in the wiring layer 32E. Each via 14 is formed at least in the buildup layer 32, for example, in the same layer as at least the insulating layer 32D. FIG. 7 exemplifies how each via 14 is formed in the same layer as the insulating layer 32D and the wiring layer 32E. Each electrode pad 34 is formed in the buildup layer 33, and is formed, for example, in the same layer as the wiring layer 33E. The relay wiring 15 described later is formed in a wiring layer 32E which is a wiring layer on the upper surface of the wiring substrate 30.

(Fine L / S layer 40)
The fine L / S layer 40 has a wiring layer 42 and an insulating layer 41 provided between the wiring layer 42 and the top surface of the wiring substrate 30. The insulating layer 41 is in contact with the wiring layer 42 and the upper surface of the wiring substrate 30. The wiring layer 42 is a layer including the respective wirings 16. Accordingly, the insulating layer 41 is provided between each of the wires 16 and the upper surface of the wiring substrate 30, and is in contact with each of the wires 16 and the upper surface of the wiring substrate 30. The insulating layer 41 has an opening 41 A at a position facing the upper surface of each via 14. The insulating layer 41 may have an opening 41 </ b> A not at a position facing the via 14 but at a position facing the relay wiring 15 electrically connected to the via 14. The insulating layer 41 further has an opening 41A at a position facing the relay wiring 15 electrically connected to the partial electrode. At the bottom of the opening 41A, a part of the via 14 or a part of the relay wiring 15 is exposed. The insulating layer 41 is formed of, for example, VPA. VPA is generally used as a resist, and for example, VPA manufactured by Nippon Steel Chemical Co., Ltd. is put on the market. When the insulating layer 41 is formed of VPA, for example, the opening 41 can be formed in the VPA by selectively exposing and developing the VPA.

  In the wiring layer 42, a part of the wirings 16 is provided at least one for each of the vias 14, another wiring 16 is provided at least one for each of the intermediate wirings 15, and the remaining wirings 16 are More than one are provided for each of the power supply line VDD2 and the ground line GND. The wiring layer 42 (each wiring 16) has, for example, a seed layer 42A in contact with the top surface of the wiring substrate 30 including the bottom and side surfaces of the opening 41A, and a plating layer 42B in contact with the top surface of the seed layer 42A. The seed layer 42A is a plating growth surface when the plating layer 42B is formed by plating in the manufacturing process. The seed layer 42A is in contact with the bottom of the opening 41A, and is electrically connected to the via 14 and the relay wiring 15. The seed layer 42A is formed of, for example, copper. The plating layer 42B is formed by plating using the seed layer 42A as a plating growth surface in the manufacturing process. The wiring layer 42 (each wiring 16) may be, for example, a layer formed by sputtering.

  As described above, the wiring layer 42 (each wiring 16) is formed in contact with the upper surface of the insulating layer 41. On the other hand, the electrode of each pixel 11 is formed in contact with the upper surface of the seed layer 42A. Therefore, although the light emitting element 12 and the drive IC 13 are formed on the same surface (upper surface of the seed layer 42A), strictly speaking, the upper surface of the wiring layer 42 (wiring 16) (upper surface of the insulating layer 41) ) Is formed on the other side. However, from the viewpoint of mounting each pixel 11, it can be said that the surface including the upper surface of the insulating layer 41 and the upper surface of the seed layer 42A is the mounting surface 41S. Therefore, the wiring layer 42 (each wiring 16) is formed on the mounting surface 41S of each pixel 11, and is formed on a surface substantially common to each pixel 11.

  The wiring layer 42 (each wiring 16) is, for example, plated-bonded to the via 14, a member electrically connected to the via 14 (for example, the relay wiring 15), and the relay wiring 15 electrically connected to the partial electrode. It is done. When forming the wiring layer 42 (each wiring 16) by plating, the connection between the wiring layer 42 (each wiring 16) and the via 14 etc. is collectively performed in the process of forming the wiring layer 42 (each wiring 16). May be performed. The wiring layer 42 (each wiring 16) is, for example, joined by plating to the pixel 11 (the light emitting element 12 and the drive IC 13). When forming the wiring layer 42 (each wiring 16) by plating, the connection between the wiring layer 42 (each wiring 16) and the pixel 11 is collectively performed in the process of forming the wiring layer 42 (each wiring 16). It may be done.

  The L / S (line and space) of the fine L / S layer 40 is smaller than the L / S of the wiring substrate 30. L / S indicates the narrowest wiring pitch in the plane. The L / S of the fine L / S layer 40 includes a plurality of signal lines Sig, a plurality of gate lines Gate, a plurality of voltage lines VDD1, a plurality of reference voltage lines Ref1, a plurality of reference voltage lines Ref2, and a saw voltage line Saw. It is smaller than L / S. The L / S of the fine L / S layer 40 is, for example, about 25 μm. On the other hand, L / S of the wiring substrate 30 is, for example, about 75 μm.

[Production method]
Next, an example of a method for manufacturing the cell 10E will be described with reference to FIGS. 9 to 13 show an example of the manufacturing process of the cell 10E in the order of steps.

  First, the wiring board 30 is prepared. Next, the insulating layer 41 is formed on the upper surface of the wiring substrate 30, and then the opening 41A is formed at a position facing the upper surface of the via 14 in the insulating layer 41 by a predetermined method (FIG. 9). At this time, although not shown, an opening 41A is also formed at a position opposite to the upper surface of the relay wiring 15 electrically connected to the via 14 and the partial wiring by a predetermined method. Next, a seed layer 42A is formed on the top surface of the wiring substrate 30 including the bottom and side surfaces of the opening 41A (FIG. 10).

  Next, a fixing layer 43A for temporarily fixing the light emitting element 12 and the drive IC 13 is formed by, for example, applying an insulating adhesive on the entire surface (see FIG. 11). Instead of the adhesive, a layer of an adhesive represented by silicone or acrylic may be formed as the fixing layer 43A. Subsequently, the light emitting element 12 and the drive IC 13 are temporarily fixed by the fixing layer 43A (FIG. 11). At this time, the electrode pads 12a to 12e of the light emitting element 12 and the electrode pads 13a to 13p of the drive IC 13 are disposed close to the extent that they can be connected to a metal body (plating layer 42B) grown in plating described later.

  Next, the fixed layer 43A other than the portion where the light emitting element 12 and the drive IC 13 are temporarily fixed (the part of the fixed layer 43A present on the bottom surface of the light emitting element 12 and the drive IC 13) is removed. As a result, the fixed layer 43A remains only on the bottom surfaces of the light emitting element 12 and the drive IC 13 (FIG. 12). In FIG. 12, the remaining fixed layer 43 </ b> A is described as the fixed layer 43. At the time of removing the fixed layer 43A, for example, dry etching or immersion in an organic solvent can be performed. Note that an insulating adhesive may be applied in advance only to the place where the light emitting element 12 and the drive IC 13 are temporarily fixed.

  Next, plating is performed using the seed layer 42A as a plating growth surface, and a plating layer 42B is formed on the top surface of the seed layer 42A (FIG. 13). Thereby, the wiring layer 42 (each wiring 16) is formed. At this time, the connection between the wiring layer 42 (each wiring 16) and the via 14 or the like is collectively performed in the process of forming the wiring layer 42 (each wiring 16). In addition, the connection between the wiring layer 42 (each wiring 16) and the pixel 11 is collectively performed in the process of forming the wiring layer 42 (each wiring 16). Thereafter, after the light emitting element 12 and the drive IC 13 are buried with the buried layer 43, the light shielding layer 45 is formed (see FIG. 7). Thus, the cell 10E is manufactured.

[Operation / effect]
Next, the operation and effects of the display device 1 will be described. In the present embodiment, in the wiring substrate 30, a plurality of vias 14 are provided for each wiring (for example, data line Sig, gate line Gate) extending in a predetermined direction in the layer. A plurality of vias 14 provided for each wiring extending in a predetermined direction in the layer are arranged at a cycle that is an integral multiple of the arrangement cycle of the plurality of pixels 11. A plurality of pixels 11 adjacent to each other on the fine L / S layer 40 are electrically connected to the common via 14 via one or more wirings 16 in the fine L / S layer 40. In this manner, by sharing the vias 14 by the plurality of adjacent pixels 11, the number of the vias 14 required for one pixel 11 is reduced compared to the case where the vias 14 are provided for each pixel 11. As a result, the L / S of the fine L / S layer 40 on the wiring substrate 30 is determined by the L / S of a plurality of wirings (for example, a plurality of data lines Sig or a plurality of gate lines Gate) in the wiring substrate 30. In the case where the size is also reduced, the number of wiring layers 42 on the wiring substrate 30 can be one. Therefore, in the present embodiment, the wiring pitch of the mounting surface 41S can be narrowed without forming the wiring layer 42 on the wiring substrate 30 in multiple layers.

<2. Modified example>
[Modification 1]
In the above embodiment, for example, as shown in FIG. 14, the pixel 11 may be formed integrally with the light emitting element 12 and the drive IC 13.

[Modification 2]
In the above embodiment and its modification, the light emission color of the light emitting element 12 may be single. In this case, the cell 10E may have, for example, color filters of a plurality of colors in the opening 45A. In the second modification, the light emission color of the light emitting element 12 may be single. In this case, the counter substrate 10B may have color filters of a plurality of colors, for example, in the opening 45A.

<3. Second embodiment>
FIG. 15 illustrates an example of a perspective configuration of a lighting device 2 according to a second embodiment of the present technology. In the display device 1 according to the first embodiment and its modification (Modifications 1 and 2), the illumination device 2 changes a signal inputted to the data line Sig every moment like a video signal. It corresponds to what is not the fixed value according to the brightness of illumination light. The lighting device 2 includes, for example, a lighting panel 60 and a control circuit 70 for controlling the lighting panel 60, as shown in FIG.

  The lighting panel 60 is a combination of the mounting substrate 60A and the counter substrate 60B. The surface of the opposing substrate 60B is a light emitting surface. The opposing substrate 60B is disposed at a position facing the mounting substrate 60A via a predetermined gap. The opposing substrate 60B includes, for example, a light transmitting substrate that transmits visible light, and includes, for example, a glass substrate or a transparent resin substrate.

  The mounting substrate 60A is configured of, for example, a plurality of unit substrates arranged in a tile, as in FIG. The unit substrate has, for example, a plurality of cells arranged in a tile and a wiring substrate for supporting each cell. In each cell, for example, in FIG. 4, FIG. 7, FIG. 8, and FIG. 14, when the signal input to the data line Sig has a fixed value according to the brightness of the illumination light, the pixel 11 is driven. Unnecessary wiring is omitted as appropriate.

[Operation / effect]
Next, the operation and effects of the lighting device 2 will be described. In the present embodiment, as in the display device 1 according to the first embodiment and the modification thereof, in the wiring substrate 30, a plurality of vias 14 are provided for each wiring extending in a predetermined direction in the layer. It is done. A plurality of vias 14 provided for each wiring extending in a predetermined direction in the layer are arranged at a cycle that is an integral multiple of the arrangement cycle of the plurality of pixels 11. A plurality of light receiving elements adjacent to each other on the fine L / S layer 40 are electrically connected to the common via 14 via one or more wirings 16 in the fine L / S layer 40. In this manner, by sharing the vias 14 by the plurality of adjacent pixels 11, the number of the vias 14 required for one pixel 11 is reduced compared to the case where the vias 14 are provided for each pixel 11. As a result, when L / S of the fine L / S layer 40 on the wiring substrate 30 is smaller than L / S of a plurality of wires in the wiring substrate 30, the number of wiring layers 42 on the wiring substrate 30 is set. It can be one. Therefore, in the present embodiment, the wiring pitch of the mounting surface 41S can be narrowed without forming the wiring layer 42 on the wiring substrate 30 in multiple layers.

<4. Third embodiment>
FIG. 16 illustrates an example of a perspective view of a light receiving device 3 according to a third embodiment of the present technology. The light receiving device 3 corresponds to one in which a light receiving element is provided instead of the pixel 11 in the display device 1 according to the first embodiment. For example, as shown in FIG. 16, the light receiving device 2 includes a light receiving panel 80 and a control circuit 90 that controls the light receiving panel 80.

  The light receiving panel 80 is a combination of the mounting substrate 80A and the counter substrate 80B. The surface of the counter substrate 80B is a light receiving surface. The opposing substrate 80B is disposed at a position facing the mounting substrate 80A via a predetermined gap. The opposing substrate 80B includes, for example, a light transmitting substrate that transmits visible light, and includes, for example, a glass substrate or a transparent resin substrate.

  The mounting substrate 80A is configured of, for example, a plurality of unit substrates arranged in a tile shape, as in FIG. The unit substrate has, for example, a plurality of cells arranged in a tile and a wiring substrate for supporting each cell. Each cell corresponds to, for example, one in which a light receiving element is provided instead of the pixel 11 in FIGS. 4, 7 and 14. However, wiring unnecessary for driving the light receiving element is omitted as appropriate.

[Operation / effect]
Next, the operation and effects of the light receiving device 3 will be described. In the present embodiment, as in the display device 1 according to the first embodiment and the modification thereof, in the wiring substrate 30, a plurality of vias 14 are provided for each wiring extending in a predetermined direction in the layer. It is done. A plurality of vias 14 provided for each wiring extending in a predetermined direction in the layer are arranged at a cycle that is an integral multiple of the arrangement cycle of the plurality of light receiving elements. A plurality of light receiving elements adjacent to each other on the fine L / S layer 40 are electrically connected to the common via 14 via one or more wirings 16 in the fine L / S layer 40. Thus, by sharing the vias 14 by a plurality of adjacent light receiving elements, the number of the vias 14 required for one pixel 11 is reduced compared to the case where the vias 14 are provided for each light receiving element. As a result, when L / S of the fine L / S layer 40 on the wiring substrate 30 is smaller than L / S of a plurality of wires in the wiring substrate 30, the number of wiring layers 42 on the wiring substrate 30 is set. It can be one. Therefore, in the present embodiment, the wiring pitch of the mounting surface 41S can be narrowed without forming the wiring layer 42 on the wiring substrate 30 in multiple layers.

<5. Modification common to each embodiment>
In each of the above-described embodiments and the modifications thereof, the light shielding layer 45 may be disposed on the back surface (surface on the mounting substrate 10A, 60A, 80A side) of the counter substrate 10B, 60B, 80B.

  In each of the above-described embodiments and their modifications, for example, as shown in FIGS. 17 to 19, the opposing substrates 10B, 60B, and 80B may be omitted. Further, in each of the above-described embodiments and the modifications thereof, one of the counter substrates 10B, 60B, and 80B may be provided for each unit substrate 10C or for each cell 12E.

  The light shielding layer 45 may be omitted in each of the above embodiments and their modifications.

  In each of the above-described embodiments and the modifications thereof, each pixel 11 (the light emitting element 12 and the driving IC 13) is plated and connected to the wiring layer 42 (each wiring 16). Good. For example, after providing solder bumps on the electrode pads of the light emitting element 12 and the drive IC 13, the light emitting element 12 and the drive IC 13 are disposed on the respective wirings 16, and then reflow is performed. Thus, the light emitting element 12 and the drive IC 13 can be soldered to the respective wirings 16. In addition, the effect described in this specification is an illustration to the last, is not limited, and may have other effects.

Also, for example, the present technology can have the following configurations.
(1)
A wiring board,
A fine L / S (line and space) layer formed in contact with the upper surface of the wiring substrate;
A plurality of elements arranged in a matrix on the upper surface of the fine L / S layer;
The wiring board is
A plurality of first wires extending in a predetermined direction in the layer;
A plurality of vias provided for each of the first wires, and arranged at a cycle that is an integral multiple of an array cycle of the plurality of the elements,
The fine L / S layer is
A plurality of second wires provided one or more for each of the vias;
An insulating layer provided between each of the second wires and the upper surface of the wiring substrate, and in contact with each of the second wires and the upper surface of the wiring substrate;
The L / S of the fine L / S layer is smaller than the L / S of the plurality of first wires,
A plurality of adjacent elements are electrically connected to the common via via one or more of the second wires.
(2)
The plurality of first wires extend in the row direction or the column direction,
The plurality of vias are arranged in a cycle of an integral multiple of the arrangement cycle of the extending direction of the first wiring in the plurality of elements.
The mounting substrate according to (1), wherein the plurality of elements arranged in the extending direction of the first wiring are electrically connected to the common via via one or more second wirings.
(3)
The mounting substrate according to (1) or (2), wherein each of the vias is formed on or above the second wiring and exposed to the upper surface of the wiring substrate.
(4)
The mounting substrate according to any one of (1) to (3), wherein the wiring substrate is provided with one or more for each of the first wires and has a plurality of electrode pads exposed on the back surface of the wiring substrate.
(5)
The second wiring is plated and joined to the via or a member electrically connected to the via, and is further plated and joined to each of the elements (1) to (4). Mounting board described.
(6)
The wiring substrate is a buildup substrate having a core substrate and a buildup layer formed on one or more layers on both sides of the core substrate,
Each of the vias is formed in the buildup layer at least on the upper surface side of the wiring substrate,
Each of the said electrode pads is formed in the said buildup layer of the back surface side of the said wiring board, The mounting board as described in any one of (1) thru | or (5).
(7)
Each of the elements includes a light emitting element and a drive circuit for driving the light emitting element. The mounting substrate according to any one of (1) to (6).
(8)
One or more mounting boards,
A control circuit that controls one or more of the mounting boards;
The mounting board is
A wiring board,
A fine L / S (line and space) layer formed in contact with the upper surface of the wiring substrate;
A plurality of elements arranged in a matrix on the upper surface of the fine L / S layer;
The wiring board is
A plurality of first wires extending in a predetermined direction in the layer;
A plurality of vias provided for each of the first wires, and arranged at a cycle that is an integral multiple of an array cycle of the plurality of the elements,
The fine L / S layer is
A plurality of second wires provided one or more for each of the vias;
An insulating layer provided between each of the second wires and the upper surface of the wiring substrate, and in contact with each of the second wires and the upper surface of the wiring substrate;
The L / S (line and space) of the fine L / S layer is smaller than the L / S of the plurality of first wires,
An electronic device in which a plurality of adjacent elements are electrically connected to a common via via one or more second wirings.
(9)
The electronic device is
A support substrate for supporting a plurality of the mounting substrates;
And a control board for controlling a plurality of the mounting boards,
The plurality of mounting substrates are arranged in a tile on the support substrate,
Each of the wiring boards is provided with one or more for each of the first wirings, and has a plurality of electrode pads electrically connected to the first wirings and exposed on the back surface of the wiring board
The electronic device according to (8), wherein at least one of the support substrate and the control substrate is electrically connected to each of the wiring substrates via each of the electrode pads.

  DESCRIPTION OF SYMBOLS 1 display device 10 display panel 10A mounting substrate 10B opposing substrate 10C unit substrate 10D wiring substrate 10E cell 11 pixel 12 12B 12G 12R light emitting element 12a 12, 12b, 12c, 12d, 12e, 12f, 13a, 13c, 13e, 13e, 13f, 13g, 13h, 13k, 13m, 13n, 13o, 13p ... electrode pad, 12i ... protective body, 13 ... 13 IC 15 relay wiring 16 wiring 17 through wiring 20 control circuit 30 wiring board 31 core substrate 32 33 buildup substrate 32A 32C 32E 33A 33C 33E ... Wiring layer, 32B, 32D, 33B, 33D ... Insulating layer, 34 ... Electrode pad, 40 ... Fine L / S layer, 41 ... Insulating layer, 41A ... Opening, 41 ... mounting surface, 42 ... wiring layer, 42A ... seed layer, 42B ... plating layer, 43, 43A ... fixed layer, 44 ... embedded layer, 45 ... light shielding layer, 45A ... opening, 50 ... insulating layer, 50A ... opening, Gate , Gate1, Gate2 ... gate line, GND ... ground line, Ref1, Ref2 ... reference voltage line, Saw ... saw voltage line, Sig, SigB, SigB1, SigB2, SigG, SigG1, SigG2, SigR, SigR1, SigR2 ... data line, VDD1, VDD2 ... power supply lines.

Claims (6)

Equipped with multiple unit boards,
Each unit substrate is
A wiring board including a plurality of first wirings and the plurality of vias,
A plurality of second wires provided on the wiring substrate;
A plurality of pixels connected to the plurality of second wirings and including a light emitting element and a driving IC for driving the light emitting element ;
A plurality of said vias electrically connect the plurality of the first wiring and the plurality of the second wirings,
The plurality of pixels are commonly connected to one of the plurality of vias via one or more of the second wires ,
A display device in which the L / S of the plurality of second wirings is smaller than the L / S of the plurality of first wirings . A plurality of the first wiring is to extend in the row direction or the column direction,
The plurality of vias are arranged at a cycle that is an integral multiple of the arrangement cycle of the extending direction of the first wiring in the plurality of pixels.
2. The display device according to claim 1, wherein the plurality of pixels arranged in the extending direction of the first wiring are electrically connected to the common via via one or more second wirings. The display device according to claim 2, wherein each of the vias is formed on or above the first wiring and is exposed on the top surface of the wiring substrate. The display device according to claim 3, wherein one or more of the wiring substrates are provided for each of the first wirings, and the plurality of electrode pads exposed on a back surface of the wiring substrate are provided. 5. The display device according to claim 4, wherein the second wiring is plated and bonded to the via or a member electrically connected to the via, and is further plated and connected to each pixel. The wiring substrate is a buildup substrate having a core substrate and a buildup layer formed on one or more layers on both sides of the core substrate,
Each of the vias is formed in the buildup layer at least on the upper surface side of the wiring substrate,
The display device according to claim 5, wherein each of the electrode pads is formed in the buildup layer on the back surface side of the wiring substrate.

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