JP6479480B2 - Nonvolatile memory device - Google Patents
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- JP6479480B2 JP6479480B2 JP2015001745A JP2015001745A JP6479480B2 JP 6479480 B2 JP6479480 B2 JP 6479480B2 JP 2015001745 A JP2015001745 A JP 2015001745A JP 2015001745 A JP2015001745 A JP 2015001745A JP 6479480 B2 JP6479480 B2 JP 6479480B2
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- 239000010409 thin film Substances 0.000 claims description 29
- 229910002367 SrTiO Inorganic materials 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000002131 composite material Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000010408 film Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical group [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 claims description 4
- 230000005621 ferroelectricity Effects 0.000 claims description 3
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical group [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- 229910002076 stabilized zirconia Inorganic materials 0.000 claims 1
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Inorganic materials [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 19
- 229910002148 La0.6Sr0.4MnO3 Inorganic materials 0.000 description 15
- 238000000034 method Methods 0.000 description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000013078 crystal Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910004121 SrRuO Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 230000003446 memory effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 238000000089 atomic force micrograph Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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Description
本発明はメモリ素子およびその作製方法に関する。 The present invention relates to a memory element and a manufacturing method thereof.
金属電極と、導電性を有する強誘電酸化物から構成される不揮発性メモリ素子において、金属電極と強誘電酸化物の界面におけるショットキー型のバリア障壁高さが強誘電分極に依存することにより、不揮発抵抗スイッチングメモリ機能が得られる(特許文献１)。
上記導電性を有する強誘電酸化物としては、p型の半導体であるBi1-xFeO3(1＞x＞0)を使用し、上記金属電極として、Ptを使用している。
In a nonvolatile memory element composed of a metal electrode and a ferroelectric oxide having conductivity, the Schottky barrier barrier height at the interface between the metal electrode and the ferroelectric oxide depends on the ferroelectric polarization. A nonvolatile resistance switching memory function can be obtained (Patent Document 1).
As the conductive ferroelectric oxide, Bi 1-x FeO 3 (1>x> 0) which is a p-type semiconductor is used, and Pt is used as the metal electrode.
Si基板上に成長させるペロブスカイト酸化物薄膜(SrRuO3)の配向性を制御するため、複数のバッファー層を用いた積層体作製方法を提案している(特許文献２)。
本発明に類似するSrRuO3/SrO/YSZ/Si構造では、[001]配向が得られている。
平坦性を含む他の特性については記載がなく、その方法および効果については説明されていない。
In order to control the orientation of a perovskite oxide thin film (SrRuO 3 ) grown on a Si substrate, a method for producing a laminate using a plurality of buffer layers has been proposed (Patent Document 2).
In the SrRuO 3 / SrO / YSZ / Si structure similar to the present invention, [001] orientation is obtained.
Other properties including flatness are not described, and their methods and effects are not described.
厚さ数nmの強誘電酸化物をバリア層として用いたトンネル接合においては、強誘電分極の反転に伴いトンネル抵抗が不揮発スイッチングすることが知られており、不揮発性メモリ素子に応用できる。
強誘電体層の膜厚がわずか数nmのトンネル接合において良好な不揮発メモリ効果を得るためには、強誘電バリア層および下部電極層として用いるペロブスカイト酸化物薄膜が、いずれも完全な[001]配向であることに加え、高い平坦性を有していなければならない。
In a tunnel junction using a ferroelectric oxide with a thickness of several nanometers as a barrier layer, it is known that the tunnel resistance is non-volatilely switched with the reversal of the ferroelectric polarization, and can be applied to a non-volatile memory element.
In order to obtain a good non-volatile memory effect in a tunnel junction with a ferroelectric layer thickness of only a few nanometers, the perovskite oxide thin film used as the ferroelectric barrier layer and the lower electrode layer are both perfectly [001] oriented. In addition, it must have high flatness.
次に、nmオーダーの膜厚で強誘電性を安定させるためには、強いエピタキシャル格子歪(２軸性の圧力効果)が必要である。
このエピタキシャル格子歪は通常、強誘電体と同じペロブスカイト構造を有し、所望の格子定数を有する単結晶基板を用いることにより制御される。
また、高い平坦性・結晶性も、この効果を得るためには必須である。
上記の、薄膜の品質にかかわる高度な要請に対し、シリコン基板は結晶構造が異なる上、金属酸化物および酸素と容易に化学反応するため、これらすべての条件を満たす高品質のペロブスカイトの積層構造を形成することができなかった。
Next, strong epitaxial lattice strain (biaxial pressure effect) is required to stabilize the ferroelectricity with a film thickness on the order of nm.
This epitaxial lattice strain is usually controlled by using a single crystal substrate having the same perovskite structure as the ferroelectric and having a desired lattice constant.
Also, high flatness and crystallinity are essential for obtaining this effect.
In response to the above-mentioned high demands related to the quality of thin films, silicon substrates have different crystal structures and easily react chemically with metal oxides and oxygen. Therefore, a high-quality perovskite layered structure that satisfies all these conditions is used. Could not be formed.
トンネル接合の下部電極として用いるペロブスカイト酸化物層とシリコン基板の間に、平坦性制御層として、岩塩構造とペロブスカイト構造よりなる複合バッファー層を挿入する。
まず、シリコン基板の上に、シリコンとの反応を防止するために蛍石型構造のバッファー層(YSZ)を堆積し、その上に複合バッファー層としてまず岩塩型構造の酸化ストロンチウムを堆積し、ついでペロブスカイト型チタン酸酸化物を堆積する。
A composite buffer layer having a rock salt structure and a perovskite structure is inserted as a flatness control layer between the perovskite oxide layer used as the lower electrode of the tunnel junction and the silicon substrate.
First, a fluorite-type buffer layer (YSZ) is deposited on a silicon substrate to prevent reaction with silicon, and then a strontium oxide with a rock-salt structure is first deposited as a composite buffer layer. Perovskite type titanate oxide is deposited.
シリコン基板上において、高平坦性(平均荒さ0.3nm以下)、完全[001]配向、高結晶性、かつ一定の格子定数を有する高品質のペロブスカイト酸化物の薄膜積層構造を形成できる。
これにより、強誘電体をバリア層として用いたトンネル接合構造において、非常に高い平坦性を有するバリア層・電極界面を実現し、不揮発メモリ素子において、高性能の不揮発メモリ動作を提供することができる。
A high-quality perovskite oxide thin film laminated structure having high flatness (average roughness 0.3 nm or less), perfect [001] orientation, high crystallinity, and a constant lattice constant can be formed on a silicon substrate.
This realizes a barrier layer / electrode interface having very high flatness in a tunnel junction structure using a ferroelectric as a barrier layer, and can provide a high-performance nonvolatile memory operation in a nonvolatile memory element. .
図１(ａ)は、本発明に係るシリコン基板上に形成されたバッファー層積層構造と、その上に形成された強誘電体を用いたトンネル接合型の不揮発性メモリ素子の断面図である。
トンネル接合の上部電極を除く、酸化物薄膜により構成される積層構造の作製方法は次のとおりである。
FIG. 1A is a cross-sectional view of a tunnel junction type nonvolatile memory element using a buffer layer laminated structure formed on a silicon substrate according to the present invention and a ferroelectric formed thereon.
A method for manufacturing a laminated structure including an oxide thin film excluding the upper electrode of the tunnel junction is as follows.
自然酸化膜を有するシリコン(001)基板上に、反応防止層であるYSZ薄膜を基板温度800℃において酸素を供給せずに0.5nm厚により形成し、次いで酸素圧30mTorrにおいて30nm厚にパルスレーザー堆積法により形成した。
つぎに、構造・配向性制御層であるSrO薄膜を基板温度550℃, 酸素圧10mTorrで2nm厚に形成した。
つぎに、格子定数・平坦性制御層であるSrTiO3薄膜を基板温度650℃, 酸素圧10mTorrで4nm厚に形成した。
On a silicon (001) substrate with a natural oxide film, a reaction prevention layer YSZ thin film is formed with a thickness of 0.5 nm without supplying oxygen at a substrate temperature of 800 ° C., and then pulsed laser deposition to a thickness of 30 nm at an oxygen pressure of 30 mTorr Formed by the method.
Next, a SrO thin film as a structure / orientation control layer was formed to a thickness of 2 nm at a substrate temperature of 550 ° C. and an oxygen pressure of 10 mTorr.
Next, a SrTiO 3 thin film as a lattice constant / flatness control layer was formed to a thickness of 4 nm at a substrate temperature of 650 ° C. and an oxygen pressure of 10 mTorr.
上記のバッファー層を形成後、引き続いてLa0.6Sr0.4MnO3のような高い導電性を有する酸化物を下部電極層として、基板温度750℃、酸素圧力1mTorrの作製条件で、パルスレーザー堆積法により40nm厚に形成した。
さらに基板温度650℃、酸素圧力35ｍTorrの作製条件で、強誘電バリア層となるBaTiO3層を3nm厚に形成した。
After forming the above buffer layer, the oxide layer with high conductivity such as La 0.6 Sr 0.4 MnO 3 is used as the lower electrode layer, and under the conditions of the substrate temperature of 750 ° C. and the oxygen pressure of 1 mTorr by the pulse laser deposition method. The film was formed to a thickness of 40 nm.
Further, a BaTiO 3 layer serving as a ferroelectric barrier layer was formed to a thickness of 3 nm under the production conditions of a substrate temperature of 650 ° C. and an oxygen pressure of 35 mTorr.
図２(ａ)は、本発明に係る方法で作製した積層構造の、原子間力顕微鏡像により観察した表面形状像とその断面プロファイルである。
peak-to-valleyも最大1nm程度であり、表面の二乗平均平坦度は僅か0.25nmであると見積もられる。
FIG. 2A shows a surface shape image and a cross-sectional profile of the laminated structure produced by the method according to the present invention, observed with an atomic force microscope image.
The peak-to-valley is also about 1 nm at the maximum, and the root mean square flatness of the surface is estimated to be only 0.25 nm.
図２(ｂ)は、従来技術で作製したSrRuO3/SrO/YSZ積層構造の表面形状像とその断面プロファイルである。
peak-to-valleyが約10nmに達するピンホールが多数見られ、二乗平均平坦度も1.1nmであり、トンネル接合に使用することはできない。
FIG. 2B shows a surface shape image and a cross-sectional profile of the SrRuO 3 / SrO / YSZ laminated structure produced by the conventional technique.
Many pinholes with a peak-to-valley of about 10 nm are observed, and the mean square flatness is 1.1 nm, which cannot be used for tunnel junctions.
すなわち、SrTiO3とSrOのエピタキシャル薄膜よりなる複合バッファー層を用いることが平坦化のためには必須であることを示している。 That is, the use of a composite buffer layer made of an epitaxial thin film of SrTiO 3 and SrO is essential for planarization.
図３(ａ)は、本発明に係る方法で作製したBaTiO3/La0.6Sr0.4MnO3/SrTiO3/SrO/YSZ/Si積層構造において、Ｘ線回折２θ-θパターンから見積もったBaTiO3層の積層方向の格子定数を、BaTiO3層の膜厚依存性としてプロットしたものである。
BaTiO3層の積層方向の格子定数は、0.418〜0.419nmと見積もられ、バルクのc軸長さに対応する0.4038nmを大きく上回っている。
この格子定数値は、BaTiO3層の膜厚が8nm以下の範囲でほぼ一定である。
FIG. 3A shows a BaTiO 3 layer estimated from an X-ray diffraction 2θ-θ pattern in a BaTiO 3 / La 0.6 Sr 0.4 MnO 3 / SrTiO 3 / SrO / YSZ / Si laminated structure produced by the method according to the present invention. The lattice constant in the stacking direction is plotted as the film thickness dependence of the BaTiO 3 layer.
The lattice constant in the stacking direction of the BaTiO 3 layer is estimated to be 0.418 to 0.419 nm, which is much larger than 0.4038 nm corresponding to the bulk c-axis length.
This lattice constant value is almost constant when the thickness of the BaTiO 3 layer is 8 nm or less.
図３(ｂ)は本発明に係る方法で作製した、膜厚8nmのBaTiO3層を有する積層構造の(１１４)逆格子点のマッピングパターンである。
BaTiO3層・La0.6Sr0.4MnO3層・SrTiO3層を示す逆格子点の分布中心におけるqx値は、ほぼ共通であることが分かる。薄膜面内方向の格子定数は、√2/qxにより求められ、約0.391nmと見積もられる。
この値は、SrTiO3の格子定数(0.3905nm)に最も近いことから、高い平坦性と結晶性を有するSrTiO3バッファー層が、BaTiO3層とLa0.6Sr0.4MnO3層の積層面内方向の格子定数を決定していることが分かる。
その結果、SrTiO3より格子定数の大きいBaTiO3層は圧縮歪を受けて成長する。BaTiO3層の有する格子歪の大きさ(積層方向の格子定数と面内方向の格子定数の比)は、0.419/0.391=1.07に達している。
逆にSrTiO3より格子定数の小さいLa0.6Sr0.4MnO3層は、伸長歪を受けて成長する。
FIG. 3B is a mapping pattern of (114) reciprocal lattice points of a laminated structure having a BaTiO 3 layer having a thickness of 8 nm, which was produced by the method according to the present invention.
It can be seen that the q x values at the distribution centers of the reciprocal lattice points indicating the BaTiO 3 layer, La 0.6 Sr 0.4 MnO 3 layer, and SrTiO 3 layer are almost the same. The lattice constant in the in-plane direction of the thin film is obtained by √2 / q x and is estimated to be about 0.391 nm.
Since this value is closest to the lattice constant of SrTiO 3 (0.3905 nm), an SrTiO 3 buffer layer having high flatness and crystallinity is in the in-plane direction of the BaTiO 3 layer and La 0.6 Sr 0.4 MnO 3 layer. It can be seen that the lattice constant is determined.
As a result, a BaTiO 3 layer having a larger lattice constant than SrTiO 3 grows under compressive strain. The magnitude of the lattice strain of the BaTiO 3 layer (ratio of the lattice constant in the stacking direction to the lattice constant in the in-plane direction) has reached 0.419 / 0.391 = 1.07.
Conversely, a La 0.6 Sr 0.4 MnO 3 layer having a lattice constant smaller than that of SrTiO 3 grows under elongation strain.
上記の酸化物の積層構造の上に、さらに金属の上部電極を形成し、トンネル接合を作製する方法は次のとおりである。 A method for forming a tunnel junction by further forming a metal upper electrode on the above-described oxide laminated structure is as follows.
膜厚3nmのBaTiO3層を有するBaTiO3/La0.6Sr0.4MnO3/SrTiO3/SrO/YSZ/Si積層構造の上に、フォトリソグラフィーにより、3μm×3μmの大きさの素子の反転レジストパターンを作製した。次に室温で電子線蒸着によりCoのような金属を10nm厚形成し、さらに酸化防止のためAuのような金属を10nm厚に形成した。
ついで、リフトオフにより、Au/Co/BaTiO3/La0.6Sr0.4MnO3/SrTiO3/SrO/YSZ/Si不揮発性メモリ素子構造を作製した。
On the BaTiO 3 / La 0.6 Sr 0.4 MnO 3 / SrTiO 3 / SrO / YSZ / Si multilayer structure with a 3 nm-thick BaTiO 3 layer, a reverse resist pattern of 3 μm × 3 μm element is formed by photolithography. Produced. Next, a metal such as Co was formed to a thickness of 10 nm by electron beam evaporation at room temperature, and a metal such as Au was formed to a thickness of 10 nm to prevent oxidation.
Then, an Au / Co / BaTiO 3 / La 0.6 Sr 0.4 MnO 3 / SrTiO 3 / SrO / YSZ / Si nonvolatile memory element structure was fabricated by lift-off.
図４は、本発明に係る方法で作製した不揮発性メモリ素子構造において、La0.6Sr0.4MnO3とCoの間に-3V〜+3Vの範囲で掃引した場合に流れる電流を、原子間力顕微鏡の導電性チップを探針として用いて、室温にて測定した結果である。
電流-電圧特性は、特に-1V〜+1Vの電圧範囲で顕著なヒステリシスを描いており、+3Vから-3Vへ掃引した場合と、-3Vから+3Vへ掃引した場合とで特性が一致せず、両者が原点で交差している。
これは、強誘電電気分極が下向きの時と上向きの時とでトンネル障壁高さが異なることを意味し、強誘電特性に対応したトンネル抵抗状態を可逆的にスイッチする抵抗変化メモリ効果が実現されていることが分かる。
FIG. 4 shows an atomic force microscope showing the current that flows when a non-volatile memory device structure manufactured by the method of the present invention is swept between La 0.6 Sr 0.4 MnO 3 and Co in the range of −3 V to +3 V. It is the result of having measured at room temperature using the electroconductive chip | tip of this as a probe.
The current-voltage characteristics show remarkable hysteresis especially in the voltage range of -1V to + 1V, and the characteristics are the same when swept from + 3V to -3V and when swept from -3V to + 3V. Instead, they intersect at the origin.
This means that the tunnel barrier height differs between when the ferroelectric electric polarization is downward and when it is upward, and a resistance change memory effect that reversibly switches the tunnel resistance state corresponding to the ferroelectric characteristics is realized. I understand that
図１(ｂ)は本発明に係る方法で作製したバッファー層の結晶構造を示している。
YSZとSrOは結晶構造が異なるが、格子定数がほぼ同一であるため、SrOはYSZ上に良好なエピタキシャル成長が可能である。
また、SrOとSrTiO3は、結晶構造も格子定数も異なるが、SrOの構造はSrTiO3におけるSrサイト副格子の構造と同一の原子配列と組成を有するため、SrTiO3はSrO上に良好なエピタキシャル成長が可能である。
このことから、各バッファー層は、バルクに近い安定構造を維持してエピタキシャル成長しているとともに、各バッファー層間の界面も安定な状態を有していると考えられる。
その結果、SrTiO3バッファー層の表面は、単結晶基板に近い性質を有し、その上に積層するペロブスカイト薄膜に対して、完全配向性はもちろん、高平坦性・高結晶性・エピタキシャル格子歪の付与が同時に可能になったと考えられる。
FIG. 1B shows the crystal structure of the buffer layer produced by the method according to the present invention.
Although YSZ and SrO have different crystal structures, since the lattice constants are almost the same, SrO can be satisfactorily grown on YSZ.
Further, SrO and SrTiO 3 also differ crystal structure also lattice constant, the structure of SrO is to have a composition the same atomic arrangement and structure of the Sr site sublattice in SrTiO 3, SrTiO 3 is good epitaxial growth on SrO Is possible.
From this, it is considered that each buffer layer is epitaxially grown while maintaining a stable structure close to the bulk, and the interface between the buffer layers has a stable state.
As a result, the surface of the SrTiO 3 buffer layer has a property close to that of a single crystal substrate, and it has high flatness, high crystallinity, and epitaxial lattice strain as well as perfect orientation with respect to the perovskite thin film stacked on it. It is thought that the grant became possible at the same time.
積層構造におけるBaTiO3層の格子定数は、各バッファー層の膜厚に殆ど依存しない。
しかし、各バッファー層の膜厚の増大に伴い、結晶性が向上するが平坦性は劣化する傾向がある。そのため、各バッファー層の膜厚は、YSZ：10-50nm, SrO：2-3nm, SrTiO3：3-6nmの範囲から選択される。
The lattice constant of the BaTiO 3 layer in the laminated structure hardly depends on the film thickness of each buffer layer.
However, as the film thickness of each buffer layer increases, the crystallinity improves, but the flatness tends to deteriorate. Therefore, the thickness of each buffer layer is selected from the ranges of YSZ: 10-50 nm, SrO: 2-3 nm, and SrTiO 3 : 3-6 nm.
本実施例では、反応防止バッファー層としてYSZを用いたが、構造及び化学的性質の類似するHfO2であってもよい。 In this example, YSZ was used as the reaction preventing buffer layer, but HfO 2 having a similar structure and chemical property may be used.
また、本実施例では、格子定数制御バッファー層としてエピタキシャルSrTiO3薄膜を使用したが、これに代えて類似物質のSr1-xAxTiO3, (A=Ca,Ba;0<x<1)やSrTi1-xBxO3 (B=Sn,Hf,Zr; 0<x<1)などを使用すれば、その上に積層するペロブスカイト酸化物薄膜の面内格子定数を0.38nm-0.41nmの範囲の任意の値に設定することができる。
従って、この範囲の格子定数を有するペロブスカイト酸化物であれば、本発明方法により平坦性の高い高品質薄膜をSi(001)基板上に形成することが可能である。
In this example, an epitaxial SrTiO 3 thin film was used as the lattice constant control buffer layer, but instead of this, Sr 1-x A x TiO 3 , (A = Ca, Ba; 0 < x < 1 ) And SrTi 1-x B x O 3 (B = Sn, Hf, Zr; 0 < x < 1), etc., the in-plane lattice constant of the perovskite oxide thin film to be deposited is 0.38 nm-0.41 It can be set to any value in the nm range.
Therefore, a perovskite oxide having a lattice constant in this range can form a high-quality thin film with high flatness on a Si (001) substrate by the method of the present invention.
本実施例では、下部電極材料としてLa0.6Sr0.4MnO3を用いたが、金属的電気伝導度を示すことがしられているLa1-xSrxMnO3(0.2<x<0.5)の組成範囲であれば、同様に使用することができる。 In this example, La 0.6 Sr 0.4 MnO 3 was used as the lower electrode material, but the composition of La 1-x Sr x MnO 3 (0.2 < x < 0.5), which is supposed to exhibit metallic electrical conductivity If it is within the range, it can be used similarly.
本発明は、高速動作、低消費電力、非破壊読出し等の特徴を有する不揮発メモリ素子(Resistance Random Access Memory：ReRAM)として利用する事ができる。 The present invention can be used as a nonvolatile memory element (Resistance Random Access Memory: ReRAM) having features such as high-speed operation, low power consumption, and non-destructive reading.
１ Si基板
２ 反応防止バッファー層
３ 平坦性制御複合バッファー層
４ トンネル接合
５ YSZ層
６ SrO層
７ SrTiO3層
８ 下部電極層(La0.6Sr0.4MnO3)
９ トンネルバリア層(BaTiO3)
１０ 上部電極層(Co)
１１ YSZ
１２ SrO
１３ SrTiO3
１４ Srサイト副格子
１５ La0.6Sr0.4MnO3
１６ SrTiO3
１７ BaTiO3
1
9 Tunnel barrier layer (BaTiO 3 )
10 Upper electrode layer (Co)
11 YSZ
12 SrO
13 SrTiO 3
14
16 SrTiO 3
17 BaTiO 3
Claims (5)
自然酸化膜を有するシリコン（００１）基板と、
蛍石型構造の薄膜からなるバッファー層と、
岩塩構造の酸化物薄膜とその表面が平坦なペロブスカイト構造の酸化物薄膜よりなる複合バッファー層構造と、
前記複合バッファー層の上に、下部電極として電気伝導性を有するペロブスカイト酸化物薄膜と、該下部電極の上にトンネルバリア層として強誘電性を有するペロブスカイト酸化物薄膜とが、
順に積層され、
前記複合バッファー層構造のペロブスカイト構造の酸化物薄膜と、前記下部電極の電気伝導性を有するペロブスカイト酸化物薄膜、及び前記トンネルバリア層の強誘電性を有するペロブスカイト酸化物薄膜が、堆積面内方向に同じ格子定数を有するものであり、
前記トンネルバリア層の上に上部電極として金属薄膜が積層されてなることを特徴とする、不揮発性メモリ素子。 A non-volatile memory device of a tunnel junction type using a ferroelectric as a tunnel barrier layer ,
A silicon (001) substrate having a natural oxide film ;
A buffer layer made of a thin film having a fluorite structure ;
A composite buffer layer structure consisting of an oxide thin film with a rock salt structure and an oxide thin film with a perovskite structure with a flat surface ,
On the prior SL composite buffer layer, a perovskite oxide thin film having an electric conductivity as the lower electrode, the perovskite-oxide thin film having ferroelectricity as a tunnel barrier layer on the lower electrode is,
In order ,
An oxide thin film having a perovskite structure having a composite buffer layer structure, a perovskite oxide thin film having electrical conductivity of the lower electrode, and a perovskite oxide thin film having ferroelectricity of the tunnel barrier layer are disposed in a deposition in-plane direction. Have the same lattice constant ,
You wherein a metal thin film as an upper electrode on the tunnel barrier layer are laminated, non-volatile memory device.
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