JP6456799B2 - Memory controller - Google Patents

Description

  The present invention relates to a memory controller that accesses a semiconductor memory in response to a request from a host device.

  The semiconductor memory device includes a memory controller and a semiconductor memory such as a NAND flash memory. When receiving a data read instruction or a data write instruction from the host device, the memory controller controls access to the semiconductor memory in accordance with the instruction from the host device.

  Conventionally, various measures such as authentication and data encryption have been taken in order to ensure the security of data such as contents stored in a semiconductor memory. In the case of using authentication, the host device and the memory controller read data stored in the semiconductor memory after confirming the validity of each other. When encryption is used, the memory controller encrypts data read from the semiconductor memory and transmits the encrypted data to the host device. Alternatively, the memory controller encrypts the data, writes it to the semiconductor memory, decrypts the encrypted data read from the semiconductor memory, and transmits it to the host device.

  Patent Document 1 discloses a semiconductor memory device that encrypts read data when the data read from the memory cell is output to the outside. When receiving a read command from the outside, the semiconductor memory device reads data at an address designated by the read command from the memory cell. The semiconductor memory device encrypts the read data by taking an exclusive OR of the read data and the address specified by the read command using a logic circuit mounted therein. The semiconductor memory device outputs the encrypted data as a response to the read command.

JP-A-7-219852

  When encryption is used as in the semiconductor memory device according to Patent Document 1, the encryption key may be stolen by a malicious third party. When the encryption key is stolen, the security of the data stored in the semiconductor memory device is invalidated. Even when security is ensured by authentication, the security of data stored in the semiconductor memory is invalidated by stealing a password or the like used for authentication.

  If a third party succeeds in stealing the encryption key or password used to access the semiconductor memory device, the third party can read all the data stored in the semiconductor memory. It is possible to easily create a copy of stored data. As a result, there is a problem that illegal copies of semiconductor memory devices are distributed in the market.

  An object of the present invention is to provide a technique that makes it difficult to manufacture an illegal duplicate of a semiconductor memory device.

  In order to solve the above-described problem, the invention described in claim 1 is a memory controller that accesses a semiconductor memory in response to a request from a host device, and transmits the semiconductor memory with a minimum latency in response to a read command received from the host device An address acquisition unit for acquiring a latency designation address that is the address of the semiconductor memory that stores data to be stored and that is the same as the address held by the host device, and reads the data of the latency designation address from the semiconductor memory and buffers it Based on the comparison result by the comparison unit, the comparison unit that compares the address included in the read command received from the host device, the comparison unit that compares the address included in the read command received from the host device with the latency designation address acquired The timing at which the shortest latency ends And a transmission control unit for transmitting the data stored in the buffer to the host device.

  According to a second aspect of the present invention, in the memory controller according to the first aspect, the address acquisition unit specifies the latency after the transmission control unit outputs the data stored in the buffer to the host device. The address is updated, and the pre-acquisition unit reads the updated latency designation address data from the semiconductor memory, and updates the data stored in the buffer with the updated latency designation address data.

  The invention according to claim 3 is the memory controller according to claim 1, wherein the transmission control unit determines that the comparison unit determines that the address included in the read command matches the latency designation address. The transmission control unit transmits the data stored in the buffer to the host device at a timing when the shortest latency ends.

  According to a fourth aspect of the present invention, in the memory controller according to any one of the first to third aspects, the transmission control unit is configured so that the address included in the read command does not match the latency designation address. When judged by the comparison unit, the address data included in the read command is read from the semiconductor memory, and the data read from the semiconductor memory is transmitted.

  A fifth aspect of the present invention is the memory controller according to any one of the first to fourth aspects, wherein the transmission control unit compares the address when the address included in the read command matches the latency designation address. If it is determined by the unit, the data stored in the buffer is transmitted immediately after the reception of the read command is completed.

  A sixth aspect of the present invention is the memory controller according to any one of the first to fourth aspects, wherein the transmission control unit compares the address when the address included in the read command matches the latency designation address. If it is determined by the unit, the data stored in the buffer is transmitted after one busy signal and one ready signal.

  A seventh aspect of the present invention is the memory controller according to any one of the first to sixth aspects, wherein the address acquisition unit includes a random number generator that generates a random number used for generating the latency designation address. And an address generation unit that generates the latency designation address from the random number generated by the random number generator using a predetermined algorithm.

  The invention according to claim 8 is the memory controller according to any one of claims 1 to 6, wherein the address acquisition unit acquires a latency designation address generated by the host device.

  The invention according to claim 9 is a memory system, comprising: a host device; a semiconductor memory; and a memory controller that accesses the semiconductor memory in response to a request from the host device. In response to a read command received from the host device, an address acquisition unit that acquires a latency designation address that is an address of a semiconductor memory that stores data to be transmitted with the shortest latency, and reads data at the latency designation address from the semiconductor memory A pre-acquisition unit stored in the buffer, a first comparison unit that compares an address included in a read command received from the host device with a latency designation address acquired by the address acquisition unit, and a first comparison unit Based on the comparison result, the shortest latency is A transmission control unit that transmits the data stored in the buffer to the host device at a timing of termination, the host device transmitting the read command to the memory controller, and a storage unit that stores the latency designation address Before the address is stored in the buffer at the timing when the shortest latency ends based on a comparison result by the second comparison unit that compares the address included in the read command with the latency designation address and the comparison result by the second comparison unit. An access control unit for receiving the received data from the memory controller.

  A tenth aspect of the present invention is the memory system according to the ninth aspect, wherein the access control unit receives a preset period after receiving the data stored in the buffer from the memory controller. The latency designation address is updated by the time until the address acquisition unit transmits the data stored in the buffer to the host device until the preset period elapses. The latency designation address is updated, and the pre-acquisition unit reads the updated latency designation address data from the semiconductor memory, and updates the data stored in the buffer with the updated latency designation address data. .

  The invention according to claim 11 is the memory system according to claim 9 or claim 10, wherein the memory controller further includes a first random number generator for generating a first random number, and the host device is And a second random number generator for generating a second random number, wherein each of the address acquisition unit and the access control unit uses a predetermined algorithm to calculate the second random number from the first random number and the second random number. Generate a latency specified address.

  The memory controller according to the present invention transmits the data of the latency designated address stored in the buffer to the host device with the shortest latency based on the result of comparing the address included in the read command with the latency designated address. On the other hand, since the third party cannot specify the latency designated address, the memory controller in the semiconductor storage device illegally copied by the third party must transmit the data of the latency designated address to the host device with the shortest latency. I can't. That is, the memory controller of the semiconductor memory device illegally copied cannot perform the same operation as the memory controller according to the present invention. Accordingly, it is possible to make it difficult to manufacture illegally copied semiconductor memory devices.

It is a functional block diagram which shows the structure of the memory system which concerns on embodiment of this invention. It is a functional block diagram which shows the structure of the host apparatus shown in FIG. FIG. 2 is a functional block diagram showing a configuration of the semiconductor memory device shown in FIG. 1. FIG. 2 is a functional block diagram illustrating a configuration of the semiconductor memory illustrated in FIG. 1. It is a figure which shows operation | movement of the host apparatus shown in FIG. 1, and a memory controller, Comprising: It is a sequence diagram which shows operation | movement at the time of the production | generation of a latency designation | designated address. FIG. 3 is a sequence diagram showing operations of the host device and the memory controller when the host device shown in FIG. 1 transmits a read command including a normal address. FIG. 3 is a sequence diagram showing operations of the host device and the memory controller when the host device shown in FIG. 1 transmits a read command including a latency designation address. FIG. 3 is a diagram showing data transmission timing when the memory controller shown in FIG. 1 executes fixed latency processing. FIG. 3 is a diagram showing data transmission timing when the memory controller shown in FIG. 1 executes variable latency processing. FIG. 10 is a diagram showing another example of data transmission timing when the memory controller shown in FIG. 1 executes fixed latency processing. FIG. 10 is a diagram showing another example of data transmission timing when the memory controller shown in FIG. 1 executes fixed latency processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

{1. Memory system configuration}
{1.1. overall structure}
FIG. 1 is a functional block diagram showing a configuration of a memory system 100 according to an embodiment of the present invention. As shown in FIG. 1, the memory system 100 includes a host device 10 and a semiconductor memory device 20. The semiconductor memory device 20 includes a memory controller 30 and a semiconductor memory 40.

  The memory controller 30 accesses the semiconductor memory 40 in response to a request from the host device 10.

  The semiconductor memory 40 is nonvolatile, for example, a NAND flash memory. The semiconductor memory 40 stores a program 41 and content data 42 used by the host device 10. The program 41 is a program for using the content data 42.

{1.2. Configuration of Host Device 10}
FIG. 2 is a functional block diagram showing the configuration of the host device 10 shown in FIG. As shown in FIG. 2, the host device 10 includes a CPU (Central Processing Unit) 11, a RAM (Random Access Memory) 12, a random number generator 13, and a host-side controller 14. The CPU 11, RAM 12, random number generator 13, and host-side controller 14 are connected via a bus.

  The CPU 11 executes a program loaded on the RAM 12 and controls the operation of the host device 10. The RAM 12 is a main memory of the host device 10.

  The random number generator 13 generates a genuine random number. The random number generator 13 generates a random number 13A that is used to generate the latency designation address 51. The latency designation address 51 is an address for storing data to be transmitted with the shortest latency when the memory controller 30 receives a read command among the addresses of the semiconductor memory 40. The latency designation address 51 is held by the access control unit 141. Details of the latency designation address 51 will be described later.

  The host-side controller 14 controls access to the semiconductor memory device 20 by the host device 10 in accordance with an instruction from the CPU 11. The host-side controller 14 includes an access control unit 141, an address generation unit 142, a storage unit 143, and a comparison unit 144.

  The access control unit 141 transmits a command based on an instruction from the CPU 11 to the memory controller 30 and receives a response to the transmitted command. The comparison unit 144 compares the address included in the read command with the latency designation address 51.

  The address generation unit 142 generates the latency designation address 51 from the random number 13A and the random number 35A stored in the storage unit 143. The random number 35A is generated by the memory controller 30 as will be described later.

  The storage unit 143 is, for example, a register, and stores the random number 13A generated by the random number generator 13 and the random number 35A generated by the memory controller 30.

{1.3. Configuration of Memory Controller 30}
FIG. 3 is a functional block diagram showing a configuration of the semiconductor memory device 20 shown in FIG. As shown in FIG. 3, the memory controller 30 includes a command decoder 31, an address acquisition unit 32, an access control unit 33, a buffer 34, a random number generator 35, and a selector 36.

  The memory controller 30 is connected to the host-side controller 14. In FIG. 3, the display of the interface circuit (host I / F) with the host device 10 and the interface circuit (memory I / F) with the semiconductor memory 40 in the memory controller 30 is omitted.

  The command decoder 31 acquires a command transmitted from the host-side controller 14 and decodes the acquired command. For example, when receiving a read command, the command decoder 31 decodes the read command and extracts an address from the read command. The command decoder 31 outputs a read instruction and the extracted address to the access control unit 33. Hereinafter, an address included in the read command is referred to as a “read address”.

  The address acquisition unit 32 acquires a latency designation address 51. The address acquisition unit 32 includes a register 321, a register 322, and an address generation unit 323.

  The register 321 stores the random number 13A generated by the random number generator 13 (see FIG. 2). The register 322 stores the random number 35A generated by the random number generator 35. The address generation unit 323 generates a latency designation address 51 from the random number 13A stored in the register 321 and the random number 35A stored in the register 322. The address generation unit 323 and the address generation unit 142 of the host device 10 generate the same latency designation address 51.

  The access control unit 33 transmits data read from the semiconductor memory 40 to the host-side controller 14 in response to a read command from the host device 10. The access control unit 33 includes a pre-acquisition unit 331, a comparison unit 332, and a transmission control unit 333.

  The prior acquisition unit 331 instructs the semiconductor memory 40 to read the data of the latency designation address 51 acquired by the address acquisition unit 32 and stores the data of the latency specification address 51 read from the semiconductor memory 40 in the buffer 34. .

  The comparison unit 332 compares the read address with the latency designation address 51 generated by the address acquisition unit 32. The comparison unit 332 outputs the comparison result to the transmission control unit 333.

  The transmission control unit 333 reads the data at the read address from the semiconductor memory 40 or the buffer 34 according to the comparison result by the comparison unit 332 and transmits the read address data to the host-side controller 14. Specifically, when the read address matches the latency designation address 51, the transmission control unit 333 outputs the data stored in the buffer 34 to the host device 10 as a response to the read command at a timing when the latency becomes zero. . When the read address does not match the latency designation address 51, the transmission control unit 333 instructs the semiconductor memory 40 to read the data at the read address. The transmission control unit 333 outputs the data read from the semiconductor memory 40 to the host device 10 as a response to the read command.

  The buffer 34 stores data read from the semiconductor memory 40 in response to an instruction from the prior acquisition unit 331. Data stored in the buffer 34 is data of the latency designation address 51 in the semiconductor memory 40.

  The random number generator 35 generates a random number 35A. The random number 35A is used to determine the latency designation address 51. The random number generator 35 generates a genuine random number. Accordingly, the random number 35A generated by the random number generator 35 is different from the random number 13A generated by the random number generator 13.

  The selector 36 transmits one of the data stored in the buffer 34, the random number 35 </ b> A generated by the random number generator 35, and the data read from the semiconductor memory 40 in response to an instruction from the transmission control unit 333. Output to. The operation of the selector 36 is determined by the transmission control unit 333.

{1.4. Configuration of Semiconductor Memory 40}
FIG. 4 is a functional block diagram showing a configuration of the semiconductor memory 40 shown in FIG. As shown in FIG. 4, the semiconductor memory 40 is composed of a single die. The die includes J blocks. The block includes N pages. J and N are both natural numbers of 1 or more. A block is a data erasing unit in the semiconductor memory 40. The page is a data reading unit and writing unit in the semiconductor memory 40.

  In the semiconductor memory 40, the block 40B includes pages P-1 to PN. Programs 41A to 41C are stored in pages P-1 to P-3. The programs 41A to 41C constitute the program 41 shown in FIG. The programs 41A to 41C are generated by dividing the program 41 by the data size that can be stored in the page. Therefore, the programs 41A to 41C cannot be executed individually. The content data 42 is stored in the page PN.

{2. Operation of memory system}
Hereinafter, the operation of the memory system 100 will be described. A description of the logical address to physical address conversion process executed in the memory controller 30 is omitted.

{2.1. Outline}
The latency designation address 51 is generated by the host device 10 and the memory controller 30 when the power of the host device 10 is turned on. Since the latency designation address 51 is generated from the random number 13A and the random number 35A, it has a random value. The latency designation address 51 is updated after the memory controller 30 transmits the data of the latency designation address 51 to the host device 10.

  When the memory controller 30 receives a read command from the host device 10, the memory controller 30 compares the read address with the latency designation address 51. The memory controller 30 executes either one of fixed latency processing and variable latency processing according to the comparison result.

  The variable latency process is a normal read process, and is executed when the read address is an address other than the latency designation address 51. The memory controller 30 reads the read address data from the semiconductor memory 40 and transmits the read data to the host device 10.

  When variable latency processing is executed, latency of a certain time or longer occurs. Latency is the time required from when the memory controller 30 completes acceptance of the read command until the read address data is output to the host device 10. The time required to read data from the semiconductor memory 40 varies depending on the performance of the semiconductor memory 40, the read address, and the like.

  On the other hand, the fixed latency process is executed when the read address matches the latency designation address 51. In the fixed latency process, the data stored in the buffer 34 is output as a response to the read command. Although details will be described later, the latency can be made zero by executing the fixed latency processing.

  As described above, when the memory controller 30 receives a read command including the latency designation address 51, the memory controller 30 transmits the data of the latency designation address 51 to the host device 10 at a timing when the latency becomes zero. Since the latency designation address 51 has a random value, a third party cannot specify the latency designation address 51. Therefore, even if an illegal copy of the semiconductor memory device 20 is manufactured by a third party, if the memory controller in the copy receives a read command including the latency specification address 51, the data of the latency specification address 51 is transferred to the latency specification address 51. Cannot be transmitted to the host device 10 at a timing when becomes zero. Since the duplicated memory controller cannot operate in the same manner as the memory controller 30, it is difficult to manufacture an illegally duplicated product of the semiconductor memory device 20. Hereinafter, an illegally copied product of the semiconductor memory device 20 is simply referred to as a “replicated product”.

{2.2. Determination of latency designation address 51}
FIG. 5 is a sequence diagram showing operations of the host device 10 and the memory controller 30 when the latency designation address 51 is determined. The sequence diagram shown in FIG. 5 is started when the host apparatus 10 is powered on.

  First, the operation of the host device 10 will be described. When the host device 10 is powered on, the CPU 11 instructs the random number generator 13 to generate the random number 13A. The random number generator 13 generates a random number 13A in response to an instruction from the CPU 11 (step S111). The generated random number 13A is output to the CPU 11 and the host-side controller 14.

  In the host-side controller 14, the access control unit 141 stores the random number 13A input from the random number generator 13 in the storage unit 143 (step S112).

  The CPU 11 generates a random number exchange command (step S113). The CPU 11 sets the random number 13A output from the random number generator 13 in the random number exchange command. The random number exchange command is a command for transmitting the random number 13A to the memory controller 30 and requesting transmission of the random number 35A generated by the memory controller 30.

  The access control unit 141 acquires from the CPU 11 a random number exchange command in which the random number 13A is set. The host-side controller 14 transmits the acquired random number exchange command to the memory controller 30 (step S114). The access control unit 141 waits until a response to the random number exchange command is received.

  Next, the operation of the memory controller 30 will be described. The memory controller 30 is activated when the host device 10 is powered on. In the memory controller 30, the random number generator 35 generates a random number 35A (step S211). The random number generators 13 and 35 generate true random numbers. Therefore, the random numbers 13A and 35A generated immediately after the activation of the memory system 100 are different from each other.

  The random number 35A is stored in the register 322 (step S212). Specifically, the transmission control unit 333 outputs a select signal 54 for instructing output of the random number 35 </ b> A to the selector 36 immediately after the memory controller 30 is activated. The selector 36 switches the input to the random number generator 35 in accordance with the select signal 54 output from the transmission control unit 333. Thereby, the transmission control unit 333 acquires the random number 35A from the random number generator 35. The transmission control unit 333 outputs the acquired random number 35A to the register 322. The register 322 stores the random number 35A output from the transmission control unit 333.

  The memory controller 30 receives the random number exchange command transmitted from the host-side controller 14 in step S114. The memory controller 30 stores the random number 13A set in the received random number exchange command in the register 321 (step S213). Specifically, the command decoder 31 decodes the received random number exchange command, and determines that the host device 10 requests exchange of random numbers. The command decoder 31 extracts the random number 13A set in the random number exchange command and outputs it to the register 321. The register 321 stores the random number 13A output from the command decoder 31.

  The memory controller 30 transmits the random number 35A generated by the random number generator 35 to the host device 10 as a response to the received random number exchange command (step S214). Specifically, the command decoder 31 notifies the transmission control unit 333 that the random number exchange command has been received. In response to the notification from the command decoder 31, the transmission control unit 333 transmits the random number 35A acquired from the random number generator 35 as a response to the random number exchange command.

  The address acquisition unit 32 generates a latency designation address 51 (step S215). Specifically, the address generation unit 323 generates a latency designation address 51 from the random number 13A stored in the register 321 and the random number 35A stored in the register 322 using a preset algorithm. The algorithm is not particularly limited, and for example, a pseudo-random number generation algorithm, HMAC (Hash-based Message Authentication Code), or the like can be used.

  The memory controller 30 reads data at the latency designation address 51 from the semiconductor memory 40 (step S216). Specifically, the address generation unit 323 outputs the generated latency designation address 51 to the prior acquisition unit 331. The prior acquisition unit 331 outputs the latency designation address 51 to the semiconductor memory 40 and instructs the semiconductor memory 40 to read data of the latency designation address 51. The semiconductor memory 40 reads data at the latency designation address 51 in accordance with an instruction from the prior acquisition unit 331. The data of the latency designation address 51 read from the semiconductor memory 40 is stored in the buffer 34 (step S217). Thereby, the processing of the memory controller 30 at the time of starting the memory system 100 ends.

  In the host device 10, the access control unit 141 receives the random number 35A as a response to the random number exchange command. The access control unit 141 stores the received random number 35A in the storage unit 143 (step S115).

  The address generation unit 142 generates the latency designation address 51 from the random numbers 13A and 35A stored in the storage unit 143 (step S116). The algorithm used by the address generator 142 to generate the latency designation address 51 is the same as the algorithm used by the address generator 323 of the memory controller 30. Accordingly, the latency designation address 51 generated by the address generation unit 142 is the same as the latency designation address 51 generated by the address generation unit 323 of the memory controller 30.

{2.3. Variable latency processing}
FIG. 6 is a sequence diagram illustrating operations of the host device 10 and the memory controller 30 when the host device 10 transmits a read command including an address other than the latency designation address 51. Hereinafter, an address other than the latency designation address 51 is referred to as a “normal address”.

  The host device 10 executes steps S311 to S314, and transmits a read command including a normal address to the memory controller 30. In the host device 10, the CPU 11 generates a read command and sets a read address in the generated read command. In the example shown in FIG. 6, the read address to be set is a normal address. Thereby, a read command including the normal address is generated (step S311).

  The CPU 11 outputs the generated read command to the access control unit 141. The comparison unit 144 inputs the latency designation address 51 and the read address included in the read command from the access control unit 141, and compares the read address with the latency designation address 51 (step S312).

  In the example shown in FIG. 6, since the normal address is set as the read address in the read command, the comparison unit 144 determines that the two addresses to be compared do not match and notifies the access control unit 141 of the comparison result. . Based on the notification from the comparison unit 144, when the access control unit 141 transmits a read command to the memory controller 30, the access control unit 141 determines that the memory controller 30 executes variable latency processing. The access control unit 141 determines the start of access control for variable latency processing (step S313).

  The access control unit 141 transmits the read command supplied from the CPU 11 to the memory controller 30 (step S314). The access control unit 141 starts access control for variable latency processing. Specifically, the access control unit 141 waits until a ready signal transmitted from the memory controller 30 is received (step S315).

  In the memory controller 30, the command decoder 31 receives the read command transmitted from the host device 10 in step S314. The command decoder 31 decodes the received read command. As a result, the command decoder 31 determines that reading has been instructed by the host device 10, and extracts a read address from the received read command (step S411).

  The command decoder 31 outputs the decoding result (read instruction and extracted read address) to the comparison unit 332 and the transmission control unit 333. The comparison unit 332 compares the read address acquired from the command decoder 31 with the latency designation address 51 (step S412). In the example illustrated in FIG. 6, since the normal address is set as the read command in the read command, the comparison unit 332 notifies the transmission control unit 333 that the read address does not match the latency designation address 51. Based on the notification from the comparison unit 332, the transmission control unit 333 determines the execution of variable latency processing for reading the read address data from the semiconductor memory 40 (step S413). The variable latency process corresponds to the processes in steps S414 to S418.

  The transmission control unit 333 starts transmitting a busy signal to the host device 10 (step S414). Further, the transmission control unit 333 outputs an access control signal instructing reading of data at the read address to the semiconductor memory 40 (step S415). The transmission control unit 333 transmits a select signal 54 to the selector 36 so that the read address data can be read from the semiconductor memory 40.

  The transmission control unit 333 waits until a latency signal is output from the semiconductor memory 40 while continuing to transmit the busy signal. The latency signal is a signal for notifying that the data at the read address can be read from the semiconductor memory 40. When the transmission control unit 333 detects a latency signal (step S416), the transmission control unit 333 transmits a ready signal to the host device 10 (step S417). The transmission control unit 333 reads the read address data from the semiconductor memory 40. The transmission control unit 333 transmits the read address data to the host device 10 following the ready signal (step S418).

  In the host device 10, when the ready signal is transmitted from the memory controller 30, the access control unit 141 determines that transmission of the read address data is started. The access control unit 141 receives data transmitted after the ready signal as read address data. The access control unit 141 supplies read address data to the CPU 11. The CPU 11 executes processing using read address data.

{2.4. Fixed latency processing}
FIG. 7 is a sequence diagram illustrating operations of the host device 10 and the memory controller 30 when the host device 10 transmits a read command including the latency designation address 51.

  As illustrated in FIG. 7, the host device 10 executes Steps S <b> 511 to S <b> 513 and transmits a read command including the latency designation address 51 to the memory controller 30. Specifically, the CPU 11 generates a read command and sets a read address in the generated read command. In the example shown in FIG. 7, a latency designation address 51 is set in the read command as a read address. As a result, a read command including the latency designation address 51 is generated (step S511).

  The CPU 11 outputs the generated read command to the access control unit 141. The comparison unit 144 inputs the latency designation address 51 and the read address included in the read command from the access control unit 141, and compares the read address with the latency designation address 51 (step S512).

  In the example shown in FIG. 7, since the latency designation address 51 is set as the read command in the read command, the comparison unit 144 determines that the two addresses to be compared match and notifies the access control unit 141 of the comparison result. To do. Based on the notification from the comparison unit 144, when the access control unit 141 transmits a read command to the memory controller 30, the access control unit 141 determines that the memory controller 30 executes fixed latency processing. The access control unit 141 starts access control for fixed latency processing (step S513). The access control for fixed latency processing will be described later.

  The access control unit 141 transmits the read command supplied from the CPU 11 to the memory controller 30 (step S514).

  When the memory controller 30 receives the read command transmitted from the host device 10 in step S514, the memory controller 30 executes steps S611 to S615 and transmits the data of the latency designation address 51 to the host device 10.

  Specifically, the command decoder 31 decodes the read command. As a result of the decoding, the command decoder 31 determines that reading has been instructed from the host device 10, and extracts a read address from the read command (step S611). The command decoder 31 outputs the decoding result (read instruction and extracted read address) to the comparison unit 332 and the transmission control unit 333.

  The comparison unit 332 compares the read address output from the command decoder 31 with the latency designation address 51 (step S612). In the example shown in FIG. 7, a latency designation address 51 is set in the read command as a read address. For this reason, the comparison unit 332 determines that the two addresses to be compared match, and notifies the transmission control unit 333 of the comparison result. The transmission control unit 333 determines execution of the fixed latency processing based on the notification from the comparison unit 332 (step S613).

  The transmission control unit 333 outputs the select signal 54 instructing connection with the buffer 34 to the selector 36, and reads the data of the latency designation address 51 stored in the buffer 34 (step S614). The transmission control unit 333 transmits the read data of the latency designation address 51 to the host device 10 (step S615). The memory controller 30 does not output the busy signal and the ready signal until the data of the latency designation address 51 is transmitted after the read command is received. The data of the latency designation address 51 is transmitted immediately after the memory controller 30 receives the read command. That is, when the latency designation address 51 is included in the read command, the memory controller 30 transmits the data of the latency designation address 51 at a timing when the latency becomes zero.

  The access control for fixed latency processing executed by the host device 10 will be described. As described above, when executing the fixed latency process, the memory controller 30 transmits the data of the latency designation address 51 immediately after receiving the read command without transmitting the busy signal and the ready signal. For this reason, the access control unit 141 does not wait until a ready signal is received in the access control for fixed latency processing. Since the timing when the transmission of the read command is completed is the timing when the latency is zero, the access control unit 141 acquires the data received from the memory controller 30 immediately after the transmission of the read command as the data of the latency designation address 51. .

  Hereinafter, the reason why the memory controller 30 can transmit the data of the latency designation address 51 immediately after receiving the read command in the fixed latency processing will be described. FIG. 8 is a diagram illustrating the transmission timing of data at the latency designation address 51 when the memory controller 30 executes the fixed latency process. As shown in FIG. 8, the read command includes a 1-byte command ID and a 2-byte read address. The command ID is a value that uniquely indicates a read command. The command decoder 31 receives a read command byte by byte. Therefore, the command decoder 31 can determine that the host device 10 has instructed reading of data from the semiconductor memory 40 when the first byte of the read command is received. The command decoder 31 outputs a 2-byte read address subsequent to the command ID to the comparison unit 332 byte by byte for address comparison.

  The comparison unit 332 compares the read address with the latency designation address 51 byte by byte. The comparison unit 332 notifies the transmission control unit 333 of the comparison result when the comparison of the last 1 byte of the read address is completed. The transmission control unit 333 controls the selector 36 so as to output the data stored in the buffer 34 according to the notified comparison result. The transmission control unit 333 transmits the data output from the buffer 34 (data at the latency designation address 51) to the host device 10 as it is. As a result, the memory controller 30 can transmit the data of the latency designation address 51 to the host device 10 immediately after receiving the read command. That is, as shown in FIG. 8, the data of the latency designation address 51 is transmitted to the host device 10 at the timing when the latency becomes zero.

{2.5. Update of latency specification address 51}
When the process shown in FIG. 7 is completed, the latency designation addresses 51 held by the host device 10 and the memory controller 30 are updated. The procedure for updating the latency designation address 51 is executed in the same procedure as the processing shown in FIG. The update of the latency designation address 51 is executed in the memory controller 30 after the data of the latency designation address 51 is transmitted until the next read command is received. In the host device 10, the update of the latency designation address 51 is executed after the data of the latency designation address 51 is received until the next read command is generated. That is, the host device 10 and the memory controller 30 are updated within a preset period after the data reading process of the latency designation address 51 is completed.

  In FIG. 5, when the latency designation address 51 is updated, the host device 10 generates a new random number different from the random number 13A after the processing related to the read command is completed (step S111). In addition, the memory controller 30 generates a new random number different from the random number 35A (step S211). The new random number generated by the host device 10 and the new random number generated by the memory controller 30 are exchanged between the host device 10 and the memory controller 30 (steps S114 and S214). The host device 10 and the memory controller 30 newly generate a latency designation address 51 from the two generated new random numbers (steps S116 and S215). Each time the data of the latency designation address 51 is transmitted to the host device 10, the latency designation address 51 is randomly changed. Therefore, the third party cannot know in advance the address of the data read at the timing when the latency becomes zero.

{2.6. Difficulty in manufacturing replica of semiconductor memory device 20}
Next, the reason why it becomes difficult for a third party to manufacture a duplicate by transmitting the data of the latency designation address 51 at the timing when the latency becomes zero will be described.

  FIG. 9 is a diagram illustrating the timing at which the read address data is transmitted when the memory controller 30 executes the variable latency process. In FIG. 9, the read command has the same configuration as the read command shown in FIG.

  As illustrated in FIG. 9, when executing the variable latency process, the memory controller 30 starts transmitting a busy signal after receiving a read command. The memory controller 30 continues to transmit the busy signal until it becomes possible to read the data at the read address from the semiconductor memory 40. The memory controller 30 transmits a ready signal to the host device 10 when reading from the semiconductor memory 40 becomes possible. Following the transmission of the ready signal, the read address data is transmitted to the host device 10.

  On the other hand, as shown in FIG. 8, the data of the latency designation address 51 is transmitted to the host device 10 by the fixed latency processing. In this case, the memory controller 30 starts transmission of data of the latency designation address 51 at a timing when the latency becomes zero after the reception of the read command is completed. In contrast, the third party cannot specify the latency designation address 51 because the latency designation address 51 has a random value. Therefore, even if the replicated memory controller receives a read command including the latency designation address 51, the data of the latency designation address 51 cannot be transmitted to the host device 10 at a timing when the latency becomes zero. As a result, a third party cannot manufacture a replica of the semiconductor storage device 20.

  The latency designation address 51 is updated at random each time the data of the latency designation address 51 is read by the host device 10. Even when the latency designation address 51 is temporarily leaked, the latency designation address 51 has already been updated at the time of leakage. Therefore, it is possible to further make it difficult to specify the latency designation address 51 by a third party, and it is possible to make it difficult to manufacture a duplicate product.

  Since the memory controller of the copy product cannot transmit the data of the latency designation address 51 to the host device 10 by the fixed latency process, the host device 10 cannot process the data recorded on the copy product. Hereinafter, an example in which the address of the page P-2 is the latency designation address 51 will be described with reference to FIG. When the host device 10 transmits a read command including the address of the page P-2 to the memory controller 30, the host device 10 executes access control for fixed latency processing. However, the replicated memory controller transmits the data (program 41B) of the address of page P-2 by variable latency processing. The host device 10 specifies the legitimate program 41B in order to process the busy signal and the ready signal transmitted from the replica memory controller as the address data of the page P-2 by the access control for the fixed latency processing. I can't. The host device 10 cannot reconfigure the program 41 and cannot execute the program 41. As a result, a third party cannot manufacture a copy that can be used by the host device 10.

  In the semiconductor memory 40, the address set as the latency designation address 51 is preferably an address that is highly likely to be read by the host device 10. The address that is the target of the latency designation address 51 is preferably an address of data that is read at least once by the host device 10 such as a page that stores the boot code of the host device 10. Or you may limit to the address of the area | region where the host device 10 has high access frequency.

  As described above, in the present embodiment, the host device 10 and the memory controller 30 generate the latency designation address 51 from the random numbers 13A and 35A, read the data of the latency designation address 51 from the semiconductor memory 40, and store it in the buffer 34. Store. When the memory controller 30 is instructed to read the data of the latency designation address 51, the memory controller 30 transmits the data of the latency designation address 51 stored in the buffer 34 to the host device 10 at a timing when the latency becomes zero. That is, the memory controller 30 stores the data of the latency designation address 51 in the buffer 34 by transmitting the data of the latency designation address 51 at the timing when the latency that cannot be realized by the normal reading process becomes zero. Realized. Furthermore, since the latency designation address 51 is set at random, a third party cannot specify the latency designation address 51. As a result, the memory controller of the semiconductor memory device illegally copied by a third party cannot transmit the data of the latency designation address 51 at the timing when the latency becomes zero. As a result, it is possible to make it difficult to manufacture an illegal duplicate of the semiconductor memory device 20.

{Modification}
In the above embodiment, the example in which the memory controller 30 outputs the data of the latency designation address 51 immediately after receiving the read command has been described, but the present invention is not limited to this.

  FIG. 10 is a diagram illustrating another example of timing at which data of the latency designation address 51 is transmitted from the memory controller 30. As illustrated in FIG. 10, when the memory controller 30 receives a read command, the memory controller 30 outputs a preset pattern (one busy signal and one ready signal), and then sends the data of the latency designation address 51 to the host device 10. May be sent to.

  For example, when the transmission control unit 333 transmits the data of the address included in the read command, there may be a case where the specification is such that at least one busy signal and one ready signal must be output. In this case, the transmission control unit 333 can respond to the read command with the shortest latency by transmitting data of the latency designation address 51 after transmitting one busy signal and one ready signal. That is, the shortest latency is the shortest time in which the memory controller can start transmitting the data at the read address when the memory controller receives the read command. In the example shown in FIG. 10, the shortest latency is shorter than the period from when the memory controller 30 instructs the semiconductor memory 40 to output the read address data until the read address data is acquired. In other words, the transmission control unit 333 transmits the data of the latency designation address 51 at a timing earlier than when the read address data is transmitted by the variable latency process. Even in this case, since the third party cannot specify the latency designation address 51, it is possible to make it difficult for the third party to manufacture a duplicate.

  Further, when the memory controller 30 transmits one busy signal and one ready signal in the fixed latency processing, the host device 10 may determine whether or not the semiconductor memory device 20 has been illegally copied. Is possible. This will be specifically described below.

  As described above, even when the memory controller of the replicated product receives a read command including the latency designation address 51, it executes variable latency processing and transmits the data of the latency designation address 51 to the host device 10. That is, the replicated memory controller does not transmit a preset pattern (one busy signal and one ready signal) immediately after receiving the read command including the latency designation address 51. When the host device 10 cannot receive the busy signal and ready signal of the preset pattern before transmitting the data of the latency designation address 51, the connected semiconductor memory device is illegally copied. As a result, access to the connected semiconductor memory device can be stopped.

  Further, the predetermined pattern is not limited to the example shown in FIG. For example, as illustrated in FIG. 11, the memory controller 30 may transmit only one ready signal before transmitting data of the latency designation address 51. Alternatively, the memory controller 30 may transmit a plurality of busy signals and one ready signal, or may transmit a pattern unrelated to the busy signal and the ready signal.

  In the above embodiment, the example in which the update of the latency designation address 51 is performed after the memory controller 30 transmits the data of the latency designation address 51 has been described. However, the present invention is not limited to this. The latency designation address 51 may be updated periodically or may not be updated.

  In the above embodiment, the example in which the latency designation address 51 is generated from the random numbers 13A and 35A has been described. However, the present invention is not limited to this. For example, the latency designation address 51 may be generated only from the random number 13A. In this case, steps S115, S211, S212, and S214 shown in FIG. 5 are omitted. Alternatively, the latency designation address 51 may be generated only from the random number 35A. In this case, the processing of S111 to S114 and S213 shown in FIG. 5 is omitted.

  In the above embodiment, the example in which the random numbers generated by the host device 10 and the memory controller 30 are exchanged has been described. However, the present invention is not limited to this. When the random number generators 13 and 35 are pseudo random number generators that use the same algorithm, the exchange of random numbers can be omitted. Specifically, both of the random number generators 13 and 35 generate the same pseudo-random number by updating the random number generated at a preset timing. Thereby, since the host device 10 and the memory controller 30 do not need to exchange random numbers, the confidentiality of the latency designation address 51 can be improved. The timing for updating the random number may be, for example, when a read process based on the read command is performed a predetermined number of times, or when the host device 10 transmits a command instructing to update the random number. Note that the use of the above pseudo-random numbers does not limit the exchange of random numbers. For example, the random number generators 13 and 35 may generate pseudo-random numbers using different algorithms. In this case, the pseudo random numbers generated by the random number generators 13 and 35 are exchanged.

  In the above embodiment, the host device 10 and the memory controller 30 each generate the latency designation address 51. However, the present invention is not limited to this. It is only necessary that the host device 10 and the memory controller 30 hold the same latency designation address 51.

  For example, only the host device 10 may generate the latency designation address 51. In this case, the latency designation address 51 is generated only from the random number 13A. The host device 10 may transmit the generated latency designation address 51 to the memory controller 30 instead of the random number exchange command. Conversely, only the memory controller 30 may generate the latency designation address 51 and transmit the generated latency designation address 51 to the host device 10.

  Alternatively, the initial value of the latency designation address 51 may be set in advance in the host device 10 and the memory controller 30. Alternatively, the initial value of the latency designation address 51 may be set in advance only for the host device 10. In this case, the host device 10 may transmit the address of the latency designation address 51 to the memory controller 30 at the time of activation.

  In addition, part or all of the memory controller 30 described in the above embodiments may be realized as an integrated circuit (for example, an LSI, a system LSI, or the like).

  In addition, a part or all of each processing in the above embodiment may be realized by hardware, or may be realized by software (including a case where it is realized together with an OS (operating system), middleware, or a predetermined library). It may be realized. Further, it may be realized by mixed processing of software and hardware.

  While the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.

100 memory system 10 host device 11 CPU
12 RAM
13, 35 Random number generator 14 Host-side controller 20 Semiconductor storage device 30 Memory controller 31 Command decoder 32 Address acquisition unit 33, 141 Access control unit 34 Buffer 36 Selector 40 Semiconductor memory 51 Latency designation address 142, 323 Address generation unit 143 Storage unit 144, 332 Comparison unit 331 Prior acquisition unit 333 Transmission control unit

Claims (11)

A memory controller that accesses a semiconductor memory in response to a request from a host device,
An address acquisition unit that acquires a latency designation address that is the address of a semiconductor memory that stores data to be transmitted with the shortest latency in response to a read command received from the host device and is the same as the address held by the host device When,
A pre-acquisition unit that reads the data of the latency designation address from the semiconductor memory and stores it in a buffer;
A comparison unit that compares an address included in a read command received from the host device with a latency designation address acquired by the address acquisition unit;
A transmission control unit that transmits the data stored in the buffer to the host device at a timing when the shortest latency ends based on a comparison result by the comparison unit;
A memory controller. The memory controller of claim 1,
The address acquisition unit updates the latency designation address after the transmission control unit transmits the data stored in the buffer to the host device,
The pre-acquisition unit is a memory controller that reads updated latency designation address data from the semiconductor memory and updates the data stored in the buffer with the updated latency designation address data. The memory controller of claim 1,
If the comparison unit determines that the address included in the read command matches the latency designation address, the transmission control unit stores the transmission control unit in the buffer at a timing when the shortest latency ends. A memory controller that transmits data to the host device. A memory controller according to any one of claims 1 to 3,
The transmission control unit reads data of an address included in the read command from the semiconductor memory when the comparison unit determines that an address included in the read command does not match the latency designation address, and the semiconductor memory Memory controller that transmits data read from the memory. A memory controller according to any one of claims 1 to 4,
The transmission control unit transmits the data stored in the buffer immediately after completing the reception of the read command when the comparison unit determines that the address included in the read command matches the latency designation address. Memory controller. A memory controller according to any one of claims 1 to 4,
When the comparison unit determines that the address included in the read command matches the latency designation address, the transmission control unit stores data stored in the buffer after one busy signal and one ready signal. Send memory controller. A memory controller according to any one of claims 1 to 6,
The address acquisition unit
A random number generator for generating a random number used to generate the latency designation address;
Using a predetermined algorithm, an address generation unit that generates the latency designation address from the random number generated by the random number generator;
Including memory controller. A memory controller according to any one of claims 1 to 6,
The address acquisition unit is a memory controller that acquires a latency designation address generated by the host device. A host device;
Semiconductor memory,
A memory controller that accesses the semiconductor memory in response to a request from the host device;
With
The memory controller is
An address acquisition unit that acquires a latency designation address that is an address of a semiconductor memory that stores data to be transmitted with the shortest latency in response to a read command received from the host device;
A pre-acquisition unit that reads the data of the latency designation address from the semiconductor memory and stores it in a buffer;
A first comparison unit that compares an address included in a read command received from the host device with a latency designation address acquired by the address acquisition unit;
A transmission control unit configured to transmit data stored in the buffer to the host device at a timing when the shortest latency ends based on a comparison result by the first comparison unit;
With
The host device is
A storage unit for storing the latency designation address;
A second comparison unit that compares an address included in the read command with a latency designation address stored in the storage unit before transmitting the read command to the memory controller;
An access control unit that receives data stored in the buffer from the memory controller at a timing when the shortest latency ends based on a comparison result by the second comparison unit;
A memory system comprising: The memory system according to claim 9, comprising:
The access control unit updates the latency designation address until a preset period elapses after receiving the data stored in the buffer from the memory controller,
The address acquisition unit updates the latency designation address until the preset period elapses after the transmission control unit transmits the data stored in the buffer to the host device.
The pre-acquisition unit reads the updated latency designation address data from the semiconductor memory, and updates the data stored in the buffer with the updated latency designation address data. The memory system according to claim 9 or 10, wherein
The memory controller further includes:
A first random number generator for generating a first random number;
With
The host device further includes:
A second random number generator for generating a second random number;
With
Each of the address acquisition unit and the access control unit generates a latency designation address from the first random number and the second random number using a predetermined algorithm.

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