JP6452838B2 - Vector composition type phase shifter and wireless communication device - Google Patents

Description

  The present invention relates to a vector synthesizing phase shifter that shifts the phase of an input signal, and a wireless communication device that implements the vector synthesizing phase shifter.

For example, a vector synthesis type phase shifter that shifts the phase of an RF (radio frequency) signal that is a high-frequency signal has a polyphase filter that extracts an I signal (in-phase signal) and a Q signal (quadrature signal) from the RF signal. The polyphase filter is generally realized by a resistor and a capacitor. Hereinafter, a polyphase filter realized by a resistor and a capacitor is referred to as an RC polyphase filter. The I signal and the Q signal have the property that the phase difference is 90 ° and the amplitude is equal.
The RC type polyphase filter is arranged at the first stage of the vector synthesis type phase shifter, but the RC type polyphase filter has a large signal passing loss and has a passing loss of −3 dB or more per stage. For this reason, the noise characteristics of the vector synthesis type phase shifter are deteriorated.

Non-Patent Document 1 below discloses a vector synthesis type phase shifter in which an LC type polyphase filter realized by an inductor element and a capacitive element is mounted instead of an RC type polyphase filter.
The ideal pass loss of the LC polyphase filter is 0 dB, and noise and high gain can be achieved as compared with the RC polyphase filter.

“An Improved Wideband All-Pass I / Q Network for Millimeter-Wave Phase Shifters”, Sang Young Kim, MTT, 2012, Vol.60

Since the conventional vector synthesis type phase shifter is configured as described above, if the LC type polyphase filter is mounted, good noise characteristics can be obtained, but the LC type polyphase filter becomes a load. Since it is sensitive to changes in the input impedance of the variable gain circuit, the orthogonality tends to deteriorate. The deterioration of the orthogonality directly leads to the deterioration of the phase shift accuracy of the vector synthesis type phase shifter.
The deterioration of the orthogonality of the LC type polyphase filter is caused not only by the manufacturing error of the LC type polyphase filter but also by the fluctuation of the input impedance of the variable gain circuit due to the manufacturing variation in addition to the usage environment such as temperature and power supply. It is. For this reason, the LC type polyphase filter has a problem that it is difficult to apply to a vector synthesis type phase shifter that is weak against manufacturing variations and changes in use environment and requires high phase shift accuracy.
For this reason, the vector synthesis type phase shifter mounted with the LC type polyphase filter achieves lower noise and higher gain than the vector synthesis type phase shifter mounted with the RC type polyphase filter. However, when high phase shift accuracy is required, the yield is deteriorated.
The phase shift accuracy is the accuracy related to the error between the set value of the phase shift amount in the vector synthesis type phase shifter and the phase shift amount actually observed from the output signal of the vector synthesis type phase shifter. The mean square error of errors for all set values is called phase shift accuracy.

The present invention has been made in order to solve the above-described problems. It is an object of the present invention to obtain a vector synthesis type phase shifter that can achieve low noise and high gain and can improve the phase shift accuracy. Objective.
It is another object of the present invention to obtain a radio communication device equipped with a vector synthesizing phase shifter capable of reducing noise and increasing gain and improving phase shift accuracy.

A vector synthesis type phase shifter according to the present invention is a filter including an inductor element and a capacitive element, a polyphase filter that extracts an in-phase signal and a quadrature signal from an input signal, and an in-phase signal extracted by the polyphase filter A first variable gain amplifier whose input impedance changes when the bias current of the transistor changes, and a quadrature signal extracted by a polyphase filter The input signal is amplified by a second variable gain amplifier whose input impedance changes when the bias current of the transistor changes , and the first variable gain amplifier. Combining the in-phase signal and the quadrature signal amplified by the second variable gain amplifier, the in-phase signal A signal synthesizer for outputting a synthesized signal of orthogonal signals, and the gain controller changes the amplitude of the synthesized signal output from the signal synthesizer by controlling the gains of the first and second variable gain amplifiers. Instead, the phase of the combined signal is adjusted, and the bias control unit controls the bias current of the transistors in the input stage of the first and second variable gain amplifiers.

  According to the present invention, the gain control unit controls the gains of the first and second variable gain amplifiers to change the phase of the combined signal without changing the amplitude of the combined signal output from the signal combining unit. Since the bias control unit is configured to control the bias current of the transistors in the input stage included in the first and second variable gain amplifiers, the noise can be reduced and the gain can be increased. There is an effect that the phase accuracy can be increased.

It is a block diagram which shows the vector synthetic | combination type phase shifter by Embodiment 1 of this invention. It is a block diagram which shows VGA5 for I of the vector synthetic | combination type phase shifter by Embodiment 1 of this invention. It is a block diagram which shows VGA6 for Q of the vector synthetic | combination type phase shifter by Embodiment 1 of this invention. It is a block diagram which shows the inside of the variable current sources 13a and 13b of VGA5 for I. It is a block diagram which shows the inside of the variable current sources 23a and 23b of VGA6 for Q. It is a block diagram which shows the bias control part 10 of the vector composition type phase shifter by Embodiment 1 of this invention. It is explanatory drawing which shows the circuit where LPF3 and HPF4 were simplified. It is explanatory drawing which shows the passage gain characteristic and passage phase characteristic of LPF3 and HPF4. It is explanatory drawing which shows a mode that the orthogonality of I signal and Q signal output from LPF3 and HPF4 changes by adjusting the termination impedances 51 and 52. FIG. It is explanatory drawing which shows the circuit simulation result of the passage phase difference of LPF3 and HPF4 when the termination impedances 51 and 52 are changed from 90% to 110%, and the passage gain difference of LPF3 and HPF4. It is explanatory drawing which shows the image of the setting gain to I VGA5 and Q VGA6 in the case of setting the passage phase of a vector synthetic | combination type phase shifter to 60 degrees and 135 degrees. It is explanatory drawing which shows the relationship between the control signal voltage of the variable gain parts 18 and 28 of I VGA5 and Q VGA6, and the current gain of the variable gain parts 18 and 28. FIG. It is explanatory drawing which shows an example of the lookup table memorize | stored in the table part. It is a block diagram which shows the vector synthetic | combination type phase shifter by Embodiment 2 of this invention. It is a block diagram which shows the bias control part 10 of the vector composition type | mold phase shifter by Embodiment 2 of this invention. It is a block diagram which shows the vector synthetic | combination type phase shifter by Embodiment 3 of this invention. It is a block diagram which shows a part of inside of VGA5 for I and VGA6 for Q of the vector synthetic | combination type phase shifter by Embodiment 3 of this invention. It is a block diagram which shows the vector synthetic | combination type phase shifter by Embodiment 4 of this invention. It is a block diagram which shows a part of VGA5 for I and VGA6 for Q of the vector synthetic | combination type phase shifter by Embodiment 4 of this invention. It is a block diagram which shows VGA5 for I of the vector composition type | mold phase shifter by Embodiment 5 of this invention. It is a block diagram which shows VGA6 for Q of the vector synthetic | combination type phase shifter by Embodiment 5 of this invention. It is a block diagram which shows the unit cell mounted in the variable gain parts 121,122,131,132.

  Hereinafter, in order to describe the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG.
1 is a block diagram showing a vector synthesis type phase shifter according to Embodiment 1 of the present invention.
The vector synthesis type phase shifter of FIG. 1 is mounted on a radio communication device such as a radio transmitter or a radio receiver, for example, and an RF signal whose phase is shifted by the vector synthesis type phase shifter is wireless. It is assumed that the signal is transmitted by a communication device, or the phase of an RF signal received by a wireless communication device is shifted by a vector synthesis type phase shifter.
In FIG. 1, input terminals 1a and 1b are terminals to which a differential RF (radio frequency) signal which is an input signal of a vector synthesis type phase shifter is input. In the first embodiment, an example in which the input signal of the vector synthesis type phase shifter is an RF signal will be described. However, the input signal is not limited to the RF signal, and a signal having a frequency other than the radio frequency is input. It may be.

The polyphase filter 2 includes a low-pass filter (LPF) 3 and a high-pass filter (HPF) 4, and a differential RF input from input terminals 1 a and 1 b. An I (In-phase) signal that is an in-phase signal and a Q (Quadrature) signal that is a quadrature signal are extracted from the signal.
The LPF 3 includes inductor elements 3a and 3b and capacitive elements 3c and 3d, and extracts an I signal from a differential RF signal input from the input terminals 1a and 1b.
The inductor element 3a is inserted on a signal line connecting the input terminal 1a and an input terminal 5a of an I VGA (Variable Gain Amplifier) 5 and the inductor element 3b connects the input terminal 1b and the input terminal 5b of the I VGA 5. It is inserted on the signal line.
The capacitive element 3c is connected between a signal line connecting the input terminal 1a and the input terminal 5a of the I VGA 5 and the ground, and the capacitive element 3d is a signal line connecting the input terminal 1b and the input terminal 5b of the I VGA. And the ground.

The HPF 4 includes capacitive elements 4a and 4b and inductor elements 4c and 4d, and extracts a Q signal from the differential RF signal input from the input terminals 1a and 1b.
The capacitive element 4a is inserted on a signal line connecting the input terminal 1a and the input terminal 6a of the Q VGA 6, and the capacitive element 4b is inserted on a signal line connecting the input terminal 1b and the input terminal 6b of the Q VGA 6. Yes.
The inductor element 4c is connected between a signal line connecting the input terminal 1a and the input terminal 6a of the Q VGA 6 and the ground, and the inductor element 4d is a signal line connecting the input terminal 1b and the input terminal 6b of the Q VGA 6. And the ground.

The I VGA 5 has an input stage transistor for inputting a differential I signal extracted by the LPF 3, and is a first variable gain amplifier that amplifies the differential I signal.
The input terminals 5a and 5b are terminals for inputting a differential I signal output from the LPF 3.
The output terminals 5c and 5d are terminals for outputting differential I signals amplified by the I VGA 5.
The gain control terminal 5e is a terminal for inputting the gain control signal output from the gain control unit 9.
The bias control terminal 5 f is a terminal for inputting a bias control signal output from the bias control unit 10.

The Q VGA 6 has an input stage transistor for inputting a differential Q signal extracted by the HPF 4 and is a second variable gain amplifier for amplifying the differential Q signal.
The input terminals 6a and 6b are terminals for inputting a differential Q signal output from the HPF 4.
The output terminals 6c and 6d are terminals for outputting a differential Q signal amplified by the Q VGA 6.
The gain control terminal 6e is a terminal for inputting the gain control signal output from the gain control unit 9.
The bias control terminal 6 f is a terminal for inputting a bias control signal output from the bias control unit 10.

The signal synthesizer 7 includes load impedances 7a and 7b. The signal synthesizer 7 synthesizes the differential I signal amplified by the I VGA 5 and the differential Q signal amplified by the Q VGA 6, and outputs the I signal. And a synthesized signal of the Q signal are output.
The load impedance 7a has one end connected to the output terminal 5c of the I VGA 5 and the output terminal 6c of the Q VGA 6, and the other end connected to the power supply terminal 7c.
The load impedance 7b has one end connected to the output terminal 5d of the I VGA 5 and the output terminal 6d of the Q VGA 6, and the other end connected to the power supply terminal 7d.
The output terminals 8 a and 8 b are terminals for outputting a differential composite signal synthesized by the signal synthesis unit 7.

The gain controller 9 controls the gains of the I VGA 5 and the Q VGA 6 to adjust the phase of the synthesized signal without changing the amplitude of the synthesized signal output from the signal synthesizer 7.
The bias controller 10 controls the bias current of the transistors in the input stage of the I VGA 5 and the Q VGA 6.

FIG. 2 is a block diagram showing the I-use VGA 5 of the vector synthesis type phase shifter according to the first embodiment of the present invention.
In FIG. 2, common gate transistors 11a and 11b are transistors having a common gate configuration, and constitute an input stage transistor in the I VGA 5.
The source terminals of the common-gate transistors 11a and 11b are connected to the input terminals 5a and 5b, and a bias voltage 12 is applied to the gate terminals.
When a bias control signal that is an output signal of the bias control unit 10 is input from the bias control terminal 5f to the variable current sources 13a and 13b, currents output to the source terminals of the gate-grounded transistors 11a and 11b according to the bias control signal, That is, the bias current of the common gate transistors 11a and 11b is adjusted.
The variable current sources 13a and 13b adjust the bias current of the grounded gate transistors 11a and 11b, so that the input impedances of the grounded gate transistors 11a and 11b are adjusted.
The input impedance of the grounded gate transistors 11a and 11b is determined by the reciprocal of the transconductance gm of the grounded gate transistors 11a and 11b.

The variable gain unit 14 has a current steering type circuit configuration. When a gain control signal, which is an output signal of the gain control unit 9, is input from the gain control terminal 5e, the grounded gate transistor 11a, The gain of the differential I signal output from the drain terminal of 11b is adjusted, and the I signal after gain adjustment is output to the signal combining unit 7 from the output terminals 5c and 5d.
Transistors 15a and 15b have gate terminals connected to gain control terminal 5e, source terminals connected to drain terminals of grounded gate transistors 11a and 11b, and drain terminals connected to power supply terminals 18a and 18b. The transistors 15a and 15b form a path for discarding part of the current signal that is the I signal output from the drain terminals of the common-gate transistors 11a and 11b in accordance with the gain control signal.

Transistors 16a and 16b have gate terminals connected to gain control terminal 5e, source terminals connected to drain terminals of grounded gate transistors 11a and 11b, and drain terminals connected to output terminals 5c and 5d. In order to realize a gain with a positive polarity, the transistors 16a and 16b output a part of the current signal, which is an I signal output from the drain terminals of the grounded gate transistors 11a and 11b, according to the gain control signal, to the output terminal 5c. , 5d.
Transistors 17a and 17b have gate terminals connected to gain control terminal 5e, source terminals connected to drain terminals of common-gate transistors 11a and 11b, and drain terminals connected to output terminals 5d and 5c. In order to realize a gain with a negative polarity, the transistors 17a and 17b receive a part of the current signal, which is an I signal output from the drain terminals of the common-gate transistors 11a and 11b, according to the gain control signal, as the output terminal 5d. , 5c.

FIG. 3 is a block diagram showing the Q VGA 6 of the vector synthesis type phase shifter according to the first embodiment of the present invention.
In FIG. 3, common gate transistors 21a and 21b are transistors having a common gate configuration, and constitute an input stage transistor in the Q VGA 6.
The source terminals of the common-gate transistors 21a and 21b are connected to the input terminals 6a and 6b, and a bias voltage 22 is applied to the gate terminals.
When the variable current sources 23a and 23b receive a bias control signal, which is an output signal from the bias control unit 10, from the bias control terminal 6f, That is, the bias current of the common gate transistors 21a and 21b is adjusted.
The variable current sources 23a and 23b adjust the bias currents of the grounded gate transistors 21a and 21b, so that the input impedances of the grounded gate transistors 21a and 21b are adjusted.
The input impedance of the common gate transistors 21a and 21b is determined by the reciprocal of the transconductance gm of the common gate transistors 21a and 21b.

The variable gain unit 24 has a current steering type circuit configuration. When a gain control signal that is an output signal of the gain control unit 9 is input from the gain control terminal 6e, the gate grounded transistors 21a, The gain of the differential Q signal output from the drain terminal of 21b is adjusted, and the Q signal after gain adjustment is output to the signal synthesizer 7 from the output terminals 6c and 6d.
Transistors 25a and 25b have gate terminals connected to gain control terminal 6e, source terminals connected to drain terminals of grounded gate transistors 21a and 21b, and drain terminals connected to power supply terminals 28a and 28b. The transistors 25a and 25b form a path for discarding a part of the current signal that is the Q signal output from the drain terminals of the common-gate transistors 21a and 21b according to the gain control signal.

Transistors 26a and 26b have gate terminals connected to gain control terminal 6e, source terminals connected to drain terminals of common-gate transistors 21a and 21b, and drain terminals connected to output terminals 6c and 6d. In order to realize a gain with a positive polarity, the transistors 26a and 26b receive a part of a current signal, which is a Q signal output from the drain terminals of the common-gate transistors 21a and 21b, in accordance with the gain control signal. , 6d.
Transistors 27a and 27b have gate terminals connected to gain control terminal 6e, source terminals connected to drain terminals of grounded gate transistors 21a and 21b, and drain terminals connected to output terminals 6d and 6c. In order to realize a gain with a negative polarity, the transistors 26a and 26b can output a part of a current signal, which is a Q signal output from the drain terminals of the common-gate transistors 21a and 21b, according to the gain control signal to the output terminal 6d. , 6c.

FIG. 4 is a block diagram showing the inside of the variable current sources 13a and 13b of the VGA 5 for I.
In FIG. 4, transistors 31 and 32 have gate terminals connected to the bias control terminal 5f and drain terminals connected to source terminals of the common gate transistors 11a and 11b.
The transistor 33 has a drain terminal and a gate terminal connected to the bias control terminal 5 f, and a gate terminal connected to the gate terminals of the transistors 31 and 32.
The bias control signal input from the bias control terminal 5f is current mirrored by the transistors 31 to 33, and the bias currents of the grounded gate transistors 11a and 11b are adjusted, thereby adjusting the input impedances of the grounded gate transistors 11a and 11b. The That is, the input impedance of the I VGA 5 viewed from the input terminals 5a and 5b is adjusted.
The input impedance of the I VGA 5 viewed from the input terminals 5a and 5b is the reciprocal of the transconductance gm of the grounded gate transistors 11a and 11b, and is determined by the bias current of the grounded gate transistors 11a and 11b.

FIG. 5 is a block diagram showing the inside of the variable current sources 23a and 23b of the VGA 6 for Q.
In FIG. 5, transistors 41 and 42 have gate terminals connected to the bias control terminal 6f and drain terminals connected to source terminals of the common gate transistors 21a and 21b.
The transistor 43 has a drain terminal and a gate terminal connected to the bias control terminal 6 f, and a gate terminal connected to the gate terminals of the transistors 41 and 42.
The bias control signal input from the bias control terminal 6f is current mirrored by the transistors 41 to 43, and the bias currents of the grounded gate transistors 21a and 21b are adjusted, so that the input impedances of the grounded gate transistors 21a and 21b are adjusted. The That is, the input impedance of the VGA 6 for Q viewed from the input terminals 6a and 6b is adjusted.
The input impedance of the Q VGA 6 viewed from the input terminals 6a and 6b is the reciprocal of the transconductance gm of the grounded gate transistors 21a and 21b, and is determined by the bias current of the grounded gate transistors 21a and 21b.

FIG. 6 is a block diagram showing the bias controller 10 of the vector composition type phase shifter according to the first embodiment of the present invention. In FIG. 6, for simplification of description, a single-phase configuration is shown instead of differential.
The bias control unit 10 in FIG. 6 does not control the bias current of the transistors in the input stage of the I VGA 5 and the Q VGA 6 in real time. For example, when the vector synthesis type phase shifter is powered on or shipped, It controls the bias current of the transistors in the input stage.
The configuration of the bias control unit 10 that controls the bias current of the transistor in the input stage in real time will be described in the second embodiment.

6, the phase shifter 60 includes the polyphase filter 2, the I VGA 5, the Q VGA 6, and the signal synthesis unit 7 shown in FIG. 1.
The phase shift amount setting unit 71 sets the phase shift amount, and outputs a phase shift amount setting signal indicating the phase shift amount to the phase shifter 60 via the output terminal 72. The phase shift amount setting signal output from the phase shift amount setting unit 71 corresponds to the gain control signal output from the gain control unit 9.
Therefore, when controlling the bias current of the transistor in the input stage, the gain control unit 9 sets the phase shift amount, and outputs a phase shift amount setting signal indicating the phase shift amount to the phase shifter 60 as a gain control signal. You may do it. In this case, the phase shift amount setting unit 71 in the bias control unit 10 is not necessary.
Specifically, the phase shift amount setting unit 71 outputs a phase shift amount setting signal indicating that the phase shift amount is α ₁ to the phase shifter 60, and then indicates that the phase shift amount is α _2. A phase shift amount setting signal is output to the phase shifter 60. α ₁ and α ₂ may be any value, and for example, α ₁ = 0, α ₂ = 90, etc. are conceivable.
When the phase shift amount setting signal indicating that the phase shift amount is α ₁ is given as a gain control signal from the phase shift amount setting device 71, the phase shifter 60 has a phase of (θ + α ₁ ) from the signal combining unit 7. When a combined signal is output and a phase shift amount setting signal indicating that the phase shift amount is α ₂ is provided from the phase shift amount setting unit 71 as a gain control signal, the signal combining unit 7 has a phase of (θ + α ₂ ). Output the composite signal. θ is the phase of the RF signal before the phase is shifted by the phase shifter 60.

The input terminal 73 is a terminal for inputting an RF signal that is an input signal of the phase shifter 60.
The analog / digital converter 74 converts the RF signal input from the input terminal 73 into a digital signal and outputs the digital RF signal to the multiplier 77.
The input terminal 75 is a terminal for inputting the combined signal output from the signal combining unit 7 of the phase shifter 60.
The analog-digital converter 76 converts the combined signal input from the input terminal 75 into a digital signal and outputs the digital combined signal to the multiplier 77.

The multiplier 77 multiplies the digital RF signal output from the analog / digital converter 74 and the digital composite signal output from the analog / digital converter 76, and outputs a signal indicating the multiplication result to the difference calculation unit 78.
The output signal of the multiplier 77 includes information indicating the phase difference between the RF signal that is the input signal of the phase shifter 60 and the combined signal output from the phase shifter 60.

The difference calculation unit 78 outputs the output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase shift amount is α ₁ is output from the phase shift amount setter 71 and the phase shift amount setter 71. The output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase amount is α ₂ is output is stored.
Further, the difference calculation unit 78 outputs a phase difference (α ₁ − −) indicated by the output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase shift amount is α ₁ is output from the phase shift amount setting unit 71. θ) and the phase difference (α ₂ −θ) indicated by the output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase shift amount is α ₂ is output from the phase shift amount setter 71. The difference ΔPh is calculated.
The difference ΔPh calculated by the difference calculation unit 78 is 90 (= α ₂ −α ₁ ) if the orthogonality between the I signal and the Q signal is maintained. For this reason, when ΔPh = 90 is not true, it means that the orthogonality between the I signal and the Q signal is deteriorated.
The table unit 79 stores a look-up table showing the relationship between the phase difference difference ΔPh and the amount of adjustment of the bias current in the common-gate transistors 11a, 11b, 21a, and 21b of the I VGA 5 and the Q VGA 6.

The bias control signal generation unit 80 refers to the lookup table stored in the table unit 79, acquires the adjustment amount of the bias current corresponding to the difference ΔPh calculated by the difference calculation unit 78, and from the adjustment amount, A bias control signal for controlling the bias current of the common gate transistors 11a, 11b, 21a, and 21b is generated.
FIG. 6 shows an example in which the bias control signal applied to the I VGA 5 and the bias control signal applied to the Q VGA 6 are the same for the sake of simplicity.
When the bias control signal applied to the I VGA 5 is different from the bias control signal applied to the Q VGA 6, the table unit 79 includes a lookup table for the I VGA 5 and a lookup table for the Q VGA 6. Are separately stored, and the bias control signal generator 80 refers to the separate look-up tables to generate a bias control signal to be applied to the I VGA 5 and a bias control signal to be applied to the Q VGA 6. That's fine.
The digital-analog converter 81 converts the bias control signal generated by the bias control signal generation unit 80 into an analog signal, and converts the analog bias control signal to the I VGA 5 and Q for the phase shifter 60 via the output terminal 82. Output to VGA6.

  In the first embodiment, it is assumed that all the transistors of the vector synthesis type phase shifter are configured by NMOS transistors, but the present invention is not limited to the configuration in which the transistors are configured by NMOS transistors. A PMOS transistor or a bipolar transistor may be used.

Next, the operation will be described.
Differential RF signals input from the input terminals 1 a and 1 b are input to the LPF 3 and the HPF 4 of the polyphase filter 2.
When a differential RF signal is input, the LPF 3 extracts an I signal from the differential RF signal and outputs the differential I signal to the I VGA 5.
When the differential RF signal is input, the HPF 4 extracts the Q signal from the differential RF signal and outputs the differential Q signal to the Q VGA 6.

Here, FIG. 7 is an explanatory diagram showing a simplified circuit of the LPF 3 and the HPF 4.
FIG. 7 shows a single-phase configuration instead of differential for the sake of simplicity.
In FIG. 7, termination impedances 51 and 52 are equivalent to the input impedances of the VGA 5 for I and the VGA 6 for Q.
Hereinafter, the bias control unit 10 to be described later adjusts the bias current of the common-gate transistors 11a and 11b, thereby adjusting the LPF 3 when the termination impedance 51 corresponding to the input impedance of the I VGA 5 is adjusted, and the bias control unit. The HPF 4 when the terminal impedance 52 corresponding to the input impedance of the Q VGA 6 is adjusted by adjusting the bias current of the common gate transistors 21a and 21b by 10 will be described.

For example, when the _{LPF 3} and the _{HPF 4} are composed of secondary filters, the transfer function H _LPF (s) of the _{LPF 3} and the transfer function H _HPF (s) of the _{HPF 4} are expressed by the following equations (1) and (2). It is expressed in

In Expressions (1) to (4), the circuit constants of the inductor element and the capacitive element in the LPF 3 are denoted by L _L [H] and C _L [F], and the circuit constants of the inductor element and the capacitive element in the HPF 4 are denoted by L _H [H ], C _H [F].
The terminal impedances 51 and 52 are defined as R _L [ohm] with the same value, the Laplace operator is defined as s, the operating angular frequency is defined as ω _c [rad / sec], and the Q value of the filter is defined as Q.
Α in the equation (3) is a coefficient for adjusting the cutoff frequency of the LPF 3 and the HPF 4.
Here, an example in which the LPF 3 and the HPF 4 are configured by secondary filters is shown, but it is only necessary to generate two orthogonal signals, and the filter configuration and the filter order are not limited.
Here, an example is shown in which the termination impedances 51 and 52 have the same value in R _L [ohm], but this is set to the same value in order to simplify the control configuration. , 52 can be independently controlled to further increase the degree of freedom of adjustment, and the final phase shift accuracy can be further improved.

FIG. 8 is an explanatory diagram showing pass gain characteristics and pass phase characteristics of LPF 3 and HPF 4.
In the first embodiment, it is assumed that LPF 3 and HPF 4 are constituted by secondary filters, and the difference between the pass phase of LPF 3 and the pass phase of HPF 4 is about 90 ° at the cut-off frequency.
In the first embodiment, it is assumed that the phase difference between the pass phase of the LPF 3 and the pass phase of the HPF 4 is adjusted to 90 ° by the coefficient α for adjusting the cutoff frequency.
This phase difference of 90 ° can be realized by overlapping the passbands of LPF 3 and HPF 4, and the coefficient α usually takes a value of 1 or less.

FIG. 9 is an explanatory diagram showing a state in which the orthogonality between the I signal and the Q signal output from the LPF 3 and the HPF 4 is changed by adjusting the termination impedances 51 and 52.
When the Q value in Expression (4) is changed, the pass gain characteristic of the LPF 3 changes as in the pass gain plot of the LPF 3 shown in FIG.
That is, if the Q value is 1, the LPF 3 has a pass gain characteristic of the characteristic curve A, and if the Q value is greater than 1, the LPF 3 has a pass gain characteristic having a ripple characteristic like the characteristic curve B. Further, the LPF 3 has a damped pass gain characteristic like the characteristic curve C if the Q value is smaller than 1.
As the Q value changes, the pass phase characteristic of the LPF 3 also varies as in the pass phase plot of the LPF 3 shown in FIG.
That is, the LPF 3 has a pass phase characteristic of the characteristic curve A if the Q value is 1, and has a pass phase characteristic of the characteristic curve B if the Q value is greater than 1, and if the Q value is less than 1. , Having a passing phase characteristic of a characteristic curve C.

Further, when the Q value of the equation (4) is changed, the pass gain characteristic of the HPF 4 changes as in the pass gain plot of the HPF 4 shown in FIG.
That is, the HPF 4 has a pass gain characteristic of the characteristic curve D if the Q value is 1, and has a pass gain characteristic having a ripple characteristic like the characteristic curve E if the Q value is larger than 1. Further, the HPF 4 has a damped pass gain characteristic like the characteristic curve F if the Q value is smaller than 1.
As the Q value changes, the pass phase characteristic of the HPF 4 also varies as in the pass phase plot of the HPF 4 shown in FIG.
That is, the HPF 4 has a pass phase characteristic of the characteristic curve D if the Q value is 1, and has a pass phase characteristic of the characteristic curve E if the Q value is greater than 1, and if the Q value is less than 1. , Having a passing phase characteristic of a characteristic curve F.

Here, when the pass gain characteristic and pass phase characteristic of LPF 3 are compared with the pass gain characteristic and pass phase characteristic of HPF 4, the following can be understood.
(1) The Q value and the pass gain have a positive phase relationship in both LPF 3 and HPF 4.
That is, if the Q value is larger than 1, the LPF 3 has a passing gain characteristic of the characteristic curve B having a larger passing gain than the characteristic curve A, and the HPF 4 also has a passing gain of the characteristic curve E having a larger passing gain than the characteristic curve D. Has characteristics.
If the Q value is smaller than 1, the LPF 3 has a pass gain characteristic of the characteristic curve C having a smaller pass gain than the characteristic curve A, and the HPF 4 also has a pass gain of the characteristic curve F having a smaller pass gain than the characteristic curve D. Has characteristics.
(2) The Q value and the passing phase have a positive correlation in LPF3, but have a negative correlation in HPF4.
That is, if the Q value is larger than 1, the LPF 3 has a pass phase characteristic of a characteristic curve B in which the pass phase at the operating frequency is a positive direction than the characteristic curve A, while the HPF 4 has an operating frequency of Has a passing phase characteristic of a characteristic curve E in which the passing phase is in a negative direction with respect to the characteristic curve D.
If the Q value is smaller than 1, the LPF 3 has a passing phase characteristic of a characteristic curve C in which the passing phase at the operating frequency is in a negative direction with respect to the characteristic curve A, but the HPF 4 has an operating frequency of Has a pass phase characteristic of a characteristic curve F in which the pass phase is more positive than the characteristic curve D.
Therefore, from (1) and (2), when the termination impedances 51 and 52 are adjusted, the pass gain difference between the LPF 3 and the HPF 4 changes little, and the pass phase difference between the LPF 3 and the HPF 4 changes.

FIG. 10 is an explanatory diagram showing circuit simulation results of the pass phase difference between LPF 3 and HPF 4 and the pass gain difference between LPF 3 and HPF 4 when termination impedances 51 and 52 are changed from 90% to 110%.
From FIG. 10, it is confirmed that the pass phase difference changes while the pass gain difference between the LPF 3 and the HPF 4 hardly changes.
However, this circuit simulation result is an example, and the circuit simulation result varies depending on the filter design parameters such as the Q value and the deviation from the center of the operating frequency.

In the VGA 5 for I, when the LPF 3 outputs a differential I signal, the gate-grounded transistors 11a and 11b as input stage transistors input the differential I signal.
When a bias control signal that is an output signal of the bias control unit 10 is input from the bias control terminal 5f to the variable current sources 13a and 13b of the VGA 5 for I, the bias currents of the grounded gate transistors 11a and 11b according to the bias control signal. Is adjusted to adjust the input impedance of the common-gate transistors 11a and 11b.
When the gain control signal which is the output signal of the gain control unit 9 is input from the gain control terminal 5e, the variable gain unit 14 of the I VGA 5 outputs from the drain terminals of the common-gate transistors 11a and 11b according to the gain control signal. The gain of the differential I signal thus adjusted is adjusted, and the I signal after gain adjustment is output from the output terminals 5 c and 5 d to the signal synthesizer 7.

In the Q VGA 6, when the HPF 4 outputs a differential Q signal, the grounded gate transistors 21a and 21b, which are transistors in the input stage, input the differential Q signal.
When a bias control signal that is an output signal of the bias control unit 10 is input from the bias control terminal 6f to the variable current sources 23a and 23b of the VGA 6 for Q, the bias currents of the grounded gate transistors 21a and 21b according to the bias control signal. Is adjusted to adjust the input impedance of the common-gate transistors 21a and 21b.
When the gain control signal that is the output signal of the gain control unit 9 is input from the gain control terminal 6e, the variable gain unit 24 of the Q VGA 6 outputs from the drain terminals of the common-gate transistors 21a and 21b according to the gain control signal. The gain of the differential Q signal thus adjusted is adjusted, and the Q signal after gain adjustment is output from the output terminals 6 c and 6 d to the signal synthesis unit 7.

  The signal synthesizer 7 receives a differential I signal from the I VGA 5 and, when receiving a differential Q signal from the Q VGA 6, synthesizes the I signal and the Q signal and outputs the differential synthesized signal as an output terminal. Output to 8a and 8b.

The gain controller 9 controls the gains of the I VGA 5 and the Q VGA 6 so that the passing gain of the vector synthesis type phase shifter is constant and only the passing phase is arbitrarily changed.
FIG. 11 is an explanatory diagram showing an image of set gains for the VGA for I 5 and the VGA 6 for Q when the passing phase of the vector composition type phase shifter is set to 60 ° and −135 °.
In FIG. 11, the dotted arrow “Gain for I” indicates the set gain for the VGA 5 for I, the dotted arrow “Gain for Q” indicates the set gain for the VGA 6 for Q, and “Synthesized Gain” indicates the combined gain. Show.

FIG. 12 is an explanatory diagram showing the relationship between the control signal voltage of the variable gain sections 14 and 24 of the I VGA 5 and the Q VGA 6 and the current gain of the variable gain sections 14 and 24.
FIG. 12 shows a gain control curve G having a positive polarity and a gain control curve H having a negative polarity.
The control signal voltages of the variable gain sections 14 and 24 are determined by the gain control signal output from the gain control section 9, but the control signal voltages V ₁₅ and V applied to the gate terminals of the transistors 15a, 15b, 25a, and 25b. ₂₅ , control signal voltages V ₁₆ and V ₂₆ applied to the gate terminals of the transistors 16a, 16b, 26a and 26b, and control signal voltages V ₁₇ and V ₂₇ applied to the gate terminals of the transistors 17a, 17b, 27a and 27b, Is different.
V ₁₅ = Control signal voltage applied to the gate terminals of the transistors 15a and 15b V ₂₅ = Control signal voltage applied to the gate terminals of the transistors 25a and 25b V ₁₆ = Control signal voltage applied to the gate terminals of the transistors 16a and 16b V ₂₆ = Control signal voltage applied to gate terminals of transistors 26a and 26b V ₁₇ = Control signal voltage applied to gate terminals of transistors 17a and 17b V ₂₇ = Control signal voltage applied to gate terminals of transistors 27a and 27b

In the VGA 5 for I, in order to realize gain control with positive polarity, the gain controller 9 applies the gain control signal to the gate terminals of the transistors 17a and 17b so that the transistors 17a and 17b are cut off. controlling the control signal voltage _{V 17.} Further, the gain control unit 9, the gain control signal is the difference between the control signal voltage _{V 15} to be applied to the gate terminal of the transistor 15a, 15b, and the control signal voltage _{V 16} to be applied to the transistor 16a, the gate terminal of 16b The gate potential difference ΔVp is controlled.
ΔVp = V ₁₆ −V ₁₅
The gain control unit 9 controls the gate potential difference ΔVp with the gain control signal, so that only a desired proportion of the I signal output from the drain terminals of the common-gate transistors 11a and 11b is a transistor. It passes through 16a and 16b and is output to output terminals 5c and 5d.
Thereby, the passing gain which is the current gain of the variable gain section 14 in the I VGA 5 changes between 0 and 1 (the true number).

In the VGA 5 for I, in order to realize gain control with negative polarity, the gain controller 9 applies a gain control signal to the gate terminals of the transistors 16a and 16b so that the transistors 16a and 16b are cut off. controlling the control signal voltage _{V 16.} Further, the gain control unit 9, the gain control signal is the difference between the control signal voltage _{V 15} to be applied to the gate terminal of the transistor 15a, 15b, and the control signal voltage _{V 17} to be applied to the transistor 17a, 17b the gate terminal of the The gate potential difference ΔVm is controlled.
ΔVm = V ₁₇ −V ₁₅
The gain control unit 9 controls the gate potential difference ΔVm with the gain control signal, so that only a desired proportion of the I signal output from the drain terminals of the common-gate transistors 11a and 11b is a transistor. It passes through 17a and 17b and is output to output terminals 5d and 5c.
Thereby, the passing gain which is the current gain of the variable gain section 14 in the I VGA 5 changes between 0 and −1 (the true number).

In the Q VGA 6, in order to realize the positive polarity gain control, the gain control unit 9 applies the gain control signal to the gate terminals of the transistors 27 a and 27 b so that the transistors 27 a and 27 b are cut off. controlling the control signal voltage _{V 27.} Further, the gain control unit 9 is a difference between the control signal voltage V ₂₅ applied to the gate terminals of the transistors _{25 a} and ₂₅ b and the control signal voltage V ₂₆ applied to the gate terminals of the transistors 26 a and 26 b according to the gain control signal. The gate potential difference ΔVp is controlled.
ΔVp = V ₂₆ −V ₂₅
The gain control unit 9 controls the gate potential difference ΔVp with the gain control signal, so that only a desired proportion of the Q signals output from the drain terminals of the common-gate transistors 21a and 21b are transistors. It passes through 26a and 26b and is output to output terminals 6c and 6d.
Thereby, the pass gain which is the current gain of the variable gain section 24 in the Q VGA 6 changes between 0 and 1 (the true number).

In the Q VGA 6, in order to realize gain control with negative polarity, the gain controller 9 applies a gain control signal to the gate terminals of the transistors 26a and 26b so that the transistors 26a and 26b are cut off. Control signal voltage V ₂₆ is controlled. Further, the gain control unit 9 is a difference between the control signal voltage V ₂₅ applied to the gate terminals of the transistors 25a and 25b and the control signal voltage V ₂₇ applied to the gate terminals of the transistors 27a and 27b by the gain control signal. The gate potential difference ΔVm is controlled.
ΔVm = V ₂₇ −V ₂₅
The gain control unit 9 controls the gate potential difference ΔVm with the gain control signal, so that only a desired proportion of the Q signals output from the drain terminals of the common-gate transistors 21a and 21b are transistors. It passes through 27a and 27b and is output to the output terminals 6d and 6c.
As a result, the pass gain, which is the current gain of the variable gain section 24 in the Q VGA 6, changes between 0 and −1 (the true number).

The bias control unit 10 controls the bias current of the common gate transistors 11a, 11b, 21a, and 21b, which are transistors in the input stage of the I VGA 5 and the Q VGA 6, thereby improving the orthogonality between the I signal and the Q signal. .
Hereinafter, the control content of the bias current by the bias control unit 10 will be specifically described with reference to FIG.

The phase shift amount setting unit 71 of the bias control unit 10 sets the phase shift amount when the vector synthesis type phase shifter is turned on or shipped, and shows the phase shift amount via the output terminal 72, for example. The phase amount setting signal is output as a gain control signal to the gain control terminal 5e of the I VGA 5 and the gain control terminal 6e of the Q VGA 6 in the phase shifter 60.
That is, the phase shift amount setting unit 71 outputs a phase shift amount setting signal indicating that the phase shift amount is α ₁ to the gain control terminals 5e and 6e of the phase shifter 60 as a bias control signal, and then shifts. Airyo as the bias control signal of phase shift amount setting signal indicating a alpha _2, and outputs the gain control terminal 5e of the phase shifter 60, to 6e. α ₁ and α ₂ may be any value, and for example, α ₁ = 0, α ₂ = 90, etc. are conceivable.
At this time, the bias control signal generation unit 80 of the bias control unit 10 outputs an initial bias control signal set in advance to the digital / analog converter 81, and the digital / analog converter 81 outputs the bias control signal generation unit. The initial bias control signal output from 80 is converted into an analog signal, and the analog bias control signal is output to the I VGA 5 and Q VGA 6 of the phase shifter 60 via the output terminal 82.

When the phase shift amount setting signal indicating that the phase shift amount is α ₁ is given from the phase shift amount setting device 71, the phase shifter 60 outputs a combined signal having a phase of (θ + α ₁ ) from the signal combining unit 7. To do.
Further, when a phase shift amount setting signal indicating that the phase shift amount is α ₂ is given from the phase shift amount setting device 71, the phase shifter 60 is a combined signal having a phase of (θ + α ₂ ) from the signal combining unit 7. Is output.
θ is the phase of the RF signal before the phase is shifted by the phase shifter 60.

When an RF signal is input from the input terminal 73, the analog / digital converter 74 converts the RF signal into a digital signal and outputs the digital RF signal to the multiplier 77.
When the phase shift amount setting signal indicating that the phase shift amount is α ₁ is output from the phase shift amount setting unit 71, the analog-digital converter 76 performs the synthesis output from the signal synthesis unit 7 of the phase shifter 60. When a signal is input from the input terminal 75, the combined signal is converted into a digital signal, and the digital combined signal is output to the multiplier 77.
The analog-digital converter 76 outputs the phase shift amount setting signal indicating that the phase shift amount is α ₂ from the phase shift amount setter 71 and is output from the signal synthesis unit 7 of the phase shifter 60. When the combined signal is input from the input terminal 75, the combined signal is converted into a digital signal, and the digital combined signal is output to the multiplier 77.

When the multiplier 77 receives the digital RF signal from the analog-digital converter 74 and receives the digital composite signal from the analog-digital converter 76, the multiplier 77 multiplies the digital RF signal and the digital composite signal, and outputs a signal indicating the multiplication result. It outputs to the difference calculation part 78.
The output signal of the multiplier 77 includes information indicating the phase difference between the RF signal that is the input signal of the phase shifter 60 and the combined signal that is the output signal of the phase shifter 60.

When the difference calculating unit 78 receives the output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase shift amount is α ₁ is output from the phase shift amount setting unit 71, the difference calculating unit 78 outputs the output signal. Remember.
When the difference calculating unit 78 receives the output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase shift amount is α ₂ is output from the phase shift amount setting unit 71, the difference calculating unit 78 outputs the signal. Store the signal.
Then, the difference calculating unit 78 outputs the phase difference (α ₁₎ indicated by the output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase shift amount is α ₁ is output from the phase shift amount setting unit 71. −θ) and the phase difference (α ₂ −θ) indicated by the output signal of the multiplier 77 when the phase shift amount setting signal indicating that the phase shift amount is α ₂ is output from the phase shift amount setting unit 71. The difference ΔPh is calculated.
At this time, the difference ΔPh calculated by the difference calculation unit 78 is (α ₂ −α ₁ ). For example, when α ₁ = 0 and α ₂ = 90, the orthogonality between the I signal and the Q signal is maintained. If so, the difference ΔPh is 90 (= (α ₂ −α ₁ )). For this reason, when ΔPh = 90 is not true, it means that the orthogonality between the I signal and the Q signal is deteriorated. That is, when ΔPh−90 = 0 is not true, it means that the orthogonality between the I signal and the Q signal is deteriorated.

The table unit 79 stores a look-up table showing the relationship between the phase difference difference ΔPh−90 and the adjustment amount of the bias current in the common-gate transistors 11a, 11b, 21a, and 21b of the I VGA 5 and the Q VGA 6. Yes.
Here, FIG. 13 is an explanatory diagram illustrating an example of a lookup table stored in the table unit 79.
In FIG. 13, the lookup table is a common table for the I VGA 5 and the Q VGA 6 for simplification of explanation.

For example, if the phase difference difference ΔPh−90 is 0, the orthogonality between the I signal and the Q signal is maintained, and the initial bias control signal output from the bias control unit 10 is appropriate. For this reason, in the lookup table of FIG. 13, an adjustment amount [100%] indicating that the initial bias control signal is maintained is recorded as an adjustment amount corresponding to ΔPh−90 = 0.
On the other hand, when the phase difference difference ΔPh−90 is not 0, the orthogonality between the I signal and the Q signal is deteriorated, and the initial bias control signal output from the bias control unit 10 is inappropriate. ing. Therefore, in the lookup table of FIG. 13, an adjustment amount indicating that the initial bias control signal is adjusted is recorded as an adjustment amount corresponding to ΔPh−90 ≠ 0.
For example, when the phase difference difference ΔPh−90 is −3, the adjustment amount [95%] indicating that 95% of the initial bias control signal output from the bias control unit 10 is output is recorded. ing.
When the phase difference difference ΔPh−90 is +6, an adjustment amount [120%] indicating that 120% of the initial bias control signal output from the bias control unit 10 is output is recorded. Yes.

When the difference calculation unit 78 calculates the difference ΔPh, the bias control signal generation unit 80 refers to the lookup table stored in the table unit 79 and acquires the adjustment amount of the bias current corresponding to the difference ΔPh−90. To do.
For example, if the phase difference difference ΔPh−90 is +3, an adjustment amount [105%] indicating that 105% of the initial bias control signal output from the bias control unit 10 is output is acquired. .
When the bias control signal generation unit 80 acquires the adjustment amount of the bias current, the bias control signal generation unit 80 generates a bias control signal corresponding to the bias currents of the common-gate transistors 11a, 11b, 21a, and 21b from the adjustment amount.
For example, if the adjustment amount is [105%], a bias control signal that is 1.05 times the initial bias control signal output from the bias control unit 10 is generated.

When the bias control signal generation unit 80 generates a bias control signal, the digital-analog converter 81 converts the bias control signal into an analog signal, and converts the analog bias control signal of the phase shifter 60 via the output terminal 82. Output to the VGA 5 for I and the VGA 6 for Q.
Thereby, the bias currents of the common-gate transistors 11a, 11b, 21a, and 21b of the I VGA 5 and the Q VGA 6 are adjusted by the bias control signal output from the digital / analog converter 81.
As a result, the phase difference between the I signal output from the I VGA 5 and the Q signal output from the Q VGA 6 approaches 90 °, and the orthogonality between the I signal and the Q signal is improved.

  As is apparent from the above, according to the first embodiment, the gain controller 9 controls the gains of the I VGA 5 and the Q VGA 6 so that the amplitude of the synthesized signal output from the signal synthesizer 7 is reduced. Without changing, the phase of the composite signal is adjusted, and the bias control unit 10 is configured to control the bias currents of the common-gate transistors 11a, 11b, 21a, and 22b included in the I VGA 5 and the Q VGA 6. It is possible to achieve low noise and high gain, and to increase the phase shift accuracy.

Embodiment 2. FIG.
In the first embodiment, the example in which the bias control unit 10 controls the bias current of the transistors in the input stage included in the I VGA 5 and the Q VGA 6 when the vector synthesis type phase shifter is turned on or shipped is described. However, in the second embodiment, an example will be described in which the bias control unit 10 controls the bias current of the transistors in the input stage included in the I VGA 5 and the Q VGA 6 in real time.

14 is a block diagram showing a vector synthesis type phase shifter according to Embodiment 2 of the present invention. In FIG. 14, the same reference numerals as those in FIG.
The vector synthesis type phase shifter of FIG. 14 is substantially the same as the vector synthesis type phase shifter of FIG. 1, but is not the synthesized signal output from the signal synthesis unit 7 but the I signal output from the VGA 5 for I. The Q signal output from the Q VGA 6 is different in that it is input to the bias control unit 10.
FIG. 15 is a block diagram showing the bias controller 10 of the vector composition type phase shifter according to the second embodiment of the present invention. In FIG. 15, for simplification of description, a single-phase configuration is shown instead of differential. In FIG. 15, the same reference numerals as those in FIG.

The input terminal 83 is a terminal for inputting the I signal output from the I VGA 5 of the phase shifter 60.
The analog / digital converter 84 converts the I signal input from the input terminal 83 into a digital signal and outputs the digital I signal to the multiplier 87.
The input terminal 85 is a terminal for inputting the Q signal output from the Q VGA 6 of the phase shifter 60.
The analog / digital converter 86 converts the Q signal input from the input terminal 85 into a digital signal and outputs the digital Q signal to the multiplier 88.

The multiplier 87 multiplies the digital RF signal output from the analog-digital converter 74 and the digital I signal output from the analog-digital converter 84, and outputs a signal indicating the multiplication result to the difference calculation unit 89.
The output signal of the multiplier 87 includes information indicating the phase difference between the RF signal that is the input signal of the phase shifter 60 and the I signal output from the I VGA 5.
The multiplier 88 multiplies the digital RF signal output from the analog-digital converter 74 and the digital Q signal output from the analog-digital converter 86, and outputs a signal indicating the multiplication result to the difference calculation unit 89.
The output signal of the multiplier 88 includes information indicating the phase difference between the RF signal that is the input signal of the phase shifter 60 and the Q signal output from the Q VGA 6.
The difference calculation unit 89 calculates a difference ΔPh between the phase difference indicated by the output signal of the multiplier 87 and the phase difference indicated by the output signal of the multiplier 88.

Next, the operation will be described.
Since the operations other than the bias control unit 10 are the same as those in the first embodiment, only the operation of the bias control unit 10 will be described here.
When an RF signal is input from the input terminal 73, the analog-digital converter 74 converts the RF signal into a digital signal and outputs the digital RF signal to the multipliers 87 and 88.
When the I signal is input from the input terminal 83, the analog / digital converter 84 converts the I signal into a digital signal and outputs the digital I signal to the multiplier 87.
When the Q signal is input from the input terminal 85, the analog-digital converter 86 converts the Q signal into a digital signal and outputs the digital Q signal to the multiplier 88.

When the multiplier 87 receives the digital RF signal from the analog-digital converter 74 and receives the digital I signal from the analog-digital converter 84, the multiplier 87 multiplies the digital RF signal and the digital I signal, and outputs a signal indicating the multiplication result. The result is output to the difference calculation unit 89.
When the multiplier 88 receives the digital RF signal from the analog-digital converter 74 and receives the digital Q signal from the analog-digital converter 86, the multiplier 88 multiplies the digital RF signal by the digital Q signal, and outputs a signal indicating the multiplication result. The result is output to the difference calculation unit 89.
Here, it is assumed that the phase of the RF signal is θ, the phase shift amount in the I VGA 5 and the Q VGA 6 is β, and the phase difference between the I signal and the Q signal is γ. In this case, the phase of the I signal output from the VGA for I 5 is (θ + β), and the phase of the Q signal output from the VGA 6 for Q is (θ + β + γ).

The difference calculation unit 89 calculates a difference ΔPh between the phase difference (= β) indicated by the output signal of the multiplier 87 and the phase difference (= β + γ) indicated by the output signal of the multiplier 88.
At this time, the difference ΔPh calculated by the difference calculation unit 89 is γ (= (β + γ) −β). However, if the orthogonality between the I signal and the Q signal is maintained, γ = 90, and thus ΔPh = 90. For this reason, when ΔPh = 90 is not true, it means that the orthogonality between the I signal and the Q signal is deteriorated.
When the difference calculation unit 89 calculates the difference ΔPh, the bias control signal generation unit 80 refers to the lookup table stored in the table unit 79 and corresponds to the difference ΔPh as in the first embodiment. Get the adjustment amount of the bias current.
When the bias control signal generation unit 80 acquires the adjustment amount of the bias current, the bias control signal generation unit 80 generates a bias control signal corresponding to the bias currents of the common-gate transistors 11a, 11b, 21a, and 21b from the adjustment amount.
When the bias control signal generation unit 80 generates a bias control signal, the digital-analog converter 81 converts the bias control signal into an analog signal, and converts the analog bias control signal of the phase shifter 60 via the output terminal 82. Output to the VGA 5 for I and the VGA 6 for Q.

  As apparent from the above, according to the second embodiment, the analog-digital converter 84 that converts the I signal output from the VGA 5 for I into a digital signal and outputs the digital I signal to the multiplier 87; An analog-to-digital converter 86 that converts the Q signal output from the VGA 6 for Q into a digital signal and outputs the digital Q signal to the multiplier 88; a digital RF signal output from the analog-to-digital converter 74; The multiplier I that multiplies the digital I signal output from the converter 84 and outputs a signal indicating the multiplication result to the difference calculation unit 89; the digital RF signal output from the analog-digital converter 74; Multiplier 8 that multiplies the digital Q signal output from converter 86 and outputs a signal indicating the multiplication result to difference calculation unit 89. Since it is configured to include the door, it offers an advantage of being able to control the bias current of the transistors of the input stage with the I for VGA5 and Q for VGA6 in real time.

Embodiment 3 FIG.
In the first and second embodiments, the LPF 3 and the I VGA 5 are connected and the HPF 4 and the Q VGA 6 are connected. However, in the third embodiment, the resonance occurs between the LPF 3 and the I VGA 5. Will be described in which a resonator is connected between the HPF 4 and the Q VGA 6.

FIG. 16 is a block diagram showing a vector composition type phase shifter according to Embodiment 3 of the present invention. In FIG. 16, the same reference numerals as those in FIG.
The resonator 91 is a first resonator that is connected between the LPF 3 and the I VGA 5 and increases the impedance (input side impedance) of the source terminals of the common-gate transistors 11a and 11b that are transistors in the input stage of the I VGA 5. is there.
The resonator 92 is a second resonator that is connected between the HPF 4 and the Q VGA 6 and increases the impedance (input side impedance) of the source terminals of the common-gate transistors 21a and 21b that are transistors in the input stage of the Q VGA 6. is there. The resonators 91 and 92 include an inductor element L and a capacitive element C.
The vector synthesis type phase shifter of FIG. 16 shows an example in which the resonators 91 and 92 are applied to the vector synthesis type phase shifter of FIG. 1 in the first embodiment, but FIG. 14 in the second embodiment. The resonators 91 and 92 may be applied to the vector synthesis type phase shifter.

FIG. 17 is a block diagram showing a part of the interior of the VGA 5 for I and the VGA 6 for Q of the vector synthesis type phase shifter according to the third embodiment of the present invention. In FIG. 17, the same reference numerals as those in FIGS.
In FIG. 17, for simplicity of description, a single-phase configuration is shown instead of differential. Therefore, the input terminals 1a and 1b are expressed as the input terminal 1, the gate grounded transistors 11a and 11b are expressed as the gate grounded transistor 11, and the gate grounded transistors 21a and 21b are expressed as the gate grounded transistor 21. doing.
Further, the description of the variable gain units 14 and 24 is omitted, the variable gain unit 14 is connected to the drain terminal 101 of the common-gate transistor 11, and the variable gain unit 24 is connected to the drain terminal 102 of the common-gate transistor 21. Yes.

The gate terminal of the transistor 103 is grounded to the bias control terminal 5 f and the gate terminal of the grounded gate transistor 11.
The bias control signal input from the bias control terminal 5f is current mirrored by the grounded gate transistor 11 and the transistor 103, and the bias current of the grounded gate transistor 11 is adjusted, so that the input impedance of the grounded gate transistor 11 is adjusted. .
The gate terminal of the transistor 104 is grounded to the bias control terminal 6 f and the gate terminal of the grounded gate transistor 21.
The bias control signal input from the bias control terminal 6f is current mirrored by the grounded gate transistor 21 and the transistor 104, and the bias current of the grounded gate transistor 21 is adjusted, so that the input impedance of the grounded gate transistor 21 is adjusted. .

Next, the operation will be described.
The common-gate transistor 11 of the VGA 5 for I inputs an I signal that is an output signal of the LPF 3 from the source terminal, and outputs the I signal from the drain terminal 101 to the variable gain unit 14.
The common-gate transistor 21 of the Q VGA 6 inputs a Q signal that is an output signal of the HPF 4 from the source terminal, and outputs the Q signal from the drain terminal 102 to the variable gain unit 24.
Therefore, in order for the grounded gate transistors 11 and 21 to transmit the signal component from the source terminal to the drain terminals 101 and 102 without leaking, it is necessary to sufficiently increase the impedance of the source terminal at the operating frequency.
If the impedance of the source terminal of the grounded-gate transistors 11 and 21 is not sufficiently high, the gain characteristics of the grounded-gate transistors 11 and 21 deteriorate due to the influence of the parasitic capacitance at the source terminals of the grounded-gate transistors 11 and 21. As a result, the orthogonality between the I signal and the Q signal may deteriorate.

Therefore, in the third embodiment, in order to sufficiently increase the impedance of the source terminal of the grounded-gate transistors 11 and 21, a resonator 91 is connected between the LPF 3 and the I VGA 5, and between the HPF 4 and the Q VGA 6. Is connected to the resonator 92.
By connecting the resonators 91 and 92, the parasitic capacitance component at the source terminals of the common-gate transistors 11 and 21 can be canceled by the reactance component of the inductor element L included in the resonators 91 and 92.
Thereby, even if the frequency of the RF signal which is an input signal is high, there is an effect that the orthogonality between the I signal and the Q signal can be improved and the phase shift accuracy can be improved.

Embodiment 4 FIG.
In the third embodiment, an example in which the resonator 91 is connected between the LPF 3 and the I VGA 5 and the resonator 92 is connected between the HPF 4 and the Q VGA 6 is shown. In the fourth embodiment, an example in which the LPF 3 and the HPF 4 include a resonator will be described.

FIG. 18 is a block diagram showing a vector synthesis type phase shifter according to Embodiment 4 of the present invention. In FIG. 18, the same reference numerals as those in FIG.
The LPF 111 includes inductor elements 111a and 111b and capacitive elements 111c and 111d, and extracts an I signal from a differential RF signal input from the input terminals 1a and 1b.
The inductor element 111a is inserted on the signal line connecting the input terminal 1a and the input terminal 5a of the I VGA 5, and the inductor element 111b is inserted on the signal line connecting the input terminal 1b and the input terminal 5b of the I VGA 5. Yes.
The capacitive element 111c is connected between a signal line connecting the input terminal 1a and the input terminal 5a of the I VGA 5 and the ground, and the capacitive element 111d is a signal line connecting the input terminal 1b and the input terminal 5b of the I VGA. And the ground.
The LPF 111 is common to the LPF 3 shown in FIGS. 1, 14, and 16 in that the I signal is extracted from the RF signal, but the LPF 111 is the LPF 3 shown in FIGS. 1, 14, and 16. Unlike this, it also functions as the resonator 91 shown in FIG.
That is, the inductor elements 111a and 111b of the LPF 111 include reactance components of the inductor element L included in the resonator 91 illustrated in FIG. 16, and the capacitors 111c and 111d of the LPF 111 include the resonator 91. The reactance component of the capacitive element C is included.
For this reason, the LPF 111 has a function of extracting the I signal from the RF signal and a function of the resonator 91.

The HPF 112 includes capacitive elements 112a and 112b and inductor elements 112c and 112d, and extracts a Q signal from the differential RF signal input from the input terminals 1a and 1b.
The capacitive element 112a is inserted on the signal line connecting the input terminal 1a and the input terminal 6a of the Q VGA 6, and the capacitive element 112b is inserted on the signal line connecting the input terminal 1b and the input terminal 6b of the Q VGA 6. Yes.
The inductor element 112c is connected between a signal line connecting the input terminal 1a and the input terminal 6a of the Q VGA 6 and the ground, and the inductor element 112d is a signal line connecting the input terminal 1b and the input terminal 6b of the Q VGA 6 And the ground.
The HPF 112 is common to the HPF 4 shown in FIGS. 1, 14, and 16 in that the Q signal is extracted from the RF signal, but the HPF 112 is common, but the HPF 112 is similar to the HPF 112 shown in FIGS. Unlike the HPF 4 shown in FIG. 16, it also functions as the resonator 92 shown in FIG.
That is, the inductor elements 112c and 112d of the HPF 112 include reactance components of the inductor element L included in the resonator 92 illustrated in FIG. 16, and the capacitor elements 112a and 112b of the HPF 112 include the resonator 92. The reactance component of the capacitive element C is included.
For this reason, the HPF 112 has a function of extracting a Q signal from the RF signal and a function of the resonator 92.

  The vector synthesis type phase shifter of FIG. 18 shows an example in which a resonator is applied to the vector synthesis type phase shifter of FIG. 1 in the first embodiment, but the vector synthesis of FIG. 14 in the second embodiment. A resonator may be applied to the type phase shifter.

FIG. 19 is a block diagram showing a part of the I VGA 5 and Q VGA 6 of the vector synthesis type phase shifter according to the fourth embodiment of the present invention. In FIG. 19, the same reference numerals as those in FIGS. 2, 3 and 17 denote the same or corresponding parts, and the description thereof will be omitted.
In FIG. 19, for simplicity of description, a single-phase configuration is shown instead of differential. Therefore, the input terminals 1a and 1b are expressed as the input terminal 1, the gate grounded transistors 11a and 11b are expressed as the gate grounded transistor 11, and the gate grounded transistors 21a and 21b are expressed as the gate grounded transistor 21. doing.
Further, the description of the variable gain units 14 and 24 is omitted, the variable gain unit 14 is connected to the drain terminal 101 of the common-gate transistor 11, and the variable gain unit 24 is connected to the drain terminal 102 of the common-gate transistor 21. Yes.

The vector synthesis type phase shifter of the fourth embodiment operates in the same manner as the vector synthesis type phase shifter of the third embodiment. For this reason, as in the third embodiment, even when the frequency of the RF signal that is the input signal is high, the orthogonality between the I signal and the Q signal can be increased and the phase shift accuracy can be increased. Play.
Since LPF 111 is an integrated LPF 3 and resonator 91, and HPF 112 is an integrated HPF 4 and resonator 92, compared to the third embodiment, an inductor element is provided. In addition, the number of capacitive elements can be reduced. Therefore, the circuit can be reduced in size.

Embodiment 5. FIG.
In the first embodiment, the I VGA 5 has the common gate transistors 11a and 11b and the variable gain section 14 as shown in FIG. 2, and the Q VGA 6 has the common gate transistors 21a and 21a, as shown in FIG. In this example, 21b and the variable gain section 24 are stacked vertically. In the fifth embodiment, an I VGA 5 and a Q VGA 6 in which a grounded gate transistor and a variable gain unit are integrated will be described.

FIG. 20 is a block diagram showing an I VGA 5 for a vector synthesis type phase shifter according to Embodiment 5 of the present invention, and FIG. 21 shows a Q VGA 6 for a vector synthesis type phase shifter according to Embodiment 5 of the present invention. FIG. 20 and FIG. 21, the same reference numerals as those in FIG. 2 and FIG.
In FIG. 20 and FIG. 21, a single-phase configuration is shown instead of differential for the sake of simplicity. For this reason, the input terminals 5a and 5b of the I VGA 5 for inputting a differential I signal are represented as an input terminal 5g, and the output terminals 5c and 5d of the I VGA 5 for outputting a differential I signal are It is written as an output terminal 5h.
Further, the input terminals 6a and 6b of the Q VGA 6 for inputting the differential Q signal are expressed as an input terminal 6g, and the output terminals 6c and 6d of the Q VGA 6 for outputting the differential Q signal are output. It is represented as a terminal 6h.

The variable gain unit 121 plays a role of increasing the current gain, and is realized by connecting N (N is an integer of 2 or more) unit cells including a common-gate transistor in parallel. In the variable gain unit 121, the number of grounded gate transistors corresponding to the gain control signal input from the gain control terminal 5e among the N gate grounded transistors is turned on, and the on-state transistors are input from the input terminal 5g. The I signal thus output is output to the signal synthesizer 7 via the output terminal 5h.
The variable gain section 122 plays a role of reducing the current gain, and is realized by connecting N unit cells including a common-gate transistor in parallel. In the variable gain unit 122, the number of grounded gate transistors corresponding to the gain control signal input from the gain control terminal 5e is turned off among the N grounded gate transistors, and the on-state transistors that are not turned off are turned on. The I signal input from the input terminal 5g is output to the power supply terminal 120.

The transistor 123 has a gate terminal and a drain terminal connected to the bias control terminal 5 f, and a gate terminal connected to the gate terminal of the common-gate transistor included in the N unit cells of the variable gain sections 121 and 122.
The bias control signal input from the bias control terminal 5f is current-mirrored by the transistor 123, and the bias current of the gate-grounded transistor included in the N unit cells in the variable gain sections 121 and 122 is adjusted.
The variable gain units 121 and 122 enable positive polarity gain control. However, in the case of a differential configuration, if a variable gain unit that outputs a signal having a phase opposite to that of the output signal of the variable gain unit 121 is provided, a negative gain can be obtained. It is also possible to control the gain of the polarity.

The variable gain unit 131 plays a role of increasing the current gain, and is realized by connecting N unit cells including a common-gate transistor in parallel. In the variable gain section 131, the number of grounded gate transistors corresponding to the gain control signal input from the gain control terminal 6e among the N gate grounded transistors is turned on, and the on-state transistors are input from the input terminal 6g. The Q signal thus output is output to the signal synthesis unit 7 via the output terminal 6h.
The variable gain unit 132 plays a role of reducing the current gain, and is realized by connecting N unit cells including a common-gate transistor in parallel. In the variable gain section 132, the number of grounded gate transistors corresponding to the gain control signal input from the gain control terminal 6e is turned off among the N grounded gate transistors, and the on-state transistors that are not turned off are turned on. The Q signal input from the input terminal 6 g is output to the power supply terminal 130.

The transistor 133 has a gate terminal and a drain terminal connected to the bias control terminal 6 f, and a gate terminal connected to the gate terminal of a common-gate transistor included in the N unit cells of the variable gain sections 131 and 132.
The bias control signal input from the bias control terminal 6 f is current mirrored by the transistor 133, and the bias current of the gate-grounded transistor included in the N unit cells in the variable gain sections 131 and 122 is adjusted.
The variable gain units 131 and 132 can control the gain of positive polarity. However, in the case of a differential configuration, if a variable gain unit that outputs a signal having a phase opposite to that of the output signal of the variable gain unit 131 is provided, a negative gain can be obtained. It is also possible to control the gain of the polarity.

FIG. 22 is a configuration diagram showing unit cells mounted on the variable gain sections 121, 122, 131, and 132.
In FIG. 22, a common-gate transistor 141 is a transistor included in a unit cell. The source terminal 142 is connected to the input terminal 5g of the I VGA 5 or the input terminal 6g of the Q VGA 6, and the drain terminal 143 is connected to the I VGA 5. Output terminal 5h or Q output terminal 6h of VGA 6.
The gate bias input terminal 144 is connected to the bias control terminal 5 f and the gate terminal of the transistor 123.
The on / off control terminal 145 receives, for example, an H level signal as an on / off control signal when the grounded gate transistor 141 is turned on, and an L level signal as an on / off control signal when the grounded gate transistor 141 is turned off. Is done.
Here, an example is shown in which an H level signal is input when turning on and an L level signal is input when turning off, but an L level signal is input when turning on. In order to turn it off, an H level signal may be input.

For example, if the gain control signal input from the gain control terminal 5e indicates that a large current gain is realized, the unit cell to which the H level signal is input so that the number of the grounded gate transistors 141 in the ON state increases. The number of On the other hand, if the gain control signal input from the gain control terminal 5e indicates that a small current gain is realized, the unit cell to which an H level signal is input so that the number of on-gate grounded transistors 141 is reduced. The number of
In the fifth embodiment, a circuit that generates an on / off control signal to be supplied to N unit cells from a gain control signal input from the gain control terminal 5e is not specified, but input from the gain control terminal 5e is not specified. It is assumed that the current gain indicated by the gain control signal is proportional to the number of unit cells to which an H level signal is input among the N unit cells. It is assumed that the number of on / off control signals that become H level signals increases as the current gain shown increases.

The switch 146 is turned on when an H level signal is input from the on / off control terminal 145, and is turned off when an L level signal is input from the on / off control terminal 145.
The inverter 147 which is a logic inverting circuit outputs an L level signal when an H level signal is input from the on / off control terminal 145, and an H level signal when an L level signal is input from the on / off control terminal 145. Is output.
The switch 148 is turned off when an L level signal is output from the inverter 147, and is turned on when an H level signal is output from the inverter 147.

Next, the operation will be described.
When a gain control signal is input from the gain control terminals 5e and 6e, N unit cells in the variable gain sections 121, 122, 131, and 132 are turned on / off control signals corresponding to the gain control signal from the on / off control terminal 145. Is entered.
The relationship between the current gain indicated by the gain control signal and the number of on / off control signals to be H level signals is as described above. However, the impedance of the I VGA 5 viewed from the input terminal 5g minimizes the current gain. Regardless, since it is desirable to be constant, the total number of unit cells including the on-gate grounded transistor 141 is constant among the total of 2 × N unit cells in the variable gain sections 121 and 122 of the I VGA 5. The number of ON / OFF control signals that are H level signals is determined so as to be a value.
Specifically, for example, if the number of unit cells that provide an H level signal as an on / off control signal among N unit cells in the variable gain unit 121 is (N−3), the variable gain unit 122. Of the N unit cells, the number of unit cells that supply an H level signal as an on / off control signal is three.
For example, if the number of unit cells that provide an H level signal as an on / off control signal among N unit cells in the variable gain unit 121 is (N−5), the N unit cells in the variable gain unit 122 Of the unit cells, the number of unit cells that provide an H level signal as an on / off control signal is five.

Since the impedance of the Q VGA 6 viewed from the input terminal 6g is preferably constant regardless of the minimum current gain, the impedance of the 2 × N unit cells in the variable gain sections 131 and 132 in the Q VGA 6 is also desirable. Among them, the number of ON / OFF control signals that are H level signals is determined so that the total number of unit cells including the grounded-gate transistor 141 in the ON state becomes a constant value.
As a result, the total value of the bias current flowing through the variable gain sections 121, 122, 131, 132 is also constant, and the input impedance viewed from the source terminal is also constant.

In the unit cells in the variable gain sections 121, 122, 131, 132, when an H level signal is input from the on / off control terminal 145 as an on / off control signal, the switch 146 becomes conductive. In addition, since the signal level of the on / off control signal is inverted by the inverter 147, the switch 148 is turned off.
In the unit cell, when the switch 146 is turned on and the switch 148 is turned off, the bias control signal that is current-mirrored by the transistors 123 and 133 is supplied to the gate terminal of the grounded gate transistor 141 and the grounded gate transistor The bias current of 141 is adjusted.

In the unit cells in the variable gain sections 121, 122, 131, and 132, when an L level signal is input from the on / off control terminal 145 as an on / off control signal, the switch 146 is turned off. Further, the signal level of the on / off control signal is inverted by the inverter 147, so that the switch 148 becomes conductive.
The unit cell is configured such that when the switch 146 is turned off and the switch 148 is turned on, the potential between the gate terminal and the source terminal of the grounded gate transistor 141 is equal to or lower than the threshold potential of the grounded gate transistor 141. The potential of the gate terminal of the ground transistor 141 is set. As a result, the grounded-gate transistor 141 is turned off.

Among the N unit cells in the variable gain sections 121 and 131, the unit cell to which the H level signal is input as the on / off control signal is connected to the gate grounded transistor 141 whose bias current is adjusted, from the source terminal 142 to the I signal. Alternatively, when a Q signal is input, the current gain is increased by outputting the I signal or the Q signal from the drain terminal 143 to the signal synthesis unit 7.
Among the N unit cells in the variable gain sections 122 and 132, the unit cell to which the H level signal is input as the on / off control signal is connected to the gate grounded transistor 141 whose bias current is adjusted, from the source terminal 142 to the I signal. Alternatively, when a Q signal is input, the current gain is lowered by outputting the I signal or the Q signal from the drain terminal 143 to the power supply terminals 120 and 130.
As a result, the I signal and the Q signal are amplified with the current gain indicated by the gain control signal output from the gain control unit 9 as in the first embodiment. Further, the orthogonality between the I signal and the Q signal is enhanced by the bias control signal output from the bias control unit 10.
In the fifth embodiment, since the I-use VGA 5 and the Q-use VGA 6 in which the common-gate transistor and the variable gain unit are integrated are mounted, the number of transistors stacked in the vertical direction is larger than that in the first embodiment. Therefore, an improvement in linearity and an improvement in high frequency characteristics due to a decrease in parasitic components are realized.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  The vector synthesizing phase shifter according to the present invention is suitable for a wireless communication device that shifts the phase of an input signal.

  1a, 1b input terminal, 2 polyphase filter, 3 LPF (low pass filter), 3a, 3b inductor element, 3c, 3d capacitive element, 4 HPF (high pass filter), 4a, 4b capacitive element, 4c, 4d Inductor element, 5I VGA (first variable gain amplifier), 5a, 5b, 5g input terminal, 5c, 5d, 5h output terminal, 5e gain control terminal, 5f bias control terminal, 6Q VGA (second Variable gain amplifier), 6a, 6b, 6g input terminal, 6c, 6d, 6h output terminal, 6e gain control terminal, 6f bias control terminal, 7 signal synthesizer, 7a, 7b load impedance, 7c, 7d power supply terminal, 8a, 8b Output terminal, 9 Gain control unit, 10 Bias control unit, 11a, 11b Common gate transistor, 12 Bias voltage, 1 3a, 13b Variable current source, 14 Variable gain section, 15a, 15b, 16a, 16b, 17a, 17b Transistor, 18a, 18b Power supply terminal, 21a, 21b Common gate transistor, 22 Bias voltage, 23a, 23b Variable current source, 24 Variable gain section, 25a, 25b, 26a, 26b, 27a, 27b Transistor, 28a, 28b Power supply terminal, 31, 32, 33 Transistor, 41, 42, 43 Transistor, 51, 52 Termination impedance, 60 Phase shifter, 71 Shift Phase amount setting unit, 72 output terminal, 73 input terminal, 74 analog-digital converter, 75 input terminal, 76 analog-digital converter, 77 multiplier, 78 difference calculation unit, 79 table unit, 80 bias control signal generation unit, 81 Digital-to-analog converter, 82 outputs Terminal, 83 input terminal, 84 analog-digital converter, 85 input terminal, 86 analog-digital converter, 87,88 multiplier, 89 difference calculation unit, 91 resonator (first resonator), 92 resonator (second resonator) ), 101, 102 Drain terminal of the grounded gate transistor, 103, 104 transistor, 111 LPF (low pass filter), 111a, 111b inductor element, 111c, 111d capacitive element, 112 HPF (high pass filter), 112a, 112b Capacitance element, 112c, 112d Inductor element, 120 power supply terminal, 121, 122 variable gain section, 123 transistor, 130 power supply terminal, 131, 132 variable gain section, 133 transistor, 141 common gate transistor, 142 source terminal, 143 Do In terminal, 144 a gate bias input terminal, 145 on-off control terminal, 146 switch, 147 inverter, 148 switch.

Claims (6)

A polyphase filter that includes an inductor element and a capacitive element, and extracts an in-phase signal and a quadrature signal from an input signal;
A first variable gain having an input-stage transistor for inputting the common-mode signal extracted by the polyphase filter; amplifying the common-mode signal; and changing a bias current of the transistor to change an input impedance. An amplifier;
A second variable gain amplifier having an input stage transistor for inputting a quadrature signal extracted by the polyphase filter, amplifying the quadrature signal, and changing an input impedance when a bias current of the transistor changes ; ,
A signal that combines the in-phase signal amplified by the first variable gain amplifier and the quadrature signal amplified by the second variable gain amplifier, and outputs a combined signal of the in-phase signal and the quadrature signal A synthesis unit;
A gain control unit that adjusts the phase of the combined signal without changing the amplitude of the combined signal output from the signal combining unit by controlling the gains of the first and second variable gain amplifiers;
And a bias control unit that controls a bias current of a transistor of an input stage included in the first and second variable gain amplifiers. The polyphase filter is
A low-pass filter including an inductor element and a capacitive element;
A high-pass filter including an inductor element and a capacitive element;
The vector synthesis type phase shifter according to claim 1, wherein the low-pass filter extracts the in-phase signal from the input signal, and the high-pass filter extracts the quadrature signal from the input signal. . A first resonator connected between the polyphase filter and the first variable gain amplifier to increase an input side impedance in an input stage transistor of the first variable gain amplifier;
A second resonator connected between the polyphase filter and the second variable gain amplifier, and configured to increase an input side impedance of an input stage transistor included in the second variable gain amplifier; The vector synthesis type phase shifter according to claim 1. The polyphase filter is
A first resonator for increasing an input side impedance in an input stage transistor of the first variable gain amplifier;
2. The vector synthesis type phase shifter according to claim 1, further comprising: a second resonator that increases an input side impedance in an input stage transistor of the second variable gain amplifier. 3.   2. The vector synthesis according to claim 1, wherein the polyphase filter, the first variable gain amplifier, the second variable gain amplifier, and the signal synthesis unit have a differential configuration that handles differential signals. Type phase shifter. A polyphase filter that includes an inductor element and a capacitive element, and extracts an in-phase signal and a quadrature signal from an input signal;
A first variable gain having an input-stage transistor for inputting the common-mode signal extracted by the polyphase filter; amplifying the common-mode signal; and changing a bias current of the transistor to change an input impedance. An amplifier;
A second variable gain amplifier having an input stage transistor for inputting a quadrature signal extracted by the polyphase filter, amplifying the quadrature signal, and changing an input impedance when a bias current of the transistor changes ; ,
A signal that combines the in-phase signal amplified by the first variable gain amplifier and the quadrature signal amplified by the second variable gain amplifier, and outputs a combined signal of the in-phase signal and the quadrature signal A synthesis unit;
A gain control unit that adjusts the phase of the combined signal without changing the amplitude of the combined signal output from the signal combining unit by controlling the gains of the first and second variable gain amplifiers;
A wireless communication device mounting a vector synthesis type phase shifter comprising: a bias control unit that controls a bias current of a transistor in an input stage included in the first and second variable gain amplifiers.

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