JP6409697B2 - Semiconductor device inspection circuit and inspection method - Google Patents

Description

  The present invention relates to an inspection circuit and an inspection method for a semiconductor element having a switching element.

  Conventionally, as this type of inspection circuit, for example, Patent Document 1 has proposed the following inspection circuit. That is, in this inspection circuit, a switch is disposed between a power supply and a semiconductor element (DUT: Device Under Test) to be inspected, and an ammeter for measuring a current flowing through the DUT is disposed. Further, a controller for controlling on / off of the switch based on the measurement result of the ammeter is arranged. As the DUT, a switching element such as an IGBT element that has a gate electrode and is controlled to be turned on and off by applying high-level and low-level gate signals to the gate electrode is used.

  In such an inspection circuit, when the DUT is turned off (when a low-level gate signal is applied to the gate electrode), the current is easily concentrated and destroyed. In the inspection circuit, when the result measured by the ammeter is larger than a predetermined threshold, the controller determines that the DUT is destroyed and turns off the switch. That is, when the DUT is destroyed and a large current flows through the DUT, the switch is turned off by the controller. For this reason, when a DUT is destroyed, it can control that inspection equipment, such as a stage used for inspecting DUT, and a probe, is damaged.

JP 2008-164364 A

  However, the inspection circuit requires a period from when the DUT is actually destroyed until it is determined that the DUT is destroyed, and a period from when it is determined that the DUT is destroyed until the switch is turned off. For this reason, a large current may flow through the DUT before the switch is turned off, and in this case, the inspection device may be damaged.

  In this regard, the present inventors have inspected a DUT as an inspection target having a gate electrode and a switching element that is controlled to be turned on and off by applying a high-level and low-level gate signal to the gate electrode. In the DUT inspection circuit, an inspection circuit having the following features has been proposed.

  That is, in this inspection circuit, a gate electrode is provided between the DUT and a power source connected to the DUT, and on / off is controlled by applying high-level and low-level gate signals to the gate electrode. A protective element having a switching element having a greater breakdown resistance than the switching element is disposed. Then, when a low level gate signal is applied to the gate electrode of the DUT to turn off the DUT, the protection element has a predetermined period after the low level gate signal is applied to the gate electrode of the DUT. The connection between the power source and the DUT is cut off by applying a low level gate signal to the gate electrode.

  According to this, even if the DUT is destroyed by a transient current by applying a low-level gate signal to the gate electrode of the DUT, a predetermined period elapses after the low-level gate signal is applied to the gate electrode of the DUT. The protection element is always turned off. Accordingly, by appropriately adjusting the period between the time point when the low level gate signal is applied to the gate electrode of the DUT and the time point when the low level gate signal is applied to the gate electrode of the protection element, a large current is generated in the DUT. Flow can be suppressed and damage to the inspection device can be suppressed. Moreover, since the protection element has a greater breakdown resistance than the DUT, it is possible to suppress the protection element from being destroyed at the same time when the DUT is destroyed.

  However, there is a delay time from when the low level gate signal is applied to the protection element until the current flowing through the DUT starts to decrease due to the application of the low level gate signal to the protection element. Therefore, depending on the length of the period from when the low level gate signal is applied to the DUT to when the low level gate signal is applied to the protection element, and the length of the delay time, the current may flow after the DUT is destroyed. The time until it starts to decrease becomes longer, and the damage to the inspection equipment increases. In the above-described inspection circuit proposed by the present inventors, it is necessary to further suppress damage to the inspection device in this respect.

  In view of the above points, the present invention provides a DUT inspection circuit and an inspection method capable of suppressing damage to an inspection device when the DUT is destroyed.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a switching element (5a) which is controlled to be turned on and off by applying a high level and a low level gate signal. In an inspection circuit for a semiconductor element for inspecting a semiconductor element (5) as an inspection object having a characteristic that the interruption of a current passing through a switching element is completed when a predetermined interruption time has elapsed since the application of a level gate signal, Protection connected between a semiconductor element and a power source (1) connected to the semiconductor element, and controlled to be turned on and off by applying high-level and low-level gate signals, and has a greater breakdown resistance than a switching element A switching element (4a), and a predetermined delay after a low-level gate signal is applied to the protective switching element; A protection element (4) having a characteristic that a current passing through the protection switching element starts to decrease when time elapses, and a control unit (10) for controlling on / off of the semiconductor element and the protection element, the control unit When the semiconductor element is turned off, the timing at which the low-level gate signal is applied to the protective element and the delay after the timing between when the low-level gate signal is applied to the semiconductor element and until the cutoff time elapses. The timing of applying a low-level gate signal to the protection element is set so that time is included.

  According to this, when the semiconductor element is turned off, the control unit applies the low-level gate signal to the protective element between the application of the low-level gate signal to the semiconductor element and the passage of the cutoff time. The timing for applying the low-level gate signal to the protection element is set so that the timing and the delay time after the timing are included. Further, the period from when the low-level gate signal is applied to the semiconductor element until the cutoff time elapses includes a period during which the semiconductor element is highly likely to be destroyed. Therefore, by applying a low-level gate signal to the protection element at this timing, it is possible to suppress damage to the inspection device when the semiconductor element is destroyed.

  According to the fifth aspect of the present invention, the switching element (5a), which is controlled to be turned on and off by application of high level and low level gate signals, has a low level gate signal. In a semiconductor element inspection method for inspecting a semiconductor element (5) as an inspection object having a characteristic of completing the interruption of a current passing through a switching element when a predetermined interruption time has elapsed since the application, the semiconductor element and the semiconductor element A high-level and low-level gate signal is applied to the power supply (1) connected to the power supply (1), and the protection switching element (4a) having a higher breakdown resistance than the switching element is controlled by turning on and off. Protection when a predetermined delay time has elapsed since the low-level gate signal was applied to the protection switching element. When the protective element (4) having the characteristic that the current passing through the switching element starts to decrease is disposed and the semiconductor element is turned off, the low-level gate signal is applied to the semiconductor element and the cutoff time elapses. The timing for applying the low level gate signal to the protection element is set so that the timing at which the low level gate signal is applied to the protection element and the delay time after the timing are included.

  Thus, the present invention can be grasped as a DUT inspection method. According to this inspection method, when the semiconductor element is turned off, the low-level gate signal is applied to the protective element between the time when the low-level gate signal is applied to the semiconductor element and the cutoff time elapses. The timing for applying the low-level gate signal to the protection element is set so that the timing and the delay time after the timing are included. Further, the period from when the low-level gate signal is applied to the semiconductor element until the cutoff time elapses includes a period during which the semiconductor element is highly likely to be destroyed. Therefore, by applying a low-level gate signal to the protection element at this timing, it is possible to suppress damage to the inspection device when the semiconductor element is destroyed.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is a circuit diagram of the inspection circuit of DUT in a 1st embodiment of the present invention. It is a flowchart which shows the inspection method of DUT. It is a timing chart which shows operation | movement of 1st Embodiment. It is a timing chart which shows operation of a comparative example. It is a timing chart which shows the relationship between the OFF speed of a protection element, and an electric current. It is a circuit diagram of the test | inspection circuit in 2nd Embodiment of this invention. It is a circuit diagram of the test | inspection circuit in 3rd Embodiment of this invention. It is a circuit diagram of the test | inspection circuit in 4th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. In this embodiment, an inspection circuit and an inspection method for performing a DUT switching test will be described.

  As shown in FIG. 1, the inspection circuit of this embodiment includes a power source 1, an overcurrent protection switch 2, a coil 3, a protection element 4, a DUT 5, an ammeter 6, a diode element 7, a first capacitor 8, and a second capacitor 9. The control unit 10 is provided.

  An overcurrent protection switch 2, a coil 3, a protection element 4, a DUT 5, and an ammeter 6 are connected in series to the power source 1. The overcurrent protection switch 2 is for protecting the power supply 1 and a tester (not shown) when the DUT 5 is destroyed, and is turned off when the destruction of the DUT 5 is detected. The overcurrent protection switch 2 is composed of, for example, an N-channel IGBT (insulated gate bipolar transistor) element having a gate electrode, a collector electrode, and an emitter electrode.

  The coil 3 is for controlling a current flowing through the DUT 5 in order to examine characteristics when the DUT 5 is turned on and off. Specifically, when the overcurrent protection switch 2 and the protection element 4 are turned on and the DUT 5 is switched from OFF to ON in a state where no current flows through the coil 3, the current flowing through the coil 3 and the DUT 5 It gradually increases due to the inductance of 3.

  A diode element 7 is arranged in the inspection circuit so as to be parallel to the coil 3. When the DUT 5 is turned off, a reflux current flows through a loop path formed by the coil 3 and the diode element 7. When the DUT 5 is turned on while the return current is flowing through the loop path, the return current path is switched, and the current flowing through the DUT 5 increases sharply.

  In the present embodiment, the diode element 7 is composed of an FWD (free wheel diode) element. The cathode electrode of the diode element 7 is connected to the connection point between the overcurrent protection switch 2 and the coil 3, and the anode electrode of the diode element 7 is connected to the connection point between the coil 3 and the protection switch 4.

  The protection element 4 is for protecting the inspection device when the DUT 5 is destroyed. Although the overcurrent protection switch 2 is arranged to protect the inspection device in the same manner as the protection element 4, the protection element 4 plays a role of protecting the inspection device when the first capacitor 8 is discharged.

  The DUT 5 is an inspection target in this embodiment, and corresponds to a semiconductor element of the present invention. In this embodiment, the protection element 4 and the DUT 5 are configured by N-channel IGBT elements having a gate electrode, a collector electrode, and an emitter electrode.

  That is, the protection element 4 and the DUT 5 are configured by switching elements that are controlled to be turned on and off by applying high-level and low-level gate signals to the gate electrodes. Further, the protection element 4 is composed of an IGBT element having a greater breakdown resistance than the DUT 5.

  The DUT 5 has a characteristic that the current passing through the DUT 5 starts to decrease when a predetermined delay time Td1 has elapsed since the low level gate signal was applied. Further, the DUT 5 has a characteristic that the interruption of the current passing through the DUT 5 is completed when a predetermined interruption time has elapsed after the low-level gate signal is applied. Further, the protection element 4 has a characteristic that the current passing through the protection element 4 starts to decrease when a predetermined delay time Td2 has elapsed after the low-level gate signal is applied.

  One end of the coil 3 is connected to the positive electrode of the power supply 1 via the overcurrent protection switch 2, and the collector electrode of the protection element 4 is connected to the other end of the coil 3. The collector electrode of the DUT 5 is connected to the emitter electrode of the protection element 4, and the negative electrode (ground) of the power source 1 is connected to the emitter electrode of the DUT 5 via the ammeter 6. The protection element 4 may be arranged in series with the coil 3 with respect to the power source 1. However, as described above, the protection element 4 has a role of protecting the inspection device from the discharge of the first capacitor 8. The protective element 4 is preferably arranged on the DUT 5 side with respect to the first capacitor 8.

  The ammeter 6 measures the current flowing through the DUT 5 in order to detect the destruction of the DUT 5. The method described in Patent Document 1 can be used as a method for detecting destruction. The ammeter 6 is connected to the control unit 10 as shown in FIG. 1, and the control unit 10 detects an overcurrent based on the output of the ammeter 6 and determines whether or not the DUT 5 is destroyed. .

  As described above, the ammeter 6 measures the current flowing through the DUT 5, and the control unit 10 detects the destruction of the DUT 5 based on the output of the ammeter 6. Therefore, the ammeter 6 and the control unit 10 correspond to the destruction detection means of the present invention.

  The first capacitor 8 is a capacitor for reducing parasitic inductance, reducing ripple during switching, and suppressing the influence of noise. The first capacitor 8 is arranged so as to be in parallel with the coil 3, the protection element 4, the DUT 5, the ammeter 6, and the diode element 7 with respect to the power supply 1.

  The second capacitor 9 is a capacitor for reducing the parasitic inductance to form a constant power supply voltage, and a capacitor having a larger capacity than the first capacitor 8 is used as the second capacitor 9. The second capacitor 9 is arranged in parallel with the overcurrent protection switch 2, the coil 3, the protection element 4, the DUT 5, the ammeter 6, the diode element 7, and the first capacitor 8 with respect to the power source 1.

  The control unit 10 is configured by a known microcomputer that includes a CPU, a ROM, a RAM, an I / O, and the like. The control unit 10 executes processing such as various calculations in accordance with a program stored in a ROM or the like, controls on / off of the protection element 4 and the DUT 5, and performs a switching test of the DUT 5. As shown in FIG. 1, the overcurrent protection switch 2, the protection element 4, the DUT 5, and the ammeter 6 are connected to the control unit 10. The above is the inspection circuit in the present embodiment.

  Next, a method for inspecting the DUT 5 using the above inspection circuit will be described. Inspecting the DUT 5 is basically performed by applying high-level or low-level gate signals Vg1 and Vg2 to the gate electrodes of the DUT 5 and the protection element 4 to control on and off, and changing the current and voltage flowing through the DUT 5. By doing. 3 and 4, the high-level gate signals Vg1 and Vg2 are illustrated as H, and the low-level gate signals Vg1 and Vg2 are illustrated as L.

  In the inspection circuit of the present embodiment, a switching test when the DUT 5 is turned off is performed by the control unit 10 performing the operation shown in the flowchart of FIG. Specifically, the control unit 10 inspects the DUT 5 by alternately repeating the operation of turning on the DUT 5 and the protection element 4 and the operation of turning off the DUT 5 and the protection element 4 multiple times.

  In the present embodiment, the control unit 10 changes the length of time from when the low level gate signal is applied to the DUT 5 to when the low level gate signal is applied to the protection element 4, and thus the DUT 5 and the protection element 4. Repeat the operation to turn off the sever. Further, the control unit 10 determines whether or not the DUT 5 is destroyed while alternately repeating the operation of turning on the DUT 5 and the protection element 4 and the operation of turning off the DUT 5 and the protection element 4 a plurality of times.

  When the switching test is started, in step S101, the control unit 10 performs an operation according to condition 1, and proceeds to step S102. Specifically, after the overcurrent protection switch 2 and the protection element 4 are turned on, the control unit 10 turns on the DUT 5 at time T1 as shown in FIG. Then, the control unit 10 turns off the DUT 5 at a time point T2 after a lapse of a predetermined time, and turns off the protection element 4 when a certain period Tdelay1 has elapsed from the time point T2.

  As shown in FIG. 3, the current Ic starts to decrease at time T3 when the delay time Td1 has elapsed from time T2. If the DUT 5 is not destroyed in step S107, which will be described later, the current Ic becomes 0 at the time T4 when the cutoff time of the DUT 5 has elapsed from the time T2.

  When the DUT 5 is turned off, the control unit 10 applies a low-level gate signal to the protection element 4 between the time T2 when the low-level gate signal is applied to the DUT 5 and the time T4 when the DUT 5 shutoff time elapses. The timing for applying the low-level gate signal to the protection element 4 is set so that the applied timing and the delay time Td2 after this timing are included. That is, the control unit 10 applies the low-level gate signal to the protection element 4 so that the sum of the period Tdelay1 and the delay time Td2 becomes smaller than the difference between the time T4 and the time T2.

  The period between the time point T3 at which the decrease in the current Ic flowing through the DUT 5 is started by turning off the DUT 5 and the time point T4 at which the interruption of the current Ic is completed is a period during which the DUT 5 is highly likely to be destroyed. By starting reduction of the current Ic due to the protection element 4 being turned off within this period, it is possible to suppress damage to the inspection equipment when the DUT 5 is destroyed.

  In the present embodiment, at the time T5 between the time T3 and the time T4, the decrease in the current Ic due to the protection element 4 being turned off is started.

  In step S <b> 102, the control unit 10 determines whether the DUT 5 has been destroyed based on the signal from the ammeter 6. Specifically, for example, after the DUT 5 is turned off in step S101, when the current flowing through the DUT 5 becomes a value larger than a predetermined threshold, the control unit 10 determines that the DUT 5 has been destroyed.

  When it is determined that the DUT 5 has not been destroyed, the control unit 10 proceeds to step S103. When the control unit 10 determines that the DUT 5 has been destroyed, the control unit 10 stops the subsequent operation of turning off the DUT 5 and the protection element 4, and ends the switching test of the DUT 5. In step S103, the control unit 10 performs an operation according to condition 2, and proceeds to step S104.

  Specifically, after the overcurrent protection switch 2 and the protection element 4 are turned on, the control unit 10 turns on the DUT 5 at time T1 as shown in FIG. Then, the control unit 10 turns off the DUT 5 at a time point T2 after a lapse of a predetermined time, and turns off the protective element 4 when a certain period Tdelay2 longer than the period Tdelay1 has elapsed from the time point T2.

  In step S104, the control unit 10 determines whether or not the DUT 5 has been destroyed, as in step S102. If the control unit 10 determines that the DUT 5 is not destroyed, the process proceeds to step S105. If the control unit 10 determines that the DUT 5 is destroyed, the application of the power supply voltage and the gate voltage to the DUT 5 is stopped, and the test ends. In step S105, the control unit 10 performs an operation according to condition 3, and proceeds to step S106.

  Specifically, after the overcurrent protection switch 2 and the protection element 4 are turned on, the control unit 10 turns on the DUT 5 at time T1 as shown in FIG. Then, the control unit 10 turns off the DUT 5 at a time point T2 after a lapse of a predetermined time, and turns off the protection element 4 when a certain period Tdelay3 longer than the period Tdelay2 has elapsed from the time point T2.

  In step S106, the control unit 10 determines whether or not the DUT 5 is destroyed as in step S102. When determining that the DUT 5 is not destroyed, the control unit 10 proceeds to step S107, and when determining that the DUT 5 is destroyed, the control unit 10 ends the switching test of the DUT 5. In step S107, the control unit 10 performs an operation of always turning on the protection element 4.

  Specifically, the control unit 10 turns on the DUT 5 at the time T1 after turning on the overcurrent protection switch 2 and the protection element 4. And control part 10 turns off DUT5 in time T2 after progress of predetermined time. After step S107, the control unit 10 keeps the protection element 4 on until the switching test for the DUT 5 is completed. By the operation in step S107 of the control unit 10, the confirmation of the characteristics of the DUT 5 that has not been destroyed under the conditions 1 to 3 is completed.

  The controller 10 performs the above operation by applying a single pulse gate signal to the protection element 4 and the DUT 5. That is, the control unit 10 performs the operation of step S103 after a sufficiently long time has elapsed after the protection element 4 and the DUT 5 are turned off in step S101.

  When the DUT 5 is turned off, a reflux current flows through the coil 3 and the diode element 7. When the protection element 4 and the DUT 5 are turned on while the return current is flowing, the current Ic increases sharply. However, after step S101, a sufficiently long time has elapsed, that is, the return current is attenuated to 0. When the operation of step S103 is performed after the current becomes, the current Ic gradually increases. Therefore, by applying a single pulse gate signal to the protection element 4 and the DUT 5 and performing the above operation, the ON characteristic of the DUT 5 is not inspected, and only the OFF characteristic can be examined. Similarly, the control unit 10 performs the operation in step S105 after a sufficiently long time has elapsed after step S103, and performs the operation in step S107 after a sufficiently long time has elapsed after step S105.

  FIG. 4 shows changes in the current Ic in the inspection circuit and the inspection method of the comparative example. In the inspection method of the comparative example, the control unit 10 turns off the protection element 4 after a lapse of a certain period Tdelay from the time point T2, but the delay time Td2 is before the current Ic starts to decrease after the protection element 4 is turned off. Exists.

  Therefore, due to the timing of destruction of the DUT 5, the length of the fixed period Tdelay and the delay time Td2, the time from the destruction of the DUT 5 to the time T6 when the current Ic starts to decrease due to the protection element 4 being turned off becomes longer. Damage increases.

  For example, when the DUT5 destruction timing is early and the DUT5 is destroyed at the time T7, the DUT5 destruction timing is late, and when the DUT5 is destroyed at the time T8 after the time T7, the time when the DUT5 is destroyed. To the time T6 is long. For this reason, when the DUT 5 is destroyed early, the inspection equipment is greatly damaged.

  In the graph of current Ic in FIG. 4, the broken line after time T7 indicates current Ic when the characteristics of DUT 5 are normal and DUT 5 is not destroyed. The solid line indicates the current Ic when the DUT 5 is destroyed at the time T7. The alternate long and short dash line indicates the current Ic when the DUT 5 is destroyed at time T8.

  On the other hand, in the present embodiment, when the control unit 10 turns off the DUT 5 in step S101, the control unit 10 applies a low level to the protection element 4 after the low level gate signal is applied to the DUT 5 until the cutoff time elapses. The timing at which the low-level gate signal is applied to the protection element 4 is set so that the timing at which the level gate signal is applied and the delay time after this timing are included. That is, as shown in FIG. 3, the control unit 10 turns off the protection element 4 so that the time T5 is earlier than the time T4.

  Further, the period from when the low level gate signal is applied to the DUT 5 until the cutoff time elapses includes a period during which the DUT 5 is likely to be destroyed. Further, by applying a low level gate signal to the protection element 4 at this timing, the current Ic starts to decrease within a period in which the DUT 5 is highly likely to be destroyed. Therefore, it is possible to suppress a large current from flowing through the DUT 5 and suppress damage to the inspection equipment due to the destruction of the DUT 5 when the DUT 5 has an early destruction timing. Thereby, the inspection cost can be reduced.

  Moreover, since damage to the inspection device is suppressed in this way, a switching test can be performed using a larger current than in the comparative example.

  Further, the protection element 4 has a greater breakdown resistance than the DUT 5. For this reason, when DUT5 is destroyed, it can control that protection element 4 is also destroyed simultaneously.

  Further, in the inspection circuit of the comparative example, the magnitude of damage of the inspection device changes due to variations in the timing of the DUT 5 destruction. On the other hand, in this embodiment, as shown in FIGS. 2 and 3, the control unit 10 applies the low level gate signal to the DUT 5 until the low level gate signal is applied to the protection element 4. The operation of turning off the DUT 5 and the protection element 4 is repeated a plurality of times by gradually increasing the time. Thereby, as shown in FIG. 3, even if DUT5 is destroyed at any time from time T2 to time T4, damage to the inspection device can be suppressed.

  For example, when the DUT 5 is not destroyed by the operation according to the condition 1 of the control unit 10 and is destroyed by the operation according to the condition 2, when the time period including the period Tdelay2 and the delay time Td2 elapses after the time T2, The current Ic begins to decrease. In step S104, it is determined that the DUT 5 has been destroyed, and the subsequent pulse application to the DUT 5 is stopped.

  Further, when the DUT 5 has characteristics that are not destroyed by the operation according to the conditions 1 and 2 of the control unit 10 and is destroyed by the operation according to the condition 3, the time when the period Tdelay3 and the delay time Td2 are combined has elapsed. The current Ic begins to decrease. In step S106, it is determined that the DUT 5 has been destroyed, and the subsequent voltage application to the DUT 5 is stopped.

  Further, when the DUT 5 is not destroyed even in the operation according to the condition 3 of the control unit 10, an operation of always turning on the protective element 4 after the time T2 is performed in step S107, and the test is completed.

  That is, the control unit 10 determines the DUT 5 with the earlier breakdown timing by performing the operations of Steps S101 to S106 before the switching test of Step S107 in which the protection element 4 is always turned on, and stops the switching test for the DUT 5 To do. Therefore, since the switching test DUT5 in which the protection element 4 is always turned on is performed only for the DUT 5 with a late destruction timing, it is possible to suppress an increase in the time from when the DUT 5 is destroyed until the current Ic is cut off. .

  In the graph of current Ic when DUT 5 in FIG. 3 is destroyed, the solid line indicates current Ic when DUT 5 is destroyed in step S103, and the alternate long and short dash line indicates current Ic when DUT 5 is destroyed in step S105. Indicates.

  As described above, in the present embodiment, it is possible to suppress an increase in the time from when the DUT 5 is destroyed until the current Ic is cut off, regardless of when the DUT 5 is destroyed from the time T2 to the time T4. It is possible to suppress damage to the inspection equipment when the is destroyed.

  In addition, since the operation of always turning on the protective element 4 is performed in step S107, the DUT 5 that is not destroyed in the condition 3 can be inspected without reducing the inspection load such as current and voltage.

  Further, when a switching test is performed on a plurality of DUTs 5, it is possible to suppress an increase in the time from when the DUT 5 is destroyed until the current Ic is cut off for each DUT 5. Thereby, the dispersion | variation in the magnitude | size of the damage of a test | inspection apparatus by the timing of destruction of each DUT5 can be made small. This also stabilizes the maintenance cycle of inspection equipment such as a stage and a probe, thereby reducing inspection costs.

  In the present embodiment, the inspection according to the conditions 1 to 3 is performed before the switching test in step S107 in which the protection element 4 is always turned on. However, only the inspection according to the condition 1 may be performed before step S107. Moreover, you may perform only the test | inspection by the conditions 1 and 2 before step S107. Further, an inspection for determining the DUT 5 with the earlier destruction timing is performed before the step S107 by changing the length of the period from the time T2 to the time when the low-level gate signal is applied to the protection element 4 more finely than in the present embodiment. May be performed four or more times. The timing of applying the low-level gate signal to the protection element 4 is finely changed to perform a plurality of inspections, thereby further suppressing the damage of the inspection equipment and the magnitude of the damage of the inspection equipment due to the timing of the DUT 5 destruction. The variation can be further reduced.

  In the present embodiment, a single pulse gate signal is applied to the protection element 4 and the DUT 5, but a double pulse gate signal may be applied to the protection element 4 and the DUT 5. That is, after the DUT 5 is turned off in step S101, the protection element 4 and the DUT 5 may be turned on in step S103 before the return current flowing through the coil 3 and the diode element 7 is attenuated to zero. Thereby, when the DUT 5 is turned on in step S103, the current Ic increases steeply, so that not only the off characteristic of the DUT 5 but also the on characteristic can be examined. Further, since the control unit 10 does not wait for the return current to become zero and proceeds to step S103, the switching test can be performed in a shorter time than when a single pulse gate signal is applied to the protection element 4 and the DUT 5. it can.

  Similarly, the operation of turning on the protection element 4 and the DUT 5 may be repeated three or more times after the DUT 5 is turned off and before the return current flowing through the coil 3 and the diode element 7 is attenuated to zero.

  In the inspection circuit, a first capacitor 8 is arranged in parallel with the coil 3, the protection element 4, the DUT 5, the ammeter 6, and the diode element 7. That is, the protective element 4 is disposed between the current paths formed by the first capacitor 8 and the DUT 5. For this reason, the connection between the first capacitor 8 and the DUT 5 can be cut off by turning off the protection element 4, and a large current flows through the DUT 5 due to the energy accumulated in the coil 3 when the DUT 5 is destroyed. Can be suppressed.

  As shown by the broken line in FIG. 5, when the off speed di / dt of the protection element 4 is slow, the time from when the protection element 4 is turned off until the current Ic is cut off increases, and the inspection equipment is damaged. growing. Therefore, it is preferable that the off speed of the protection element 4 is made faster than the off speed of the DUT 5 indicated by a one-dot chain line in FIG. 5 by selecting an element having a small gate resistance, selecting an appropriate gate driver, or the like. Thereby, as shown by the solid line in FIG. 5, it is possible to shorten the time from when the protection element 4 is turned off until the current Ic is cut off, thereby further suppressing damage to the inspection device.

  In this embodiment, in step S107, the control unit 10 performs an operation of turning on the protection element 4 at all times. However, after the control unit 10 applies a low-level gate signal to the DUT 5, May be turned on for a sufficiently long time.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the first embodiment is used for both the switching test and the recovery test, and the other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here.

  In the present embodiment, as shown in FIG. 6, the DUT 5 includes an IGBT element 5a and a diode element 5b connected in parallel with the IGBT element 5a. In FIG. 6, the ammeter 6 and the control unit 10 are not shown. The protection element 4 includes an IGBT element 4a and a diode element 4b connected in parallel with the IGBT element 4a. The IGBT elements 4a and 5a correspond to the protection switching element and the switching element of the present invention, respectively.

  And the opposing element 11 comprised by the IGBT element 11a and the diode element 11b is arrange | positioned so that it may be connected with the protection element 4 and DUT5 in series with respect to the power supply 1, and in this embodiment, the power supply 1 of The counter element 11, the protection element 4, and the DUT 5 are arranged in this order from the positive electrode side.

  The IGBT element 11a of the counter element 11 is controlled to be turned on / off by applying a high level or low level gate signal to the gate electrode. Each diode element 4b, 5b, 11b has a cathode electrode connected to the collector electrode of each IGBT element 4a, 5a, 11a, and an anode electrode connected to the emitter electrode of each IGBT element 4a, 5a, 11a. Further, each of the IGBT elements 4a, 5a, 11a and the respective diode elements 4b, 5b, 11b in the protection element 4, the DUT 5, and the counter element 11 may have a one-chip structure formed on a common semiconductor substrate. It may be a separate chip structure formed on a separate semiconductor substrate.

  And the 1st switch 12 and the 2nd switch 13 are arrange | positioned so that it may become in parallel with the opposing element 11, the protection element 4, and DUT5. The coil 3 is arranged so as to connect a connection point between the first switch 12 and the second switch 13 and a connection point between the counter element 11 and the protection element 4. In addition, the 1st switch 12 and the 2nd switch 13 are comprised by switching elements, such as an IGBT element and a MOS element.

  In such a test circuit, the IGBT element 11a, 4a, 5a, the first switch 12, and the second switch 13 of the counter element 11, the protection element 4, and the DUT 5 are controlled to turn on and off the current and voltage flowing through the DUT 5. The characteristic inspection of the DUT 5 is performed by changing it.

  That is, when the characteristics of the diode element 5b in the DUT 5 are mainly inspected, the first switch 12 is turned off and the second switch 13 is turned on, and the protection element 4 and the IGBT elements 4a and 5a of the DUT 5 are turned off. The IGBT element 11a of the element 11 may be driven and controlled.

  When the characteristics of the IGBT element 5a in the DUT 5 are mainly inspected, the first switch 12 is turned on and the second switch 13 is turned off, and the IGBT element 4a of the protection element 4 is turned on, and the IGBT element 5a of the DUT 5 is turned on. May be driven and controlled.

  As described above, even when the DUT 5 includes the IGBT element 5a and the diode element 5b, the same effect as that of the first embodiment can be obtained by performing the switching test by the method shown in FIG.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the configuration of the inspection circuit is changed so that the avalanche test of the DUT 5 is performed with respect to the first embodiment. .

  As shown in FIG. 7, the inspection circuit of the present embodiment does not include the diode element 7 and is configured to perform an avalanche test on the DUT 5. Then, when performing the avalanche test, as in the first embodiment, the operation of turning off the protection element 4 after turning off the DUT 5 is repeated a plurality of times while changing the conditions of the timing at which the protection element 4 is turned off. In FIG. 7, the ammeter 6 and the control unit 10 are not shown.

  Thus, even when the present invention is applied to the inspection circuit for the avalanche test, the same effect as that of the first embodiment can be obtained.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, the configuration of the inspection circuit is changed so as to perform a short circuit test of the DUT 5 with respect to the first embodiment. The other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here. .

  As shown in FIG. 8, the inspection circuit of the present embodiment does not include the coil 3 and the diode element 7, and is configured to perform a short circuit test on the DUT 5. When performing the short-circuit test, as in the first embodiment, the operation of turning off the protection element 4 after turning off the DUT 5 is repeated a plurality of times while changing the timing conditions for turning off the protection element 4. In FIG. 8, illustration of the ammeter 6 and the control unit 10 is omitted.

  Thus, even when the present invention is applied to the inspection circuit for the short circuit test, the same effect as that of the first embodiment can be obtained.

(Other embodiments)
In addition, this invention is not limited to above-described embodiment, In the range described in the claim, it can change suitably.

  For example, in the first to fourth embodiments, the DUT 5 does not have an IGBT element, but may have a switching element such as a MOS element or a bipolar transistor.

  Alternatively, a voltmeter that measures the voltage applied to the DUT 5 may be used as the destruction detection means, and it may be determined that the DUT 5 has been destroyed when the voltage applied to the DUT 5 becomes smaller than a predetermined threshold value. The inspection circuit may not include the overcurrent protection switch 2 and the first capacitor 8.

  In the first to fourth embodiments, the protection element 4 may be disposed on the negative electrode side of the power source 1 from the DUT 5. In the first embodiment, the diode element 7 and the coil 3 may be disposed on the negative electrode side of the power source 1 with respect to the DUT 5 and the protection element 4. That is, the arrangement of the coil 3, the protection element 4, and the DUT 5 can be changed as appropriate. Similarly, in the second to fourth embodiments, the arrangement location of the DUT 5 can be changed as appropriate. Moreover, in each said embodiment, you may arrange | position the protection element 4 between the positive electrode of the power supply 1, and the coil 3, for example.

1 Power supply 4 Protection element 5 DUT
10 Control unit

Claims (7)

It has a switching element (5a) that is controlled to be turned on and off by applying a high level and a low level gate signal, and a predetermined cutoff time has elapsed since the low level gate signal was applied to the switching element. In the semiconductor element inspection circuit for inspecting the semiconductor element (5) as an inspection object having a characteristic that the interruption of the current passing through the switching element is completed when
It is connected between the semiconductor element and a power source (1) connected to the semiconductor element, and is controlled to be turned on and off by applying high level and low level gate signals, and is more resistant to breakdown than the switching element. Having a large protection switching element (4a), and having a characteristic that the current passing through the protection switching element starts to decrease when a predetermined delay time has elapsed since a low-level gate signal was applied to the protection switching element. A protective element (4);
A control unit (10) for controlling on and off of the semiconductor element and the protective element,
The control unit applies a low-level gate signal to the protection element during a period from when a low-level gate signal is applied to the semiconductor element until the cutoff time elapses when the semiconductor element is turned off. An inspection circuit for a semiconductor element, wherein a timing for applying a low-level gate signal to the protection element is set so that the timing and the delay time after the timing are included.   The control unit changes the length of time from application of a low level gate signal to the semiconductor element to application of a low level gate signal to the protection element, thereby controlling the semiconductor element and the protection element. The semiconductor element inspection circuit according to claim 1, wherein the turning-off operation is repeated a plurality of times. Destruction detection means (6, 10) for detecting destruction of the semiconductor element,
The breakdown detecting means is configured such that during the inspection, the control unit repeats the operation of turning on the semiconductor element and the protective element and the operation of turning off the semiconductor element and the protective element alternately several times. Determine if the element is destroyed,
3. The semiconductor element inspection circuit according to claim 2, wherein when the destruction detection unit detects the destruction of the semiconductor element, the control unit stops the inspection of the semiconductor element thereafter.   4. The semiconductor element inspection circuit according to claim 1, wherein an off speed of the protection element is faster than an off speed of the semiconductor element. 5. It has a switching element (5a) that is controlled to be turned on and off by applying a high level and a low level gate signal, and a predetermined cutoff time has elapsed since the low level gate signal was applied to the switching element. In the semiconductor element inspection method for inspecting the semiconductor element (5) as an inspection object having a characteristic that the interruption of the current passing through the switching element is completed when
High and low level gate signals are applied between the semiconductor element and the power source (1) connected to the semiconductor element to control on / off, and the breakdown resistance is larger than that of the switching element. A protective element having a protective switching element (4a) and having a characteristic that a current passing through the protective switching element starts to decrease when a predetermined delay time has elapsed after a low-level gate signal is applied to the protective switching element. (4) is placed,
When the semiconductor element is turned off, the timing at which the low-level gate signal is applied to the protection element between the time when the low-level gate signal is applied to the semiconductor element and the time when the blocking time elapses, and the timing after The timing for applying a low-level gate signal to the protection element is set so that the delay time is included.   A plurality of operations of turning off the semiconductor element and the protection element by changing a length of time from application of a low level gate signal to the semiconductor element to application of a low level gate signal to the protection element 6. The method for inspecting a semiconductor device according to claim 5, wherein the method is repeated a number of times. It is determined whether or not the semiconductor element is destroyed during an inspection performed by alternately repeating the operation of turning on the semiconductor element and the protection element and the operation of turning off the semiconductor element and the protection element. ,
The method for inspecting a semiconductor element according to claim 6, wherein when it is determined that the semiconductor element has been destroyed, the subsequent inspection of the semiconductor element is stopped.

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