JP6399871B2 - Imaging apparatus and control method thereof - Google Patents

Description

  The present invention relates to an imaging apparatus and a control method thereof.

  There is an imaging apparatus that records and reproduces still images and moving images captured by a solid-state imaging device such as a CCD image sensor or a CMOS image sensor. CMOS imaging devices are increasingly used as solid-state imaging devices mounted on imaging devices in terms of low voltage and low power consumption. In this CMOS image sensor, when a very strong light such as sunlight is irradiated, the level of the output voltage of the pixel irradiated with the strong light abruptly attenuates, and the gradation of the pixel sinks to a black gradation. Sometimes. This phenomenon is referred to as a high-luminance black sun phenomenon in this specification.

  The high-intensity black sun phenomenon occurs when the CMOS image pickup device is irradiated with strong light at the time of reading out the noise level signal, and the charge overflows from the photoelectric conversion unit and the noise level signal increases. Specifically, when a noise level signal is read from the detection node (floating diffusion) of the pixel, a part of a large amount of charge generated in the photoelectric conversion unit (photodiode) leaks to the detection node of the pixel. .

  When a large amount of charge flows into the detection node of the pixel, the noise level voltage becomes smaller than the ideal reset level voltage and becomes close to the optical signal level voltage. In this case, when an image signal is obtained by correlated double sampling (CDS) processing for calculating the difference between the voltage at the noise level and the voltage at the optical signal level, the luminance component of the image signal is calculated to be smaller than the original luminance component. . This is the mechanism of the high-intensity black sun phenomenon.

  The above-described voltage magnitude relationship is an example in which electrons are used as signal charges and an N-type MOS transistor is used as an amplification MOS transistor that reads a signal to a signal line. When holes are used as signal charges or P-type MOS transistors are used as amplification MOS transistors, the direction of voltage change is reversed, and the noise level voltage rises due to the black sun phenomenon.

  As a technique for solving such a high-intensity black sun phenomenon, for example, a method of operating clip means for preventing a noise level signal from lowering below a predetermined potential has been proposed (see Patent Document 1). .

  By the way, while CMOS image sensors of recent digital cameras are increasing in number of pixels, there is a need for high frame rate shooting such as outputting image data of 1920 × 1080 pixels at 30 fps or 60 fps, for example, as in full HD video. Is also growing. In response to this need, a thinning method is known as a technique for reducing the number of pixels in order to perform high frame rate imaging with a CMOS image sensor having a high number of pixels. In the thinning-out method, the driving method is switched to reduce the number of pixels by skipping pixels at a specific period, and the frame rate is increased by reducing the data rate.

  In the thinning-out method, pixels are skipped at a specific period, and as a feature of image quality to be captured, there is a problem that moire, which is a kind of aliasing noise, is conspicuous while it is advantageous for detecting an edge of a subject. As a technique for reducing this moire, a technique has been proposed in which the output of a pixel skipped in the thinning-out method is mixed with the output of an adjacent readout pixel to reduce the number of pixels for output. For example, in the pixel mixing method described in Patent Document 2, a plurality of rows of pixel signals are mixed and output by simultaneously selecting and outputting a plurality of rows by a row selection circuit.

JP 2004-222273 A Japanese Patent No. 4723994

  However, in the readout drive in which a plurality of rows are simultaneously selected and mixed output of pixel signals of a plurality of rows is performed, the output signal clip as described above is performed on the signal output on the vertical output line as a countermeasure against the high luminance black sun phenomenon. The following concerns arise. When a plurality of rows are selected simultaneously for mixed output, the drive current of the amplification MOS transistors per row depends on the number of selected rows unless the total amount of current supplied to the vertical output line is increased according to the number of selected rows. fluctuate. As a result, the source voltage of the amplification MOS transistor changes according to the number of selected rows, and the operating point such as the reset level potential on the vertical output line changes. As a result, the appropriate clip potential as a countermeasure against the high-intensity black sun phenomenon will differ depending on whether mixed output is performed or not. Therefore, it is sufficient to use a fixed clip potential regardless of the driving method. There is a risk that the effect of preventing black sun set may not be obtained.

  An object of the present invention is to provide an imaging apparatus capable of appropriately suppressing the high-intensity black sun phenomenon regardless of the driving mode of pixel signal readout in a solid-state imaging device.

  An imaging apparatus according to the present invention includes a photoelectric conversion unit that converts incident light into charges, a charge-voltage conversion unit that converts charges generated in the photoelectric conversion unit into voltage, and charges generated in the photoelectric conversion unit as the charge voltage. A plurality of pixels arranged two-dimensionally, each having a transfer unit for transferring to the conversion unit, and an output unit for outputting a signal corresponding to the voltage converted by the charge-voltage conversion unit to a signal line; A clipping circuit that clips the potential of the first voltage, and outputs a first signal to the signal line in a state where the charge-voltage conversion unit is reset, and charges generated in the photoelectric conversion unit are transferred to the charge-voltage conversion unit A solid-state imaging device that outputs a second signal to the signal line in a transferred state, and the first signal is output from the output unit to the signal line when a pixel signal is read from a pixel of the solid-state imaging device When the chestnut Clips potential of the signal line by flop circuit, and having a control unit for controlling in accordance with the number of rows of pixels are selected simultaneously.

  According to the present invention, the potential of the signal line can be clipped at an appropriate clip level according to the driving mode of pixel signal readout in the solid-state imaging device, and the high-intensity black-sink phenomenon can be implemented, and the high-intensity black-sink phenomenon is appropriately suppressed It becomes possible to do.

It is a figure which shows the structural example of the imaging device in embodiment of this invention. It is a figure which shows the structural example of the solid-state image sensor in this embodiment. It is a figure which shows the structural example of the pixel in this embodiment. It is explanatory drawing of the example of the combination of the read-out pixel in 1st Embodiment. It is a figure which shows the structural example of the clip circuit in 1st Embodiment. It is a figure which shows the relationship between incident light quantity and a vertical output line electric potential. It is a figure which shows the relationship between an incident light quantity and an output signal. It is explanatory drawing of the clip electric potential of the still image drive in 1st Embodiment. It is explanatory drawing of the clip electric potential of the 1st moving image drive in 1st Embodiment. 6 is a timing chart illustrating an example of driving during still image driving in the first embodiment. 5 is a timing chart illustrating an example of driving during the first moving image driving in the first embodiment. 3 is a flowchart illustrating an example of control of the imaging apparatus according to the first embodiment. It is explanatory drawing of the example of the combination of the read-out pixel in 2nd Embodiment. It is a figure which shows the structural example of the clip circuit in 2nd Embodiment. It is explanatory drawing of the clip electric potential of the still image drive in 2nd Embodiment. It is explanatory drawing of the clip potential of the 1st moving image drive in 2nd Embodiment. It is explanatory drawing of the clip electric potential of the 2nd moving image drive in 2nd Embodiment. 10 is a flowchart illustrating an example of control of the imaging apparatus according to the second embodiment. It is explanatory drawing of the example of the combination of the read-out pixel in 3rd Embodiment. It is a figure which shows the structural example of the clip circuit in 3rd Embodiment. It is explanatory drawing of the clip electric potential of the 1st moving image drive in 3rd Embodiment. It is explanatory drawing of the clip electric potential of the 3rd moving image drive in 3rd Embodiment. It is explanatory drawing of the clip electric potential of the 4th moving image drive in 3rd Embodiment. 10 is a flowchart illustrating an example of control of the imaging apparatus according to the third embodiment. It is explanatory drawing of the example of the combination of the read-out pixel in 4th Embodiment. It is a figure which shows the structural example of the clip circuit in 4th Embodiment. It is explanatory drawing of the clip electric potential at the time of VOB part read in 4th Embodiment. It is explanatory drawing of the clip electric potential at the time of the effective pixel part read-out in 4th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described. The imaging device according to the first embodiment is configured to vary the clip potential of the pixel reset output signal on the vertical output line (column output line) between the still image driving and the moving image driving in the solid-state imaging device included in the imaging device. is there.

  FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to the present embodiment. In FIG. 1, 101 is an optical system including a lens and a diaphragm, and 102 is a mechanical shutter. Reference numeral 103 denotes a solid-state imaging device that converts incident light into an electrical signal, and in this embodiment is a CMOS imaging device. An analog signal processing circuit 104 performs analog signal processing on an image signal output from the solid-state image sensor 103. A timing signal generation circuit 105 generates a signal (operation pulse) for operating the solid-state image sensor 103 and the analog signal processing circuit 104. A drive circuit 106 drives the optical system 101 and the mechanical shutter 102.

  A digital signal processing circuit 107 performs digital signal processing on the captured image data. Reference numeral 108 denotes an image memory for storing image-processed image data. The image memory 108 is used, for example, for temporarily storing image data being signal-processed or for storing image-processed image data. Reference numeral 109 denotes an image recording medium that can be removed from the imaging apparatus, and reference numeral 110 denotes a recording circuit that records image-processed image data on the image recording medium 109. Reference numeral 111 denotes an image display unit that displays an image, and reference numeral 112 denotes a display circuit that causes the image display unit 111 to display an image related to signal-processed image data.

  A system control unit 113 controls the entire imaging apparatus. The system control unit 113 includes, for example, a microcontroller and an arithmetic processing unit (CPU). 114 is a nonvolatile memory for storing a program describing a control method executed by the system control unit 113, control data such as parameters and tables used when executing the program, correction data such as a scratch address, and the like (ROM). Reference numeral 115 denotes a volatile memory (RAM) that transfers and stores a program, control data, correction data, and the like stored in the nonvolatile memory 114 and is used when the system control unit 113 controls the imaging apparatus. . Reference numeral 116 denotes a shooting mode setting unit for setting shooting conditions such as shooting sensitivity (ISO sensitivity) setting and switching between shooting modes of still image shooting and moving image shooting.

  Hereinafter, a photographing operation using the imaging apparatus according to the present embodiment will be described. Prior to the shooting operation, the program, control data, correction data, and the like are transferred from the non-volatile memory 114 to the volatile memory 115 and stored at the start of the operation of the system control unit 113 such as when the imaging apparatus is turned on. And These programs, data, and the like are used when the system control unit 113 controls the imaging apparatus. Further, if necessary, additional programs and data are transferred from the non-volatile memory 114 to the volatile memory 115, or the system control unit 113 directly reads out and uses the data in the non-volatile memory 114. And

  In the shooting operation, the optical system 101 such as a lens is driven so as to form a subject image on the solid-state image sensor 103 with appropriate brightness by a control signal from the system control unit 113. Further, during still image shooting, the mechanical shutter 102 is driven by a control signal from the system control unit 113 so as to shield the solid-state image sensor 103 in accordance with the operation of the solid-state image sensor 103 so as to have an appropriate exposure time. The In the case where the solid-state imaging device 103 has an electronic shutter function, an appropriate exposure time may be ensured in combination with the mechanical shutter 102. In addition, the mechanical shutter 102 is maintained in an open state so that the solid-state imaging device 103 is always exposed during shooting by a control signal from the system control unit 113 during moving image shooting and live view driving.

  The solid-state image sensor 103 is driven by a driving pulse based on an operation pulse generated by the timing signal generation circuit 105 controlled by the system control unit 113, and converts the subject image into an electric signal by photoelectric conversion as an analog image signal. Output. The analog image signal output from the solid-state image sensor 103 is amplified by the analog signal processing circuit 104 with a gain of an amplification factor set according to the amount of incident light, and clamped using the signal output in the optical black (OB) region as a reference voltage. And converted into a digital image signal. The analog signal processing circuit 104 is driven by operation pulses generated by the timing signal generation circuit 105 controlled by the system control unit 113. The optical black (OB) region is a light-shielded pixel region in which the front surface of a photodiode (photoelectric conversion element) of a pixel in the region is shielded from light.

  Next, the digital image signal output from the analog signal processing circuit 104 is subjected to image processing such as color conversion, white balance, and gamma correction, resolution conversion processing, and image processing in the digital signal processing circuit 107 controlled by the system control unit 113. Compression processing or the like is performed. The image data signal-processed by the digital signal processing circuit 107 and the image data stored in the image memory 108 are converted into data suitable for the image recording medium 109 by the recording circuit 110 and recorded on the image recording medium 109, for example. . For example, after the resolution conversion process is performed by the digital signal processing circuit 107, the display circuit 112 converts the signal into a signal suitable for the image display unit 111 and displays the signal on the image display unit 111.

  Here, the digital signal processing circuit 107 may output the digital image signal as it is as image data to the image memory 108 or the recording circuit 110 without performing signal processing by the control signal from the system control unit 113. The digital signal processing circuit 107 outputs the digital image signal and image data information generated in the signal processing process to the system control unit 113 when requested by the system control unit 113. The information output to the system control unit 113 is, for example, information such as the spatial frequency of the image, the average value of the designated area, the data amount of the compressed image, or information extracted from them. Further, the recording circuit 110 outputs information such as the type and free capacity of the image recording medium 109 to the system control unit 113 when requested by the system control unit 113.

  A reproduction operation when image data is recorded on the image recording medium 109 will be described. The recording circuit 110 reads image data from the image recording medium 109 by a control signal from the system control unit 113. In addition, when the read image data is a compressed image, the digital signal processing circuit 107 performs an image expansion process according to a control signal from the system control unit 113 and stores it in the image memory 108. The image data stored in the image memory 108 is subjected to resolution conversion processing by the digital signal processing circuit 107, converted to a signal suitable for the image display unit 111 by the display circuit 112, and displayed on the image display unit 111. The

  Next, the solid-state image sensor 103 in the present embodiment will be described with reference to FIG. FIG. 2 is a diagram illustrating a configuration example of the solid-state imaging device 103 in the present embodiment. In the solid-state image sensor 103, a plurality of unit pixels 200 are arranged in a matrix (two-dimensional). In FIG. 2, a total of 16 unit pixels 200 of 4 rows and 4 columns are illustrated, but actually, the solid-state image sensor 103 has millions and tens of millions of unit pixels 200. The unit pixels 200 are arranged according to a Bayer array, and generally provided with red (R), green (G), and blue (B) color filters, respectively. In addition, in order to raise the light reception efficiency of the infrared light generally used as projection light and reflected light more, you may arrange | position the pixel which formed the infrared filter and the transparent filter.

  FIG. 3 is a circuit diagram illustrating a configuration example of the unit pixel 200 of the solid-state imaging device 103 in the present embodiment. The unit pixel 200 has one photodiode 301. One transfer switch 302 is connected to the photodiode 301, and a floating diffusion 303 is connected to the transfer switch 302. A reset switch 304 and a source follower amplifier 305 are connected to the floating diffusion 303, and a selection switch 306 is connected to the source follower amplifier 305. The drains of the reset switch 304 and the source follower amplifier 305 share the reference potential VDD 307.

  The photodiode 301 functions as a photoelectric conversion unit, receives light incident through the microlens, and generates a signal charge corresponding to the amount of incident light. The transfer switch 302 functions as a transfer unit, is controlled by a transfer pulse signal PTX, and transfers charges generated in the photodiode 301 to the floating diffusion 303. The floating diffusion 303 functions as a charge-voltage conversion unit, temporarily holds the charge transferred from the photodiode 301, and converts the held charge into a voltage signal.

  The reset switch 304 is controlled by the reset pulse signal PRES, and resets the potential of the floating diffusion 303 to the reference potential VDD307. The source follower amplifier 305 functions as a photoelectric conversion unit, constitutes a reference follower VDD 307 and a source follower circuit, amplifies a voltage signal based on the charge held in the floating diffusion 303, and outputs it as a pixel signal. The selection switch 306 is controlled by the selection pulse signal PSEL and outputs the pixel signal amplified by the source follower amplifier 305 to the vertical output line 202. The source follower amplifier 305 and the selection switch 306 function as an output unit. The vertical output line (column output line) 202 is shared by a plurality of unit pixels 200 sharing a column.

  Returning to FIG. 2, the vertical shift register (vertical scanning circuit) 201 selects pixels arranged in a matrix (two-dimensional form) in units of rows via signal lines φRES, φTX, and φSEL connected to each row. Drive. The reset pulse signal PRES is supplied via the signal line φRES, the transfer pulse signal PTX is supplied via the signal line φTX, and the selection pulse signal PSEL is supplied via the signal line φSEL.

  The voltage signal converted by the floating diffusion 303 of the unit pixel 200 is input to the column circuit 203 through the vertical output lines 202A and 202B. The column circuit 203 includes a clamp capacitor (C0) 208, a feedback capacitor (Cf) 209, an operational amplifier 210, a reference power supply 211, a switch 212, a capacitor (CTS) 213, a capacitor (CTN) 214, and switches 215, 216, 217, and 218. Have.

  The clamp capacitor (C0) 208 has one end connected to the vertical output line 202 and the other end connected to one input terminal of the operational amplifier 210. The feedback capacitor (Cf) 210 is connected between the output terminal of the operational amplifier 210 and one input terminal. A reference voltage Vref is supplied from the reference power supply 211 to the other input terminal of the operational amplifier 210. The switch 212 is a switch for short-circuiting both ends of the feedback capacitor (Cf) 209 and is controlled by a reset signal PC0R.

  A capacitor (CTS) 213 and a capacitor (CTN) 214 are capacitors for holding a signal voltage. The capacitor (CTS) 213 holds the optical signal level (optical signal component and noise component), and the capacitor (CTN) 214 holds the reset signal level (noise component). The switches 215 and 216 are switches that control writing to the capacitor (CTS) 213 and the capacitor (CTN) 214. The switch 215 is controlled by a control signal PTS, and the switch 216 is controlled by a control signal PTN. The switches 217 and 218 are switches for outputting signals to the output amplifier 207 via the horizontal output lines 205 and 206. The switch 217 is controlled by a control signal PHS from a horizontal shift register (horizontal scanning circuit) 204, and the switch 218 is controlled by a control signal PHN from the horizontal shift register 204.

  The current source 219 is a current source load that becomes a load of the source follower amplifier 305 included in the unit pixel 200. The signal processed by the column circuit 203 is transferred by the horizontal shift register 204 to the output amplifier 207 via the horizontal output lines 205 and 206. The output amplifier 207 outputs a difference signal between the signals transferred through the horizontal output lines 205 and 206. Further, a clip circuit 220 as clip means for limiting the potential is connected to the vertical output lines 202A, 202B and the like. The configuration of the clip circuit 220 will be described later with reference to FIG.

  Next, an example of a combination of pixels that mix pixel signals when the pixel output signals are mixed in the vertical direction (column direction) of the pixel array in the solid-state imaging device during moving image driving will be described with reference to FIG. FIG. 4 is a diagram for explaining an example of a combination of vertical pixel mixing in the first embodiment. The letters “R” and “G” in the pixel 200 shown in FIG. 4 indicate the types of color filters on the pixel, respectively. “R” is a red filter and “G” is a green filter. Indicates a pixel. A line connecting the pixels 200 indicates a combination of pixels when the pixel signals are vertically mixed.

In still image driving, since signals of pixels in all rows are read without being mixed, the lines between the pixels 200 are shown without being connected (FIG. 4A).
In the moving image drive, the first embodiment has a configuration in which pixel signals of three pixels in the vertical direction (column direction) are mixed and read out, and the three pixels 200 having the same color are connected to each other (FIG. 4 ( b)). In the example shown in FIG. 4B, for the pixel “R”, for example, the pixel 200 in the n-th row is connected to the pixel 200 in the (n−2) -th and (n + 2) -th rows. That is, the pixel signals of the pixels 200 in the (n−2) th row, the nth row, and the (n + 2) th row are mixed and read out. Similarly, for the pixel “G”, for example, the pixel signals of the pixels 200 in the (n + 1) th row, the (n + 3) th row, and the (n + 5) th row are mixed and read out.

  Next, a configuration example of the clip circuit 220 in the first embodiment will be described with reference to FIG. FIG. 5 is a circuit diagram illustrating the clip circuit 220 of the solid-state image sensor 103 according to the first embodiment. The clip circuit 220 includes switch transistors 501, 502, 503, and 504, a source follower (SF) transistor 506, and an inverter 507. The switch transistors 501 to 504 and the SF transistor 506 are all NMOS transistors.

  The switch transistor 503 is controlled by the control signal PCLN0 and supplies the potential VCLN0 to the node VCLN when the control signal PCLN0 is at a high level. The switch transistor 504 is controlled by the control signal PCLN1, and supplies the potential VCLN1 to the node VCLN when the control signal PCLN1 is at a high level. Note that the control signal PCLN0 and the control signal PCLN1 are controlled so as not to be at a high level at the same time. Further, the potential VCLN0 and the potential VCLN1 are different from each other, and in this embodiment, the potential VCLN0 <the potential VCLN1.

  The switch transistor 502 is controlled by the control signal PCLS supplied via the inverter 507, and applies the potential of the node VCLN to the gate of the SF transistor 506 when the control signal PCLS is at a low level. The SF transistor 506 performs a source follower operation together with the constant current source 219, and supplies the voltage of the node VCLN to the vertical output line (column output line) 202. At this time, the switch transistor 501 is off. As a result, the potential generated in the vertical output line 202 is limited by the potential VCLN0 or the potential VCLN1 which is the gate potential of the SF transistor 506.

  The switch transistor 501 is controlled by the control signal PCLS, and applies the potential VCLS to the gate of the SF transistor 506 when the control signal PCLS is at a high level. The SF transistor 506 performs a source follower operation together with the constant current source 219 and supplies the voltage VCLS to the vertical output line 202. At this time, the switch transistor 502 is off. Thereby, the potential generated in the vertical output line 202 is limited by the potential VCLS which is the gate potential of the SF transistor 506.

  As described above, the potential generated on the vertical output line 202 is limited to the potential VCLS by the clip circuit 220 when the control signal PCLS is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN0 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN0 is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN1 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN1 is at a high level. Note that the potential VCLS described with reference to FIG. 5 is a clip level that restricts the potential of the vertical output line 202 so as not to exceed a predetermined amount when the optical signal level is read.

  Next, an appropriate clip level (clip potential) set by the clip circuit 220 will be described with reference to FIGS. FIG. 6 is a graph showing the transition of the signal potential (N signal potential) when reading the reset signal and the signal potential (S signal potential) when reading the optical signal in the vertical output line 202 with respect to the incident light amount. FIG. 7 is a graph showing the transition of the output signal with respect to the amount of incident light. Note that the broken line shown in FIG. 7 is an output saturation level that is set to align the output signal values of the respective pixels at the time of signal saturation. An output signal that exceeds a predetermined upper limit value set by the digital signal processing circuit 107 with respect to the output signal digitized by the analog signal processing circuit 106 is clipped to this output saturation level.

  FIGS. 6A and 7A show transitions of the potential of the S signal, the potential of the N signal, and the output signal with respect to the amount of incident light when the potential of the vertical output line is not clipped when the reset signal is read. 6A, the potential of the S signal in the vertical output line 202 decreases in proportion to the amount of incident light when the amount of incident light is small, and maintains the saturation level above the amount of light reaching the saturation level (FIG. 6). The same applies to 6 (b) to FIG. 6 (d). Further, the potential of the N signal in the vertical output line 202 maintains a level close to the reset level in the normal incident light amount region. The potential of the N signal in the vertical output line 202 is such that, in a region where high-luminance light that saturates the photodiode is incident during the reset signal readout period, charge overflow to the N signal occurs. It goes down.

  As a result, as shown in FIG. 7A, the output signal increases as the S signal increases while the amount of incident light is small, and maintains the saturation level of the S signal even after the S signal is saturated. Also, the output signal starts to decrease as the N signal increases due to the incidence of the high-intensity light, and both the S signal and the N signal are saturated in a region where the N signal is saturated or more than the amount of incident light. The output signal which is a difference signal is almost 0 output.

  FIGS. 6B and 7B show the potential of the S signal and the potential of the N signal and the output signal when the vertical output line is clipped at the potential VCLN lower than the reset level when the reset signal is read. It shows the transition. In FIG. 6B, the potential of the N signal in the vertical output line 202 drops in the region where the high-intensity light is incident as in the case where the potential of the vertical output line shown in FIG. 6A is not clipped. To go. However, the potential of the N signal in the vertical output line 202 is clipped at the potential VCLN and is not lowered further.

  As a result, as shown in FIG. 7B, the output signal is saturated as the N signal increases due to the incidence of high-intensity light, as in the case where the potential of the vertical output line shown in FIG. 7A is not clipped. Start to decrease from the level. However, since the N signal does not fall below the predetermined level, the output signal that is the difference signal also does not decrease below the predetermined level. However, since the level is lower than the output saturation level, some darkening occurs in the output image.

  FIGS. 6C and 7C show the potential of the S signal and the potential of the N signal and the output when the vertical output line is clipped at the potential VCLN slightly lower than the reset level when the reset signal is read. It shows the transition of the signal. Also in FIG. 6C, the potential of the N signal in the vertical output line 202 is the same as that in the case where the vertical output line shown in FIG. It is not lowered beyond a predetermined level.

  As a result, as shown in FIG. 7C, the output signal decreases from a predetermined level when high-intensity light is incident, as in the case where the vertical output line shown in FIG. 7B is clipped at the potential VCLN. No longer. In addition, since the level is higher than the output saturation level, it is possible to eliminate blackout in the output image.

  6D and 7D show the potential of the S signal and the potential of the N signal and the output signal when the vertical output line is clipped at a potential VCLN higher than the reset level when the reset signal is read. It shows the transition. In this case, as shown in FIG. 6D, the potential of the N signal in the vertical output line 202 is clipped to a potential higher than the actual reset level, and information as the N signal is lost. As a result, as shown in FIG. 7D, the output signal is floated, the correct value cannot be maintained, and the effect of the correlated double sampling (CDS) processing is impaired.

  As can be seen from the description using FIGS. 6 and 7, the potential VCLN for clipping the vertical output line when reading the reset signal is slightly lower than the reset level in consideration of the variation of each N signal column. It is desirable to set the potential. 8 and 9 illustrate an appropriate clip level (clip potential) in each drive when the reset level potential in the vertical output line is different between the still image drive and the moving image drive in the first embodiment. It is a figure to do.

  8 and 9, the potential V0 is a reset level in the vertical output line during still image driving, and the potential V1 is a reset level in the vertical output line during moving image driving. In this embodiment, since a plurality of rows are selected simultaneously to perform mixed output during moving image driving, the reset level potential V1 during moving image driving is the reset level potential during still image driving that selects only one row. It becomes higher than V0. The potential VCLN0 is a clip level appropriate for still image driving, and the potential VCLN1 is a clip level appropriate for moving image driving.

  FIG. 8A is a graph showing the transition of the N signal potential at the time of reading the reset signal and the S signal potential at the time of reading the optical signal in the vertical output line 202 with respect to the incident light amount in the still image driving in the first embodiment. is there. FIG. 8B is a graph showing the transition of the output signal with respect to the incident light amount in the still image driving in the first embodiment.

  FIG. 9A is a graph showing the transition of the N signal potential at the time of reading the reset signal and the S signal potential at the time of reading the optical signal in the vertical output line 202 with respect to the incident light amount in the moving image driving in the first embodiment. . FIG. 9B is a graph showing the transition of the output signal with respect to the incident light amount in the moving image driving in the first embodiment.

  As shown in FIGS. 8A and 9A, since the reset level of the vertical output line is different between the still image driving and the moving image driving, the appropriate clip level for each driving is also different. The appropriate clip level for each drive is preferably a potential slightly lower than the reset level in the vertical output line, as shown in the description using FIG. In the examples of FIGS. 8A and 9A, as the clip level, the potential VCLN0 is appropriate during still image driving, and the potential VCLN1 is appropriate during moving image driving.

  Conversely, if the clip level is set to the potential VCLN1 during still image driving, the output signal will float as shown in FIG. 8B. Also, if the clip level is set to the potential VCLN0 during moving image driving, as shown in FIG. 9B, if the output signal becomes lower than the output saturation level when high-luminance light is incident, the output image is somewhat reduced. Black sun set will occur. As described above with reference to FIGS. 6 to 9, it is desirable to set different potentials as the clip level in the vertical output line in the reset signal reading between the still image driving and the moving image driving with mixed output. .

  Next, read timing and control during still image driving and moving image driving in the first embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a timing chart illustrating an example of a pixel signal reading operation in still image driving according to the first embodiment. The driving method shown in FIG. 10 is a form in which the charges generated in the photodiode 301 of the unit pixel 200 are read for each row without being mixed in the vertical direction (column direction).

  In the period from time t0 to time t16, signal reading is performed on the pixels in the nth row. At time t0, as the signal HD indicating the start of one horizontal scanning period falls, the signal readout operation for the pixels in the n-th row is started. Thereafter, the floating diffusion 303 is reset while the reset pulse signal PRES is at a high level. At time t1, the transfer pulse signal PTXn is set to the high level, and the photodiode 301 of the pixel in the nth row is reset. At time t2, the transfer pulse signal PTXn is set to low level, and charge accumulation in the photodiode 301 of the pixel in the n-th row is started.

  After the charge accumulation is started, the selection pulse signal PSELn is set to the high level at time t3, and the source follower amplifier 305 of the pixel in the n-th row is set in an operating state. By resetting the reset pulse signal PRESn to the low level at time t4, the reset of the floating diffusion 303 of the pixels in the n-th row is released. The potential of the floating diffusion 303 at this time is read out as a reset signal level (noise component) to the vertical output line 202 and input to the column circuit 203.

  In the column circuit 203, the reset signal PC0R is set to low level at time t5, and the reference voltage Vref output buffer of the operational amplifier 210 is released. Then, at time t7 to t8, the control signal PTN is set to a high level in a pulse shape to operate the switch 216 (to bring it into a conductive state), thereby writing the reset signal level in the capacitor (CTN) 214. At this time, by setting the control signal PCLS to the low level at time t6, the clip level by the clip circuit 220 is set to the potential VCLN0 in addition to the control signal PCLN0 being always at the high level when driving the still image. . As a result, the lower limit of the signal potential of the vertical output line 202 is limited to the potential VCLN0 that is slightly lower than the reset level of the vertical output line during still image driving. At time t9, the control signal PCLS is set to the high level, and the clip level by the clip circuit 220 is set to the potential VCLS.

  Next, at time t <b> 10, the transfer pulse signal PTXn is set to the high level, and photocharges accumulated in the photodiodes 301 of the pixels in the n-th row are started to be transferred to the floating diffusion 303. Thereafter, at time t11, the transfer pulse signal PTXn is set to the low level, and the charge transfer to the floating diffusion 303 is completed. The potential fluctuation of the floating diffusion 303 according to the amount of charge transferred in such a series of processes is read as an optical signal level (light component + noise component) to the vertical output line 202 and input to the column circuit 203.

  In the column circuit 203, the optical signal level is written in the capacitor (CTS) 213 by setting the control signal PTS to a high level in a pulse shape at time t 12 to t 13 and operating the switch 215 (conducting). At this time, since the control signal PCLS is at a high level, the clipping level by the clipping circuit 220 is set to the potential VCLS, and thereby the lower limit of the signal potential of the vertical output line 202 is limited to the potential VCLS. When signals are written to the capacitor (CTS) 213 and the capacitor (CTN) 214, an inversion gain corresponding to the ratio of the clamp capacitor (C0) 208 and the feedback capacitor (Cf) 209 is applied and output.

  Thereafter, at time t14, the reset pulse signal PRES is set to the high level, and the floating diffusion 303 is reset. Next, signals held in the capacitor (CTS) 213 and the capacitor (CTN) 214 are read by the horizontal shift register 204. Between time t15 and time t16, the switches 217 and 218 are operated by sequentially setting the control signal PHS and the control signal PHN to a high level in pulses for each column circuit 203. As a result, signals held in the capacitor (CTS) 213 and the capacitor (CTN) 214 are input to the output amplifier 207 via the horizontal output lines 205 and 206, and are output as differential signal levels (light components) by the output amplifier 207. Is output.

  Subsequently, in the period from time t16 to time t32, signal readout is performed for the pixels in the next (n + 1) th row. However, the signal readout for the pixels in the (n + 1) -th row is (n + 1) by the signals PSEL (n + 1), PRES (n + 1), and PTX (n + 1) corresponding to the pixels in the (n + 1) -th row. ) The description is omitted because the only difference is the operation performed on the pixels in the row. After time t32, the next (n + 2) line, (n + 3) line,... Are read in order. As described above, signal readout from the pixels is sequentially performed row by row, thereby realizing readout driving for a still image.

  FIG. 11 is a timing chart illustrating an example of a pixel signal reading operation in moving image driving according to the first embodiment. In the driving method shown in FIG. 11, pixel signals are mixed and read in the vertical direction (column direction) by simultaneously reading out the charges generated in the photodiode 301 of the unit pixel 200 for every three pixels in the vertical direction (column direction). It is.

  During the period from time t0 to time t16, signal readout is performed on the pixels in the (n-2) th row, the nth row, and the (n + 2) th row, which are the three rows shown in FIG. Since the readout operation in the period from time t0 to time t16 is the same as the signal readout for the pixels in the n-th row in the still image driving shown in FIG. 10 except for the control for the clip circuit 220, the detailed description is omitted. To do. Since the signal PCLN1 is always at a high level during moving image driving, when the control signal PCLS becomes a low level at time t6, the clip level by the clip circuit 220 is set to the potential VCLN1. Thereby, the lower limit of the signal potential of the vertical output line 202 at the time of reading the signal of the reset signal level is limited to the potential VCLN1 slightly lower than the reset level of the vertical output line at the time of moving image driving.

  Subsequently, during the period from time t16 to time t32, signal readout is performed on the pixels in the (n + 1) th, (n + 3) th, and (n + 5) th rows, which are the three rows shown in FIG. 4B. . The readout operation in the period from time t16 to time t32 is the same as the signal readout for the pixels in the (n + 1) th row in the still image driving shown in FIG. Will be omitted. As described above, readout drive during moving images is realized by sequentially reading out signals from the pixels every three rows.

  With the drive control as described above, in the present embodiment, when the reset signal is read out, the still image driving without mixing in the vertical direction (column direction) and the moving image driving with mixing in the vertical direction (column direction) are performed. Control is performed so that the potential of the clip level in the vertical output line is different. Thereby, the operating point of the vertical output line is made to correspond to a different state in the vertical direction (column direction) between mixing and non-mixing.

  FIG. 12 is a flowchart illustrating an example of a method for controlling the imaging apparatus according to the first embodiment. First, a shooting mode setting such as still image shooting or moving image shooting is performed by the shooting mode setting unit 116 or the like (S1201). Subsequently, the system control unit 113 determines whether the mode set by the shooting mode setting unit 116 is the still image mode or the moving image mode (S1202).

  When it is determined that the mode set by the shooting mode setting unit 116 is the still image mode, the system control unit 113 performs initial setting of shooting conditions such as sensitivity, aperture value, and exposure time according to the mode. Is performed (S1203). Further, the system control unit 113 fixes the control signal PCLN0 to the high level so that the clip level on the vertical output line at the time of reset signal reading is set to the potential VCLN0 (S1204). After that, the system control unit 113 determines whether shooting start processing such as pressing the release switch has been performed (S1205). After the shooting start processing is performed, the system control unit 113 is stopped according to the driving of the timing chart shown in FIG. Image driving is executed (S1206).

  When it is determined that the mode set by the shooting mode setting unit 116 is the moving image mode, the system control unit 113 performs initial setting of shooting conditions such as sensitivity, aperture value, and exposure time according to the mode. This is performed (S1207). Further, the system control unit 113 fixes the control signal PCLN1 to a high level so that the clip level in the vertical output line at the time of reset signal reading is set to the potential VCLN1 (S1208). Thereafter, the system control unit 113 determines whether shooting start processing such as a moving image recording button is pressed (S1209), and after the shooting start processing is executed, the timing chart shown in FIG. 11 is driven. Accordingly, moving image driving is executed (S1210). Then, the system control unit 113 determines whether or not shooting end processing such as pressing the moving image recording button is performed again (S1211), and after the shooting end processing is executed, the moving image driving ends.

  In both the still image mode and the moving image mode, the image signal is finally output to the image memory 108, the recording circuit 110, or the display circuit 112 (S1212), and the photographing operation is terminated.

  According to the first embodiment, a plurality of rows are simultaneously selected during moving image driving and mixing in the vertical direction (column direction) of pixel signals is performed, and mixing in the vertical direction (column direction) is not performed during still image driving. Then, control is performed so that the clip level potential on the vertical output line at the time of reset signal reading differs between when moving images are driven and when still images are driven. As a result, even when the operating point of the vertical output line is different between when mixing and when not mixing in the vertical direction, an appropriate clip level is set according to the driving mode of pixel signal readout in the solid-state imaging device, and an appropriate clip level is set. It is possible to realize a black sun countermeasure and suppress the black sun phenomenon.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. The image pickup apparatus according to the second embodiment has a pixel reset output signal on a vertical output line (column output line) at the time of still image driving, at the time of first moving image reading read at a low speed, and at the time of second moving image reading read at a high speed. The clip potential is made different. Note that the configuration of the imaging apparatus, the configuration of the solid-state imaging device 103, and the configuration of the unit pixel 200 of the solid-state imaging device 103 in the second embodiment are the same as those in the first embodiment shown in FIGS. Therefore, the description is omitted.

  First, an example of a combination of pixels that mix pixel signals when the pixel signals are mixed and output in the vertical direction (column direction) of the pixel array in the solid-state imaging device during moving image driving will be described with reference to FIG. In the second embodiment, there are two types of driving modes at the time of moving image driving. It is assumed that the signals of the three pixels in the vertical direction are simultaneously read during the first moving image drive that is read at a low speed, and the signals of the five pixels in the vertical direction are simultaneously read during the second moving image drive that is read at a high speed. FIG. 13 is a diagram for explaining an example of a combination of vertical pixel mixing in the second embodiment. In FIG. 13, the lines connecting the pixels 200 indicate pixel combinations when the pixel signals are mixed in the vertical direction (column direction), as in FIG. 4.

In still image driving, pixels in all rows are read out without being mixed in the vertical direction, so the lines between the pixels 200 are not connected (FIG. 13A).
In the first moving image drive, in the second embodiment, it is assumed that the pixel signals of the three pixels in the vertical direction are mixed and read out, and the three pixels 200 having the same color are connected to each other (FIG. 13 ( b)). In the example illustrated in FIG. 13B, for the pixel “R”, for example, the pixel 200 in the n-th row is connected to the pixel 200 in the (n−2) -th and (n + 2) -th rows. That is, the pixel signals of the pixels 200 in the (n−2) th row, the nth row, and the (n + 2) th row are mixed and read out. Similarly, for the pixel “G”, for example, the pixel signals of the pixels 200 in the (n + 1) th row, the (n + 3) th row, and the (n + 5) th row are mixed and read out.

  In the second moving image drive, in the second embodiment, it is assumed that the pixel signals of five pixels in the vertical direction are mixed and read, and five pixels 200 of the same color are connected to each other (FIG. 13 ( c)). In the example illustrated in FIG. 13C, for the pixel “R”, for example, the pixel 200 in the nth row, the (n−4) th row, the (n−2) th row, the (n + 2) th row, and the (n + 4) row. ) The pixel 200 in the row is connected. That is, the pixel signals of the pixels 200 in the (n-4) th row, the (n-2) th row, the nth row, the (n + 2) th row, and the (n + 4) th row are mixed and read out. Similarly, for the pixel “G”, for example, the pixel signals of the pixels 200 in the (n + 1) th row, the (n + 3) th row, the (n + 5) th row, the (n + 7) th row, and the (n + 9) th row are mixed. And read out.

  Next, a configuration example of the clip circuit 220 in the second embodiment will be described with reference to FIG. FIG. 14 is a circuit diagram illustrating the clip circuit 220 of the solid-state image sensor 103 according to the second embodiment. The clip circuit 220 includes switch transistors 1401, 1402, 1403, 1404, 1405, a source follower (SF) transistor 1406, and an inverter 1407. The switch transistors 1401 to 1405 and the SF transistor 1406 are all NMOS transistors.

  The switch transistor 1403 is controlled by the control signal PCLN0, and supplies the potential VCLN0 to the node VCLN when the control signal PCLN0 is at a high level. The switch transistor 1404 is controlled by the control signal PCLN1, and supplies the potential VCLN1 to the node VCLN when the control signal PCLN1 is at a high level. The switch transistor 1405 is controlled by the control signal PCLN2, and supplies the potential VCLN2 to the node VCLN when the control signal PCLN2 is at a high level.

  Note that the control signal PCLN0, the control signal PCLN1, and the control signal PCLN2 are controlled so as not to be at a high level at the same time. That is, when any one of the control signal PCLN0, the control signal PCLN1, and the control signal PCLN2 is at a high level, the other two are at a low level. Further, the potential VCLN0, the potential VCLN1, and the potential VCLN2 are different from each other. In this embodiment, the potential VCLN0 <the potential VCLN1 <the potential VCLN2.

  The switch transistor 1402 is controlled by the control signal PCLS supplied via the inverter 1407, and applies the potential of the node VCLN to the gate of the SF transistor 1406 when the control signal PCLS is at a low level. The SF transistor 1406 performs a source follower operation together with the constant current source 219, and supplies the voltage of the node VCLN to the vertical output line (column output line) 202. At this time, the switch transistor 1401 is off. As a result, the potential generated in the vertical output line 202 is limited by any one of the potential VCLN0, the potential VCLN1, or the potential VCLN2, which is the gate potential of the SF transistor 1406.

  The switch transistor 1401 is controlled by the control signal PCLS, and applies the potential VCLS to the gate of the SF transistor 1406 when the control signal PCLS is at a high level. The SF transistor 1406 performs a source follower operation together with the constant current source 219 and supplies the voltage VCLS to the vertical output line 202. At this time, the switch transistor 1402 is off. As a result, the potential generated in the vertical output line 202 is limited by the potential VCLS that is the gate potential of the SF transistor 1406.

  As described above, the potential generated on the vertical output line 202 is limited to the potential VCLS by the clip circuit 220 when the control signal PCLS is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN0 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN0 is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN1 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN1 is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN2 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN2 is at a high level.

  Next, an appropriate clip level (clip potential) set by the clip circuit 220 will be described with reference to FIGS. FIGS. 15, 16, and 17 show the case where the reset level potential in the vertical output line is different between the still image driving, the first moving image driving, and the second moving image driving in the second embodiment. It is a figure explaining the appropriate clip level (clip potential) in each drive.

  In FIG. 15, FIG. 16, and FIG. 17, the potential V0 is the reset level of the vertical output line during still image driving, the potential V1 is the reset level of the vertical output line during first moving image driving, and the potential V2 is This is the reset level in the vertical output line during the second moving image drive. In the present embodiment, three pixels are simultaneously selected to perform mixed output every three rows during the first moving image driving, and five pixels are used to perform mixed output every five rows during the second moving image driving. Select simultaneously. Therefore, the reset level potential V1 during the first moving image driving and the reset level potential V2 during the second moving image driving are higher than the reset level potential V0 during the still image driving in which only one row is selected. The relationship is V2> V1> V0.

  Further, the potential VCLN0 is an appropriate clip level for still image driving, the potential VCLN1 is an appropriate clip level for first moving image driving, and the potential VCLN2 is an appropriate clipping level for second moving image driving. Is a level.

  FIG. 15A shows a signal potential (N signal potential) at the time of reading a reset signal and a signal potential at the time of reading an optical signal (S signal) in the vertical output line 202 with respect to the incident light amount in the still image driving in the second embodiment. It is a graph showing transition of potential. FIG. 15B is a graph showing the transition of the output signal with respect to the incident light amount in the still image driving in the second embodiment.

  FIG. 16A shows the transition of the N signal potential at the time of reading the reset signal and the S signal potential at the time of reading the optical signal in the vertical output line 202 with respect to the incident light amount in the first moving image driving in the second embodiment. It is a graph. FIG. 16B is a graph showing the transition of the output signal with respect to the amount of incident light in the first moving image drive in the second embodiment.

  FIG. 17A shows the transition of the N signal potential at the time of reading the reset signal and the S signal potential at the time of reading the optical signal in the vertical output line 202 with respect to the incident light amount in the second moving image driving in the second embodiment. It is a graph. FIG. 17B is a graph showing the transition of the output signal with respect to the amount of incident light in the second moving image driving in the second embodiment.

  As shown in FIGS. 15 (a), 16 (a), and 17 (a), the reset level in the vertical output line is set during still image driving, first moving image driving, and second moving image driving. Because they are different, the appropriate clip level for each drive is also different. The appropriate clip level for each drive is preferably a potential slightly lower than the reset level in the vertical output line, as shown in the description using FIG. In the examples of FIGS. 15A, 16A, and 17A, as the clip level, the potential VCLN0 is appropriate at the time of still image driving, and the potential VCLN1 is at the time of the first moving image driving. Appropriate, and the potential VCLN2 is appropriate during the second moving image drive.

  Conversely, if the clip level is set to the potential VCLN1 or the potential VCLN2 during still image driving, the output signal will float as shown in FIG. 15B. Also, if the clip level is set to the potential VCLN0 or VCLN1 during the second moving image driving, as shown in FIG. 17B, when the output signal becomes lower than the output saturation level when high luminance light is incident, Some darkening occurs in the image.

  Further, when the first moving image is driven, as shown in FIG. 16B, if the clip level is set to the potential VCLN2, the output signal is floated and set to the potential VCLN0. As a result, some darkening occurs in the output image when high luminance light is incident. As described above with reference to FIGS. 15 to 17, different potentials are used as clip levels in the vertical output line in reset signal reading during still image driving, first moving image driving, and second moving image driving. It is desirable to set

  FIG. 18 is a flowchart illustrating an example of a method for controlling the imaging apparatus according to the second embodiment. First, a shooting mode setting such as still image shooting or movie shooting is set by the shooting mode setting unit 116 or the like (S1901). Subsequently, the system control unit 113 determines the mode set by the shooting mode setting unit 116 (S1902).

  When it is determined that the mode set by the shooting mode setting unit 116 is the still image mode, the system control unit 113 performs initial setting of shooting conditions such as sensitivity, aperture value, and exposure time according to the mode. Is performed (S1903). Further, the system control unit 113 fixes the control signal PCLN0 to a high level so that the clip level on the vertical output line at the time of reset signal reading is set to the potential VCLN0 (S1904). Thereafter, the system control unit 113 determines whether shooting start processing such as pressing the release switch has been performed (S1905), and after the shooting start processing has been performed, still image driving is executed (S1906).

  If it is determined that the mode set by the shooting mode setting unit 116 is the moving image mode, the system control unit 113 continues to determine whether the moving image mode is the high speed mode or the low speed mode (S1907). When it is determined that the mode set by the shooting mode setting unit 116 is the low-speed moving image mode, the system control unit 113 initially sets shooting conditions such as sensitivity, aperture value, and exposure time according to the mode. Is performed (S1908). Further, the system control unit 113 fixes the control signal PCLN1 to a high level so that the clip level on the vertical output line at the time of reset signal reading is set to the potential VCLN1 (S1909). Thereafter, the system control unit 113 determines whether a shooting start process such as a moving image recording button being pressed has been executed (S1910), and after the shooting start process is executed, the first moving image drive is executed. (S1911). Then, the system control unit 113 determines whether shooting end processing such as pressing the movie recording button is performed again (S1912), and after the shooting end processing is executed, the first movie driving is ended.

  If it is determined that the mode set by the shooting mode setting unit 116 is the high-speed moving image mode, the system control unit 113 sets the shooting conditions such as sensitivity, aperture value, and exposure time according to the mode. Initial setting is performed (S1913). Further, the system control unit 113 fixes the control signal PCLN2 to a high level so that the clip level in the vertical output line at the time of reset signal reading is set to the potential VCLN2 (S1914). Thereafter, the system control unit 113 determines whether a shooting start process such as a moving image recording button being pressed has been executed (S1915), and after the shooting start process is executed, the second moving image drive is executed. (S1916). Then, the system control unit 113 determines whether shooting end processing such as pressing the movie recording button is performed again (S1917), and after the shooting end processing is executed, the second movie driving is ended.

  In both the still image mode and the moving image mode, the image signal is finally output to the image memory 108, the recording circuit 110, or the display circuit 112 (S1918), and the photographing operation is terminated.

  Note that the read timing and control during each drive in the second embodiment are the same as those in the first embodiment shown in FIGS. 10 and 11 except for the polarity control of the control signals PCLN0, PCLN1, and PCLN2. Since it exists, description is abbreviate | omitted.

  According to the second embodiment, pixel signals are not mixed in the vertical direction when driving a still image, pixel signals of three pixels are mixed in the vertical direction when driving the first moving image, and vertical when driving the second moving image. Mix the pixel signals of 5 pixels in the direction. Then, control is performed so that the clip level potentials on the vertical output line at the time of reset signal reading differ between the still image driving, the first moving image driving, and the second moving image driving. As a result, even if the operating point of the vertical output line is different for each number of rows to be selected at the same time, an appropriate clip level is set according to the driving mode of pixel signal readout in the solid-state imaging device, and an appropriate black It is possible to realize sinking countermeasures and suppress the black sunning phenomenon.

(Third embodiment)
Next, a third embodiment of the present invention will be described. The imaging apparatus according to the third embodiment is configured to drive a first moving image aiming at high image quality, during a third moving image drive aiming to achieve both high image quality and high resolution, and fourth moving image aiming at high resolution. The clip potential of the pixel reset output signal in the vertical output line (column output line) is made different between when driving. The configuration of the imaging apparatus, the configuration of the solid-state imaging device 103, and the configuration of the unit pixel 200 of the solid-state imaging device 103 in the third embodiment are the same as those in the first embodiment shown in FIGS. Therefore, the description is omitted.

  First, an example of a combination of pixels when a pixel signal is read out in the vertical direction (column direction) of the pixel arrangement in the solid-state imaging device during moving image driving will be described with reference to FIG. In the third embodiment, there are three types of drive modes when driving a moving image. It is assumed that the signals of three pixels in the vertical direction are read out simultaneously during the first moving image drive aiming at high image quality. Further, at the time of the third moving image driving aiming to achieve both high image quality and high resolution, signals of two pixels among the three pixels in the vertical direction are read out simultaneously. Further, at the time of the fourth moving image driving aiming at high resolution, it is assumed that the signal of one pixel among the three pixels in the vertical direction is read out alone.

  FIG. 19 is a diagram for explaining an example of a combination of vertical pixel mixing according to the third embodiment. In FIG. 19, lines connecting the pixels 200 indicate pixel combinations when the pixel signals are mixed in the vertical direction (column direction), as in FIG. 4.

  In the first moving image drive, in the third embodiment, it is assumed that the pixel signals of three pixels in the vertical direction (column direction) are mixed and read out, and the three pixels 200 of the same color are connected to each other. (FIG. 19A). In the example shown in FIG. 19A, for the pixel “R”, for example, the pixel 200 in the n-th row is connected to the pixel 200 in the (n−2) -th and (n + 2) -th rows. That is, the pixel signals of the pixels 200 in the (n−2) th row, the nth row, and the (n + 2) th row are mixed and read out. Similarly, for the pixel “G”, for example, the pixel signals of the pixels 200 in the (n + 1) th row, the (n + 3) th row, and the (n + 5) th row are mixed and read out. In the first moving image drive, pixel signals of three pixels in the vertical direction are mixed and output, so that random noise components and the like are reduced, and moving image driving when aiming at high image quality is performed.

  In the third moving image drive, in the third embodiment, it is assumed that the pixel signals of two of the three pixels in the vertical direction are mixed and read, and two different pixels 200 of the same color are connected to each other. (FIG. 19B). In the example illustrated in FIG. 19B, the “R” pixel is illustrated by connecting, for example, the pixel 200 in the n-th row and the pixel 200 in the (n−2) -th row. That is, the pixel signals of the pixels 200 in the (n-2) th row and the nth row are mixed and read out.

  Similarly, for the pixel “G”, for example, the pixel signals of the pixels 200 in the (n + 1) th and (n + 3) th rows are mixed and read out. Further, pixel signals are not read out from the pixels 200 indicated by hatching in the drawing, such as the pixels 200 in the (n−4) th and (n−1) th rows. In the third moving image drive, since pixel signals of 2 pixels out of 3 pixels in the vertical direction are mixed and output, the random noise component is somewhat reduced and the number of mixed pixels is also suppressed to 2 pixels. This is a video drive when aiming to achieve both high image quality and high resolution.

  In the fourth moving image drive, in the third embodiment, the vertical mixing is not performed, but the thinned-out readout is performed, and the lines between the pixels 200 are not connected (FIG. 19C). . In the example shown in FIG. 19C, for the “R” pixel, for example, the pixel signal of the pixel 200 in the nth row, the (n + 6) th row, and the like is read out alone. Similarly, for the “G” pixel, for example, the pixel signal of the pixel 200 such as the (n−3) th row and the (n + 3) th row is read out independently. Also, pixel signals are read from the pixels 200 indicated by diagonal lines in the drawing, such as the pixels 200 in the (n-4) th row, the (n-2) th row, the (n-1) th row, and the (n + 1) th row. Not issued. In the fourth moving image drive, only the pixel signal of 1 pixel out of 3 pixels in the vertical direction is thinned out and output, so that the moving image drive is performed when aiming at high resolution.

  Next, a configuration example of the clip circuit 220 in the third embodiment will be described with reference to FIG. FIG. 20 is a circuit diagram illustrating the clip circuit 220 of the solid-state image sensor 103 according to the third embodiment. The clip circuit 220 includes switch transistors 2101, 2102, 2103, 2104, 2105, a source follower (SF) transistor 2106, and an inverter 2107. The switch transistors 2101 to 2105 and the SF transistor 2106 are all NMOS transistors.

  The switch transistor 2103 is controlled by the control signal PCLN1, and supplies the potential VCLN1 to the node VCLN when the control signal PCLN1 is at a high level. The switch transistor 2104 is controlled by the control signal PCLN3, and supplies the potential VCLN3 to the node VCLN when the control signal PCLN3 is at a high level. The switch transistor 2105 is controlled by the control signal PCLN4, and supplies the potential VCLN4 to the node VCLN when the control signal PCLN4 is at a high level.

  Note that the control signal PCLN1, the control signal PCLN3, and the control signal PCLN4 are controlled so as not to be at a high level at the same time. That is, when any one of the control signal PCLN1, the control signal PCLN3, and the control signal PCLN4 is at a high level, the other two are at a low level. Further, the potential VCLN1, the potential VCLN3, and the potential VCLN4 are different from each other. In this embodiment, the potential VCLN1> the potential VCLN3> the potential VCLN4.

  The switch transistor 2102 is controlled by the control signal PCLS supplied via the inverter 2107, and applies the potential of the node VCLN to the gate of the SF transistor 2106 when the control signal PCLS is at a low level. The SF transistor 2106 performs a source follower operation together with the constant current source 219 and supplies the voltage of the node VCLN to the vertical output line (column output line) 202. At this time, the switch transistor 2101 is off. As a result, the potential generated in the vertical output line 202 is limited by any one of the potential VCLN1, the potential VCLN3, or the potential VCLN4 that is the gate potential of the SF transistor 2106.

  The switch transistor 2101 is controlled by the control signal PCLS, and applies the potential VCLS to the gate of the SF transistor 2106 when the control signal PCLS is at a high level. The SF transistor 2106 performs a source follower operation together with the constant current source 219, and supplies the voltage VCLS to the vertical output line 202. At this time, the switch transistor 2102 is off. As a result, the potential generated in the vertical output line 202 is limited by the potential VCLS that is the gate potential of the SF transistor 2106.

  As described above, the potential generated on the vertical output line 202 is limited to the potential VCLS by the clip circuit 220 when the control signal PCLS is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN1 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN1 is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN3 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN3 is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN3 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN4 is at a high level.

  Next, an appropriate clip level (clip potential) set by the clip circuit 220 will be described with reference to FIGS. 21, FIG. 22, and FIG. 23 show the case where the reset level potential on the vertical output line is different between the first moving image drive, the third moving image drive, and the fourth moving image drive in the third embodiment. It is a figure explaining the appropriate clip level (clip potential) in each drive.

  In FIG. 21, FIG. 22, and FIG. 23, the potential V1 is a reset level in the vertical output line during the first moving image drive. The potential V3 is a reset level in the vertical output line during the third moving image drive, and the potential V4 is a reset level in the vertical output line during the fourth moving image drive. In the present embodiment, three pixels are simultaneously selected to perform mixed output every three rows during the first moving image drive, and mixed output every two rows among the three rows during the third moving image drive. 2 pixels are selected at the same time, and only one of the three rows is selected when the fourth moving image is driven. Therefore, the reset level potential V1 at the time of the first moving image driving and the reset level potential V3 at the time of the third moving image driving are the reset level potentials at the time of the fourth moving image driving in which only one of the three rows is selected. It becomes higher than V4, and the relationship is V1> V3> V4.

  Further, the potential VCLN1 is an appropriate clip level for the first moving image drive, the potential VCLN3 is an appropriate clip level for the third moving image drive, and the potential VCLN4 is appropriate for the fourth moving image drive. Clip level.

  FIG. 21A shows a signal potential (N signal potential) at the time of reading a reset signal and a signal potential at the time of reading an optical signal in the vertical output line 202 with respect to the incident light amount in the first moving image drive in the third embodiment. It is a graph showing transition of S signal potential. FIG. 21B is a graph showing the transition of the output signal with respect to the amount of incident light in the first moving image drive in the third embodiment.

  FIG. 22A shows the transition of the N signal potential at the time of reading the reset signal and the S signal potential at the time of reading the optical signal in the vertical output line 202 with respect to the incident light amount in the third moving image driving in the third embodiment. It is a graph. FIG. 22B is a graph showing the transition of the output signal with respect to the amount of incident light in the third moving image drive in the third embodiment.

  FIG. 23A shows the transition of the N signal potential at the time of reading the reset signal and the S signal potential at the time of reading the optical signal in the vertical output line 202 with respect to the incident light amount in the fourth moving image drive in the third embodiment. It is a graph. FIG. 23B is a graph showing the transition of the output signal with respect to the amount of incident light in the fourth moving image drive in the third embodiment.

  As shown in FIGS. 21 (a), 22 (a), and 23 (a), the vertical output line is reset during the first moving image driving, the third moving image driving, and the fourth moving image driving. Since the levels are different, the appropriate clip level for each drive is also different. The appropriate clip level for each drive is preferably a potential slightly lower than the reset level in the vertical output line, as shown in the description using FIG. In the examples of FIGS. 21A, 22A, and 23A, as the clip level, the potential VCLN1 is appropriate during the first moving image drive and the potential during the third moving image drive. VCLN3 is appropriate, and the potential VCLN4 is appropriate during the fourth moving image drive.

  Conversely, if the clip level is set to the potential VCLN3 or the potential VCLN4 during the first moving image driving, as shown in FIG. 21B, the output signal becomes lower than the output saturation level when high luminance light is incident. Some black sun is generated in the output image. Also, if the clip level is set to the potential VCLN1 or VCLN3 during the fourth moving image driving, the output signal will float as shown in FIG.

  Further, when the third moving image is driven, as shown in FIG. 22B, if the clip level is set to the potential VCLN1, the output signal is floated and set to the potential VCLN4. As a result, some darkening occurs in the output image when high luminance light is incident. As described above with reference to FIGS. 21 to 23, when the first moving image is driven, the third moving image is driven, and the fourth moving image is driven, the reset signal is read as the clip level in the vertical output line. It is desirable to set different potentials.

  FIG. 24 is a flowchart illustrating an example of a method for controlling the imaging apparatus according to the third embodiment. First, moving image shooting mode setting is performed by the shooting mode setting unit 116 or the like (S2701). Subsequently, the system control unit 113 determines the mode set by the shooting mode setting unit 116 (S2702).

  When it is determined that the mode set by the shooting mode setting unit 116 is the high-quality moving image mode, the system control unit 113 initializes shooting conditions such as sensitivity, aperture value, and exposure time according to the mode. Setting is performed (S2703). Further, the system control unit 113 fixes the control signal PCLN1 to a high level so that the clip level on the vertical output line at the time of reset signal reading is set to the potential VCLN1 (S2704). Thereafter, the system control unit 113 determines whether a shooting start process such as a moving image recording button being pressed has been executed (S2705), and after the shooting start process is executed, the first moving image drive is executed. (S2706). Then, the system control unit 113 determines whether shooting end processing has been performed such as pressing the moving image recording button again (S2707), and after the shooting end processing is executed, the first moving image driving is ended.

  When it is determined that the mode set by the shooting mode setting unit 116 is the high-quality / high-resolution moving image mode, the system control unit 113 determines sensitivity, aperture value, exposure time according to the mode. The initial setting of the shooting conditions is performed (S2708). Further, the system control unit 113 fixes the control signal PCLN3 to a high level so that the clip level in the vertical output line at the time of reset signal reading is set to the potential VCLN3 (S2709). Thereafter, the system control unit 113 determines whether a shooting start process such as a moving image recording button being pressed has been executed (S2710), and after the shooting start process is executed, the third moving image drive is executed. (S2711). Then, the system control unit 113 determines whether shooting end processing such as pressing the movie recording button is performed again (S2712), and after the shooting end processing is executed, the third movie driving is ended.

  If it is determined that the mode set by the shooting mode setting unit 116 is the high-resolution video mode, the system control unit 113 sets the sensitivity, aperture value, exposure time, etc. according to the mode. An initial setting of shooting conditions is performed (S2713). Further, the system control unit 113 fixes the control signal PCLN4 to a high level so that the clip level in the vertical output line at the time of reset signal reading is set to the potential VCLN4 (S2714). Thereafter, the system control unit 113 determines whether a shooting start process such as a moving image recording button being pressed has been executed (S2715), and after the shooting start process is executed, the fourth moving image drive is executed. (S2716). Then, the system control unit 113 determines whether shooting end processing such as pressing the movie recording button is performed again (S2717), and after the shooting end processing is executed, the fourth movie driving ends.

  In each moving image mode, the image signal is finally output to the image memory 108, the recording circuit 110, or the display circuit 112 (S2718), and the photographing operation is terminated.

  The read timing and control during each drive in the third embodiment are the same as those in the first embodiment shown in FIGS. 10 and 11 except for the polarity control of the control signals PCLN1, PCLN3, and PCLN4. Since it exists, description is abbreviate | omitted.

  According to the third embodiment, in the vertical output line at the time of reset signal reading according to the number of rows selected simultaneously during the first moving image drive, the third moving image drive, and the fourth moving image drive. The clip level is controlled to be different. As a result, even if the operating point of the vertical output line is different for each number of rows to be selected at the same time, an appropriate clip level is set according to the driving mode of pixel signal readout in the solid-state imaging device, and an appropriate black It is possible to realize sinking countermeasures and suppress the black sunning phenomenon.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. The image pickup apparatus according to the fourth embodiment outputs a pixel reset output from a vertical output line (column output line) when reading a pixel signal of a vertical optical black pixel unit (VOB unit) and reading a pixel signal of an effective pixel unit. The clip potential of the signal is made different. The vertical optical black pixel portion is a region where the front surface of the photodiode of the pixel in the region is shielded, and the effective pixel portion is a region where the front surface of the photodiode of the pixel in the region is not shielded. The configuration of the imaging apparatus, the configuration of the solid-state imaging device 103, and the configuration of the unit pixel 200 of the solid-state imaging device 103 in the fourth embodiment are the same as those in the first embodiment shown in FIGS. Therefore, the description is omitted.

  First, an example of a combination of pixels when a pixel signal is read in the vertical direction (column direction) of the pixel array in the solid-state imaging device will be described with reference to FIG. In the fourth embodiment, it is assumed that the number of pixel signals mixed in the vertical direction differs between when reading a pixel signal of the VOB portion and when reading a pixel signal of the effective pixel portion. FIG. 25 is a diagram for explaining an example of a combination of vertical pixel mixing according to the fourth embodiment. In FIG. 25, lines connecting the pixels 200 indicate pixel combinations when the pixel signals are mixed in the vertical direction (column direction), as in FIG.

  In the fourth embodiment, when reading the pixel signals of the VOB unit, the pixel signals in the vertical direction are not mixed, and the pixels in all the rows are read independently for each row without being mixed. It is written without being tied. In the example shown in FIG. 25, the pixels in the row above the (n−1) th row that is the VOB portion are all read out independently without being connected to the pixels in the other rows.

  In addition, when reading out the pixel signal of the effective pixel portion, it is assumed that the pixel signals of the three pixels in the vertical direction are mixed and read out, and the three pixels 200 having the same color are connected to each other. In the example illustrated in FIG. 25, the “R” pixel in the effective pixel portion is illustrated by connecting the pixels 200 in the nth row, the (n + 2) th row, and the (n + 4) th row, for example. That is, the pixel signals of the pixels 200 in the nth row, the (n + 2) th row, and the (n + 4) th row are mixed and read out. Similarly, for the “G” pixel in the effective pixel portion, for example, the pixel signals of the pixels 200 in the (n + 3) th row, the (n + 5) th row, and the (n + 7) th row are mixed and read out.

  Next, a configuration example of the clip circuit 220 in the fourth embodiment will be described with reference to FIG. FIG. 26 is a circuit diagram illustrating the clip circuit 220 of the solid-state image sensor 103 according to the fourth embodiment. The clip circuit 220 includes switch transistors 2901, 2902, 2903, 2904, a source follower (SF) transistor 2906, and an inverter 2907. The switch transistors 2901 to 2904 and the SF transistor 2906 are all NMOS transistors.

  The switch transistor 2903 is controlled by the control signal PCLN5, and supplies the potential VCLN5 to the node VCLN when the control signal PCLN5 is at a high level. The switch transistor 2904 is controlled by the control signal PCLN1, and supplies the potential VCLN1 to the node VCLN when the control signal PCLN1 is at a high level. Note that the control signal PCLN5 and the control signal PCLN1 are controlled so as not to be at a high level at the same time.

  The switch transistor 2902 is controlled by the control signal PCLS supplied via the inverter 2907, and applies the potential of the node VCLN to the gate of the SF transistor 2906 when the control signal PCLS is at a low level. The SF transistor 2906 performs a source follower operation together with the constant current source 219, and supplies the voltage of the node VCLN to the vertical output line (column output line) 202. At this time, the switch transistor 2901 is off. As a result, the potential generated in the vertical output line 202 is limited by the potential VCLN5 or the potential VCLN1 which is the gate potential of the SF transistor 2906.

  The switch transistor 2901 is controlled by the control signal PCLS, and applies the potential VCLS to the gate of the SF transistor 2906 when the control signal PCLS is at a high level. The SF transistor 2906 performs a source follower operation together with the constant current source 219, and supplies the voltage VCLS to the vertical output line 202. At this time, the switch transistor 2902 is off. Thereby, the potential generated in the vertical output line 202 is limited by the potential VCLS which is the gate potential of the SF transistor 2906.

  As described above, the potential generated on the vertical output line 202 is limited to the potential VCLS by the clip circuit 220 when the control signal PCLS is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN5 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN5 is at a high level. The potential generated on the vertical output line 202 is limited to the potential VCLN1 by the clip circuit 220 when the control signal PCLS is at a low level and the control signal PCLN1 is at a high level.

  Next, an appropriate clip level (clip potential) set by the clip circuit 220 will be described with reference to FIGS. FIGS. 27 and 28 show the appropriate driving in each case when the reset level potential in the vertical output line is different between the pixel signal readout of the VOB portion and the pixel signal readout of the effective pixel portion in the fourth embodiment. It is a figure explaining an easy clip level (clip potential).

  27 and 28, the potential V5 is a reset level in the vertical output line when reading the pixel signal in the VOB portion, and the potential V1 is a reset level in the vertical output line when reading the pixel signal in the effective pixel portion. In the present embodiment, when reading out the pixel signal of the effective pixel portion, a plurality of rows are simultaneously selected in order to perform mixed output. Therefore, the reset level potential V1 when the pixel signal of the effective pixel portion is read out is higher than the reset level potential V5 when the pixel signal is read out of the VOB portion that selects only one row. The potential VCLN5 is an appropriate clip level for reading the pixel signal of the VOB portion, and the potential VCLN1 is an appropriate clip level for reading the pixel signal of the effective pixel portion.

  FIG. 27A shows a signal potential (N signal potential) when reading a reset signal and a signal potential when reading an optical signal in the vertical output line 202 with respect to the incident light amount when reading a pixel signal of the VOB portion in the fourth embodiment. It is a graph showing transition of (S signal potential). FIG. 27B is a graph showing the transition of the output signal with respect to the amount of incident light when the pixel signal is read from the VOB portion in the fourth embodiment.

  FIG. 28A shows the transition of the N signal potential when reading the reset signal and the S signal potential when reading the optical signal in the vertical output line 202 with respect to the amount of incident light when reading the pixel signal of the effective pixel portion in the fourth embodiment. It is a graph showing. FIG. 28B is a graph showing the transition of the output signal with respect to the amount of incident light when reading out the pixel signal of the effective pixel portion in the fourth embodiment.

  As shown in FIGS. 27A and 28A, since the reset level of the vertical output line is different between the pixel signal readout of the VOB portion and the pixel signal readout of the effective pixel portion, appropriate clipping for each drive is performed. The level is also different. The appropriate clip level for each drive is preferably a potential slightly lower than the reset level in the vertical output line, as shown in the description using FIG. In the examples of FIGS. 27A and 28A, as the clip level, the potential VCLN5 is appropriate when reading the pixel signal of the VOB portion, and the potential VCLN1 is appropriate when reading the pixel signal of the effective pixel portion. is there.

  Conversely, if the clip level is set to the potential VCLN1 when the pixel signal is read out from the VOB portion, the output signal will float as shown in FIG. Also, if the clip level is set to the potential VCLN5 when reading the pixel signal of the effective pixel portion, as shown in FIG. 28B, if the output signal becomes lower than the output saturation level when high luminance light is incident, Some darkening occurs in the image. As described above with reference to FIGS. 27 and 28, different potentials are set as the clip level in the vertical output line when reading the reset signal and when reading the pixel signal of the VOB portion and when reading the pixel signal of the effective pixel portion. It is desirable.

  Regarding the readout timing and control during readout of pixel signals in the fourth embodiment, readout of pixel signals in the VOB portion corresponds to still image driving, and readout of pixel signals in the effective pixel portion corresponds to first moving image driving. By doing so, it is the same as in the first embodiment. Further, the control method of the image pickup apparatus in the fourth embodiment is similar to that in the first embodiment by correspondingly correspondingly and replacing the control signal PCLN0 and the potential VCLN0 with the control signal PCLN5 and the potential VCLN5, respectively.

  According to the fourth embodiment, the pixel signals are mixed in the vertical direction when reading the pixel signals in the VOB portion, and the three vertical pixels are mixed when reading the pixel signals in the effective pixel portion. Then, control is performed so that the clip level potential on the vertical output line at the time of reset signal reading differs between when the pixel signal of the VOB portion is read and when the pixel signal of the effective pixel portion is read. As a result, even if the operating point of the vertical output line is different for each number of rows to be selected at the same time, an appropriate clip level is set according to the driving mode of pixel signal readout in the solid-state imaging device, and an appropriate black It is possible to realize sinking countermeasures and suppress the black sunning phenomenon.

  In the first to fourth embodiments, the mode for performing the vertical pixel mixing or the vertical pixel thinning has been described as the moving image driving mode. However, the present invention is not limited to this. For example, instead of the moving image mode, the image signal obtained by the imaging device may be replaced with live view driving that displays in real time on the image display unit.

(Other embodiments of the present invention)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 103: Solid-state image sensor 105: Timing signal generation circuit 113: System control part 116: Shooting mode setting part 200: Unit pixel 201: Vertical shift register (vertical scanning circuit) 202: Vertical output line 203: Column circuit 220: Clip circuit 207 : Output amplifier 301: Photodiode 302: Transfer switch 303: Floating diffusion 304: Reset switch 305: Source follower amplifier 306: Selection switch

Claims (6)

A photoelectric conversion unit that converts incident light into charges, a charge-voltage conversion unit that converts charges generated in the photoelectric conversion unit into voltage, a transfer unit that transfers charges generated in the photoelectric conversion unit to the charge-voltage conversion unit, A plurality of pixels each having an output unit for outputting a signal corresponding to the voltage converted by the charge voltage conversion unit to a signal line, and a clip circuit for clipping the potential of the signal line; The signal line is output in a state where the charge voltage conversion unit is reset and the first signal is output to the signal line, and the charge generated in the photoelectric conversion unit is transferred to the charge voltage conversion unit. A solid-state imaging device that outputs a second signal to
Rows of pixels that simultaneously select the clipping potential of the signal line by the clipping circuit when the first signal is output from the output unit to the signal line when the pixel signal is read from the pixel of the solid-state imaging device An image pickup apparatus comprising: a control unit that performs control according to the number of the image pickup devices. In the solid-state imaging device, a first area where a first number of rows are simultaneously selected and a pixel signal is read out, and a second number of rows different from the first value are simultaneously displayed. A second region that is selected and from which pixel signals are read out,
The control unit outputs the first signal from the output unit of the pixel in the first region to the signal line, and outputs the first signal from the output unit of the pixel in the second region. The imaging apparatus according to claim 1, wherein the clipping potential of the signal line by the clipping circuit is different depending on when the signal is output to the signal line.   The control unit selects a plurality of rows at the same time and mixes and reads pixel signals of a plurality of pixels in the vertical direction, and selects a row and reads a pixel signal of one pixel at the time of non-mixing The imaging apparatus according to claim 1, wherein the clipping potential of the signal line by the clipping circuit is made different. The first region is an optical black pixel unit in which a front surface of the photoelectric conversion unit of the pixel in the region is shielded from light.
The imaging device according to claim 2, wherein the second region is an effective pixel unit in which a front surface of the photoelectric conversion unit of the pixel in the region is not shielded from light.   5. The imaging device according to claim 2, wherein the number of rows of pixels that are simultaneously selected in the second region is greater than the number of rows of pixels that are simultaneously selected in the first region. A photoelectric conversion unit that converts incident light into charges, a charge-voltage conversion unit that converts charges generated in the photoelectric conversion unit into voltage, a transfer unit that transfers charges generated in the photoelectric conversion unit to the charge-voltage conversion unit, A plurality of pixels each having an output unit for outputting a signal corresponding to the voltage converted by the charge voltage conversion unit to a signal line, and a clip circuit for clipping the potential of the signal line; A method for controlling an imaging apparatus including a solid-state imaging device having:
The selected pixel of the solid-state imaging device outputs a first signal to the signal line in a state where the charge-voltage conversion unit is reset; and
The selected pixel of the solid-state imaging device outputs a second signal to the signal line in a state where charges generated in the photoelectric conversion unit are transferred to the charge voltage conversion unit;
When the pixel signal is read from the pixel of the solid-state imaging device and the first signal is output from the output unit to the signal line, the potential of the signal line depends on the number of rows of pixels to be selected simultaneously. A method of controlling the imaging apparatus, comprising: a step of clipping at a predetermined potential.

Images