JP6398909B2 - Schottky barrier diode and manufacturing method thereof - Google Patents

Description

  The present invention relates to a Schottky barrier diode.

  As a Schottky Barrier Diode (SBD), one having one or more semiconductor layers mainly formed of gallium nitride (GaN) is known (for example, Patent Document 1). In the SBD of Patent Document 1, a nickel (Ni) layer and a gold (Au) layer are stacked in this order on a gallium nitride (GaN) layer as a semiconductor layer.

JP 2009-59912 A

  Since gold (Au) is expensive, it is preferable to use a relatively inexpensive metal such as aluminum (Al). However, when aluminum (Al) is used instead of gold (Au) and aluminum (Al) and nickel (Ni) are brought into contact with each other, there is a problem that the reverse breakdown voltage is lowered. In order to solve this problem, a titanium (Ti) layer, a titanium nitride (TiN) layer, and a titanium (Ti) layer are laminated in this order between an aluminum (Al) layer and a nickel (Ni) layer. A structure can be adopted.

  Furthermore, the inventors have discovered a method of laminating a palladium (Pd) layer on a nickel (Ni) layer as a method for improving the barrier height between gallium nitride (GaN) and a Schottky electrode. When this method is adopted, the palladium (Pd) layer and the titanium (Ti) layer are brought into contact with each other. However, the inventors have also discovered that when the palladium (Pd) layer and the titanium (Ti) layer are brought into contact with each other, the reverse breakdown voltage is lowered.

  For this reason, there has been a demand for a technology that realizes cost reduction, suppression of reduction of reverse breakdown voltage, and improvement of barrier height. In addition, in SBD, miniaturization, ease of manufacture, resource saving, improvement in usability, improvement in durability, and the like have been desired.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.

(1) According to one aspect of the present invention, a Schottky barrier diode is provided. The Schottky barrier diode includes a semiconductor layer mainly formed of gallium nitride, a nickel layer mainly formed of nickel on the semiconductor layer, and mainly palladium on the nickel layer. A palladium layer formed, a molybdenum layer mainly formed of molybdenum on the palladium layer, a first titanium layer mainly formed of titanium on the molybdenum layer, and A titanium nitride layer mainly formed of titanium nitride on the first titanium layer, a second titanium layer mainly formed of titanium on the titanium nitride layer, and the second titanium layer An aluminum layer containing aluminum is provided on the titanium layer, and the titanium content of the palladium layer is 1.0 × 10 ¹⁸ (atm / cm ³ ) or less. According to this form of the Schottky barrier diode, it is possible to realize cost reduction, suppression of reduction in reverse breakdown voltage, and improvement of barrier height.

(2) According to another aspect of the present invention, a method for manufacturing a Schottky barrier diode is provided. The Schottky barrier diode manufacturing method includes a step of forming a nickel layer mainly from nickel on a semiconductor layer mainly formed from gallium nitride, and a palladium layer mainly formed from palladium on the nickel layer. A step of forming a molybdenum layer mainly from molybdenum on the palladium layer, a step of forming a first titanium layer mainly from titanium on the molybdenum layer, and the first titanium. Forming a titanium nitride layer mainly on the titanium nitride layer; forming a second titanium layer mainly on the titanium nitride layer; and on the second titanium layer. And a step of forming an aluminum layer containing aluminum, wherein the palladium layer has a titanium content of 1.0 × 10 ¹⁸ (atm / cm ³ ) or less. According to this method of manufacturing a Schottky barrier diode, it is possible to manufacture a Schottky barrier diode that realizes cost reduction, suppression of reduction in reverse breakdown voltage, and improvement of barrier height.

(3) In the manufacturing method described above, from the step of forming the nickel layer to the step of forming the aluminum layer, the step of heat treatment is not included, and the step of heat treatment is included after the step of forming the aluminum layer. Good. According to this method of manufacturing a Schottky barrier diode, it is possible to manufacture a Schottky barrier diode in which the reduction in reverse breakdown voltage is further suppressed.

  The present invention can be realized in various forms other than the Schottky barrier diode and the Schottky barrier diode manufacturing method. For example, it can be realized in the form of a semiconductor device including the above Schottky barrier diode, a manufacturing method for manufacturing the semiconductor device, and the like.

  According to the Schottky barrier diode of the present invention, it is possible to realize cost reduction, suppression of reduction in reverse breakdown voltage, and improvement of barrier height. In addition, according to the method for manufacturing a Schottky barrier diode of the present invention, it is possible to manufacture a Schottky barrier diode that realizes cost reduction, suppression of reduction in reverse breakdown voltage, and improvement of barrier height.

FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor device 10 according to the first embodiment. FIG. 5 is a process diagram illustrating a method for manufacturing the semiconductor device 10. The figure which shows the relationship between the depth of a semiconductor device, and each component density | concentration. The figure which shows the relationship between a current density (A / cm < ² >) and reverse voltage (V). The figure which shows the relationship between the depth of a semiconductor device, and each component density | concentration. The figure which shows the relationship between a current density (A / cm < ² >) and reverse voltage (V). It is process drawing which shows the manufacturing method of the semiconductor device 20 in 2nd Embodiment.

A. First embodiment A-1. Configuration of Semiconductor Device FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor device 10 in the first embodiment. In the present embodiment, the semiconductor device 10 is a vertical Schottky barrier diode. FIG. 1 shows XYZ axes orthogonal to each other.

  Of the XYZ axes in FIG. 1, the X axis is an axis from the left side of FIG. 1 toward the right side of the page, the + X axis direction is a direction toward the right side of the page, and the −X axis direction is a direction toward the left side of the page. It is. Of the XYZ axes in FIG. 1, the Y axis is an axis from the front of the paper to the back of the paper in FIG. 1, the + Y axis direction is a direction toward the back of the paper, and the −Y axis direction is a direction toward the front of the paper. It is. Among the XYZ axes in FIG. 1, the Z axis is an axis that goes from the bottom of FIG. 1 to the top of the paper, the + Z axis direction is a direction that goes on the paper, and the −Z axis direction is a direction that goes down the paper. It is.

  The semiconductor device 10 is a GaN-based semiconductor device formed using gallium nitride (GaN). The semiconductor device 10 includes a substrate 110, a semiconductor layer 120, a wiring layer 160, an insulating layer 180, a Schottky electrode 190, and a back electrode 170.

  The substrate 110 of the semiconductor device 10 is a semiconductor layer having a plate shape extending along the X axis and the Y axis. In the present embodiment, the substrate 110 is an n-type semiconductor layer that is mainly formed of gallium nitride (GaN) and contains silicon (Si) as a donor. In the present specification, “mainly formed” means containing 90% or more by mole fraction.

The semiconductor layer 120 of the semiconductor device 10 is an n-type semiconductor layer that extends along the X axis and the Y axis. In the present embodiment, the semiconductor layer 120 is mainly formed of gallium nitride (GaN) and contains silicon (Si) as a donor. The semiconductor layer 120 is stacked on the + Z axis direction side of the substrate 110. The semiconductor layer 120 has an interface 121. The interface 121 is a surface along the XY plane in which the semiconductor layer 120 extends and facing the + Z-axis direction. At least a part of the interface 121 may be a curved surface or may have undulations. In the present embodiment, the thickness of the semiconductor layer 120 is 10 μm, and the donor concentration is 1 × 10 ¹⁶ cm ⁻³ .

  The insulating layer 180 of the semiconductor device 10 has electrical insulation and covers the + Z-axis side surfaces of the substrate 110 and the semiconductor layer 120. The insulating layer 180 includes a first insulating layer 181 and a second insulating layer 182.

The first insulating layer 181 in the insulating layer 180 is a layer formed of aluminum oxide (Al ₂ O ₃ ) and in contact with the substrate 110 and the semiconductor layer 120. In the present embodiment, the thickness of the first insulating layer 181 is 100 nm. The second insulating layer 182 in the insulating layer 180 is made of silicon dioxide (SiO ₂ ). In the present embodiment, the thickness of the second insulating layer 182 is 500 nm.

  In the insulating layer 180, an opening 185 that penetrates the first insulating layer 181 and the second insulating layer 182 is formed. The opening 185 is formed by wet etching.

  The Schottky electrode 190 of the semiconductor device 10 is a conductive electrode and is a Schottky junction with the interface 121 of the semiconductor layer 120. The Schottky electrode 190 includes a nickel layer 192, a palladium layer 194, and a molybdenum layer 196 in order from the layer in contact with the semiconductor layer 120. In this specification, a Schottky electrode refers to an electrode in which the difference between the electron affinity of the semiconductor layer 120 and the work function of a metal used as the Schottky electrode is 0.5 eV or more.

The nickel layer 192 in the Schottky electrode 190 is mainly formed of nickel (Ni). In the present embodiment, the thickness of the nickel layer 192 is 100 nm. The palladium layer 194 in the Schottky electrode 190 is mainly formed of palladium (Pd). In the present embodiment, the palladium layer 194 has a thickness of 100 nm. The titanium content of the palladium layer 194 in the semiconductor device 10 is 1.0 × 10 ¹⁸ (atm / cm ³ ) or less. In addition, the molybdenum layer 196 in the Schottky electrode 190 is mainly formed of molybdenum (Mo). In the present embodiment, the molybdenum layer 196 has a thickness of 10 nm. The thickness of the molybdenum layer 196 is preferably 5 nm or more in order to obtain a homogeneous layer, and is preferably 500 nm or less from the viewpoint of preventing peeling due to stress. Note that the nickel layer 192 is in contact with the semiconductor layer 120. The palladium layer 194 is in contact with the nickel layer 192. The molybdenum layer 196 is in contact with the palladium layer 194.

  The wiring layer 160 of the semiconductor device 10 is an electrode layer provided on the Schottky electrode as a pad electrode or an extraction wiring electrode. In general, the wiring layer 160 often includes a metal material having a relatively low resistivity such as Al, Au, or Cu so as to have a smaller resistance than the Schottky electrode layer. The wiring layer 160 of the semiconductor device 10 includes a first titanium layer 162, a titanium nitride layer 164, a second titanium layer 166, and an aluminum layer 168 in order from the layer in contact with the Schottky electrode 190.

  The first titanium layer 162 in the wiring layer 160 is mainly made of titanium (Ti). In the present embodiment, the thickness of the first titanium layer 162 is 20 nm. The titanium nitride layer 164 in the wiring layer 160 is mainly formed of titanium nitride (TiN). In the present embodiment, the thickness of the titanium nitride layer 164 is 200 nm. The second titanium layer 166 in the wiring layer 160 is mainly formed of titanium (Ti). In the present embodiment, the thickness of the second titanium layer 166 is 20 nm. Note that the first titanium layer 162 is in contact with the molybdenum layer 196. The titanium nitride layer 164 is in contact with the first titanium layer 162. The second titanium layer 166 is in contact with the titanium nitride layer 164.

  The aluminum layer 168 in the wiring layer 160 is a layer containing aluminum (Al). In the present embodiment, the aluminum layer 168 is formed from aluminum silicon (AlSi). The aluminum layer 168 is made of aluminum silicon (AlSi) obtained by adding 1% of silicon (Si) to aluminum (Al). Note that the aluminum layer 168 may be a layer mainly formed of aluminum. The aluminum layer 168 may be formed of aluminum copper (AlCu). In the present embodiment, the thickness of the aluminum layer 168 is 2000 nm. The wiring layer 160 and the Schottky electrode 190 serve as the anode electrode of the Schottky barrier diode. Note that the aluminum layer 168 is in contact with the second titanium layer 166.

  Of the wiring layer 160 of the semiconductor device 10, the first titanium layer 162, the titanium nitride layer 164, and the second titanium layer 166 formed on the Schottky electrode 190 side are also referred to as barrier metal layers. These layers are provided in order to suppress metal diffusion between the Schottky electrode 190 and the aluminum layer 168.

  The back electrode 170 of the semiconductor device 10 is an electrode that is ohmic-bonded to the −Z-axis direction side of the substrate 110. The back electrode 170 includes, in order from the layer in contact with the substrate 110, (i) a titanium layer 171 containing titanium (Ti), (ii) an aluminum layer 172 containing aluminum (Al), and (iii) titanium (Ti). A titanium layer 173, (iv) a titanium nitride layer 174 containing titanium nitride (TiN), (v) a titanium layer 175 containing titanium (Ti), and (vi) a silver layer 176 containing silver (Ag). Prepare. In this embodiment, the thickness of the titanium layer 171 is 30 nm, the thickness of the aluminum layer 172 is 300 nm, the thickness of the titanium layer 173 is 20 nm, the thickness of the titanium nitride layer 174 is 200 nm, and the thickness of the titanium layer 175 is The thickness is 20 nm, and the thickness of the silver layer 176 is 100 nm.

A-2. FIG. 2 is a process diagram showing a method for manufacturing the semiconductor device 10. When manufacturing the semiconductor device 10, the manufacturer forms the semiconductor layer 120 on the substrate 110 by epitaxial growth in Step P <b> 110. In this embodiment, the manufacturer forms the semiconductor layer 120 on the substrate 110 by epitaxial growth using an MOCVD apparatus that realizes a metal organic chemical vapor deposition (MOCVD) method.

  After forming the semiconductor layer 120 (process P110), in step P115, the manufacturer performs etching so that the cross section perpendicular to the Y axis (see FIG. 1) of the semiconductor layer 120 has a mesa (plateau) shape.

  After etching (process P110) (see FIG. 2), a Schottky electrode 190 is formed on the interface 121 of the semiconductor layer 120 in process P120. The process P120 includes a process P122, a process P124, and a process P126.

  Step P122 is a step of forming the nickel layer 192 mainly on the semiconductor layer 120 from nickel (Ni). Step P124 is a step of forming a palladium layer 194 mainly on palladium (Pd) on the nickel layer 192 after the step P122. Step P126 is a step of forming a molybdenum layer 196 mainly of molybdenum (Mo) on the palladium layer 194 after the step P124. In this embodiment, the manufacturer forms the Schottky electrode 190 by a lift-off method.

  After forming the Schottky electrode 190 (process P120), the manufacturer forms the insulating layer 180 on the + Z-axis side surfaces of the substrate 110, the semiconductor layer 120, and the Schottky electrode 190 in process P130. The process P130 includes a process P132 and a process P134.

Step P132 is a step of forming a first insulating layer 181 made of aluminum oxide (Al ₂ O ₃ ) on the + Z-axis side surfaces of the substrate 110, the semiconductor layer 120, and the Schottky electrode 190. In the present embodiment, the manufacturer forms the first insulating layer 181 by an ALD (Atomic Layer Deposition) method.

Step P134 is a step of forming the second insulating layer 182 made of silicon dioxide (SiO ₂ ) on the first insulating layer 181 after the step P132. In this embodiment, the manufacturer forms the second insulating layer 182 by a chemical vapor deposition (CVD) method.

  After forming the insulating layer 180 (process P130), the manufacturer forms the opening 185 (see FIG. 1) in the insulating layer 180 using wet etching in the process P140. In this embodiment, the manufacturer forms the opening 185 by photolithography.

  After forming the opening 185 (process P140 (see FIG. 2)), the manufacturer forms the back electrode 170 on the surface on the −Z-axis direction side of the substrate 110 in process P150. In this embodiment, the manufacturer provides a titanium layer 171, an aluminum layer 172, a titanium layer 173, a titanium nitride layer 174, a titanium layer 175, and a silver layer 176 on the −Z-axis direction side of the substrate 110. They are formed in this order. In the present embodiment, the back electrode 170 is formed using a vapor deposition method, but a sputtering method may be used.

  After forming the back electrode 170 (process P150), the manufacturer performs heat treatment in process P160. The heat treatment in this embodiment is performed at 400 ° C. for 30 minutes in a nitrogen atmosphere.

  After the heat treatment (process P160), the manufacturer forms the wiring layer 160 on the insulating layer 180 and the Schottky electrode 190 in process P170. The process P170 includes a process P172, a process P174, a process P176, and a process P178.

  Step P172 is a step of forming the first titanium layer 162 mainly using titanium (Ti) on the molybdenum layer 196 that is the Schottky electrode 190 and the second insulating layer 182 that is the insulating layer 180. is there. Step P174 is a step of forming titanium nitride layer 164 mainly on titanium nitride (TiN) on first titanium layer 162 after step P172. Step P176 is a step of forming second titanium layer 166 mainly on titanium (Ti) on titanium nitride layer 164 after step P174. Step P178 is a step of forming an aluminum layer 168 containing aluminum (Al) on the second titanium layer 166. In the present embodiment, the wiring layer 160 is formed by sputtering, but vapor deposition may be used. After the film formation, unnecessary portions are removed by etching, whereby the wiring layer 160 is formed. In this embodiment, dry etching using ICP (Inductively Coupled Plasma) is employed as etching, but other etching methods may be used. Further, the lift-off method may be used without performing etching.

  After forming the wiring layer 160 (process P170), the manufacturer performs heat treatment in process P180. The heat treatment in this embodiment is performed at 400 ° C. for 30 minutes in a nitrogen atmosphere.

  Through these steps, the semiconductor device 10 is completed.

The semiconductor device 10 of this embodiment includes a semiconductor layer 120, a nickel layer 192, a palladium layer 194, a molybdenum layer 196, a first titanium layer 162, a titanium nitride layer 164, and a second titanium layer 166. The aluminum layer 168 is laminated in this order. Further, the titanium content of the palladium layer 194 in the semiconductor device 10 is 1.0 × 10 ¹⁸ (atm / cm ³ ) or less.

  In the semiconductor device 10 of this embodiment, an aluminum (Al) layer is used as the outermost layer of the wiring layer 160 instead of the gold (Au) layer. For this reason, compared with the case where gold (Au) is included as a material of the semiconductor device, the semiconductor device 10 can be manufactured at low cost.

  In the semiconductor device 10 of this embodiment, a plurality of layers are laminated between the nickel layer 192 and the aluminum layer 168. For this reason, according to the semiconductor device 10, it is possible to reduce the decrease in the reverse breakdown voltage caused by the contact between the nickel layer 192 and the aluminum layer 168.

  In the semiconductor device 10 according to the present embodiment, the Schottky electrode 190 includes a nickel layer 192 having adhesiveness with the semiconductor layer 120 and a palladium layer 194 having a high work function. Since the palladium layer 194 is included as the Schottky electrode 190, according to the semiconductor device 10, the barrier height between the semiconductor layer 120 and the Schottky electrode can be improved.

In the semiconductor device 10 of this embodiment, a molybdenum layer 196 is laminated between the palladium layer 194 and the first titanium layer 162. For this reason, diffusion of titanium (Ti) into the palladium layer 194 is suppressed, and the titanium content of the palladium layer 194 in the semiconductor device 10 is 1.0 × 10 ¹⁸ (atm / cm ³ ) or less. As a result, the reduction in reverse breakdown voltage caused by the contact between the palladium layer 194 and the first titanium layer 162 or the presence of a large amount of titanium (Ti) in the palladium layer 194 is reduced in the semiconductor device 10. Can be reduced. Below, the experimental result which shows the relationship between the titanium content rate of a palladium layer and reverse direction pressure | voltage resistance is shown.

A-3. Experimental Results In this experiment, examples and comparative examples were used. As an example, the semiconductor device 10 manufactured by the above manufacturing method was used. As a comparative example, a semiconductor device 10A in which titanium (Ti) was previously mixed with 10 ²¹ (atm / cm ³ ) in the palladium layer 194 of the semiconductor device 10 was used. Except for the above, the examples and comparative examples are the same. 3 and 4 show the results of the example, and FIGS. 5 and 6 show the results of the comparative example.

FIG. 3 is a diagram illustrating the relationship between the depth of the semiconductor device and the concentration of each component. As the sample of FIG. 3, the semiconductor device 10 (Example) manufactured by the above manufacturing method was used. FIG. 3 shows the results obtained by secondary ion mass spectrometry (SIMS). In FIG. 3, the vertical axis indicates the concentration (atm / cm ³ ) of each component, and the horizontal axis indicates the depth (μm) of the semiconductor device. The point where the depth is 0 μm indicates an arbitrary point of the semiconductor layer 120, and each component of the Schottky electrode 190, each component of the wiring layer 160, and the like from about 1.6 μm to about 2.5 μm. Are detected in this order.

In FIG. 3, a peak of palladium (Pd) is present at a depth of about 1.8 μm to about 1.9 μm. The portion with the highest concentration of palladium (Pd) compared to other materials is the palladium layer 194. In FIG. 3, it can be seen that the titanium content of the palladium layer 194 of the semiconductor device 10 (Example) is 1.0 × 10 ¹⁸ (atm / cm ³ ) or less. Note that the titanium content of the molybdenum layer 196 is also 1.0 × 10 ¹⁸ (atm / cm ³ ) or less.

FIG. 4 is a diagram illustrating the relationship between current density (A / cm ² ) and reverse voltage (V). The semiconductor device 10 (Example) was used as the sample of FIG. FIG. 4 shows the current density when a reverse voltage is applied to the semiconductor device 10. That is, FIG. 4 shows the current density when the wiring layer 160 of the semiconductor device 10 is connected to the cathode of the power source and the back electrode 170 of the semiconductor device 10 is connected to the anode of the power source.

  In FIG. 4, when the reverse voltage applied to the semiconductor device 10 is in the range from 0V to about 20V, the current density decreases as the reverse voltage increases. In the range from about 20V to 200V, the reverse voltage It can be seen that the current density increases with increasing.

FIG. 5 is a diagram showing the relationship between the depth of the semiconductor device and the concentration of each component. A semiconductor device 10A (comparative example) was used as the sample of FIG. FIG. 5 shows the results obtained by secondary ion mass spectrometry (SIMS), similar to the results of FIG. In FIG. 5, the vertical axis indicates the concentration (atm / cm ³ ) of each component, and the horizontal axis indicates the depth (μm) of the semiconductor device. The point where the depth is 0 μm indicates an arbitrary point of the semiconductor layer, and the components of the Schottky electrode 190A and the components of the wiring layer 160A are divided between about 1.2 μm and about 1.9 μm. Are detected in this order.

In FIG. 5, there is a palladium (Pd) peak at a depth of about 1.3 μm to about 1.4 μm. The portion having the highest palladium (Pd) concentration compared to other materials is the palladium layer 194A of the semiconductor device 10A. 5 that the titanium content of the palladium layer 194A of the semiconductor device 10A (comparative example) is about 1.0 × 10 ²¹ (atm / cm ³ ).

FIG. 6 is a diagram illustrating the relationship between current density (A / cm ² ) and reverse voltage. A semiconductor device 10A (comparative example) was used as the sample of FIG. FIG. 6 shows the current density when a reverse voltage is applied to the semiconductor device 10A, similarly to the result of FIG.

From the result of FIG. 6, it can be seen that the current density is about 1.0 × 10 ⁻³ (A / cm ² ) regardless of the magnitude of the reverse voltage applied to the semiconductor device 10A. From this result, it can be seen that the semiconductor device 10A has a leaked current and is short-circuited.

From the results shown in FIGS. 4 to 6, the titanium content in the palladium layer is higher than that in the semiconductor device 10A in which the titanium content in the palladium layer is larger than 1.0 × 10 ¹⁸ (atm / cm ³ ). It can be seen that the reverse breakdown voltage of the semiconductor device 10 which is 1.0 × 10 ¹⁸ (atm / cm ³ ) or less is high. That is, it can be seen that the reverse breakdown voltage decreases when the titanium content of the palladium layer is high.

B. Second embodiment:
FIG. 7 is a process diagram illustrating a method for manufacturing the semiconductor device 20 according to the second embodiment. Compared with the manufacturing method of the semiconductor device 10 in the first embodiment (see FIG. 2), the manufacturing method of the semiconductor device 20 in the second embodiment is different in that the heat treatment in the process P160 is not performed, but the other points are the same. It is.

  The manufacturing method of the semiconductor device 20 according to the second embodiment includes a process of forming an aluminum layer without including a heat treatment process from a process of forming a nickel layer (process P122) to a process of forming an aluminum layer (process P178). After (Process P178), a process of heat treatment (Process P180) is included. By doing so, it is possible to suppress the diffusion of titanium (Ti) from the first titanium layer 162 to the palladium layer 194 due to the heat treatment. As a result, an increase in the titanium content of the palladium layer 194 can be suppressed. For this reason, according to the manufacturing method of the semiconductor device 20, the fall of a reverse breakdown voltage can be reduced more.

C. Other Embodiments The present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above-described effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

  In the above-described embodiment, the method of forming each layer of the insulating layer is not limited to the ALD method or the CVD method, but may be a sputtering method or a coating method.

  In the above-described embodiment, the formation of the Schottky electrode 190 (process P110), the formation of the back electrode 170 (process P150), and the formation of the wiring layer 160 (process P170) are performed in this order. However, it is not limited to this. For example, the wiring layer 160 may be formed after the Schottky electrode 190 is formed, and then the wiring layer 160 may be formed.

In the above-described embodiment, silicon oxide (SiO ₂ ) and aluminum oxide (Al ₂ O ₃ ) are used as the insulating layer. However, the present invention is not limited to this, and a single layer or a laminated structure other than the above may be used. Examples of the insulating layer include silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), Silicon oxynitride (SiON) may be used.

  In the above-described embodiment, the donor included in the n-type semiconductor layer is not limited to silicon (Si), and may be, for example, germanium (Ge), oxygen (O), or the like.

  In the above-described embodiment, a Schottky barrier diode is used as a semiconductor device. However, the present invention is not limited to this, and a semiconductor device having a Schottky electrode such as a MESFET (Metal-Semiconductor Field Effect Transistor) or an HFET (hetero-FET) It may be used.

  In the above-described embodiment, other materials may be used for the back electrode material. As other materials, other metals such as vanadium (V) and hafnium (Hf) may be used.

  In the above-described embodiment, the film forming apparatus is not particularly limited, but it is preferable to use a film forming apparatus that does not include titanium (Ti) from the viewpoint of suppressing the mixing of titanium (Ti) into the palladium layer.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 10A ... Semiconductor device 20 ... Semiconductor device 110 ... Substrate 120 ... Semiconductor layer 121 ... Interface 160 ... Wiring layer 160A ... Wiring layer 162 ... 1st titanium layer 164 ... Titanium nitride layer 166 ... 2nd titanium layer 168 ... Aluminum layer 170 ... Back electrode 171 ... Titanium layer 172 ... Aluminum layer 173 ... Titanium layer 174 ... Titanium nitride layer 175 ... Titanium layer 176 ... Silver layer 180 ... Insulating layer 181 ... First insulating layer 182 ... Second insulating layer 185 ... Opening 190 ... Schottky electrode 190A ... Schottky electrode 192 ... Nickel layer 194 ... Palladium layer 194A ... Palladium layer 196 ... Molybdenum layer

Claims (3)

A semiconductor layer mainly formed of gallium nitride;
A nickel layer formed mainly of nickel on the semiconductor layer;
On the nickel layer, a palladium layer mainly formed of palladium;
A molybdenum layer mainly formed of molybdenum on the palladium layer;
A first titanium layer formed mainly of titanium on the molybdenum layer;
A titanium nitride layer mainly formed of titanium nitride on the first titanium layer;
A second titanium layer formed mainly of titanium on the titanium nitride layer;
An aluminum layer containing aluminum on the second titanium layer;
The Schottky barrier diode whose titanium content of the said palladium layer is 1.0 * 10 < ¹⁸ > (atm / cm < ³ >) or less. A method of manufacturing a Schottky barrier diode,
Forming a nickel layer mainly of nickel on a semiconductor layer mainly formed of gallium nitride;
Forming a palladium layer mainly on palladium on the nickel layer;
Forming a molybdenum layer mainly on molybdenum on the palladium layer;
Forming a first titanium layer mainly on titanium on the molybdenum layer;
Forming a titanium nitride layer mainly from titanium nitride on the first titanium layer;
Forming a second titanium layer mainly on titanium on the titanium nitride layer;
Forming an aluminum layer containing aluminum on the second titanium layer,
The manufacturing method of the Schottky barrier diode whose titanium content of the said palladium layer is 1.0 * 10 < ¹⁸ > (atm / cm < ³ >) or less. A method for manufacturing a Schottky barrier diode according to claim 2,
From the step of forming the nickel layer to the step of forming the aluminum layer, does not include a step of heat treatment,
A method for manufacturing a Schottky barrier diode, comprising a step of performing a heat treatment after the step of forming the aluminum layer.

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