JP6398203B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a configuration in which a bonding pad is provided and a bonding wire is connected to the bonding pad.

  In a normal semiconductor device, a semiconductor element such as a transistor is formed in a semiconductor substrate (wafer) made of silicon or the like. In this semiconductor chip, a wiring layer made of aluminum or the like is formed, and this wiring layer is connected to each electrode or the like of the semiconductor element formed in the semiconductor chip. This semiconductor chip is used by being mounted in a package. At this time, it is necessary to electrically connect a terminal formed on the package side and a wiring layer in the semiconductor chip. For this purpose, usually, a bonding pad made of metal is formed on the uppermost layer of the semiconductor chip, and the bonding pad and the terminal of the package are connected via a bonding wire. Further, in the package, the entire structure is sealed with a mold resin.

  The bonding pad has a form in which a thin bonding wire can be easily connected, for example, has a rectangular shape of about 50 μm square, and is formed of a metal such as aluminum in the same manner as the wiring layer. In addition, the bonding wire is a thin wire usually made of gold or aluminum of about several tens of μmφ, and an ultrasonic wave is applied to the end portion, or further, this is heated and pressed against the bonding pad. Thus, the connection between the end of the bonding wire and the bonding pad is made. The connection between the terminal formed on the package side and the bonding wire is similarly performed.

  At this time, in order to obtain high reliability, it is important to increase the bonding strength between the bonding wire and the bonding pad. For this reason, Patent Document 1 discloses high reliability by optimizing the combination of materials in the bonding pad and bonding wire, and further performing bonding so that an alloy having a specific composition is formed between them. It is described that it can be obtained.

In this configuration, an alloy of aluminum (Al) and copper (Cu) is used as the bonding pad material. As a material for the bonding wire, a metal material mainly composed of Cu is used. At the time of joining, heat treatment is performed so that an alloy layer of CuAl ₂ , CuAl, Cu ₉ Al ₄ , Cu ₃ Al ₂ or the like is formed at the connection portion between them. In this case, high bonding strength can be obtained, and particularly high reliability can be obtained because the bonding strength is not deteriorated even during high-temperature storage.

JP 2009-177104 A

  When the reliability of bonding between the bonding wire and the bonding pad is increased, the adhesion between the bonding pad and the underlying layer becomes a problem. That is, problems such as peeling of the bonding pad from the base occurred. Here, particularly a large amount of peeling occurred between the resin layer and the bonding pad.

  That is, it has been difficult to suppress peeling between the bonding pad and the underlying layer.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
In the semiconductor device of the present invention, a resin layer is formed on a wiring layer formed on a semiconductor substrate, and a bonding pad passes through the resin layer and reaches the wiring layer, and a bonding pad is connected to the wiring layer. A semiconductor device having a structure in which a bonding wire is connected to the bonding pad, wherein the recess has a portion whose inner diameter increases toward the lower side on the resin layer around the pad opening. The bonding pad is formed on the pad opening and the recess so that a part of the bonding pad is formed in the recess .
In the semiconductor device of the present invention, the bonding pad has a multilayer structure including a layer mainly composed of copper (Cu), and the uppermost layer is a layer mainly composed of gold (Au). The component layer is formed in the recess.
In the semiconductor device of the present invention, the bonding pad includes, from below, a layer containing titanium (Ti) as a main component, a layer containing Cu as a main component, a layer containing nickel (Ni) as a main component, and the Au. It is characterized by being composed of a main component layer.
In the semiconductor device of the present invention, the bonding wire is formed of copper (Cu) or an alloy containing Cu.
In the semiconductor device of the present invention, the resin layer is composed of polybenzoxazole (PBO).

  Since this invention is comprised as mentioned above, peeling between a bonding pad and its foundation | substrate can be suppressed.

It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a fragmentary sectional view of the modification of the semiconductor device which concerns on embodiment of this invention.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is characterized by the structure around the bonding pad. FIG. 1 is a sectional view showing this structure. Here, a structure including a bonding pad 50 connected to a wiring layer 20 connected to an electrode of a power semiconductor element (power MOSFET, IGBT, etc.) formed on a silicon substrate (semiconductor substrate) 10 is shown.

A wiring layer 20 is formed on the silicon substrate 10 via an SiO ₂ layer 11 serving as an interlayer insulating layer, and a SiN layer 12 functioning as a passivation layer is further stacked thereon. The wiring layer 20 is connected to an electrode (for example, a gate electrode or a source electrode) of a semiconductor element formed on the lower side of the SiO ₂ layer 11. On the SiN layer 12, a thick resin layer 13 serving as an interlayer insulating layer between the bonding pad 50 is laminated.

Here, the wiring layer 20 is made of an Al—Cu alloy, which is a wiring material used in a normal semiconductor device, and has a thickness of about 2.6 μm, for example. The SiN layer 12 has a thickness of about 1.6 μm, for example, and is formed so as to cover the wiring layer 20 and its end. The SiO ₂ layer 11, the wiring layer 20, and the SiN layer 12 are all the same as those used in ordinary semiconductor devices (chips).

  The resin layer 13 is made of, for example, polybenzoxazole (PBO) as a heat resistant resin material with respect to a heat process when bonding wires are bonded or sealed with a mold resin, and the thickness thereof is, for example, 7 μm. It is made thicker than the SiN layer 12 and the like. Also, a PBO resin having the same photosensitivity as that of a photoresist (only an exposed area can be locally removed with a developer, or only an unexposed area can be locally removed with a developer) is used. You can also

  In this semiconductor device, a pad opening 30 that penetrates the resin layer 13 and the SiN layer 12 and exposes the wiring layer 20 is formed on the upper side, and a bonding pad 50 is formed covering the pad opening 30. From the lower side, the bonding pad 50 includes a Ti layer 51 mainly composed of titanium (Ti), a Cu layer 52 mainly composed of copper (Cu), a Ni layer 53 mainly composed of nickel (Ni), and gold ( It has a laminated structure in which an Au layer 54 containing Au) as a main component is disposed. On this, one end of the bonding wire 60 is connected, and the other end (not shown) of the bonding wire 60 is connected to, for example, an electrode of a package. The Ti layer 51 is provided in order to increase the bonding strength between the wiring layer 20 and the resin layer 13, but has a lower conductivity than the other layers, and thus is formed thinner than the Cu layer 52 and the like thereon. The On the other hand, since the conductivity of Cu is higher than that of Au or Ni, the conductivity of the bonding pad 50 is mainly brought about by the Cu layer 52. For this reason, as shown in FIG. 1, the pad opening 30 is mainly filled with the Cu layer 52.

  The bonding wire 60 is made of an alloy containing Cu, for example, an alloy of Cu and Au. Moreover, it can also comprise only Cu. For this reason, an alloy of Cu and Au is formed at the bonding portion between the bonding wire 60 and the Au layer that is the uppermost layer of the bonding pad 50, and the bonding strength between them can be increased. That is, the Au layer 54 is used to increase the bonding strength with the bonding wire 60. Further, Au is a material that is difficult to oxidize, and is not oxidized even during heating. For this reason, the Au layer 54 also functions as an antioxidant layer in the bonding pad 50.

  Further, Au constituting the uppermost layer of the bonding pad 50 has higher mechanical strength and higher resistance to acids and alkalis than Al. For this reason, the chemical resistance of the bonding pad 50 is high. Furthermore, the mechanical strength of Ni and Cu in the Ni layer 53 and the Cu layer 52 below the Au layer 54 is also higher than that of Al. For this reason, the mechanical strength of the bonding pad 50 is higher than that of the bonding pad in the structure described in Patent Document 1.

  In addition, since an alloy is formed between Ti and Cu in the bonding pad 50, adhesion between the Ti layer 51 and the wiring layer 20 and between the Ti layer 51 and the Cu layer 52 is also increased. Further, since an alloy is formed between Cu and Ni or between Ni and Au, the adhesion between the Cu layer 52 and the Ni layer 53 and between the Ni layer 53 and the Au layer 54 is also increased. For this reason, the adhesion between each layer in the bonding pad 50 having a laminated structure is also high.

  Here, a recess 31 is formed around the pad opening 30 in the resin layer 13. Unlike the pad opening 30, there is no structure on the bottom surface of the recess 31 in the resin layer 13, but the Ti layer 51 and the Cu layer 52 are formed in the recess 31 like the pad opening 30. Yes. For this reason, a part of the bonding pad 50 is also formed in the recess 31, and the bonding pad 50 is pinned to the resin layer 13 by this part. Thereby, peeling of the bonding pad 50 from the resin layer 13 is suppressed.

  2A to 2H are process cross-sectional views when the structure of FIG. 1 is manufactured. Here, first, a wafer having a structure as shown in FIG. 2A is used as a base. In this structure, SiN that is uniformly a passivation layer on the wiring layer 20 by, for example, a CVD method. Layer 12 is formed.

  Next, as shown in FIG. 2B, a resin layer 13 is formed thereon. At this time, for example, a liquid PBO resin material is spin-coated on a wafer having the structure shown in FIG. 2A, followed by drying, heating, etc. (curing treatment), thereby realizing the structure shown in FIG. 2B. can do. At this time, the thickness thereof is also thicker than that of the SiN layer 12 or the like, and can be, for example, about 7 μm. In this case, as shown in the drawing, the surface of the resin layer 13 can be flat even when the surface of the base (the structure of FIG. 2A) is not flat.

  Next, as shown in FIG. 2C, a pad opening 30 is formed through the resin layer 13 and the SiN layer 12 and exposing the wiring layer 20. For this purpose, a photoresist pattern having an opening corresponding to the pad opening 30 is formed on the resin layer 13, and then dry etching is performed to form the resin layer 13 in a region corresponding to the pad opening 30, SiN. After removing the layer, the photoresist pattern is removed. In this dry etching, the conditions for etching the upper resin layer 13 and the conditions for etching the lower SiN layer 12 are different, so this dry etching is performed in two stages. Alternatively, when photosensitive PBO is used as the resin layer 13, an opening is provided in the resin layer 13 by exposure and development, and the SiN layer 12 exposed in this state is removed by dry etching, thereby providing a pad opening. 30 can also be formed.

  Next, as shown in FIG. 2D, a recess 31 is formed in the resin layer 13. This step is performed by dry etching as in the case of forming the pad opening 30, and this condition is the same as the dry etching condition of the resin layer 13. However, when the pad opening 30 is formed (FIG. 2C), the SiN layer 12 and the wiring layer 30 on the bottom surface serve as a stopper during etching, whereas the bottom surface of the recess 31 is not etched. There is no structure to serve as a stopper. For this reason, when the pad opening 30 is formed and when the recess 31 is formed, the etching time is different even when the same etching conditions are used, and the latter case is generally shorter. However, the recess 31 may be deepened until it reaches the surface of the SiN layer 12. In this case, the dry etching of the resin layer 13 when forming the pad opening 30 and the dry etching of the resin layer 13 when forming the recess 31 can be performed simultaneously. The resin layer 13 may be cured after the pad opening 30 and the recess 31 are formed. Further, the order of the step of forming the pad opening 30 and the step of forming the recess 31 may be reversed.

  Next, as shown in FIG. 2D, a thin Ti layer 51 is formed on the entire surface by sputtering or the like. The thickness of the Ti layer 51 can be about 200 nm, for example. According to the sputtering method or the like, the Ti layer 51 can be formed also in the pad opening 30.

  Next, as shown in FIG. 2F, the Cu layer 52 is also formed by sputtering. The Cu layer 52 is sufficiently thicker than the Ti layer 51 in order to reduce the electrical resistance of the bonding pad 50, for example, about 17 μm. The Ti layer 51 (FIG. 2 (d)) and the Cu layer 52 (FIG. 2 (e)) are continuously formed by actually changing the sputtering target with the same sputtering apparatus. A film can be formed. In addition, in order to form the Cu layer 52 thick and fill the pad opening 30 with the Cu layer 52, the Cu layer is first formed thin enough to be a base layer for plating, and then Cu plating is performed. Thus, a thick Cu layer 52 can also be obtained. In this case, only the first thin Cu layer can be formed by the sputtering method. For example, after forming 1.0 to 2.0 μm by the sputtering method, the rest can be formed by plating. Alternatively, a part of the Ti layer 51 and the Cu layer 52 may be continuously formed by vapor deposition instead of sputtering, and then Cu plating may be performed.

  Next, as shown in FIG. 2G, a Ni layer 53 and an Au layer 54 are successively formed by plating (electrolytic plating, electroless plating) using the Cu layer 52 as a base layer. The thickness of the Ni layer 53 can be about 3 μm, and the thickness of the Au layer 54 can be about 0.5 μm, which is thinner than this.

  After that, as shown in FIG. 2H, a photoresist pattern is formed on the bonding pad 50 (Au layer 54, Ni layer 53, Cu layer 52, Ti layer 51), and unnecessary portions ( By removing the photoresist pattern after etching (left and right in the drawing) (dry etching, wet etching), the bonding pad 50 having the configuration shown in FIG. 1 is formed.

  Thereafter, ultrasonic waves are applied while heating the silicon substrate 10 side, and one end of the bonding wire 60 is pressure-bonded to the bonding pad 50, thereby bonding the bonding wire 60 and the bonding pad 50 together.

  At this time, as described above, a part of the bonding pad 50 (Ti layer 51, Cu layer 52) has entered the recess 31, so that the bonding pad 50, the resin layer 13, Separation during is suppressed. Further, after that, the structure of FIG. 1 is sealed in the mold resin, but even in this step, peeling of the bonding pad 50 is suppressed. Further, even when the semiconductor device is actually used and a thermal cycle between normal temperature and high temperature is applied, the bonding pad 50 is prevented from being peeled off, so that high reliability can be obtained in this semiconductor device. .

  Next, a modified example of the semiconductor device will be described. FIG. 3 is a view showing a part of the cross-sectional structure of the semiconductor device, and shows a shape including a recess corresponding to the region surrounded by the rectangular broken line in FIG. The structure other than the recess and its surroundings is the same as in FIG.

  In the cross-sectional shape of the recess 32 in this semiconductor device, as shown in FIG. 3, the width increases from the surface of the resin layer 13 toward the lower side. Such a shape is known as a so-called bowing shape, and can be formed by dry etching.

  In dry etching, etching can be performed only in the vertical direction from the surface, and anisotropic etching that does not cause etching in the horizontal direction can be performed. As a result, a concave portion 31 having a vertical wall surface as shown in FIG. Can be formed. However, it is known that a cross-sectional shape such as the recess 32 can also be realized by adjusting dry etching conditions and controlling the balance between etching and deposition during dry etching. Since it is difficult to fill the inside of such a structure with a metal material, generally, a hole having such a shape is rarely used in a semiconductor device.

  However, since the recess 32 is not used for electrical connection, the recess 32 does not need to be filled with a metal material (Cu layer 52) without a gap. On the other hand, it is clear that the bonding pad 50 can be pinned even if the interior of the recess 32 is not filled with the metal material (Cu layer 52) without a gap. For this reason, the recessed part 32 of the shape shown by FIG. 3 can be used preferably. In FIG. 3, the Ti layer 51 is uniformly formed on the inner surface of the recess 32 and the recess 32 is filled with the Cu layer 52. However, the Ti layer 51 and the Cu layer 52 are thus formed in the recess 32. It does not need to be formed.

  Thus, it is clear that the pinning effect of the bonding pad is increased if the concave portion is formed with a portion whose inner diameter increases toward the lower side. In this case, the occurrence of peeling is further suppressed. Is done. This structure can also be manufactured by the same manufacturing method as in FIG.

  In manufacturing the structure of FIGS. 1 and 3, the resin layer 13 was dry etched after forming a photoresist pattern to form a recess. Accordingly, a concave portion having a predetermined shape and size can be formed at a predetermined location. However, the pinning effect of the bonding pad 50 can be obtained not by the concave portions formed in predetermined locations having such a predetermined shape and size but by randomly formed concave portions.

  For this purpose, a step of exposing the surface of the resin layer 13 to plasma (performing plasma irradiation on the surface of the resin layer 13) may be provided instead of the step of FIG. The surface of the resin layer 13 is roughened by such plasma treatment, and fine irregularities are randomly formed on the surface. It is clear that this recess functions in the same manner as the recesses 31 and 32 described above. In this case, since a mask (photoresist pattern) for forming the recess is not necessary, this semiconductor device can be manufactured at a lower cost.

  In the above structure, the bonding pad 50 has a laminated structure in which the Au layer 54, the Ni layer 53, the Cu layer 52, and the Ti layer 51 are formed from the top. However, the uppermost layer may be an Au layer and the lower layer side may have another configuration. Also in this case, as the bonding wire 60, an alloy of Cu and Au is used, but another alloy containing Cu may be used. Moreover, the formation method of each layer is arbitrary as long as said structure is realizable.

  Moreover, although PBO was used as the resin layer 13, other resin materials, for example, a polyimide etc., can also be used. The formation method is also arbitrary.

10 Silicon substrate (semiconductor substrate)
11 SiO ₂ layer 12 SiN layer 13 Resin layer 20 Wiring layer 30 Pad openings 31, 32 Recess 50 Bonding pad 51 Ti layer 52 Cu layer 53 Ni layer 54 Au layer 60 Bonding wire

Claims (5)

A resin layer is formed on the wiring layer formed on the semiconductor substrate, and a bonding pad is connected to the wiring layer through a pad opening that penetrates the resin layer and reaches the wiring layer. A semiconductor device having a structure to which bonding wires are connected,
On the resin layer around the pad opening, a recess having a portion whose inner diameter increases toward the bottom is formed,
A semiconductor device, wherein the bonding pad is formed on the pad opening and the recess so that a part of the bonding pad is formed in the recess. The bonding pad has a multilayer structure including a layer mainly composed of copper (Cu), and the uppermost layer is a layer mainly composed of gold (Au), and the layer mainly composed of Cu is the recess. The semiconductor device according to claim 1 , wherein the semiconductor device is formed inside. The bonding pad includes, from below, a layer containing titanium (Ti) as a main component, a layer containing Cu as a main component, a layer containing nickel (Ni) as a main component, and a layer containing Au as a main component. The semiconductor device according to claim 2 , wherein the semiconductor device is formed. The semiconductor device according to any one of claims 1 to 3, wherein the bonding wire is formed of copper (Cu) or an alloy containing Cu. The semiconductor device according to any one of claims 1 to 4, wherein the resin layer is made of polybenzoxazole (PBO).

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