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JP6349089B2 - Semiconductor device and imaging module - Google Patents

Semiconductor device and imaging module Download PDF

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Publication number
JP6349089B2
JP6349089B2 JP2014004352A JP2014004352A JP6349089B2 JP 6349089 B2 JP6349089 B2 JP 6349089B2 JP 2014004352 A JP2014004352 A JP 2014004352A JP 2014004352 A JP2014004352 A JP 2014004352A JP 6349089 B2 JP6349089 B2 JP 6349089B2
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Japan
Prior art keywords
substrate
wiring
semiconductor device
terminal
dielectric layer
Prior art date
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Expired - Fee Related
Application number
JP2014004352A
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Japanese (ja)
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JP2015133417A (en
Inventor
英之 和田
英之 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
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Fujikura Ltd
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Priority to JP2014004352A priority Critical patent/JP6349089B2/en
Priority to PCT/JP2014/084252 priority patent/WO2015107849A1/en
Publication of JP2015133417A publication Critical patent/JP2015133417A/en
Application granted granted Critical
Publication of JP6349089B2 publication Critical patent/JP6349089B2/en
Expired - Fee Related legal-status Critical Current
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    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)
  • Wire Bonding (AREA)

Description

本発明は、半導体装置、及び撮像モジュールに関する。   The present invention relates to a semiconductor device and an imaging module.

従来から固体撮像素子などの半導体装置は、例えばチップサイズパッケージ（ＣＳＰ）として製造され、配線基板に実装されて、撮像モジュールなどの各種デバイスに利用されている。このような半導体装置は、バンプ電極などの端子および配線が形成された端子面を有し、この端子面が接着剤などで配線基板に接着され、配線基板に実装される（例えば、下記の特許文献１、２参照）。   2. Description of the Related Art Conventionally, a semiconductor device such as a solid-state imaging element is manufactured as a chip size package (CSP), mounted on a wiring board, and used for various devices such as an imaging module. Such a semiconductor device has a terminal surface on which terminals such as bump electrodes and wiring are formed, and this terminal surface is bonded to the wiring substrate with an adhesive or the like and mounted on the wiring substrate (for example, the following patents) References 1 and 2).

一般的に、半導体装置には端子面には、半導体装置の表面の配線と配線基板の表面の配線との短絡を避けるために、絶縁性のオーバーコート層が設けられる。このオーバーコート層を形成するには、例えば、端子および配線を覆う絶縁膜を端子面のほぼ全面にわたって形成し、この絶縁膜に端子を露出させる開口を形成する。この開口は、端子との位置誤差、寸法誤差に対してマージンを取るように端子とギャップを介して、端子を環状に囲むように形成される。   Generally, an insulating overcoat layer is provided on a terminal surface of a semiconductor device in order to avoid a short circuit between the wiring on the surface of the semiconductor device and the wiring on the surface of the wiring substrate. In order to form this overcoat layer, for example, an insulating film covering the terminals and the wiring is formed over almost the entire surface of the terminal, and an opening exposing the terminal is formed in this insulating film. This opening is formed so as to enclose the terminal in an annular shape through the terminal and the gap so as to take a margin with respect to a positional error and a dimensional error with respect to the terminal.

特開２００９−２７７８８３号公報JP 2009-277883 A 特開２００６−１９１１２６号公報JP 2006-191126 A

上述のような半導体装置は、接着剤などを利用して実装される際に、端子とオーバーコート層の開口の内縁との間のギャップに気泡（ボイド）が残りやすい。このようなボイドは、温度変化に伴う膨張収縮により、電気的接続の破断、半導体装置と配線基板との接合部の破壊などの不具合の原因になりうる。このように、従来の半導体装置は、実装不良が発生することがありえる。本発明は、上記の事情に鑑み成されたものであって、実装不良の発生を抑制できる半導体装置、及び撮像モジュールを提供することを目的とする。   When such a semiconductor device is mounted using an adhesive or the like, bubbles (voids) tend to remain in the gap between the terminal and the inner edge of the opening of the overcoat layer. Such voids can cause problems such as breakage of electrical connection and breakage of a joint portion between a semiconductor device and a wiring board due to expansion and contraction accompanying temperature change. As described above, the conventional semiconductor device may have a mounting defect. The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device and an imaging module that can suppress the occurrence of mounting defects.

本発明の第１の態様の半導体装置は、デバイスに実装される半導体装置であって、基板と、基板の一方の面に形成され、デバイスに接続される端子と、基板の一方の面に形成され、端子に導通する配線と、配線の少なくとも一部を覆う誘電体層と、を備え、基板の一方の面は、誘電体層が形成されていない非形成領域を有し、非形成領域は、端子の位置から基板のエッジの位置まで連続している。   A semiconductor device according to a first aspect of the present invention is a semiconductor device mounted on a device, formed on a substrate, one surface of the substrate, connected to the device, and formed on one surface of the substrate. And a dielectric layer covering at least a part of the wiring, and one surface of the substrate has a non-formation region in which the dielectric layer is not formed, and the non-formation region is , From the terminal position to the edge position of the substrate.

第１の態様の半導体装置において、基板は矩形状であり、非形成領域は、基板の４辺のうち端子に最も近い辺の少なくとも一部を含んでいてもよい。   In the semiconductor device of the first aspect, the substrate may have a rectangular shape, and the non-formation region may include at least a part of the side closest to the terminal among the four sides of the substrate.

第１の態様の半導体装置は、基板を貫通して配線に導通する導電部を備え、誘電体層は、導電部の少なくとも一部を覆っていてもよい。   The semiconductor device according to the first aspect may include a conductive portion that penetrates the substrate and conducts to the wiring, and the dielectric layer may cover at least a part of the conductive portion.

第１の態様の半導体装置において、誘電体層の一部は、基板のエッジを示すアライメントマークとして形成されていてもよい。   In the semiconductor device of the first aspect, a part of the dielectric layer may be formed as an alignment mark indicating the edge of the substrate.

第１の態様の半導体装置において、基板は、互いに直交する第１辺および第２辺を含む矩形状であり、アライメントマークは、第１辺に平行な辺および第２辺に平行な辺を有していてもよい。   In the semiconductor device of the first aspect, the substrate has a rectangular shape including a first side and a second side orthogonal to each other, and the alignment mark has a side parallel to the first side and a side parallel to the second side. You may do it.

第１の態様の半導体装置は、基板の他方の面側から入射する光を電力に変換する光電変換層を備え、基板の一方の面に端子を含む複数の端子が配置され、光電変換層は、複数の端子のいずれかと電気的に接続されていてもよい。   The semiconductor device of the first aspect includes a photoelectric conversion layer that converts light incident from the other surface side of the substrate into electric power, a plurality of terminals including terminals are disposed on one surface of the substrate, and the photoelectric conversion layer is The terminal may be electrically connected to any one of the plurality of terminals.

本発明の第２の態様の撮像モジュールは、第１の態様の半導体装置と、半導体装置の一方の面に形成された接着層と、接着層を介して半導体装置が接着され、半導体装置の端子と接続された第２の配線を有する配線基板と、を備える。   An imaging module according to a second aspect of the present invention includes a semiconductor device according to the first aspect, an adhesive layer formed on one surface of the semiconductor device, and the semiconductor device bonded via the adhesive layer. And a wiring board having a second wiring connected to the wiring board.

第２の態様の撮像モジュールにおいて、半導体装置の非形成領域は、平面視した基板の一方の面のうち半導体装置の端子が配線基板の接続箇所と重なる位置に配置され、平面視した基板の一方の面のうち半導体装置の配線が配線基板の第２の配線と重ならない位置に配置されていてもよい。   In the imaging module according to the second aspect, the non-formation region of the semiconductor device is arranged at a position where the terminal of the semiconductor device overlaps the connection portion of the wiring board on one surface of the substrate in plan view, and one side of the substrate in plan view Of these surfaces, the wiring of the semiconductor device may be arranged at a position where it does not overlap with the second wiring of the wiring board.

本発明の態様によれば、実装不良の発生を抑制できる半導体装置、及び撮像モジュールを提供することができる。   According to the aspects of the present invention, it is possible to provide a semiconductor device and an imaging module that can suppress the occurrence of mounting defects.

本実施形態に係る半導体装置を搭載した光学装置を示す図である。It is a figure which shows the optical apparatus carrying the semiconductor device which concerns on this embodiment. 撮像素子（半導体装置）の端子面を示す図である。It is a figure which shows the terminal surface of an image pick-up element (semiconductor device). 図２のＡ−Ａ’線に対応する撮像素子及び配線基板の断面図である。It is sectional drawing of the image pick-up element and wiring board corresponding to the A-A 'line of FIG. 第１変形例の半導体装置を示す図である。It is a figure which shows the semiconductor device of a 1st modification. アライメントマークの利用例を説明するための説明図である。It is explanatory drawing for demonstrating the usage example of an alignment mark. （Ａ）〜（Ｃ）は、第２〜第４変形例の半導体装置を示す図である。(A)-(C) are figures which show the semiconductor device of the 2nd-4th modification.

図１は、本実施形態に係る半導体装置を搭載した光学装置１を示す図である。本実施形態において、半導体装置２は、ＣＭＯＳセンサー、ＣＣＤセンサー等のイメージセンサー（以下、撮像素子ともいう）であり、光学装置１は、半導体装置２が取得した画像データを出力する撮像モジュールの少なくとも一部であり、例えば内視鏡などの狭い空間で使用される装置に利用される。   FIG. 1 is a diagram showing an optical device 1 on which a semiconductor device according to this embodiment is mounted. In the present embodiment, the semiconductor device 2 is an image sensor (hereinafter also referred to as an image sensor) such as a CMOS sensor or a CCD sensor, and the optical device 1 is at least an imaging module that outputs image data acquired by the semiconductor device 2. For example, it is used for a device used in a narrow space such as an endoscope.

光学装置１は、撮像モジュール３と、撮像モジュール３に対する光入射側に設けられたレンズユニット４と、撮像モジュール３を収容するケース５と、撮像モジュール３の撮像結果を出力するケーブル６と、を備える。撮像モジュール３は、半導体装置２（以下、撮像素子２ともいう）、及び撮像素子２が実装された配線基板７を備える。   The optical device 1 includes an imaging module 3, a lens unit 4 provided on the light incident side with respect to the imaging module 3, a case 5 that houses the imaging module 3, and a cable 6 that outputs an imaging result of the imaging module 3. Prepare. The imaging module 3 includes a semiconductor device 2 (hereinafter also referred to as an imaging element 2) and a wiring board 7 on which the imaging element 2 is mounted.

光学装置１は、撮像対象からの光Ｌを、レンズユニット４を介して撮像素子２で受光する。また、光学装置１は、撮像素子２が撮像した結果を示す画像データを、配線基板７およびケーブル６を介して外部へ出力する。ケーブル６は、例えば、画像表示装置、記憶装置、画像処理装置などに接続され、ユーザーは、撮像対象を撮像した画像を、画像表示装置に表示させること、記憶装置に記憶させること、画像処理装置に処理させること等ができる。   The optical device 1 receives light L from the imaging target with the imaging device 2 via the lens unit 4. In addition, the optical device 1 outputs image data indicating the result of imaging by the imaging device 2 to the outside via the wiring board 7 and the cable 6. The cable 6 is connected to, for example, an image display device, a storage device, an image processing device, and the like, and the user causes the image display device to display an image captured of the imaging target, to store the image in the storage device, and the image processing device. Can be processed.

レンズユニット４は、例えば、１又は２以上のレンズと、レンズを保持する鏡筒とを含む。レンズユニット４は、撮像対象物の像を撮像素子２の受光面１０に形成する。レンズユニット４は、その光軸を撮像素子２の受光面１０に対して位置合わせされた状態で、撮像素子２との相対位置が固定されている。ケース５は、例えば金属製の筒状であり、その内部に、レンズユニット４が取り付けられた撮像モジュール３（レンズ付き撮像モジュール）を収容している。   The lens unit 4 includes, for example, one or more lenses and a lens barrel that holds the lenses. The lens unit 4 forms an image of the imaging object on the light receiving surface 10 of the imaging device 2. The lens unit 4 has its optical axis aligned with the light receiving surface 10 of the image sensor 2 and the relative position with the image sensor 2 is fixed. The case 5 is, for example, a metal cylinder, and accommodates the imaging module 3 (the imaging module with a lens) to which the lens unit 4 is attached.

配線基板７は、例えばフレキシブルプリント基板などのように、可撓性を有する基板である。配線基板７の片面は、配線が形成された配線面１１である。配線基板７は、配線面１１を外側に向けて、その両端部を合せるように折り返されている。   The wiring board 7 is a flexible board such as a flexible printed board. One side of the wiring board 7 is a wiring surface 11 on which wiring is formed. The wiring board 7 is folded so that the wiring surface 11 faces outward and the both ends thereof are aligned.

配線基板７の一端部および他端部は、配線面１１の反対側の面で互いに接合された接合部になっている。この接合部は、ケース５の軸方向に延びており、例えば、ケース５の内壁に絶縁性の樹脂などで固定される。配線基板７の中央部は、配線基板７の折り返し部分であり、図１においては配線基板７の側方から見て略三角形状である。この三角形の底辺に相当する部分は、ほぼ平面状に形成されており、撮像対象からの光が入射する側のケース５の開口を向けて配置されている。この平面状の部分には、撮像素子２が実装されている。   One end portion and the other end portion of the wiring board 7 are joined portions joined to each other on the surface opposite to the wiring surface 11. The joint extends in the axial direction of the case 5 and is fixed to the inner wall of the case 5 with an insulating resin or the like, for example. The central portion of the wiring board 7 is a folded portion of the wiring board 7 and has a substantially triangular shape when viewed from the side of the wiring board 7 in FIG. The portion corresponding to the base of the triangle is formed in a substantially flat shape, and is arranged with the opening of the case 5 on the side on which light from the imaging target is incident. The imaging element 2 is mounted on the planar portion.

撮像素子２は、例えば、チップサイズパッケージ技術を利用して製造されたＣＭＯＳセンサーである。撮像素子２は、撮像対象物からの光Ｌがレンズユニット４を介して入射する機能面１２と、機能面１２の反対を向いており複数の端子１３が配置された端子面１４とを有する。撮像素子２は、ケース５において撮像対象からの光が入射する側の開口に機能面１２を向けて、配置されている。撮像素子２は、その端子面１４を配線基板７の配線面１１に向けて、配線基板７に実装されている。複数の端子１３は、それぞれ、配線基板７の配線面１１に設けられた配線と電気的に接続されており、この配線を介してケーブル６内の導体と電気的に接続されている。   The image sensor 2 is a CMOS sensor manufactured using, for example, a chip size package technology. The imaging device 2 has a functional surface 12 on which light L from the imaging target is incident via the lens unit 4 and a terminal surface 14 facing the opposite side of the functional surface 12 and having a plurality of terminals 13 disposed thereon. The imaging element 2 is arranged with the functional surface 12 facing the opening on the side where light from the imaging target is incident in the case 5. The imaging element 2 is mounted on the wiring board 7 with its terminal surface 14 facing the wiring surface 11 of the wiring board 7. Each of the plurality of terminals 13 is electrically connected to a wiring provided on the wiring surface 11 of the wiring substrate 7, and is electrically connected to a conductor in the cable 6 through this wiring.

図２は撮像素子２の端子面１４を示す図である。図２に示すように、撮像素子２は、基板２０と、基板２０の端子面１４に形成された端子１３と、端子１３に導通する配線２１と、配線２１の少なくとも一部を覆う誘電体層２２とを備える。   FIG. 2 is a diagram illustrating the terminal surface 14 of the image sensor 2. As shown in FIG. 2, the imaging device 2 includes a substrate 20, a terminal 13 formed on the terminal surface 14 of the substrate 20, a wiring 21 conducting to the terminal 13, and a dielectric layer covering at least a part of the wiring 21. 22.

本実施形態において、端子面１４には、撮像素子２の内部に通じる導電部２３が形成されている。導電部２３は、配線２１を介して端子１３と電気的に接続されている。図２には、複数（ここでは４つ）の導電部２３、及び複数（ここでは４つ）の端子１３が図示されており、端子１３は、導電部２３と１対１で対応している。また、配線２１は、対応関係にある導電部２３と端子１３との組ごとに設けられており、図２には複数（ここでは４）の系統の配線が図示されている。   In the present embodiment, the terminal surface 14 is formed with a conductive portion 23 that communicates with the inside of the image sensor 2. The conductive portion 23 is electrically connected to the terminal 13 through the wiring 21. FIG. 2 shows a plurality of (here, four) conductive portions 23 and a plurality (here, four) of terminals 13. The terminals 13 correspond to the conductive portions 23 on a one-to-one basis. . Further, the wiring 21 is provided for each pair of the conductive portion 23 and the terminal 13 having a corresponding relationship, and FIG. 2 shows a plurality (four in this case) of wirings.

端子面１４の一部は、誘電体層２２が形成されていない非形成領域２４になっている。非形成領域２４は、端子１３の位置から基板２０のエッジ２０ａの位置まで連続している。すなわち、配線基板７に実装されていない状態の撮像素子２において、端子１３は、基板２０の端面（側方）から見た場合に、非形成領域２４を介して基板２０の外側に大気解放されている。本実施形態において、基板２０は矩形板状であり、非形成領域２４は、端子１３の位置から、基板２０の４辺のうち端子１３に最も近い辺（エッジ２０ａ）まで連続している。   A part of the terminal surface 14 is a non-formation region 24 in which the dielectric layer 22 is not formed. The non-formation region 24 is continuous from the position of the terminal 13 to the position of the edge 20a of the substrate 20. That is, in the imaging device 2 not mounted on the wiring substrate 7, the terminal 13 is released to the outside of the substrate 20 through the non-formation region 24 when viewed from the end surface (side) of the substrate 20. ing. In this embodiment, the board | substrate 20 is rectangular plate shape, and the non-formation area | region 24 continues from the position of the terminal 13 to the edge | side (edge 20a) nearest to the terminal 13 among four sides of the board | substrate 20. FIG.

図３は、図２のＡ−Ａ’線に対応する位置における撮像素子２及び配線基板７の断面図である。図３の撮像素子２は、基板２０に設けられた素子層２５と、素子層２５上に設けられ光Ｌが通る保護基板２６とを含む。保護基板２６は、例えば透光性を有するガラス基板であり、素子層２５に対して、基板２０の端子面１４の反対側に設けられている。   FIG. 3 is a cross-sectional view of the image sensor 2 and the wiring board 7 at a position corresponding to the line A-A ′ of FIG. 2. 3 includes an element layer 25 provided on the substrate 20 and a protective substrate 26 provided on the element layer 25 and through which the light L passes. The protective substrate 26 is a glass substrate having translucency, for example, and is provided on the opposite side of the terminal surface 14 of the substrate 20 with respect to the element layer 25.

素子層２５は、保護基板２６を通った光Ｌを受光する受光面１０を有する。撮像素子２は、複数の画素を有し、受光面１０には画素ごとに光電変換層が配置されている。光電変換層は、半導体材料からなり、光電変換層には入射した光Ｌの光電効果により電荷が発生する。すなわち、光電変換層は、撮像素子２において端子面１４と反対側の機能面１２から入射する光Ｌを電力に変換する。   The element layer 25 has the light receiving surface 10 that receives the light L that has passed through the protective substrate 26. The image sensor 2 has a plurality of pixels, and a photoelectric conversion layer is disposed on the light receiving surface 10 for each pixel. The photoelectric conversion layer is made of a semiconductor material, and charges are generated in the photoelectric conversion layer due to the photoelectric effect of incident light L. That is, the photoelectric conversion layer converts the light L incident from the functional surface 12 opposite to the terminal surface 14 in the image sensor 2 into electric power.

素子層２５には、各画素の光電変換層に発生した電荷を読み出す読出回路２７が設けられている。読出回路２７は、各画素に設けられたスイッチング素子、及び配線などを含む。素子層２５には、読出回路２７を構成する配線およびスイッチング素子の他に、層間絶縁膜、平坦化膜、パッシベーション膜などが設けられる。また、素子層２５に、各画素の光電変換層から読み出された電荷を示すアナログ信号を増幅するアンプ、このアナログ信号をデジタル信号へ変換するＡＤ変換器などが設けられていてもよい。   The element layer 25 is provided with a readout circuit 27 that reads out charges generated in the photoelectric conversion layer of each pixel. The readout circuit 27 includes a switching element and a wiring provided in each pixel. In the element layer 25, an interlayer insulating film, a planarizing film, a passivation film, and the like are provided in addition to the wiring and the switching element constituting the readout circuit 27. The element layer 25 may be provided with an amplifier that amplifies an analog signal indicating the electric charge read from the photoelectric conversion layer of each pixel, an AD converter that converts the analog signal into a digital signal, and the like.

読出回路２７は、導電部２３と電気的に接続されている。すなわち、各画素の光電変換層は、読出回路２７を介して導電部２３と電気的に接続されている。導電部２３は、いわゆる貫通電極（ＴＳＶ；Ｔｈｒｏｕｇｈ Ｓｉｌｉｃｏｎ Ｖｉａ）であり、基板２０を貫通しているとともに一部が端子面１４上に引き出されている。導電部２３の少なくとも一部は、端子面１４上の配線２１と同じプロセスで一括して（すなわち同一材料で）形成されていてもよいし、配線２１とは別に形成されていてもよい。   The read circuit 27 is electrically connected to the conductive portion 23. That is, the photoelectric conversion layer of each pixel is electrically connected to the conductive portion 23 via the readout circuit 27. The conductive portion 23 is a so-called through electrode (TSV; Through Silicon Via), which penetrates the substrate 20 and is partly drawn on the terminal surface 14. At least a part of the conductive portion 23 may be formed collectively (that is, with the same material) in the same process as the wiring 21 on the terminal surface 14, or may be formed separately from the wiring 21.

端子１３は、はんだバンプ、スタッドバンプ、めっきバンプ等のバンプ電極であり、基板２０の端子面１４から外部に向かって凸の突起状である。端子１３は、端子面１４の法線方向に向かって誘電体層２２よりも突出している。端子１３は、配線２１に接して形成されており、配線２１と導通する。また、端子１３は、配線基板７の配線面１１に設けられた配線２８とも接しており、配線２８と導通する。   The terminal 13 is a bump electrode such as a solder bump, a stud bump, or a plating bump, and has a protruding shape protruding outward from the terminal surface 14 of the substrate 20. The terminal 13 protrudes from the dielectric layer 22 in the normal direction of the terminal surface 14. The terminal 13 is formed in contact with the wiring 21 and is electrically connected to the wiring 21. Further, the terminal 13 is also in contact with the wiring 28 provided on the wiring surface 11 of the wiring substrate 7, and is electrically connected to the wiring 28.

誘電体層２２は、端子１３を介した配線２１と配線２８との電気的な接続部２９を避けて、形成されている。また、誘電体層２２は、撮像素子２の端子面１４上の配線２１と、配線基板７の配線面１１上の配線２８とのうち、互いに対応関係になり配線間の短絡を防止するように設けられている。以下、詳しく説明する。   The dielectric layer 22 is formed so as to avoid the electrical connection portion 29 between the wiring 21 and the wiring 28 via the terminal 13. In addition, the dielectric layer 22 has a corresponding relationship between the wiring 21 on the terminal surface 14 of the imaging element 2 and the wiring 28 on the wiring surface 11 of the wiring board 7 so as to prevent a short circuit between the wirings. Is provided. This will be described in detail below.

ここで、説明の便宜上、撮像素子２の端子面１４に設けられている複数の配線２１のうち１系統の配線を第１のチップ側配線、他の系統の配線を第２のチップ側配線という。同様に、配線基板７の配線面１１に設けられている複数の配線２８のうち１系統の配線を第１の基板側配線、他の系統の配線を基板側配線という。また、第１のチップ側配線が複数の端子１３のうちの１つを介して第１の基板側配線と電気的に接続され、第２のチップ側配線が複数の端子１３のうちの１つを介して第２の基板側配線と電気的に接続されているものとする。   Here, for convenience of explanation, one of the plurality of wirings 21 provided on the terminal surface 14 of the image sensor 2 is referred to as a first chip side wiring, and the other system wiring is referred to as a second chip side wiring. . Similarly, among a plurality of wirings 28 provided on the wiring surface 11 of the wiring substrate 7, one system wiring is referred to as a first substrate side wiring, and the other system wiring is referred to as a substrate side wiring. In addition, the first chip side wiring is electrically connected to the first substrate side wiring through one of the plurality of terminals 13, and the second chip side wiring is one of the plurality of terminals 13. It is assumed that it is electrically connected to the second substrate side wiring via

誘電体層２２は、端子面１４を平面視した状態において、第１のチップ側配線と第１の基板側配線とが重なり合う領域（例えば、図３の接続部２９）には形成されていない。また、誘電体層２２は、平面視した端子面１４のうち少なくとも、第１のチップ側配線と、その対応関係にない第２の基板側配線とが重なり合う領域に設けられる。同様に、端子面１４を平面視した状態において、第２のチップ側配線と第１の基板側配線とが重なり合う場合には、その重なり合う領域にも誘電体層２２が設けられる。   The dielectric layer 22 is not formed in a region where the first chip-side wiring and the first substrate-side wiring overlap in the state where the terminal surface 14 is viewed in plan (for example, the connection portion 29 in FIG. 3). In addition, the dielectric layer 22 is provided in a region where at least the first chip-side wiring and the second substrate-side wiring not corresponding to each other overlap on the terminal surface 14 in plan view. Similarly, when the second chip side wiring and the first substrate side wiring overlap in a state where the terminal surface 14 is viewed in plan, the dielectric layer 22 is also provided in the overlapping region.

換言すると、図２に示した誘電体層２２の非形成領域２４は、端子面１４を平面視した場合に、撮像素子２の配線２１のうちの第１の配線と、配線基板７の配線２８のうち第１の配線と対応関係にない第２の配線とが重なり合わない領域を含んで（介して）、端子１３の位置から基板２０のエッジの位置まで連続している。   In other words, the non-formation region 24 of the dielectric layer 22 shown in FIG. 2 has the first wiring of the wiring 21 of the imaging element 2 and the wiring 28 of the wiring board 7 when the terminal surface 14 is viewed in plan. Including the region where the first wiring and the second wiring not corresponding to each other are not overlapped (continuous) from the position of the terminal 13 to the position of the edge of the substrate 20.

このように、撮像素子２は、電気信号が供給される第１の導体（配線２１および端子１３）を有し、配線基板７は、第１の導体と電気的に接続される第２の導体（配線２８の１つ）と、第１の導体と絶縁とされる第３の導体（他の配線２８）とを有しており、平面視した端子面１４のうち第１の導体と第３の導体とが重なり合う領域には、誘電体層２２が形成されており、誘電体層２２の非形成領域２４は、第１の導体と第２の導体とが重なり合う領域から基板２０のエッジ２０ａまで連続している。   Thus, the image pickup device 2 has the first conductor (the wiring 21 and the terminal 13) to which an electric signal is supplied, and the wiring board 7 is the second conductor that is electrically connected to the first conductor. (One of the wirings 28) and a third conductor (another wiring 28) that is insulated from the first conductor, and the first conductor and the third of the terminal surface 14 in plan view. A dielectric layer 22 is formed in a region where the first conductor and the second conductor overlap, and a non-formation region 24 of the dielectric layer 22 extends from a region where the first conductor and the second conductor overlap to the edge 20a of the substrate 20. It is continuous.

以上のような構成の撮像素子２は、以下のような方法で配線基板７に実装される。まず、配線基板７の配線面１１上に流動性を有する絶縁性の樹脂（ＮＣＰ；Ｎｏｎ−ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）を塗布する。そして、撮像素子２の保護基板２６側をフリップチップホルダー等で保持し、撮像素子２の端子１３と配線基板７の配線２８とを位置合わせしながら、撮像素子２の端子面１４を配線基板７の配線面１１に向けて、撮像素子２を配線基板７に押し付ける。そして、端子１３と配線２８とが接触した状態を維持しつつＮＣＰを硬化させて、撮像素子２を配線基板７と接着する。これにより、撮像素子２の端子１３が配線基板７の配線２８と電気的に接続されるとともに、撮像素子２が配線基板７に固定される。なお、硬化したＮＰＣは、図３の接着層３０になる。   The image sensor 2 having the above configuration is mounted on the wiring board 7 by the following method. First, a fluid insulating resin (NCP; Non-conductive Paste) is applied on the wiring surface 11 of the wiring substrate 7. The protective substrate 26 side of the image pickup device 2 is held by a flip chip holder or the like, and the terminal surface 14 of the image pickup device 2 is placed on the wiring substrate 7 while aligning the terminal 13 of the image pickup device 2 and the wiring 28 of the wiring substrate 7. The image sensor 2 is pressed against the wiring board 7 toward the wiring surface 11. Then, the NCP is cured while maintaining the state where the terminal 13 and the wiring 28 are in contact with each other, and the imaging element 2 is bonded to the wiring board 7. Thereby, the terminal 13 of the image pickup device 2 is electrically connected to the wiring 28 of the wiring board 7 and the image pickup device 2 is fixed to the wiring board 7. The cured NPC becomes the adhesive layer 30 in FIG.

ところで、一般的な半導体装置において、端子面上の配線を覆うオーバーコート層は、端子を環状に囲む隔壁状に形成され、端子は、オーバーコート層の開口の内側に配置される。この開口は、端子との位置誤差などを考慮して、開口の内縁と端子の外縁との間にギャップを有するように形成される。このような半導体装置を配線基板に接着剤で実装すると、開口の内縁と端子の外縁との間にギャップに雰囲気ガスが取り残されてボイドとなりやすい。このようなボイドは、温度変化に伴う膨張伸縮により、電気的接続の破断、半導体装置と配線基板との接合部の破壊などの不具合の原因になりうる。   By the way, in a general semiconductor device, the overcoat layer covering the wiring on the terminal surface is formed in a partition shape surrounding the terminal in an annular shape, and the terminal is disposed inside the opening of the overcoat layer. This opening is formed so as to have a gap between the inner edge of the opening and the outer edge of the terminal in consideration of a positional error with the terminal. When such a semiconductor device is mounted on a wiring board with an adhesive, an atmospheric gas is left in the gap between the inner edge of the opening and the outer edge of the terminal, and a void is likely to occur. Such voids can cause problems such as breakage of electrical connection and breakage of the joint between the semiconductor device and the wiring board due to expansion and contraction accompanying temperature change.

本実施形態の撮像素子２（半導体装置）は、配線基板７に実装される際に、撮像素子２と配線基板７との間のガスが誘電体層２２の非形成領域２４を通って基板２０のエッジ２０ａ（図３参照）から外部へ排出されやすい。その結果、実装後の撮像素子２と配線基板７との間のボイドが低減され、ボイドの膨張収縮による破損等の発生が抑制される。また、ボイドが低減されることにより、撮像素子２側と配線基板７側との接着面積が確保され、撮像素子２を配線基板７と接着力が高くなる。このように、本実施形態に係る撮像素子２は、実装不良の発生を抑制できる。   When the imaging device 2 (semiconductor device) of the present embodiment is mounted on the wiring substrate 7, the gas between the imaging device 2 and the wiring substrate 7 passes through the non-formation region 24 of the dielectric layer 22 and is formed on the substrate 20. It is easy to be discharged to the outside from the edge 20a (see FIG. 3). As a result, voids between the image pickup device 2 after mounting and the wiring board 7 are reduced, and the occurrence of breakage due to expansion and contraction of the voids is suppressed. Further, by reducing the voids, a bonding area between the imaging element 2 side and the wiring board 7 side is secured, and the adhesive force of the imaging element 2 to the wiring board 7 is increased. Thus, the imaging device 2 according to the present embodiment can suppress the occurrence of mounting defects.

本実施形態において、誘電体層２２の非形成領域２４は、基板２０の４辺のうち端子１３に最も近い辺の少なくとも一部を含んでいる。そのため、撮像素子２を配線基板７に実装する際に、撮像素子２と配線基板７との間から雰囲気ガスが外部へ逃げやすく、ボイドが格段に低減される。   In the present embodiment, the non-formation region 24 of the dielectric layer 22 includes at least a part of the side closest to the terminal 13 among the four sides of the substrate 20. Therefore, when mounting the image pickup device 2 on the wiring board 7, the atmospheric gas easily escapes from between the image pickup device 2 and the wiring board 7, and the voids are significantly reduced.

本実施形態において、誘電体層２２は、基板２０を貫通して配線２１に導通する導電部２３の少なくとも一部を覆っている。そのため、撮像素子２は、配線基板７側との短絡を防止しながら、撮像素子２と配線基板７との間のボイドを低減できる。   In the present embodiment, the dielectric layer 22 covers at least a part of the conductive portion 23 that penetrates the substrate 20 and is electrically connected to the wiring 21. Therefore, the imaging element 2 can reduce voids between the imaging element 2 and the wiring board 7 while preventing a short circuit with the wiring board 7 side.

また、上述のような撮像素子２を備えた本実施形態の撮像モジュール３は、撮像素子２の実装不良が抑制され、耐久性を向上するとともに、撮像素子２の実装不良に起因する動作不良を抑制できる。   Moreover, the imaging module 3 of the present embodiment including the imaging device 2 as described above suppresses mounting defects of the imaging device 2, improves durability, and prevents malfunctions due to mounting failures of the imaging device 2. Can be suppressed.

＜変形例＞
次に、変形例について説明する。変形例において上記の実施形態と共通する構成については、同じ符号を付してその説明を簡略化あるいは省略する。 <Modification>
Next, a modified example will be described. In the modification, the same components as those in the above embodiment are denoted by the same reference numerals, and the description thereof is simplified or omitted.

図４は、第１変形例に係る半導体装置２を示す図である。図４の半導体装置２は、端子面１４に形成されたアライメントマーク３１を備える。このアライメントマーク３１は、誘電体層２２の一部であり、誘電体層２２のうち配線２１を覆う部分と同じ材料で形成されている。ここでは、基板２０が矩形状であり、アライメントマーク３１は、基板２０の第１辺２０ｂに平行な辺３１ｂと、基板２０の第２辺２０ｃに平行な辺３１ｃとを有する。   FIG. 4 is a diagram illustrating the semiconductor device 2 according to the first modification. The semiconductor device 2 of FIG. 4 includes an alignment mark 31 formed on the terminal surface 14. The alignment mark 31 is a part of the dielectric layer 22 and is formed of the same material as the portion of the dielectric layer 22 that covers the wiring 21. Here, the substrate 20 has a rectangular shape, and the alignment mark 31 has a side 31 b parallel to the first side 20 b of the substrate 20 and a side 31 c parallel to the second side 20 c of the substrate 20.

このような誘電体層２２は、例えば、以下のように形成される。誘電体層２２を形成するには、端子面１４に端子１３および配線２１が形成された状態で、端子１３および配線２１を覆う絶縁膜を、端子面１４にベタ状に形成する。そして、この絶縁膜のうち、配線２１を覆う部分とアライメントマーク３１に相当する部分とを残し、かつ非形成領域２４の部分を除去するように、この絶縁膜をパターニングする。このようにして、アライメントマーク３１は、誘電体層２２のうち配線２１を覆う部分と同じプロセスで一括して形成される。   Such a dielectric layer 22 is formed as follows, for example. In order to form the dielectric layer 22, an insulating film covering the terminal 13 and the wiring 21 is formed in a solid shape on the terminal surface 14 in a state where the terminal 13 and the wiring 21 are formed on the terminal surface 14. Then, this insulating film is patterned so as to leave a portion covering the wiring 21 and a portion corresponding to the alignment mark 31 in this insulating film and removing a portion of the non-formation region 24. In this way, the alignment mark 31 is collectively formed by the same process as that of the portion of the dielectric layer 22 that covers the wiring 21.

次に、アライメントマーク３１の利用例を説明する。図５は、アライメントマーク３１の利用例を説明するための説明図である。図５には、半導体装置２の製造に利用されるウエハーＷを示す図と、ウエハーＷの一部を拡大した図とを示した。   Next, a usage example of the alignment mark 31 will be described. FIG. 5 is an explanatory diagram for explaining an example of use of the alignment mark 31. FIG. 5 shows a view of the wafer W used for manufacturing the semiconductor device 2 and an enlarged view of a part of the wafer W.

上述のような半導体装置２は、ウエハーＷの複数のチップ領域Ｗ１のそれぞれに、半導体装置２を構成する導体、半導体、及び絶縁体を形成した後、チップ領域Ｗ１をダイシング（個片化）することで、製造される。アライメントマーク３１は、例えば、ウエハーＷをダイシングする際に、半導体装置２のエッジを示す識別マークとして機能し、ダイシングカッターとウエハーＷとの位置合わせなどに利用される。このような半導体装置２は、誘電体層２２のうち配線２１を覆う部分を形成するプロセスでアライメントマーク３１を形成可能であるので、アライメントマークを別のプロセスで形成するよりも生産性が高い。   In the semiconductor device 2 as described above, a conductor, a semiconductor, and an insulator constituting the semiconductor device 2 are formed in each of the plurality of chip regions W1 of the wafer W, and then the chip region W1 is diced (divided into individual pieces). With that, it is manufactured. For example, when the wafer W is diced, the alignment mark 31 functions as an identification mark indicating the edge of the semiconductor device 2 and is used for alignment between the dicing cutter and the wafer W. In such a semiconductor device 2, the alignment mark 31 can be formed by a process of forming a portion of the dielectric layer 22 that covers the wiring 21, so that the productivity is higher than that of forming the alignment mark by another process.

図６（Ａ）は、第２変形例に係る半導体装置２を示す図である。本変形例において、端子面１４には６つの端子１３が設けられている。誘電体層２２は、４つの端子１３に対応する４つの配線２１を覆う部分２２ａと、１つの端子１３に対応する配線２１を覆う部分２２ｂと、他の１つの端子１３に対応する配線２１を覆う部分２２ｃとを含む。部分２２ａ、部分２２ｂ、及び部分２２ｃは、それぞれ、非形成領域２４を介して他の部分から分離されている。ここでは、非形成領域２４は、基板２０の４辺のうちの３辺と連続している。   FIG. 6A is a diagram illustrating a semiconductor device 2 according to a second modification. In the present modification, six terminals 13 are provided on the terminal surface 14. The dielectric layer 22 includes a portion 22 a covering the four wires 21 corresponding to the four terminals 13, a portion 22 b covering the wires 21 corresponding to one terminal 13, and a wire 21 corresponding to the other one terminal 13. And a covering portion 22c. The portion 22a, the portion 22b, and the portion 22c are each separated from other portions via the non-forming region 24. Here, the non-formation region 24 is continuous with three of the four sides of the substrate 20.

図６（Ｂ）は、第３変形例に係る半導体装置２を示す図である。本変形例において、端子面１４には８つの端子１３が設けられている。誘電体層２２は、４つの端子１３に対応する４つの配線２１を覆う部分２２ｄと、他の４つの端子１３に対応する配線２１を覆う部分２２ｅとを含む。部分２２ｅは、非形成領域２４を介して部分２２ｄから分離されている。ここでは、非形成領域２４は、基板２０の４辺のうちの２辺と連続している。   FIG. 6B is a diagram illustrating a semiconductor device 2 according to a third modification. In this modification, eight terminals 13 are provided on the terminal surface 14. The dielectric layer 22 includes a portion 22 d that covers the four wirings 21 corresponding to the four terminals 13 and a portion 22 e that covers the wirings 21 corresponding to the other four terminals 13. The portion 22e is separated from the portion 22d through the non-forming region 24. Here, the non-formation region 24 is continuous with two of the four sides of the substrate 20.

図６（ｃ）は、第４変形例に係る半導体装置２を示す図である。本変形例において、端子面１４には４つの端子１３が設けられている。誘電体層２２は、端子１３ごとに島状に形成された部分を４つ含んでいる。これら４つの部分は、非形成領域２４を介して互いに離れている。ここでは、非形成領域２４は、基板２０の４辺と連続している。   FIG. 6C is a diagram illustrating a semiconductor device 2 according to a fourth modification. In this modification, four terminals 13 are provided on the terminal surface 14. The dielectric layer 22 includes four portions formed in an island shape for each terminal 13. These four portions are separated from each other via the non-forming region 24. Here, the non-formation region 24 is continuous with the four sides of the substrate 20.

図６（ａ）〜（ｃ）を参照して説明したように、本実施形態に係る半導体装置２において、端子１３の数に限定はなく、複数の端子１３の配置パターンについても限定はない。また、非形成領域２４は、複数の端子１３のうち少なくとも１つの端子１３の位置から基板２０のエッジ２０ａの位置まで連続してればよく、例えば、いずれかの端子１３については、その周囲を環状に囲むように誘電体層２２が形成されていてもよい。また、誘電体層２２は、２以上の配線２１にまたがって形成される部分を含んでいてもよいし、１つの配線２１のみを覆う部分を含んでいてもよい。基板２０が矩形状である場合に、非形成領域２４は、基板２０の１辺のみと連続していてもよいし、２辺、３辺、あるいは４辺のいずれと連続していてもよい。また、誘電体層２２が複数の島状の部分を含む場合に、端子面１４を平面視した各部分の平面形状に限定はなく、多角形、楕円形、自由曲線に囲まれる形状、直線および曲線に囲まれる形状のいずれでもよい。また、複数の島状の部分の平面形状が互いに異なっていてもよいし、複数の島状の部分のうち２以上が同一の平面形状であってもよい。   As described with reference to FIGS. 6A to 6C, in the semiconductor device 2 according to the present embodiment, the number of terminals 13 is not limited, and the arrangement pattern of the plurality of terminals 13 is not limited. Moreover, the non-formation area | region 24 should just continue from the position of the at least 1 terminal 13 among the some terminals 13 to the position of the edge 20a of the board | substrate 20, for example, the periphery of one of the terminals 13 is the circumference | surroundings. The dielectric layer 22 may be formed so as to surround the ring. In addition, the dielectric layer 22 may include a part formed over two or more wirings 21 or may include a part that covers only one wiring 21. When the substrate 20 is rectangular, the non-formation region 24 may be continuous with only one side of the substrate 20, or may be continuous with any of the two sides, the three sides, or the four sides. In addition, when the dielectric layer 22 includes a plurality of island-shaped portions, the planar shape of each portion when the terminal surface 14 is viewed in plan is not limited, and a polygon, an ellipse, a shape surrounded by a free curve, a straight line, and Any of the shapes surrounded by the curve may be used. Further, the planar shapes of the plurality of island-shaped portions may be different from each other, and two or more of the plurality of island-shaped portions may have the same planar shape.

なお、本発明の技術範囲は、上記の実施形態あるいは変形例に限定されるものではない。例えば、上記の実施形態あるいは変形例で説明した要素の１つ以上は、省略されることがある。また、上記の実施形態あるいは変形例で説明した要素は、適宜組み合わせることができる。   The technical scope of the present invention is not limited to the above-described embodiment or modification. For example, one or more of the elements described in the above embodiments or modifications may be omitted. In addition, the elements described in the above embodiments or modifications can be combined as appropriate.

上述の実施形態において半導体装置２は、撮像素子であるものとして説明したが、撮像素子以外の半導体装置、例えば太陽光発電装置などであってもよい。また、撮像モジュール３は、内視鏡以外の各種光学装置にも適用できる。また、半導体装置２は、基板２０を貫通する導電部２３が設けられていなくても構わない。例えば、基板２０の端子面１４の所定位置に半導体を利用した回路部品が形成されており、配線２１は、この回路部品を含む処理部と端子１３とを電気的に接続していてもよい。   In the above-described embodiment, the semiconductor device 2 has been described as an image sensor, but may be a semiconductor device other than the image sensor, such as a solar power generation device. The imaging module 3 can also be applied to various optical devices other than the endoscope. Further, the semiconductor device 2 may not include the conductive portion 23 that penetrates the substrate 20. For example, a circuit component using a semiconductor is formed at a predetermined position on the terminal surface 14 of the substrate 20, and the wiring 21 may electrically connect the processing unit including the circuit component and the terminal 13.

１ 光学装置、２ 撮像素子（半導体装置）、３ 撮像モジュール、７ 配線基板、１２ 機能面（基板の他方の面）、１３ 端子、１４ 端子面（基板の一方の面）、２０ 基板、２０ａ エッジ、２０ｂ 第１辺、２０ｃ 第２辺、２１ 配線、２２ 誘電体層、２３ 導電部、２４ 非形成領域、２８ 配線基板の配線、３１ アライメントマーク DESCRIPTION OF SYMBOLS 1 Optical apparatus, 2 Imaging element (semiconductor device), 3 Imaging module, 7 Wiring board, 12 Functional surface (The other surface of a board | substrate), 13 Terminal, 14 Terminal surface (One surface of a board | substrate), 20 Substrate, 20a Edge 20b 1st side, 20c 2nd side, 21 wiring, 22 dielectric layer, 23 conductive part, 24 non-formation area | region, 28 wiring of wiring board, 31 alignment mark

Claims (7)

デバイスに実装される半導体装置であって、
基板と、
前記基板の一方の面に形成され、前記デバイスに接続される端子と、
前記基板の前記一方の面に形成され、前記端子に導通する配線と、
前記配線の少なくとも一部を覆う誘電体層と、
前記基板の他方の面側から入射する光を電力に変換する光電変換層と、を備え、
前記基板の一方の面は、前記誘電体層が形成されていない非形成領域を有し、
前記非形成領域は、前記端子の位置から前記基板のエッジの位置まで連続しており、
前記基板の一方の面に前記端子を含む複数の端子が配置され、
前記光電変換層は、前記複数の端子のいずれかと電気的に接続されている半導体装置。 A semiconductor device mounted on a device,
A substrate,
A terminal formed on one side of the substrate and connected to the device;
A wiring formed on the one surface of the substrate and conducting to the terminal;
A dielectric layer covering at least a part of the wiring ;
A photoelectric conversion layer that converts light incident from the other surface side of the substrate into electric power ,
One surface of the substrate has a non-formed region where the dielectric layer is not formed,
The non-formation region is continuous from the position of the terminal to the position of the edge of the substrate ,
A plurality of terminals including the terminals are arranged on one surface of the substrate,
The photoelectric conversion layer is a semiconductor device electrically connected to any one of the plurality of terminals . 前記基板は矩形状であり、
前記非形成領域は、前記基板の４辺のうち前記端子に最も近い辺の少なくとも一部を含む
請求項１に記載の半導体装置。 The substrate is rectangular,
The semiconductor device according to claim 1, wherein the non-formation region includes at least a part of a side closest to the terminal among the four sides of the substrate. 前記基板を貫通して前記配線に導通する導電部を備え、
前記誘電体層は、前記導電部の少なくとも一部を覆っている
請求項１または２に記載の半導体装置。 A conductive portion that penetrates the substrate and is electrically connected to the wiring;
The semiconductor device according to claim 1, wherein the dielectric layer covers at least a part of the conductive portion. 前記誘電体層の一部は、前記基板のエッジを示すアライメントマークとして形成されている
請求項１〜３のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein a part of the dielectric layer is formed as an alignment mark indicating an edge of the substrate. 前記基板は、互いに直交する第１辺および第２辺を含む矩形状であり、
前記アライメントマークは、前記第１辺に平行な辺および前記第２辺に平行な辺を有する
請求項４に記載の半導体装置。 The substrate has a rectangular shape including a first side and a second side orthogonal to each other,
The semiconductor device according to claim 4, wherein the alignment mark has a side parallel to the first side and a side parallel to the second side. 請求項１〜５のいずれか一項に記載の半導体装置と、
前記半導体装置の前記一方の面に形成された接着層と、
前記接着層を介して前記半導体装置が接着され、前記半導体装置の端子と接続された第２の配線を有する配線基板と、を備える撮像モジュール。 A semiconductor device according to any one of claims 1 to 5 ;
An adhesive layer formed on the one surface of the semiconductor device;
An imaging module comprising: a wiring board having a second wiring connected to a terminal of the semiconductor device, to which the semiconductor device is bonded via the adhesive layer. 前記半導体装置の前記非形成領域は、平面視した前記基板の一方の面のうち前記半導体装置の端子が前記配線基板の接続箇所と重なる位置に配置され、平面視した前記基板の一方の面のうち前記半導体装置の配線が前記配線基板の前記第２の配線と重ならない位置に配置されている
請求項６に記載の撮像モジュール。 The non-formation region of the semiconductor device is disposed at a position where a terminal of the semiconductor device overlaps with a connection portion of the wiring board in one surface of the substrate in plan view, and is on one surface of the substrate in plan view. Of these, the wiring of the semiconductor device is arranged at a position where it does not overlap the second wiring of the wiring board.
The imaging module according to claim 6 .
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