JP6327747B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a high breakdown voltage power IC, and more particularly to a lateral MOS field effect transistor (lateral MOSFET).

  Conventionally, a technique for increasing the breakdown voltage and current density of a lateral IGBT (Insulated Gate Bipolar Transistor) has been known (see, for example, Patent Document 1 and Patent Document 2).

  Conventionally, a lateral MOSFET has a structure in which the impurity concentration of the drift region is increased in the lateral direction from the p base region side toward the drain region (see, for example, Patent Document 3).

JP-A-6-318714 JP 2009-246037 A JP-A-4-309234

  In recent years, high-breakdown-voltage power ICs using SOI substrates have been actively developed because of their small device isolation region and parasitic transistor-free characteristics. In the development of a high voltage power IC, it is essential to improve the performance of a high voltage output device that directly drives a load from the viewpoint of output characteristics and chip size reduction. Therefore, a lateral IGBT (Insulated Gate Bipolar Transistor) that can obtain a high current capacity per unit area (hereinafter referred to as current density) by conductivity modulation is mainly used as an output device. Technologies for increasing the withstand voltage and increasing the current density of the lateral IGBT have been developed. Examples thereof are disclosed in Patent Document 1 and Patent Document 2.

  However, in the IGBT, the diode formed in the collector region does not flow current in the region up to the built-in voltage (about 1V) when a voltage is applied in the forward direction. There was a disadvantage that the loss was large compared to the MOSFET. Corresponding to this, a lateral MOSFET having a high withstand voltage and a high current density (low on-resistance) has been proposed. An example is disclosed in Patent Document 3.

  The lateral MOSFET of Patent Document 3 has a configuration as shown in FIG. 9, in which a thin n-type semiconductor substrate 1 is formed on a buried oxide film 10, and the buried oxide film 10 is formed on a support substrate 9. ing. A p base region 2 is selectively formed in a part of the semiconductor substrate 1, and a source region 8 is formed in a part of the p base region 2. A drain region 3 is selectively formed in a part of the n-type substrate 1 where the p base region 2 is not formed. A gate electrode 12 is provided on the surface of the p base region 2 sandwiched between the semiconductor substrate 1 and the source region 8 via a gate oxide film 15. A source electrode 11 that contacts the source region 8 and a drain electrode 13 that contacts the drain region 3 are also provided.

  The feature of this lateral MOSFET is that the impurity concentration of the drift region 4 between the p base region 2 and the drain region 3 is constant in a general lateral MOSFET, whereas the impurity concentration of the drift region 4 is changed to the p base region 2 side. That is, it is increased in the lateral direction from the drain toward the drain region 3. As a result, the lateral electric field distribution in the drift region 4 can be made uniform to increase the breakdown voltage, and the total impurity concentration becomes higher than that of a general structure, so that a high current density can be obtained.

  However, in the lateral MOSFET shown in FIG. 9, it is necessary to make the thickness of the semiconductor substrate 1 (or the drift region 4) very thin in order to suppress the avalanche due to the vertical electric field. For example, in order to obtain a withstand voltage of 600 V, when the buried oxide film 10 has a thickness of 3.5 μm, the thickness of the semiconductor substrate 1 needs to be about 0.5 μm or less. In a high voltage power IC manufacturing process including diffusion at a high temperature for a long time and an oxidation process, variations in the thickness of the semiconductor substrate 1 are likely to occur, and this variation greatly affects the breakdown voltage characteristics. Further, the impurity concentration distribution in the drift region 4 needs to be determined in relation to the thickness of the oxide film 17 on the drift region 4 and the arrangement of the gate electrode 12 or the source electrode 11, and the influence on the breakdown voltage due to these manufacturing variations. Is also big. As a result, when an element is designed so as to obtain a desired breakdown voltage within the range of manufacturing variations, it is necessary to reduce the impurity concentration of the drift region 4 and to increase the lateral distance, resulting in a problem that the current density is lowered.

In order to solve the above-described problems, a semiconductor device of the present invention includes, for example, a semiconductor substrate, a first diffusion region of a first conductivity type selectively formed on a surface layer of one main surface of the semiconductor substrate. The second diffusion region of the second conductivity type selectively formed in a portion different from the first diffusion region of the surface layer, and selectively between the first diffusion region and the second diffusion region. A third diffusion region of the first conductivity type formed, wherein the first diffusion region and the second diffusion region are arranged in a plane direction of the main surface of the semiconductor substrate and operate in a unipolar manner. In the lateral semiconductor device, the third diffusion region includes a first layer and a second layer positioned between the first layer and the semiconductor substrate, and the second layer includes Impurity concentration is lower than the first layer, and the first layer and the second layer on the second diffusion region side are impure. Difference in density, the rather larger than the difference in the impurity concentration of the first diffusion region side of said first layer and said second layer, said first diffusion region, said second diffusion region, and said third diffusion region, Each of them functions as a drain region, a base region, and a drift region of the lateral semiconductor device .

  According to the present invention, the trade-off relationship between the breakdown voltage and the current density of the lateral MOSFET becomes good, and thus it is possible to reduce the loss and reduce the chip size of the high breakdown voltage power IC.

1 is a cross-sectional structure diagram of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the cross-sectional structure common to the prior art and this invention used as the object of the simulation calculation about the semiconductor device of a prior art, and the semiconductor device of this invention. It is a figure which shows the drift region impurity concentration of a prior art in the simulation calculation about the semiconductor device of a prior art, and the semiconductor device of this invention. It is a figure which shows the drift region impurity concentration of this invention in the simulation calculation about the semiconductor device of a prior art, and the semiconductor device of this invention. It is a simulation calculation result about the semiconductor device of a prior art, and the semiconductor device of this invention, Comprising: It is a figure which shows the pressure | voltage resistant calculation result of a prior art and this invention. It is a simulation calculation result about the semiconductor device of a prior art, and the semiconductor device of this invention, Comprising: It is a figure which shows a prior art and the ON-state voltage current characteristic calculation result of this invention. 1 is a cross-sectional structure diagram of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows impurity concentration distribution of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 6 is a cross-sectional structure diagram of a semiconductor device according to a second embodiment of the present invention. It is a figure which shows the impurity concentration distribution of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 6 is a cross-sectional structure diagram of a semiconductor device according to a third embodiment of the present invention. It is a figure which shows the impurity concentration distribution of the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 6 is a cross-sectional structure diagram of a semiconductor device according to a fourth embodiment of the present invention. It is a figure which shows the impurity concentration distribution of the semiconductor device which concerns on the 4th Embodiment of this invention. FIG. 6 is a cross-sectional structure diagram of a semiconductor device according to a fifth embodiment of the present invention. It is a figure which shows the impurity concentration distribution of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional structure drawing of the semiconductor device which concerns on the 6th Embodiment of this invention. It is a figure which shows the impurity concentration distribution of the semiconductor device which concerns on the 6th Embodiment of this invention. It is sectional structure drawing of the semiconductor device by a prior art. It is sectional structure drawing of the semiconductor device by a prior art. It is sectional structure drawing of the semiconductor device by a prior art.

  The lateral MOSFET of the present invention has the main feature that an impurity concentration gradient is formed in the vertical direction and the horizontal direction of the drift region in order to improve the trade-off between breakdown voltage and current density.

  In the lateral MOSFET of the present invention, the impurity concentration on the element surface side of the drift region is set higher than the impurity concentration on the element bottom side, and the impurity concentration on the element bottom side is laterally directed from the source region to the drain region. increase. By increasing the impurity concentration on the element surface, the on-resistance is reduced, and by setting the source-side impurity concentration on the element bottom surface to be low, the depletion layer easily spreads to the drain side, and a high breakdown voltage can be achieved.

  In the lateral MOSFET structure of the present invention, the semiconductor substrate thickness of the drift region does not need to be as thin as the structure of FIG. 9. For example, in order to obtain a withstand voltage of 600 V, the thickness of the buried oxide film is 3.5 μm. The thickness of the semiconductor substrate may be about 5 μm. Therefore, compared with the structure of FIG. 9, it is difficult to be affected by manufacturing variations, and it is easy to obtain a semiconductor device having a high breakdown voltage and a high current density.

  Hereinafter, an example of an embodiment of a semiconductor device of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a partial cross-sectional structure diagram of an example of a semiconductor device (MOSFET) according to Example 1 which is the first embodiment of the present invention. In FIG. 1, a p-type base region 2 is selectively formed in a part of an n-type semiconductor substrate 1, and an n-type source region 8 is formed in a part of the surface layer of the p-type base region 2. A p-type contact region 7 is formed adjacent to the source region 8. An n-type drain region 3 is selectively formed on the exposed surface of the n-type substrate 1 where the p-type base region 2 is not formed. A gate electrode 12 connected to the G terminal via the gate oxide film 15 is provided on the surface of the channel region 14 in the surface layer of the p-type base region 2. In addition, a source electrode 11 that is in common contact with the surfaces of the n-type source region 8 and the p-type contact region 7 is provided, and a drain electrode 13 is provided on the surface of the n-type drain region 3, and is connected to the S terminal and the D terminal, respectively. Is done. A first layer 5 and a second layer 6 are formed in the drift region 4 between the p-type base region 2 and the n-type drain region 3, and the impurity concentration of the second layer 6 is the impurity concentration of the first layer 5. The difference in impurity concentration between the first layer 5 and the second layer 6 on the p-type base region 2 side is lower than the difference in impurity concentration between the first layer 5 and the second layer 6 on the n-type drain region 3 side. It is characterized by being large. In the MOSFET of the present invention, the on-resistance is reduced by increasing the impurity concentration of the first layer 5 disposed on the element surface side, and the source-side impurity concentration of the second layer 6 on the element bottom side is set low. As a result, the depletion layer easily spreads and a high breakdown voltage can be achieved.

  FIGS. 2a, 2b, 2c, and 2e are obtained by calculating and confirming withstand voltage and current performance of a conventional general MOSFET (structure 1) and a MOSFET of the present invention (structure 2) by device simulation. FIG. 2 a shows a cross-sectional structure, which is common to structure 1 and structure 2. FIG. 2b shows the drift region impurity concentration of structure 1, and shows the relationship between the lateral position and the impurity concentration between A-A 'and B-B' in FIG. 2a. FIG. 2c shows the drift region impurity concentration of structure 2 as in FIG. 2b. 2b and 2c, in structure 1, the impurity concentration in the drift region is almost constant, whereas in structure 2, the impurity concentration of the first layer (between AA ′) is the second layer (between BB ′). The impurity concentration difference D1 between the first layer and the second layer on the source region side is set to be larger than the impurity concentration difference D2 between the first layer and the second layer on the drain region side. . Further, the first layer impurity concentration of structure 2 is higher than the impurity concentration of structure 1. FIG. 2d shows the breakdown voltage calculation results of Structure 1 and Structure 2, and FIG. 2e shows the on-state voltage-current characteristic calculation results of Structure 1 and Structure 2. FIG. The calculation conditions such as channel width and gate voltage are the same. 2d and 2e, it can be seen that the NMOSFET having the structure 2 can obtain a higher current density than the structure 1 having the same breakdown voltage.

  Note that, in the lateral semiconductor device, there are those disclosed in Patent Document 1 and Patent Document 2 as an invention in which the impurity concentration of the drift region has a gradient in the vertical direction.

  FIG. 10 shows a structure disclosed in Patent Document 1, and an n-type semiconductor substrate 40 is formed on a support substrate 9 with a buried oxide film 10 interposed therebetween. A p-type base region 2 and an n-type base region (buffer region) 16 are formed on the semiconductor substrate 40 at a predetermined distance away to reach the buried oxide film 10, and an n-type source region is formed in the p-type base region 2. 8, a p-type drain region 18 is formed in the n-type base region 16. A surface portion of the p-type base region 2 sandwiched between the n-type source region 8 and the semiconductor substrate 40 is used as a channel region, and a gate electrode 12 is formed thereon via a gate oxide film. The source electrode 11 is formed to contact the n-type source region 8 and the p-type base region 2 simultaneously, and the drain electrode 13 is formed to contact the p-type drain region 18. An insulating protective film 17 is formed between the electrodes 11 and 13. An n-type impurity layer 41 is diffused from the entire surface of the semiconductor substrate 40, and a vertical concentration gradient is given in the semiconductor substrate 40. As a result, the electric field concentration at the bottom of the semiconductor substrate 40 is alleviated and a high breakdown voltage is obtained. Here, the structure of FIG. 10 does not have an impurity concentration gradient in the lateral direction, and is different from the structure of the present invention. FIG. 10 relates to a lateral IGBT operating in a bipolar manner, and it is not preferable to provide a region having a high impurity concentration in the semiconductor substrate 40 or the impurity layer 41. This is because the IGBT is characterized by activating the conductivity modulation of the drift region and obtaining a low on-resistance in the on-state. The conductivity modulation is activated in a region where the impurity concentration is low. Therefore, if a region having a high impurity concentration exists in a part of the drift region in the lateral direction, the on-resistance is remarkably deteriorated. On the other hand, the MOSFET of the present invention is a unipolar semiconductor device, and the lower the on-resistance, the higher the impurity concentration of the drift layer. Therefore, the structure of the present invention is characterized in that a region having a high impurity concentration is provided on the n drain region 3 side in the first layer 5 and the second layer 6 of the drift region 4.

  FIG. 11 shows a structure disclosed in Patent Document 2, which includes a support substrate 9, a buried oxide film 10 provided on the support substrate 9, and a semiconductor substrate 1 provided on the buried oxide film 10. Yes. The semiconductor substrate 1 includes an n-type source region 8, a p-type drain region 18, and an n-type drift region 4. The p-type base region 2 surrounds the n-type source region 8, and the n-type source region 8 and the drift region 4 are separated. A p-type contact region 7 is provided inside the p-type base region 2 on the surface of the semiconductor substrate 1. The n-type source region 8 and the p-type contact region 7 are in contact with the source electrode 11, and the p-type drain region 18 is in contact with the drain electrode 13. A surface portion of the p-type base region 2 separating the n-type source region 8 and the drift region 4 is used as a channel region, and a gate electrode 12 is formed thereon with a gate oxide film 14 interposed therebetween. An interlayer insulating film 17 is provided on the surface of the semiconductor substrate 1. The n-type buffer region 16 surrounds the p-type drain region 18 and separates the p-type drain region 18 and the drift region 4. The drift region 4 includes a first layer 41 and a second layer 40 extending in the lateral direction. One end of the drift region 4 is in contact with the p-type body region 2, and the other end is the n-type buffer region 16. Is in contact with The impurity concentration of the second layer 40 increases toward the p-type drain region 18 side. That is, the impurity concentration of the second layer 40 increases in the order of the ranges 41, 42, 43, 44, 45, 46, 47. Here, the impurity concentration of the second layer 40 is higher than the impurity concentration of the first layer 41 and is different from the structure of the present invention. Further, FIG. 11 relates to a lateral semiconductor device IGBT operating in a bipolar manner. For the same reason as in FIG. 10, it is not preferable to provide a region having a high impurity concentration in the first layer 41.

  FIG. 3A is a partial cross-sectional structure diagram of the semiconductor device according to the first embodiment as in FIG. 1, and FIG. 3B illustrates the impurity concentration distribution in the drift region 4 of the semiconductor device in FIG. 3A. That is, the relationship between the lateral position and the impurity concentration between A-A ′ of the first layer 5 and B-B ′ of the second layer 6 shown in FIG. As shown in FIG. 3b, the impurity concentration of the second layer 6 is lower than the impurity concentration of the first layer 5, and the difference D1 between the impurity concentration of the first layer 5 and the second layer 6 on the p-type base region 2 side is The impurity concentration difference D2 between the first layer 5 and the second layer 6 on the n-type drain region 3 side is larger.

  In the configuration of this embodiment, the impurity concentration of the first layer in the drift region may be constant or may have a lateral gradient.

  According to the present embodiment described above, the on-resistance is reduced by increasing the impurity concentration on the element surface, and the depletion layer is easily spread to the drain side by setting the source-side impurity concentration on the element bottom surface to be high. It is possible to increase the breakdown voltage. Further, the thickness of the semiconductor substrate in the drift region does not need to be as thin as the structure of FIG. 9. For example, in order to obtain a withstand voltage of 600 V, when the buried oxide film has a thickness of 3.5 μm, the thickness of the semiconductor substrate is Since it may be about 5 μm, it is possible to provide a semiconductor device having a high breakdown voltage and a high current density, which is less affected by manufacturing variations than the structure of FIG.

  FIG. 4A is a partial cross-sectional structure diagram of the semiconductor device according to Example 2 which is the second embodiment of the present invention. This structure is based on FIG. 3a and is characterized in that the impurity concentration of the first layer 5 has a lateral gradient. FIG. 4b shows the relationship between the lateral position and the impurity concentration between A-A 'of the first layer 5 and B-B' of the second layer 6 described in FIG. 4a. As shown in FIG. 4b, the impurity concentration increases from the p-type base region 2 side to the n-type drain region 3 side in both the first layer and the second layer. The impurity concentration of the second layer 6 is lower than the impurity concentration of the first layer 5, and the difference D1 between the impurity concentration of the first layer 5 on the p-type base region 2 side and the second layer 6 is on the n-type drain region 3 side. The difference in impurity concentration between the first layer 5 and the second layer 6 is greater than D2.

  In the configuration of this embodiment, the lateral impurity concentration distribution of the first layer or the second layer in the drift region may change continuously or discontinuously.

  According to the present embodiment described above, the on-resistance is reduced by increasing the impurity concentration on the element surface, and the depletion layer is easily spread to the drain side by setting the source-side impurity concentration on the element bottom surface to be high. It is possible to increase the breakdown voltage. Further, the thickness of the semiconductor substrate in the drift region does not need to be as thin as the structure of FIG. 9. For example, in order to obtain a withstand voltage of 600 V, when the buried oxide film has a thickness of 3.5 μm, the thickness of the semiconductor substrate is Since it may be about 5 μm, it is possible to provide a semiconductor device having a high breakdown voltage and a high current density, which is less affected by manufacturing variations than the structure of FIG.

  FIG. 5A is a partial cross-sectional structure diagram of the semiconductor device according to Example 3 which is the third embodiment of the present invention. This structure is based on FIG. 3a and is characterized in that the impurity concentration of the second layer 6 is changed stepwise in the lateral direction. FIG. 5b shows the relationship between the lateral position and the impurity concentration between A-A 'of the first layer 5 and B-B' of the second layer 6 described in FIG. 5a. The second layer 6 includes three regions 6a, 6b, and 6c, and the impurity concentration increases in the order of 6a, 6b, and 6c. The impurity concentration of the second layer 6 is lower than the impurity concentration of the first layer 5, and the difference D1 between the impurity concentration of the first layer 5 on the p-type base region 2 side and the second layer 6 is on the n-type drain region 3 side. The difference in impurity concentration between the first layer 5 and the second layer 6 is greater than D2. In FIG. 5, the second layer 6 is described with three regions, but the number of regions is not limited to three as a matter of course.

  According to the present embodiment described above, the on-resistance is reduced by increasing the impurity concentration on the element surface, and the depletion layer is easily spread to the drain side by setting the source-side impurity concentration on the element bottom surface to be high. It is possible to increase the breakdown voltage. Further, the thickness of the semiconductor substrate in the drift region does not need to be as thin as the structure of FIG. 9. For example, in order to obtain a withstand voltage of 600 V, when the buried oxide film has a thickness of 3.5 μm, the thickness of the semiconductor substrate is Since it may be about 5 μm, it is possible to provide a semiconductor device having a high breakdown voltage and a high current density, which is less affected by manufacturing variations than the structure of FIG.

  FIG. 6A is a partial cross-sectional structure diagram of the semiconductor device according to Example 4 which is the fourth embodiment of the present invention. This structure is based on FIG. 3a and is characterized in that the impurity concentrations of the first layer 5 and the second layer 6 are changed stepwise in the lateral direction. FIG. 6B shows the relationship between the lateral position and the impurity concentration between A-A ′ of the first layer 5 and B-B ′ of the second layer 6 described in FIG. 6A. The first layer 5 includes three regions 5a, 5b, and 5c, and the impurity concentration increases in the order of 5a, 5b, and 5c. The second layer 6 includes three regions 6a, 6b, and 6c, and the impurity concentration increases in the order of 6a, 6b, and 6c. The impurity concentration of the second layer 6 is lower than the impurity concentration of the first layer 5, and the difference D1 between the impurity concentration of the first layer 5 on the p-type base region 2 side and the second layer 6 is on the n-type drain region 3 side. The difference in impurity concentration between the first layer 5 and the second layer 6 is greater than D2. In FIG. 6, the first layer 5 and the second layer 6 are described in three regions, but the number of regions is not limited to three as a matter of course. The number of regions may be different between the first layer 5 and the second layer 6.

  According to the present embodiment described above, the on-resistance is reduced by increasing the impurity concentration on the element surface, and the depletion layer is easily spread to the drain side by setting the source-side impurity concentration on the element bottom surface to be high. It is possible to increase the breakdown voltage. Further, the thickness of the semiconductor substrate in the drift region does not need to be as thin as the structure of FIG. 9. For example, in order to obtain a withstand voltage of 600 V, when the buried oxide film has a thickness of 3.5 μm, the thickness of the semiconductor substrate is Since it may be about 5 μm, it is possible to provide a semiconductor device having a high breakdown voltage and a high current density, which is less affected by manufacturing variations than the structure of FIG.

  FIG. 7A is a partial cross-sectional structure diagram of the semiconductor device according to Example 5 which is the fifth embodiment of the present invention. This structure is based on FIG. 3a, and has a feature that the impurity concentration of the first layer 5 or the second layer 6 is locally lower on the n-type drain region 3 side than on the p-type base region 2 side. It is said. FIG. 7 b shows the relationship between the lateral position and the impurity concentration between A-A ′ of the first layer 5 and B-B ′ of the second layer 6 described in FIG. 7 a. In both the first layer and the second layer, the impurity concentration increases from the p-type base region 2 side to the n-type drain region 3 side, but the n-type drain locally from the p-type base region 2 side in the center of the element. The region 3 has a low impurity concentration region. The impurity concentration of the second layer 6 is lower than the impurity concentration of the first layer 5, and the difference D1 between the impurity concentration of the first layer 5 on the p-type base region 2 side and the second layer 6 is on the n-type drain region 3 side. The difference in impurity concentration between the first layer 5 and the second layer 6 is greater than D2. In FIG. 7, both the first layer 5 and the second layer 6 are described as having regions where the impurity concentration is locally lower on the n-type drain region 3 side than on the p-type base region 2 side. And the second layer may locally have a region having a lower impurity concentration on the n-type drain region 3 side than on the p-type base region 2 side.

  According to the present embodiment described above, the on-resistance is reduced by increasing the impurity concentration on the element surface, and the depletion layer is easily spread to the drain side by setting the source-side impurity concentration on the element bottom surface to be high. It is possible to increase the breakdown voltage. Further, the thickness of the semiconductor substrate in the drift region does not need to be as thin as the structure of FIG. 9. For example, in order to obtain a withstand voltage of 600 V, when the buried oxide film has a thickness of 3.5 μm, the thickness of the semiconductor substrate is Since it may be about 5 μm, it is possible to provide a semiconductor device having a high breakdown voltage and a high current density, which is less affected by manufacturing variations than the structure of FIG.

  FIG. 8A is a partial cross-sectional structure diagram of the semiconductor device according to Example 6 which is the sixth embodiment of the present invention. This structure is based on FIG. 3 a, and is characterized in that an n-type buffer region 16 is provided so as to surround the drain region 3. Even in this case, a high breakdown voltage and a high current density can be obtained by the same effect as the structure of FIG.

  Note that the n-type buffer region 16 in FIG. 8a is also applicable to the structures in FIGS. 4a, 5a, 6a, and 7a.

  According to the present embodiment described above, the on-resistance is reduced by increasing the impurity concentration on the element surface, and the depletion layer is easily spread to the drain side by setting the source-side impurity concentration on the element bottom surface to be high. It is possible to increase the breakdown voltage. Further, the thickness of the semiconductor substrate in the drift region does not need to be as thin as the structure of FIG. 9. For example, in order to obtain a withstand voltage of 600 V, when the buried oxide film has a thickness of 3.5 μm, the thickness of the semiconductor substrate is Since it may be about 5 μm, it is possible to provide a semiconductor device having a high breakdown voltage and a high current density, which is less affected by manufacturing variations than the structure of FIG.

1 n-type semiconductor substrate 2 p-type base region 3 n-type drain region 4 drift region 5 drift region first layer 6 drift region second layer 7 p-type contact region 8 n-type source region 9 support substrate 10 buried oxide film 11 source electrode 12 gate electrode 13 drift electrode 14 channel region 15 gate oxide film 16 n buffer region 17 insulating film 18 p-type drain region 40 drift region second layer 41 drift region first layer

Claims (15)

A semiconductor substrate;
A first diffusion region of a first conductivity type selectively formed on a surface layer of one main surface of the semiconductor substrate;
A second diffusion region of a second conductivity type selectively formed in a portion different from the first diffusion region of the surface layer;
A third diffusion region of a first conductivity type selectively formed between the first diffusion region and the second diffusion region;
The first diffusion region and the second diffusion region are arranged along the surface direction of the main surface of the semiconductor substrate, and operate in a unipolar lateral type semiconductor device,
The third diffusion region comprises a first layer and a second layer located between the first layer and the semiconductor substrate,
The second layer has a lower impurity concentration than the first layer,
The difference in the impurity concentration of said second layer and said first layer of said second diffusion region side is much larger than the difference between the impurity concentration of said second layer and said first layer of said first diffusion region side,
The semiconductor device, wherein the first diffusion region, the second diffusion region, and the third diffusion region function as a drain region, a base region, and a drift region of the lateral semiconductor device, respectively. . The semiconductor device according to claim 1,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region And the third diffusion region is formed in the active layer. The semiconductor device according to claim 1,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region The third diffusion region is formed in the active layer, and the first diffusion region, the second diffusion region, and the second layer of the third diffusion region are in contact with the insulating layer. A featured semiconductor device. A semiconductor substrate;
A first diffusion region of a first conductivity type selectively formed on a surface layer of one main surface of the semiconductor substrate;
A second diffusion region of a second conductivity type selectively formed in a portion different from the first diffusion region of the surface layer;
A third diffusion region of a first conductivity type selectively formed between the first diffusion region and the second diffusion region;
The first diffusion region and the second diffusion region are arranged along the surface direction of the main surface of the semiconductor substrate, and operate in a unipolar lateral type semiconductor device,
The third diffusion region comprises a first layer and a second layer located between the first layer and the semiconductor substrate,
The second layer has a lower impurity concentration than the first layer, and the impurity concentration gradually decreases from the first diffusion region side toward the second diffusion region side ,
The semiconductor device, wherein the first diffusion region, the second diffusion region, and the third diffusion region function as a drain region, a base region, and a drift region of the lateral semiconductor device, respectively. . The semiconductor device according to claim 4,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region And the third diffusion region is formed in the active layer. The semiconductor device according to claim 4,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region The third diffusion region is formed in the active layer, and the first diffusion region, the second diffusion region, and the second layer of the third diffusion region are in contact with the insulating layer. A featured semiconductor device. The semiconductor device according to claim 4,
The semiconductor device according to claim 1, wherein the first layer has an impurity concentration that gradually decreases from the first diffusion region side toward the second diffusion region side. The semiconductor device according to claim 7,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region And the third diffusion region is formed in the active layer. The semiconductor device according to claim 7,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region The third diffusion region is formed in the active layer, and the first diffusion region, the second diffusion region, and the second layer of the third diffusion region are in contact with the insulating layer. A featured semiconductor device. A semiconductor substrate;
A first diffusion region of a first conductivity type selectively formed on a surface layer of one main surface of the semiconductor substrate;
A second diffusion region of a second conductivity type selectively formed in a portion different from the first diffusion region of the surface layer;
A third diffusion region of a first conductivity type selectively formed between the first diffusion region and the second diffusion region;
The first diffusion region and the second diffusion region are arranged along the surface direction of the main surface of the semiconductor substrate, and operate in a unipolar lateral type semiconductor device,
The third diffusion region comprises a first layer and a second layer located between the first layer and the semiconductor substrate,
The second layer has an impurity concentration lower than that of the first layer, and the impurity concentration on the second diffusion region side is lower than the impurity concentration on the first diffusion region side ,
The semiconductor device, wherein the first diffusion region, the second diffusion region, and the third diffusion region function as a drain region, a base region, and a drift region of the lateral semiconductor device, respectively. . The semiconductor device according to claim 10.
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region And the third diffusion region is formed in the active layer. The semiconductor device according to claim 10.
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region The third diffusion region is formed in the active layer, and the first diffusion region, the second diffusion region, and the second layer of the third diffusion region are in contact with the insulating layer. A featured semiconductor device. The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein the first layer has an impurity concentration on the second diffusion region side lower than the impurity concentration on the first diffusion region side. The semiconductor device according to claim 13,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region And the third diffusion region is formed in the active layer. The semiconductor device according to claim 13,
The semiconductor substrate is an SOI substrate including a support substrate, an insulating layer formed on the support substrate, and an active layer formed on the insulating layer, and the first diffusion region and the second diffusion region The third diffusion region is formed in the active layer, and the first diffusion region, the second diffusion region, and the second layer of the third diffusion region are in contact with the insulating layer. A featured semiconductor device.