JP6325846B2 - Method for creating a floor plan of a semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a method for creating a floor plan for a semiconductor integrated circuit, which creates a floor plan for a layout corresponding to a net list of the semiconductor integrated circuit.

FIG. 8 is a flowchart of an example showing each process of creating a floor plan of a conventional semiconductor integrated circuit layout.
As shown in the figure, conventionally, when creating a floor plan for a layout of a semiconductor integrated circuit, first, the area for creating the floor plan is constrained to be an area of the estimated layout area of the semiconductor integrated circuit. The macro cells included in the netlist are arranged (step S21).

  Subsequently, standard cells included in the netlist are arranged in the floor plan creation area (step S22), and further, timing optimization is performed to reduce the occurrence of timing errors (step S23).

  Subsequently, a clock tree is generated (step S24), and wiring of each path between the macro cell and the standard cell is performed to create a floor plan (step S25).

  Subsequently, delay information data including delay information and the like of each path is created from the floor plan (step S26).

  Subsequently, based on the delay information data, timing analysis of the netlist is performed, and information on a false path that is a path that does not need to take timing into consideration is extracted (step S27).

Subsequently, as a result of the timing analysis, it is determined whether or not the floor plan needs to be changed (step S28).
If it is determined in step S28 that the floor plan needs to be changed (YES in step S28), the process returns to step S21 and the above process is performed again. On the other hand, when it is determined that there is no need to change the floor plan (NO in step S28), the creation of the pro-plan is terminated.

  As the scale of semiconductor integrated circuits increases, considering the connection between hundreds and thousands of macro cells (including memory) and standard cells, as described above, the arrangement of macro cells and standard cells, timing optimization, and clock tree It takes several days to create a floor plan through the generation of data (CTS), wiring of each path, etc., create delay information data from the floor plan, and extract the fault path based on the delay information data And

  If timing constraints with added false path information can be applied and standard cell placement, timing optimization, and routing of each path can be performed, false path timing optimization can be prevented. Processing time can be saved. Further, by omitting false path timing optimization, it is possible to prevent an increase in circuit scale, thereby reducing the layout area and power consumption accordingly. Therefore, it is desirable to extract as many false paths as possible at an early stage.

  However, in the conventional method for creating a floor plan, after performing timing optimization and creating a floor plan, a false path is extracted based on delay information data created from the floor plan. Therefore, it takes several days to extract the false path, which has a great influence on TAT (turnaround time). In addition, when the floor plan needs to be redone as a result of the timing analysis, the delay information data and false path information created over several days are wasted.

  As prior art documents relevant to the present invention, there are Patent Documents 1 to 3.

  Patent Document 1 discloses a false path corresponding to a result that does not satisfy a predetermined timing specification by performing timing analysis based on a predetermined timing specification for each of a plurality of false path paths generated by a false path automatic generation tool. A false path automatic extraction device and a false path automatic extraction method are described that effectively reduce the time required for various processes using false path settings.

  In Patent Document 2, in the RTL logic circuit, among the paths from the FF to the external output terminal or between the FFs having the same clock source, a false path setting that does not require adjustment of the data delay time is facilitated. A semiconductor design support apparatus and a semiconductor design support method are described in which a dummy module that clearly indicates a false path is inserted, and an RTL logic circuit in which the dummy module is inserted is read to generate a gate level circuit.

  In Patent Document 3, in the layout design of a semiconductor device, based on the clock information of the circuit, the clock tree in the circuit is mutually exclusive, and the false path and the clock necessary for dividing the clock tree so that there is no overlapping portion A clock synthesis method for extracting leaf points for treating the points other than the flip-flops existing on the tree as leaves is described.

JP 2008-140056 A JP 2008-226069 A JP 2006-85595 A

  An object of the present invention is to solve the above-mentioned problems of the prior art, extract a lot of false paths early in the floor plan creation process, and perform a floor plan timing optimization considering the false paths. An object of the present invention is to provide a method for creating a floor plan of an integrated circuit.

In order to achieve the above object, the present invention provides a floor plan creation method for a semiconductor integrated circuit, in which a computer creates a floor plan of a layout corresponding to a net list of the semiconductor integrated circuit,
The computer is
A first placement of macrocells included in the netlist is constrained so that the floorplan creation region is a region having a larger layout area than the estimated floorplan and without considering timing. Steps,
A second step of tentatively arranging standard cells included in the netlist in the floor plan creation area without considering the timing;
A third step of temporarily generating a clock tree without considering the timing;
A fourth step of creating a temporary floor plan by performing temporary wiring of each path between the macro cell and the standard cell in which the temporary placement is performed without considering the timing;
First delay information data including delay information of each clock of the clock tree in which the temporary generation has been performed and delay information of each path in which the temporary wiring has been performed is generated from the temporary floor plan. Steps,
Based on the first delay information data, a sixth step of performing timing analysis of the netlist to extract information on false paths and information on arrangement restrictions between the macro cells;
The placement of the floor plan is constrained to be an area of the floor plan estimated placement area, and the placement of the macro cell is placed with timing constraints to which information on placement constraints between the macro cells is added. A seventh step of performing
Applying the timing constraint to which the false path information has been added, the eighth step of performing the regular placement of the standard cells in the floor plan creation area;
A ninth step of optimizing the timing by applying a timing constraint to which the false path information is added;
A tenth step of performing the main generation of the clock tree by applying a timing constraint to which delay information of each clock of the clock tree is added;
Executing the eleventh step of creating the floor plan by performing the main wiring of each path between the macro cell and the standard cell in which the main placement has been performed, with timing constraints added with the false path information. The present invention provides a method for creating a floor plan of a semiconductor integrated circuit.

The computer further includes second delay information including delay information of each clock of the clock tree in which the main generation has been performed, and delay information of each path in which the main wiring has been performed, from the floor plan. A twelfth step of creating data;
It is preferable to execute a thirteenth step of analyzing the timing of the netlist based on the second delay information data.

  Further, the macro cell is provisionally arranged along an outer peripheral portion in the floor plan creation area in the first step, and the standard cell is placed in a central part in the floor plan creation area in the second step. It is preferable to perform the arrangement.

  In addition, the macro cell provisional placement may be performed with the constraint that the floor plan creation region is a region having an arrangement area that is two to five times the estimate of the floor plan, according to the first step. preferable.

Further, the sixth step extracts the information on the restriction of the arrangement between the macro cells before the information of the false path,
According to the seventh step, the macro cell is placed in a main position,
Preferably, the standard cells are permanently arranged in the eighth step while the false path information is extracted in the sixth step.

Further, the sixth step further extracts critical path information,
It is preferable to perform the main placement of the standard cells, the timing optimization, and the main wiring of each of the paths, with timing constraints added with the critical path information.

According to the present invention, temporary placement, clock tree temporary generation, and temporary wiring are performed without imposing timing constraints for timing optimization, and a temporary floor plan is created in a short time. By creating the first delay information data and feeding it back to the creation of this floor plan, many false paths are extracted early in the floor plan creation process, and the timing of this floor plan is optimized in consideration of the extracted false paths Can be made.
In addition, since this floor plan can be fed back early to reduce the occurrence of timing errors, the created floor plan can be reduced from being wasted and TAT can be shortened.

It is a flowchart of one Embodiment showing each process which produces the floor plan of the layout of the semiconductor integrated circuit of this invention. It is a conceptual diagram of an example showing the flow of the data used at each process shown in FIG. It is a conceptual diagram showing a state where provisional placement of a macro cell and a standard cell is performed with a constraint that a floor plan creation region is a region having an arrangement area that is two to five times the floor plan estimate. It is a conceptual diagram of an example showing the path | pass in a semiconductor integrated circuit. It is a circuit diagram of an example showing the configuration of a circuit including a false path. It is a circuit diagram of another example showing the configuration of a circuit including a false path. FIG. 10 is a conceptual diagram showing a state in which a main arrangement of macro cells and standard cells is performed with a restriction that a floor plan creation area is an area of a floor plan estimation arrangement area. It is a flowchart of an example showing each process which produces the floor plan of the layout of the conventional semiconductor integrated circuit.

  Hereinafter, a method for creating a floor plan of a semiconductor integrated circuit according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a flowchart of an embodiment showing each process for creating a floor plan of a layout of a semiconductor integrated circuit according to the present invention, and FIG. 2 is an example concept showing a flow of data used in each process shown in FIG. FIG.

  As shown in these drawings, in the present embodiment, when creating a floor plan of a layout of a semiconductor integrated circuit, first, restrictions on a temporary floor plan, that is, a provisional area of a temporary floor plan, are set to 2 of floor plan estimation. The provisional placement of the macrocells included in the netlist of the semiconductor integrated circuit can be performed without restricting the timing of the arrangement, and without restricting the timing of the arrangement area to the area of 5 times or more and 5 times or less. Perform (Step S1).

For example, as shown in FIG. 3, the macro cells 12 including the memory are arranged along the outer peripheral portion in the temporary floor plan creation region 11 with the intervals between the macro cells 12 set uniformly (for example, 100 μm). At this time, there is no timing constraint that requires processing time for timing optimization, such as a timing constraint that adds information on arrangement constraints between macrocells 12 or a timing constraint that adds false path information. .
In the example of FIG. 3, the timing constraint between the blocks (the macro cell 12 and the standard cell 14) to which the same type of hatching is applied is severe, but the operation of the semiconductor integrated circuit in the temporary arrangement in the temporary floor plan. There is no need to consider timing.

  The example of the temporary floor plan in FIG. 3 shows the case where the macros have the same size, but the intervals between the macros are uniformly wide, and it can be seen that wiring between the macros can be easily performed. .

  Subsequently, the standard cells included in the netlist are temporarily arranged in the temporary floor plan creation area 11 without considering the timing (step S2).

  For example, as shown in FIG. 3, the standard cell 14 and the macro cell 12 may be arranged anywhere in the temporary floor plan creation area 11 as long as a space between the cells can be taken.

  Subsequently, the clock tree is tentatively generated without considering the timing (step S3).

  Subsequently, a temporary floor plan is created by performing temporary wiring of each path between the macro cell and the standard cell in which temporary placement has been performed without considering the timing (step S4).

If the floorplan creation area is constrained to be the area of the floorplan estimate layout area and considering the connection between macros, it takes several days to place and route the macrocells and standard cells. To do.
On the other hand, when the provisional floor plan creation area 11 is constrained to be an area having an arrangement area that is twice or more and five times or less than the estimate of the floor plan, the degree of freedom of provisional placement and provisional wiring increases. Temporary placement and wiring can be completed in a short time, and a temporary floor plan can be created.

  Subsequently, from the temporary floor plan, first delay information data including delay information of each clock of the clock tree in which temporary generation has been performed, delay information of each path in which temporary wiring has been performed, and the like is created ( Step S5).

Here, the first delay information data is the delay information (delay time) by the cell (macro cell and standard cell) for each clock of the clock tree in which temporary generation has been performed and each path in which temporary wiring has been performed. And delay information (delay time) due to temporary wiring.
The delay information for each cell is stored in the cell library shown in FIG.

  If temporary placement and provisional wiring of macro cells and standard cells are performed with the restriction that the creation area 11 of the temporary floor plan is an area having an arrangement area that is two to five times the floor plan estimate, The length of wiring is longer than when the actual placement and wiring of macro cells and standard cells are performed with the restriction of the estimated placement area, and the delay time of each path where temporary wiring is performed is greatly increased. To increase.

  Subsequently, based on the first delay information data, for example, timing analysis of a netlist by simulation is performed, and false path information, information on arrangement restrictions between macro cells, and the like are extracted (step S6).

  In step S6, critical path information may be further extracted.

  Here, the critical path and the false path will be described.

In a certain circuit in the semiconductor integrated circuit, a path in which signal propagation from a certain cell (macro cell or standard cell) to another cell has the least margin with respect to a required specification is called a critical path.
In addition, since the static timing analysis tool finds a critical path from the circuit topology and delay information without considering the logic function, it may analyze a path that is meaningless (not activated) in actual operation. . A path that does not need to consider such timing is called a false path.

FIG. 4 is a conceptual diagram of an example showing a path in the semiconductor integrated circuit. As shown in the figure, all paths in the semiconductor integrated circuit can be classified into the following (1) to (4).
(1) Path from flip-flop (FF) to FF (2) Path from input port to FF (3) Path from FF to output port (4) Path from input port to output port

  Subsequently, a specific example of a circuit including a false path will be described.

  FIG. 5 is a circuit diagram illustrating an example of a circuit configuration including a false path. The circuit shown in the figure includes three stages of FFs 16, 18, and 20 connected in series. The first stage FF16 operates in synchronization with the first clock CLK1, and the second and third stage FFs 18 and 20 operate in synchronization with the second clock CLK2 which is asynchronous with the first clock CLK1. To do. That is, the path from the data output terminal of the first stage FF16 to the data input terminal of the second stage FF18 is an asynchronous path.

  Asynchronous paths are false paths that do not require timing analysis. In the static timing analysis tool, when a plurality of clocks are defined, they are all estimated to be in a synchronous relationship, and all data and paths between them are subjected to timing analysis. Therefore, when the first clock CLK1 and the second clock CLK2 are in an asynchronous relationship, it is desirable to eliminate them by applying a timing constraint that clearly indicates the relationship.

  Next, FIG. 6 is a circuit diagram of another example showing the configuration of a circuit including a false path. The circuit shown in the figure includes an FF 22, a multiplexer 24, and two stages of FFs 26 and 28 connected in series. The FF 22 outputs a divided clock DIVCLK obtained by dividing the clock CLK by two in synchronization with the clock CLK. The multiplexer 24 selectively outputs the clock CLK or the divided clock DIVCLK, and the two stages of FFs 26 and 28 operate in synchronization with the clock selected and output from the multiplexer 24.

Since the clock CLK and the divided clock DIVCLK are selectively output by the multiplexer 24, the path between them is a false path that does not require timing analysis. In the static timing analysis tool, the following paths (1) to (4) are analyzed.
(1) FF26 (driven by CLK) → FF28 (driven by CLK)
(2) FF26 (driven by CLK) → FF28 (driven by DIVCLK)
(3) FF26 (driven by DIVCLK) → FF28 (driven by DIVCLK)
(4) FF26 (driven by DIVCLK) → FF28 (driven by CLK)
When the clock CLK and the divided clock DIVCLK are in an exclusive relationship, since (2) and (4) are false paths, it is desirable to eliminate them by applying a timing constraint that clearly indicates them.

  Although two specific examples of false paths have been described, false paths can be specified in the same manner for circuits other than these specific examples.

As described above, in the case of a temporary floor plan, the wiring length of each path where temporary wiring is performed becomes longer and the delay time increases significantly. Therefore, a critical path in which a timing error due to wiring delay occurs is detected. Easy to use. In the present embodiment, for example, false path information can be extracted from paths in which a timing error occurs in a state where the delay time of each path is significantly increased.
A specific method for extracting false path information is not limited at all, and various methods including a conventionally known method can be used.

  Further, the information on the restriction on the arrangement between the macro cells represents, for example, the restriction that the two macro cells are arranged adjacent to each other when a path connecting two macro cells is a critical path.

  Next, apply the constraint of this floor plan, that is, the constraint that makes the floor plan creation area the area of the floor plan estimated layout area, and the timing constraint that adds the information of the layout constraint between macro cells. Then, the macro cell main arrangement is performed (step S7).

For example, as shown in FIG. 7, macrocells 12 with severe timing constraints are arranged together in a floorplan creation area 10 so as to be adjacent to each other.
The example of FIG. 7 represents that the timing constraint between the macrocells 12 to which the same type of hatching is applied is severe, corresponding to the example of FIG.

  Subsequently, the standard arrangement of the standard cells is performed within the floor plan creation area with timing constraints added with false path information (step S8).

  For example, as shown in FIG. 7, the macro cell 12 and the standard cell 14 with severe timing constraints are arranged together in the floor plan creation area 10 so as to be adjacent to each other.

  Subsequently, the timing constraint to which the false path information is added is applied to reduce the occurrence of unnecessary timing errors, and then the layout is optimized to satisfy the timing specifications, that is, the timing is optimized (step S9).

  In step S6, the information on the arrangement constraints between the macro cells is extracted without waiting for the extraction of the false path information by extracting the information on the arrangement restrictions between the macro cells before the false path information. Later, the actual placement of the macrocells can be started. Further, the standard arrangement of standard cells can be performed while extracting false path information. Thereby, processing time can be shortened.

  Subsequently, the main generation of the clock tree is performed by applying the timing constraint to which the delay information of each clock of the clock tree is added (step S10).

  For example, when the delay time of a clock supplied to a certain cell is very large, the delay time of a clock with a large delay time is shortened in preference to a clock with a short delay time supplied to another cell. The main generation of the clock tree is performed.

  Subsequently, the floor plan is created by performing the main wiring of each path between the macro cell and the standard cell in which the main placement is performed, with timing constraints added with false path information (step S11).

  Further, the standard placement of the standard cells, the optimization of the timing, and the main wiring of each path may be performed by applying a timing constraint to which information on the critical path is added. As a result, this floor plan can be created so as to satisfy the timing constraint of the critical path.

  Subsequently, second delay information data including delay information of each clock of the clock tree in which the main generation is performed and delay information of each path in which the main wiring is performed is generated from the floor plan ( Step S12).

  Here, the second delay information data is the delay information (delay time) by the cell (macro cell and standard cell) for each clock of the clock tree in which the main generation is performed and each path in which the main wiring is performed. And delay information (delay time) by this wiring.

  Subsequently, based on the second delay information data, the timing analysis of the netlist is performed (step S13).

  This floor plan is based on the delay information of each clock in the clock tree, critical path information, false path information, and macro cell and standard cell layout, main wiring, and routing information. Since timing optimization is performed, there is almost no timing error due to wiring delay.

Subsequently, as a result of the timing analysis, it is determined whether or not the floor plan needs to be changed (step S14).
If it is determined that the floor plan needs to be changed (YES in step S14), the process returns to step S7 and the above process is performed again. On the other hand, if it is determined that there is no need to change the floor plan (NO in step S14), creation of the pro-plan is terminated.

In the floor plan creation method of the present embodiment, provisional placement, clock tree provisional generation, and provisional wiring are performed without imposing timing constraints for timing optimization, and a temporary floor plan is created and created in a short time. By creating the first delay information data from the provisional floor plan and feeding it back to the creation of this floor plan, many false paths are extracted early in the floor plan creation process, and the book is taken into account the extracted false paths. The timing of the floor plan can be optimized.
In addition, since this floor plan can be fed back early to reduce the occurrence of timing errors, the created floor plan can be reduced from being wasted and TAT can be shortened.

When temporary placement of macro cells and standard cells is performed, it is not essential that the temporary floor plan creation area 11 be an area having an arrangement area that is two to five times the floor plan estimate. Any region having a larger layout area than the estimated value may be used.
Further, when the temporary placement of the macro cell and the standard cell is performed, it is not essential to place the macro cell along the outer peripheral portion in the floor plan creation area and to place the standard cell in the center of the floor plan creation area.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

Creating area of 10 floor plan of creation area 11 temporary floor plan 12 macrocells 14 standard cell 16,18,20,22,26,2 8 flip-flop (FF)
24 Multiplexer

Claims (6)

A method for creating a floor plan for a semiconductor integrated circuit in which a computer creates a floor plan for a layout corresponding to a net list of the semiconductor integrated circuit,
The computer is
A first placement of macrocells included in the netlist is constrained so that the floorplan creation region is a region having a larger layout area than the estimated floorplan and without considering timing. Steps,
A second step of tentatively arranging standard cells included in the netlist in the floor plan creation area without considering the timing;
A third step of temporarily generating a clock tree without considering the timing;
A fourth step of creating a temporary floor plan by performing temporary wiring of each path between the macro cell and the standard cell in which the temporary placement is performed without considering the timing;
First delay information data including delay information of each clock of the clock tree in which the temporary generation has been performed and delay information of each path in which the temporary wiring has been performed is generated from the temporary floor plan. Steps,
Based on the first delay information data, a sixth step of performing timing analysis of the netlist to extract information on false paths and information on arrangement restrictions between the macro cells;
The placement of the floor plan is constrained to be an area of the floor plan estimated placement area, and the placement of the macro cell is placed with timing constraints to which information on placement constraints between the macro cells is added. A seventh step of performing
Applying the timing constraint to which the false path information has been added, the eighth step of performing the regular placement of the standard cells in the floor plan creation area;
A ninth step of optimizing the timing by applying a timing constraint to which the false path information is added;
A tenth step of performing the main generation of the clock tree by applying a timing constraint to which delay information of each clock of the clock tree is added;
Executing the eleventh step of creating the floor plan by performing the main wiring of each path between the macro cell and the standard cell in which the main placement has been performed, with timing constraints added with the false path information. A method for creating a floor plan of a semiconductor integrated circuit. The computer further includes second delay information including delay information of each clock of the clock tree in which the main generation has been performed, and delay information of each path in which the main wiring has been performed, from the floor plan. A twelfth step of creating data;
The floor plan creation method for a semiconductor integrated circuit according to claim 1, wherein a thirteenth step of performing timing analysis of the netlist is executed based on the second delay information data.   In the first step, the macro cells are provisionally arranged along the outer peripheral portion in the floor plan creation area, and in the second step, the standard cells are arranged in the central part in the floor plan creation area. The method for creating a floor plan of a semiconductor integrated circuit according to claim 1 or 2 to be performed.   The first step performs temporary placement of the macrocell under the constraint that the floorplan creation region is a region having an arrangement area that is two to five times the estimate of the floorplan. 4. A method for creating a floor plan of a semiconductor integrated circuit according to any one of 3 above. According to the sixth step, information on arrangement restrictions between the macro cells is extracted before information on the false path,
According to the seventh step, the macro cell is placed in a main position,
5. The floor plan for a semiconductor integrated circuit according to claim 1, wherein the standard cells are permanently arranged in the eighth step while the false path information is extracted in the sixth step. 6. How to make. The sixth step further extracts critical path information,
The main arrangement of the standard cell, the timing optimization, and the main wiring of each of the paths are performed with timing constraints added with information on the critical path. A method for creating a floor plan of a semiconductor integrated circuit.

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