[go: up one dir, main page]

JP6312134B2 - Method for manufacturing substrate with germanium layer and substrate with germanium layer - Google Patents

Method for manufacturing substrate with germanium layer and substrate with germanium layer Download PDF

Info

Publication number
JP6312134B2
JP6312134B2 JP2014144759A JP2014144759A JP6312134B2 JP 6312134 B2 JP6312134 B2 JP 6312134B2 JP 2014144759 A JP2014144759 A JP 2014144759A JP 2014144759 A JP2014144759 A JP 2014144759A JP 6312134 B2 JP6312134 B2 JP 6312134B2
Authority
JP
Japan
Prior art keywords
layer
substrate
crystallization
stress
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014144759A
Other languages
Japanese (ja)
Other versions
JP2016021503A (en
Inventor
角田 功
功 角田
健一郎 高倉
健一郎 高倉
慎一 本山
慎一 本山
豊 楠田
豊 楠田
真浩 古田
真浩 古田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samco Inc
Institute of National Colleges of Technologies Japan
Original Assignee
Samco Inc
Institute of National Colleges of Technologies Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samco Inc, Institute of National Colleges of Technologies Japan filed Critical Samco Inc
Priority to JP2014144759A priority Critical patent/JP6312134B2/en
Publication of JP2016021503A publication Critical patent/JP2016021503A/en
Application granted granted Critical
Publication of JP6312134B2 publication Critical patent/JP6312134B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Recrystallisation Techniques (AREA)
  • Electroluminescent Light Sources (AREA)

Description

本発明は、ゲルマニウム層付き基板の製造方法等に関する。   The present invention relates to a method for manufacturing a substrate with a germanium layer.

昨今の有機EL(Electro-Luminescence)等の湾曲可能な表示装置の普及に伴い、携行や使用姿勢の自由度が高い、装置全体がフレキシブルな電子デバイスの開発に期待が高まっている。例えば、表示装置のみならず外装筐体や基板等の板状部材に屈曲性を有する材料を用いることで、折り曲げたり丸めたりして携行できる、あるいはウェアラブルデバイスとして身に着けることができる等の高いユーザビリティが実現されると考えられている。   With the recent popularization of bendable display devices such as organic EL (Electro-Luminescence), there is an increasing expectation for the development of electronic devices that have a high degree of freedom in carrying and use and are flexible throughout. For example, by using a flexible material for not only a display device but also a plate-like member such as an exterior housing or a substrate, it can be folded and rolled, or can be worn as a wearable device. Usability is expected to be realized.

このようなフレキシブルデバイスを実現するためには、まず基板部を湾曲可能なPET(polyethylene terephthalate)、PP(polypropylene)等の樹脂材料で構成することが現実的である。一方、処理の高速化のためには、半導体材料は有機材料よりも遥かに電子移動度の高い無機材料(例えばシリコン(Si)等)を用いることが好ましい。   In order to realize such a flexible device, first, it is realistic that the substrate portion is made of a resin material such as bendable PET (polyethylene terephthalate) or PP (polypropylene). On the other hand, in order to increase the processing speed, it is preferable to use an inorganic material (for example, silicon (Si)) having a much higher electron mobility than the organic material as the semiconductor material.

特開2002-373858号公報JP 2002-373858 JP

ジャーナル・オブ・エレクトロニック・マテリアルズ(Journal of ELECTRONIC MATERIALS),米国,ザ・ミネラルズ・メタルズ・アンド・マテリアルズ・ソサエティ(The Minerals, Metals & Materials Society),第33巻,第4号,p.353−357Journal of ELECTRONIC MATERIALS, USA, The Minerals, Metals & Materials Society, Vol. 33, No. 4, p. 353-357

ここで、無機半導体材料としては、Siと比較して小電力で動作するIV族の半導体材料であるゲルマニウム(Ge)が近年注目されている。しかしながら、Geはインゴットの単結晶を得ることが難しいことから、これまであまり量産品に用いられてこなかった。しかし上記のような製造工程の困難が解決されれば、Geは有用な半導体材料である。そこで、一旦非晶質(アモルファス)のGe(a−Ge)を生成した後に該a−Geを結晶化させる試みが数多くなされている。   Here, as an inorganic semiconductor material, germanium (Ge), which is a group IV semiconductor material that operates with lower electric power than Si, has attracted attention in recent years. However, since Ge is difficult to obtain an ingot single crystal, it has not been used so much in mass production. However, Ge is a useful semiconductor material if the above difficulties in the manufacturing process are solved. Therefore, many attempts have been made to crystallize a-Ge after once generating amorphous Ge (a-Ge).

例えば特許文献1には、絶縁膜上に非晶質ケイ素ゲルマニウム(a−SiGe)等の非晶質構造を有する化合物半導体膜を成膜した後で該半導体膜上に熱結晶化を促すための金属含有層を形成し、熱処理による上記絶縁膜の応力の増加を利用して非晶質の半導体膜を結晶化させることが記載されている。同文献では、絶縁膜の応力を増加させるために、異なる温度で複数回の熱処理を行っているが、そのために同文献では基板として石英ガラス等、高耐熱性のガラスを用い、最高加熱温度は一般的な樹脂材料の軟化点(例えばPETでは約180℃)を遥かに超えている。   For example, Patent Document 1 discloses that after a compound semiconductor film having an amorphous structure such as amorphous silicon germanium (a-SiGe) is formed on an insulating film, thermal crystallization is promoted on the semiconductor film. It is described that a metal-containing layer is formed and an amorphous semiconductor film is crystallized by utilizing an increase in stress of the insulating film due to heat treatment. In this document, heat treatment is performed multiple times at different temperatures in order to increase the stress of the insulating film. For this reason, in this document, high heat-resistant glass such as quartz glass is used as the substrate, and the maximum heating temperature is It far exceeds the softening point of a general resin material (for example, about 180 ° C. for PET).

一方、非特許文献1には、PET製のフレキシブル基板上に非晶質Ge(a−Ge)薄膜を形成した後で該フレキシブル基板を曲げてa−Ge膜に応力を発生させることにより、Ge膜を通常の結晶化温度よりも大幅な低温で結晶化できることが記載されている。同文献にはまた、a−Ge膜上に結晶化誘起金属として銅(Cu)膜を形成することも記載されている。しかしながら、同文献ではa−Ge(及びCu)を蒸着したフレキシブル基板自体を曲げることにより外的に応力を加えるという方法をとっているため、結晶化すべき素子以外の部分にも応力が加わり、それらに悪影響を与えるという問題がある。   On the other hand, Non-Patent Document 1 discloses that an amorphous Ge (a-Ge) thin film is formed on a flexible substrate made of PET, and then the flexible substrate is bent to generate stress in the a-Ge film. It is described that the film can be crystallized at a temperature significantly lower than the normal crystallization temperature. The document also describes forming a copper (Cu) film as a crystallization-inducing metal on the a-Ge film. However, in this document, since a method of applying external stress by bending the flexible substrate itself on which a-Ge (and Cu) is deposited is applied, stress is also applied to portions other than the element to be crystallized. There is a problem of adversely affecting.

本発明は上記の事情に鑑みてなされたものであり、その目的とするところは、フレキシブル基板上の所望の箇所に、容易に結晶ゲルマニウム層を形成することのできるゲルマニウム層付き基板の製造方法、及び該方法により製造されたゲルマニウム層付き基板を提供することにある。   The present invention has been made in view of the above circumstances, and the object of the present invention is a method for producing a substrate with a germanium layer, which can easily form a crystalline germanium layer at a desired location on a flexible substrate, And providing a substrate with a germanium layer manufactured by the method.

上記課題を解決するために成された本発明に係るゲルマニウム層付き基板の製造方法は、
a) 基板上に非晶質のゲルマニウム層を形成する工程と、
b) 前記形成したゲルマニウム層上に、非晶質ゲルマニウムの結晶化を促す結晶化誘起金属層を形成する工程と、
c) 前記結晶化誘起金属層上に、前記結晶化誘起金属層に応力を印加する応力印加層を、雰囲気温度80℃〜280℃にてプラズマ蒸着法により形成する工程と、
を含むことを特徴とする。
The manufacturing method of the substrate with a germanium layer according to the present invention made to solve the above problems,
a) forming an amorphous germanium layer on the substrate;
b) forming a crystallization-inducing metal layer that promotes crystallization of amorphous germanium on the formed germanium layer;
c) forming a stress applying layer for applying stress to the crystallization-inducing metal layer on the crystallization-inducing metal layer by a plasma deposition method at an ambient temperature of 80 ° C. to 280 ° C .;
It is characterized by including.

上記の構成によれば、基板上に形成された非晶質のゲルマニウム層は、応力印加層により印加される応力によって、結晶化誘起金属層との境界から結晶化が開始し、全体に広がってゆく。さらに、応力印加層形成時の雰囲気温度が280℃以下であるため、例えばフレキシブル基板の材料としてポリイミドを用いても、熱による基板変形を回避することができる。また、ゲルマニウム層及び応力印加層は、マスキング等により基板の目的箇所にのみ形成可能であるため、基板上の他の箇所に不要な(時には有害な)応力が印加されることがない。こうして、所望の箇所に結晶ゲルマニウム層が形成されたフレキシブル基板を容易に作製することができる。
また、プラズマ蒸着法は低温での層形成に適している他、形成条件を調整することで応力印加層の内部応力を自在に設定することができる。
According to the above configuration, the amorphous germanium layer formed on the substrate starts to crystallize from the boundary with the crystallization-inducing metal layer due to the stress applied by the stress application layer, and spreads over the whole. go. Furthermore, since the atmospheric temperature at the time of forming the stress application layer is 280 ° C. or less, even if polyimide is used as the material of the flexible substrate, for example, the substrate deformation due to heat can be avoided. Further, since the germanium layer and the stress application layer can be formed only at the target location of the substrate by masking or the like, unnecessary (sometimes harmful) stress is not applied to other locations on the substrate. Thus, a flexible substrate in which a crystalline germanium layer is formed at a desired location can be easily manufactured.
The plasma deposition method is suitable for forming a layer at a low temperature, and the internal stress of the stress application layer can be freely set by adjusting the forming conditions.

前記応力印加層は好ましくは二酸化ケイ素(SiO)層であり、より好ましくはオルトケイ酸テトラエチル(TEOS)を原料として形成される二酸化ケイ素層である。
オルト珪酸テトラエチルは人体に対する安全性が高く、取り扱いが容易である点で優れている。
The stress applying layer is preferably a silicon dioxide (SiO 2 ) layer, more preferably a silicon dioxide layer formed using tetraethyl orthosilicate (TEOS) as a raw material.
Orthoethyl silicate is excellent in that it is highly safe for the human body and easy to handle.

本発明によれば、フレキシブル基板上の所望の箇所に、容易に結晶ゲルマニウム層を形成することが可能となる。   According to the present invention, it is possible to easily form a crystalline germanium layer at a desired location on a flexible substrate.

本発明の一実施形態に係るGe層付き基板の製造方法の第1工程(a)、第2工程(b)及び第3工程(c)の説明図。Explanatory drawing of the 1st process (a), 2nd process (b), and 3rd process (c) of the manufacturing method of the board | substrate with Ge layer which concerns on one Embodiment of this invention. 同実施形態の一実施例において応力印加層による応力印加が無い場合のGe膜付き基板のGe層上に成膜された結晶化誘起金属層の縁部付近の拡大上面図(a)、(a)に示す矩形領域の部分拡大図のラマンマッピング(b)及び該ラマンマッピングにより検出された領域ごとのラマンスペクトル(c)。An enlarged top view near the edge of the crystallization-inducing metal layer formed on the Ge layer of the substrate with the Ge film when no stress is applied by the stress application layer in one example of the embodiment (a), (a (B) of a partially enlarged view of the rectangular area shown in FIG. 5) and a Raman spectrum (c) for each area detected by the Raman mapping. 同実施例において応力印加層により引張応力(200MPa)が印加された場合のGe膜付き基板のGe層上に成膜された結晶化誘起金属層の縁部付近の拡大上面図(a)、(a)に示す矩形領域の部分拡大図のラマンマッピング(b)及び該ラマンマッピングにより検出された領域ごとのラマンスペクトル(c)。In the same example, an enlarged top view near the edge of the crystallization-inducing metal layer formed on the Ge layer of the substrate with the Ge film when tensile stress (200 MPa) is applied by the stress applying layer (a), ( The Raman mapping (b) of the partially enlarged view of the rectangular area shown in a) and the Raman spectrum (c) for each area detected by the Raman mapping. 同実施例において応力印加層により圧縮応力(-100MPa)が印加された場合のGe膜付き基板のGe層上に成膜された結晶化誘起金属層の縁部付近の拡大上面図(a)、(a)に示す矩形領域の部分拡大図のラマンマッピング(b)及び該ラマンマッピングにより検出された領域ごとのラマンスペクトル(c)。In the same example, an enlarged top view near the edge of the crystallization-inducing metal layer formed on the Ge layer of the substrate with the Ge film when compressive stress (-100 MPa) is applied by the stress application layer (a), The Raman mapping (b) of the partial enlarged view of the rectangular area shown to (a), and the Raman spectrum (c) for every area | region detected by this Raman mapping. 同実施例において応力印加層により圧縮応力(-200MPa)が印加された場合のGe膜付き基板のGe層上に成膜された結晶化誘起金属層の縁部付近の拡大上面図(a)、(a)に示す矩形領域の部分拡大図のラマンマッピング(b)及び該ラマンマッピングにより検出された領域ごとのラマンスペクトル(c)。In the same example, an enlarged top view near the edge of the crystallization-inducing metal layer formed on the Ge layer of the substrate with the Ge film when compressive stress (-200 MPa) is applied by the stress applying layer (a), The Raman mapping (b) of the partial enlarged view of the rectangular area shown to (a), and the Raman spectrum (c) for every area | region detected by this Raman mapping. 同実施例におけるa−Ge層の横方向(面方向)の結晶成長距離の応力依存性を示すプロット図。The plot figure which shows the stress dependence of the crystal growth distance of the horizontal direction (plane direction) of the a-Ge layer in the Example. 図5に示した実験例における、結晶化誘起金属層周辺の横方向結晶成長距離と、応力印加層領域内での相対位置との関係を示す説明図。FIG. 6 is an explanatory diagram showing the relationship between the lateral crystal growth distance around the crystallization-inducing metal layer and the relative position in the stress application layer region in the experimental example shown in FIG. 5.

以下、本発明に係るGe層付き基板の製造方法の一実施形態について図1〜図7を参照して説明を行う。以下の記載において、先に説明した図面と同一の機能を有する部材には同一の番号を付し、その説明を省略する。   Hereinafter, an embodiment of a method for producing a substrate with a Ge layer according to the present invention will be described with reference to FIGS. In the following description, members having the same functions as those in the above-described drawings are denoted by the same reference numerals, and description thereof is omitted.

図1は、本実施形態に係るGe層付き基板100の製造方法における各工程の説明図である。本実施形態では、まず(a)に示すように、絶縁膜20でコーティングした基板10上にa−Ge層30を形成する。なお、基板10が絶縁性材料から成る場合には絶縁膜20は省略可能である。   FIG. 1 is an explanatory diagram of each step in the method for manufacturing the substrate 100 with a Ge layer according to the present embodiment. In this embodiment, first, as shown in (a), the a-Ge layer 30 is formed on the substrate 10 coated with the insulating film 20. If the substrate 10 is made of an insulating material, the insulating film 20 can be omitted.

次に、同図(b)に示すように、a−Ge層30上に結晶化誘起金属層40を形成する。結晶化誘起金属層40は、Geとの共晶を形成する金属を主成分とする。図では、後述の検証実験における横方向の結晶成長観察のために、結晶化誘起金属層40はa−Ge層30の上面の一部を被覆するように形成されているが、a−Ge層30の上面全体を覆うよう形成されてもよい。   Next, as shown in FIG. 2B, a crystallization inducing metal layer 40 is formed on the a-Ge layer 30. The crystallization-inducing metal layer 40 is mainly composed of a metal that forms a eutectic with Ge. In the figure, the crystallization-inducing metal layer 40 is formed so as to cover a part of the upper surface of the a-Ge layer 30 in order to observe lateral crystal growth in the verification experiment described later. It may be formed so as to cover the entire upper surface of 30.

続いて、同図(c)に示すように、結晶化誘起金属層40(及びa−Ge層30上の該結晶化誘起金属層40に被覆されていない領域)上にTEOS−SiO層50(本発明の応力印加層に相当)を形成する。TEOS−SiO層50は、プラズマCVD(plasma-enhanced chemical vapor deposition)法を用いて80℃〜200℃程度に加熱された反応管内にオルト珪酸テトラエチル(TEOS)ガスを導入することで形成される二酸化ケイ素(SiO)層である。TEOS−SiO層50の形成後、成膜装置が備える反応管内の温度を維持し所定時間放置する。この放置時間中に、TEOS−SiO層50に内在する応力によって結晶化誘起金属層40(及びa−Ge層30上の該結晶化誘起金属層40に被覆されていない領域)に圧縮又は引張の応力が印加されることとなる。いずれの応力をどの程度印加するかは、プラズマCVD法によるTEOS−SiO層50の形成条件を調整することで任意に設定することができる。 Subsequently, as shown in FIG. 3C, the TEOS-SiO 2 layer 50 is formed on the crystallization-inducing metal layer 40 (and the region not covered with the crystallization-inducing metal layer 40 on the a-Ge layer 30). (Corresponding to the stress application layer of the present invention). The TEOS-SiO 2 layer 50 is formed by introducing tetraethyl orthosilicate (TEOS) gas into a reaction tube heated to about 80 ° C. to 200 ° C. using a plasma CVD (plasma-enhanced chemical vapor deposition) method. It is a silicon dioxide (SiO 2 ) layer. After the TEOS-SiO 2 layer 50 is formed, the temperature in the reaction tube provided in the film forming apparatus is maintained and left for a predetermined time. During this standing time, the crystallization-inducing metal layer 40 (and the region not covered with the crystallization-inducing metal layer 40 on the a-Ge layer 30) is compressed or pulled by the stress inherent in the TEOS-SiO 2 layer 50. This stress is applied. How much stress is applied can be arbitrarily set by adjusting the formation conditions of the TEOS-SiO 2 layer 50 by the plasma CVD method.

〔実施例〕
本実施形態の効果を検証するため、印加応力以外の条件を全て揃えて複数の実験(実験例1〜4)を行った。具体的には、絶縁膜20としてのSiO膜でコーティングされたSi基板(基板10)上に、スパッタリング法を用いて膜厚100nmのa−Ge層30を形成した後、真空蒸着法(マスク蒸着)によりa−Ge層30上に、膜厚200nmの金(Au)層40のポルカドットパターンを形成した。そしてプラズマCVD法により、雰囲気温度150℃にて膜厚500nmのTEOS−SiO層50をAu層(結晶化誘起金属層40)上に形成した後にヒータ温度を維持し、TEOS−SiO層50の形成開始時点から60分経過した時点でGe層付き基板100を成膜装置から取り出した。製造したGe層付き基板100におけるa−Ge層30の結晶成長量をラマン分光法を用いて評価した。なお、正確を期すために、ラマン分光法において照射するレーザー光の強度を減光フィルターにより適宜に減衰させ、全ての実験例において、レーザー光照射による測定対象領域の昇温に起因する結晶化が起きていないことを顕微鏡観察により確認した。
〔Example〕
In order to verify the effect of the present embodiment, a plurality of experiments (Experimental Examples 1 to 4) were performed with all conditions other than the applied stress all being aligned. Specifically, an a-Ge layer 30 having a film thickness of 100 nm is formed on a Si substrate (substrate 10) coated with a SiO 2 film as the insulating film 20 by using a sputtering method, and then a vacuum evaporation method (mask A polka dot pattern of a gold (Au) layer 40 having a film thickness of 200 nm was formed on the a-Ge layer 30 by vapor deposition. And by the plasma CVD method, maintaining the heater temperature TEOS-SiO 2 layer 50 having a thickness of 500nm after forming on the Au layer (the crystallization inducing metal layer 40) at ambient temperature 150 ℃, TEOS-SiO 2 layer 50 When 60 minutes had elapsed from the start of the formation of the substrate, the substrate with Ge layer 100 was taken out of the film formation apparatus. The amount of crystal growth of the a-Ge layer 30 in the manufactured substrate 100 with a Ge layer was evaluated using Raman spectroscopy. For the sake of accuracy, the intensity of laser light irradiated in Raman spectroscopy is appropriately attenuated by a neutral density filter, and in all experimental examples, crystallization due to temperature rise in the measurement target region due to laser light irradiation occurs. It was confirmed by microscopic observation that it did not occur.

<実験例1:応力なし>
まず対照実験として、結晶化誘起金属層40に応力を全く印加しなかった場合(TEOS−SiO層50による印加応力値:0)の結果を図2に示す。同図(a)は、円形の結晶化誘起金属層40(Au層)の縁部付近の拡大上面図であり、図の左側に結晶化誘起金属層40、右側にa−Ge層30が示されている。同図中に白枠で示した矩形領域の部分拡大図のラマンマッピングを図2(b)に示す。同図では結晶化誘起金属層40の縁部周辺にa−Geの結晶化は確認されず、上記の矩形領域はa−Ge層30の領域と結晶化誘起金属層40の領域とに二分されている。図2(c)はラマンマッピングにより検出された各領域のラマンスペクトルを示す。a−Ge層30の領域のスペクトル130はラマンシフト280cm−1付近になだらかなピークが現れており、当該の領域でa−Geの結晶化が起きていないことを示している。a−Geが結晶化すると、その領域のスペクトルではラマンシフト300cm−1付近に急峻なピークが現れるが、そのようなピークは結晶化誘起金属層40の領域のスペクトル140にも見られなかった。すなわち、結晶化誘起金属層40の直下でも、少なくとも観測可能なほど顕著な結晶化は起きていないと考えられる。
<Experimental example 1: no stress>
First, as a control experiment, FIG. 2 shows the result when no stress is applied to the crystallization-inducing metal layer 40 (applied stress value by the TEOS-SiO 2 layer 50: 0). FIG. 4A is an enlarged top view near the edge of a circular crystallization-inducing metal layer 40 (Au layer), with the crystallization-inducing metal layer 40 on the left side and the a-Ge layer 30 on the right side. Has been. FIG. 2B shows a Raman mapping of a partially enlarged view of the rectangular area indicated by a white frame in FIG. In the same figure, the crystallization of a-Ge is not confirmed around the edge of the crystallization-inducing metal layer 40, and the rectangular region is divided into an a-Ge layer 30 region and a crystallization-inducing metal layer 40 region. ing. FIG. 2C shows a Raman spectrum of each region detected by Raman mapping. The spectrum 130 in the region of the a-Ge layer 30 has a gentle peak in the vicinity of the Raman shift of 280 cm −1 , indicating that a-Ge crystallization has not occurred in the region. When a-Ge is crystallized, a sharp peak appears in the vicinity of the Raman shift of 300 cm −1 in the spectrum of the region, but such a peak was not found in the spectrum 140 of the region of the crystallization-inducing metal layer 40. That is, it is considered that at least observable crystallization has not occurred even immediately below the crystallization-inducing metal layer 40.

<実験例2:引張応力(200MPa)>
次に、TEOS−SiO層50の内部応力により、結晶化誘起金属層40に200MPaの引張応力を印加した場合の結果を図3に示す。本実験例では同図(a)に矢印で示すように、結晶化誘起金属層40の縁部周辺を囲繞するように結晶質のGe(c−Ge)領域31が観察された。図3(b)に示すラマンマッピングの中心部に現れた、左右端よりも一段暗い斑点状の領域がc−Ge領域31である。図3(c)に示すラマンスペクトルでは、c−Ge領域31のスペクトル131はラマンシフト300cm−1付近に急峻なピークを有し、当該領域が結晶化している、すなわちa−Ge層30が横方向に結晶成長していることを示している。さらに、結晶化誘起金属層40の領域のスペクトル140においても同じ位置に僅かながらピークが出現しており、結晶化誘起金属層40の直下でも結晶化が起きていることが窺える。
<Experimental example 2: Tensile stress (200 MPa)>
Next, FIG. 3 shows the result when a tensile stress of 200 MPa is applied to the crystallization induction metal layer 40 due to the internal stress of the TEOS-SiO 2 layer 50. In this experimental example, as indicated by an arrow in FIG. 5A, a crystalline Ge (c-Ge) region 31 was observed so as to surround the periphery of the edge of the crystallization-inducing metal layer 40. A spot-like region that is one step darker than the left and right ends and appears in the center of the Raman mapping shown in FIG. 3B is the c-Ge region 31. In the Raman spectrum shown in FIG. 3C, the spectrum 131 of the c-Ge region 31 has a steep peak near the Raman shift of 300 cm −1 , and the region is crystallized, that is, the a-Ge layer 30 is lateral. It shows that the crystal grows in the direction. Further, a slight peak appears at the same position in the spectrum 140 in the region of the crystallization-inducing metal layer 40, and it can be seen that crystallization is occurring directly under the crystallization-inducing metal layer 40.

<実験例3:圧縮応力(-100MPa)>
次に、TEOS−SiO層50の内部応力により、結晶化誘起金属層40に-100MPaの圧縮応力を印加した場合の結果を図4に示す。上記実験例2と同様、結晶化誘起金属層40の縁部周辺を囲繞するc−Ge領域31が観察された(同図(a)及び(b))。その他、同図(c)に示すラマンシフトについても、300cm−1付近のピークがやや小さいものの、上記実験例2と類似の傾向が見られた。
<Experimental example 3: Compressive stress (-100 MPa)>
Next, FIG. 4 shows a result when a compressive stress of −100 MPa is applied to the crystallization induction metal layer 40 due to the internal stress of the TEOS-SiO 2 layer 50. Similar to Experimental Example 2, a c-Ge region 31 surrounding the periphery of the edge of the crystallization-inducing metal layer 40 was observed (FIGS. 1A and 1B). In addition, the Raman shift shown in FIG. 5C also showed a tendency similar to that of Experimental Example 2 although the peak near 300 cm −1 was slightly small.

<実験例4:圧縮応力(-200MPa)>
次に、TEOS−SiO層50の内部応力により、結晶化誘起金属層40に-200MPaの圧縮応力を印加した場合の結果を図5に示す。おおよその傾向としては上記実験例2及び3と同様であるが、本実験例においてはc−Ge領域31の幅、すなわち横方向の結晶成長距離が上記2例と比較して大きいとの結果を得た(同図(a)及び(b))。さらに、同図(c)に示すように、c−Ge領域31だけでなく結晶化誘起金属層40の領域のスペクトル140においてもラマンシフト300cm−1付近に急峻なピークが見られ、結晶化誘起金属層40の直下でも顕著な結晶化が起きていることが示された。
<Experimental example 4: Compressive stress (-200 MPa)>
Next, FIG. 5 shows a result when a compressive stress of −200 MPa is applied to the crystallization induction metal layer 40 due to internal stress of the TEOS-SiO 2 layer 50. The approximate tendency is the same as in the above experimental examples 2 and 3. However, in this experimental example, the result that the width of the c-Ge region 31, that is, the crystal growth distance in the lateral direction is larger than that in the above two examples. Obtained ((a) and (b) in the figure). Further, as shown in FIG. 5C, a steep peak is observed in the vicinity of the Raman shift of 300 cm −1 not only in the c-Ge region 31 but also in the spectrum 140 of the region of the crystallization-inducing metal layer 40, It was shown that significant crystallization occurred just below the metal layer 40.

<結晶成長距離の応力依存性>
実験例1〜4の結果を元に、a−Ge層30の結晶成長距離(横方向)とTEOS−SiO層50による印加応力との関係を図6に示す。同図に示すとおり、少なくとも横方向の結晶成長に関しては無応力では観察されず、また、引張応力と圧縮応力のいずれもが結晶化を促している。但し、応力値の絶対値を考慮すれば、圧縮(-200MPa)では引張(200MPa)のほぼ2倍の距離の成長が見られたため、印加応力は圧縮がより有効である可能性が高い。
<Stress dependence of crystal growth distance>
Based on the results of Experimental Examples 1 to 4, the relationship between the crystal growth distance (lateral direction) of the a-Ge layer 30 and the applied stress by the TEOS-SiO 2 layer 50 is shown in FIG. As shown in the figure, at least the lateral crystal growth is not observed without stress, and both tensile stress and compressive stress promote crystallization. However, if the absolute value of the stress value is taken into consideration, the compression (-200 MPa) shows a growth twice as long as the tension (200 MPa), and therefore it is highly likely that compression is more effective for the applied stress.

<結晶成長距離の位置依存性>
TEOS−SiO層50は、その形成領域の中央部よりも縁部においてより強い応力が働く。そのため、図7(a)に示す位置関係でa−Ge層30、結晶化誘起金属層40(Au層)パターン及びTEOS−SiO層50が積層された場合、TEOS−SiO層50の縁部近傍に位置する結晶化誘起金属層40の周辺(図7(b))では、TEOS−SiO層50の中央部により近い位置の結晶化誘起金属層40の周辺(図7(c))と比較してc−Ge領域31の幅、すなわち横方向の結晶成長距離が大きい傾向にある。また、図7(b)及び(c)によれば、結晶化誘起金属層40及びa−Ge層30に圧縮応力が印加される場合には、TEOS−SiO層50の中部央に向かってよく結晶成長が進行するようである。こうした性質を利用して、TEOS−SiO層50の形成条件の他に、TEOS−SiO層50自体の形状や、TEOS−SiO層50との位置関係を考慮した結晶化誘起金属層40パターンの配置等を工夫して結晶成長の効率化を図ることも考えられる。なお、図7は上記実験例4と同一の実験条件にて得られた画像である。
<Position dependence of crystal growth distance>
The TEOS-SiO 2 layer 50 is subjected to stronger stress at the edge than at the center of the formation region. Therefore, a-Ge layer 30 in a positional relationship shown in FIG. 7 (a), if the crystallization inducing metal layer 40 (Au layer) pattern and TEOS-SiO 2 layer 50 are stacked, the edge of the TEOS-SiO 2 layer 50 In the vicinity of the crystallization-inducing metal layer 40 located in the vicinity of the portion (FIG. 7B), the vicinity of the crystallization-inducing metal layer 40 in a position closer to the central portion of the TEOS-SiO 2 layer 50 (FIG. 7C). The width of the c-Ge region 31, that is, the crystal growth distance in the lateral direction tends to be large. Further, according to FIGS. 7B and 7C, when compressive stress is applied to the crystallization-inducing metal layer 40 and the a-Ge layer 30, the TEOS-SiO 2 layer 50 is moved toward the center of the center. Crystal growth seems to progress well. Using these properties, in addition to the conditions for forming the TEOS-SiO 2 layer 50, the shape of the TEOS-SiO 2 layer 50 itself, the crystallization inducing metal layer with consideration of the position relationship between the TEOS-SiO 2 layer 50 40 It is conceivable to improve the efficiency of crystal growth by devising the arrangement of patterns. FIG. 7 is an image obtained under the same experimental conditions as in Experimental Example 4.

<実験例5:圧縮応力(-200MPa)+雰囲気温度80℃>
さらなる低温化の試みとして、上記実験例4において、TEOS−SiO層50の形成時の雰囲気温度を80℃としたところ、ラマンマッピングで僅かではあるもののc−Ge領域が検出された。この検出されたc−Ge領域のラマンスペクトルでも、ラマンシフト300cm−1付近に小さなピークが見られ、本実験例のような低温環境下でもa−Ge層30が横方向に結晶成長していることが示された。
<Experimental Example 5: Compressive stress (-200 MPa) + Ambient temperature 80 ° C.>
As an attempt to further lower the temperature, in Experimental Example 4 described above, when the ambient temperature during the formation of the TEOS-SiO 2 layer 50 was set to 80 ° C., the c-Ge region was detected although it was slight by Raman mapping. Even in the detected Raman spectrum of the c-Ge region, a small peak is observed in the vicinity of the Raman shift of 300 cm −1 , and the a-Ge layer 30 grows in the lateral direction even under the low temperature environment as in this experimental example. It was shown that.

以上のとおり、本実施例によれば、TEOS−SiO層50が印加する応力により、結晶化誘起金属層40との境界から開始するa−Ge層30の結晶化を極低温(150℃以下)にて実現することができる。この温度であれば軽量性に優れたポリカーボネートや比較的安価なPET等の樹脂材料を基板として用いても熱処理で軟化することがない。従って、フレキシブル基板上に成膜された非晶質のゲルマニウム層の結晶化を容易に実現することができ、これにより軽量かつ安価なフレキシブルデバイスの実現に寄与する。
さらに、印加応力はプラズマCVD法によるTEOS−SiO層50の形成条件によって自在に調整が可能であり、低温での層形成にも適している。
また、TEOS−SiO層50はマスキング等により基板10上の目的箇所にのみ形成可能であるため、基板10の他の箇所に不要な、時には基板や基板上の部品の破損等を引き起こし得る有害な応力を印加することがない。
As described above, according to the present embodiment, crystallization of the a-Ge layer 30 starting from the boundary with the crystallization-inducing metal layer 40 is performed at a very low temperature (150 ° C. or less) by the stress applied by the TEOS-SiO 2 layer 50. ). If it is this temperature, even if it uses resin materials, such as polycarbonate excellent in the lightness and comparatively cheap PET, as a board | substrate, it does not soften by heat processing. Therefore, crystallization of the amorphous germanium layer formed on the flexible substrate can be easily realized, thereby contributing to the realization of a lightweight and inexpensive flexible device.
Furthermore, the applied stress can be freely adjusted according to the formation conditions of the TEOS-SiO 2 layer 50 by the plasma CVD method, and is suitable for forming a layer at a low temperature.
In addition, since the TEOS-SiO 2 layer 50 can be formed only at a target location on the substrate 10 by masking or the like, it is unnecessary at other locations on the substrate 10 and sometimes causes damage to the substrate or components on the substrate. Stress is not applied.

本発明は上述した実施例に限定されるものではなく、本発明の趣旨の範囲で適宜変更が許容される。例えば、結晶化誘起金属層40を構成する主な成分は上記実施例で用いたAuに限定されず、例えば錫(Sn)、銀(Ag)及びアルミニウム(Al)等、Geと共晶を作る性質を持つ金属材料であればよい。   The present invention is not limited to the above-described embodiments, and appropriate modifications are allowed within the scope of the gist of the present invention. For example, the main component constituting the crystallization-inducing metal layer 40 is not limited to Au used in the above-described embodiments, and for example, eutectic is formed with Ge such as tin (Sn), silver (Ag), and aluminum (Al). Any metal material having properties may be used.

なお、上述の実験例1〜5では比較のために熱処理時間を60分に統一しているが、この時間をさらに延長すれば結晶成長距離はもちろん増大する。また、雰囲気温度150℃に関しても、これをさらに高温にすれば結晶成長はより促進されるので、基板として用いる材料の軟化点に応じて適宜設定すればよい。例えば、ポリイミド基板であれば280℃程度の高温にも耐えられる。また、各層の膜厚も上述した値に限定されるものではなく、任意に変更が可能である。   In the experimental examples 1 to 5 described above, the heat treatment time is unified to 60 minutes for comparison, but if this time is further extended, the crystal growth distance naturally increases. Further, regarding the atmospheric temperature of 150 ° C., if the temperature is further increased, crystal growth is further promoted, so that it may be appropriately set according to the softening point of the material used as the substrate. For example, a polyimide substrate can withstand a high temperature of about 280 ° C. Moreover, the film thickness of each layer is not limited to the above-mentioned value, and can be arbitrarily changed.

10…基板
100…Ge層付き基板
130…a−Ge層領域のラマンスペクトル
131…c−Ge領域のラマンスペクトル
140…結晶化誘起金属層領域のラマンスペクトル
20…絶縁膜
30…a−Ge層
31…c−Ge領域
40…結晶化誘起金属層
50…TEOS−SiO
DESCRIPTION OF SYMBOLS 10 ... Substrate 100 ... Ge layered substrate 130 ... Raman spectrum 131 in a-Ge layer region ... Raman spectrum in c-Ge region 140 ... Raman spectrum in crystallization-induced metal layer region 20 ... Insulating film 30 ... a-Ge layer 31 ... c-Ge region 40 ... crystallization-inducing metal layer 50 ... TEOS-SiO 2 layer

Claims (4)

a) 基板上に非晶質のゲルマニウム層を形成する工程と、
b) 前記形成したゲルマニウム層上に、非晶質ゲルマニウムの結晶化を促す結晶化誘起金属層を形成する工程と、
c) 前記結晶化誘起金属層上に、前記結晶化誘起金属層に応力を印加する応力印加層を、雰囲気温度80℃〜280℃にてプラズマ蒸着法により形成する工程と、
を含むことを特徴とするゲルマニウム層付き基板の製造方法。
a) forming an amorphous germanium layer on the substrate;
b) forming a crystallization-inducing metal layer that promotes crystallization of amorphous germanium on the formed germanium layer;
c) forming a stress applying layer for applying stress to the crystallization-inducing metal layer on the crystallization-inducing metal layer by a plasma deposition method at an ambient temperature of 80 ° C. to 280 ° C .;
The manufacturing method of the board | substrate with a germanium layer characterized by including these.
さらに、前記応力印加層をプラズマ蒸着法により形成した後、雰囲気温度を維持して所定時間放置する工程Furthermore, after the stress applying layer is formed by a plasma deposition method, the step of maintaining the ambient temperature and leaving it for a predetermined time
を有することを特徴とする請求項1に記載のゲルマニウム層付き基板の製造方法。  The manufacturing method of the board | substrate with a germanium layer of Claim 1 characterized by the above-mentioned.
前記応力印加層は二酸化ケイ素層であることを特徴とする請求項1又は2に記載のゲルマニウム層付き基板の製造方法。 Method for producing a germanium layer-attached substrate according to claim 1 or 2, characterized in that the stress applying layer is a silicon dioxide layer. 前記応力印加層はオルトケイ酸テトラエチルを原料として形成される二酸化ケイ素層であることを特徴とする請求項に記載のゲルマニウム層付き基板の製造方法。 The method of manufacturing a substrate with a germanium layer according to claim 3 , wherein the stress application layer is a silicon dioxide layer formed using tetraethyl orthosilicate as a raw material.
JP2014144759A 2014-07-15 2014-07-15 Method for manufacturing substrate with germanium layer and substrate with germanium layer Active JP6312134B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014144759A JP6312134B2 (en) 2014-07-15 2014-07-15 Method for manufacturing substrate with germanium layer and substrate with germanium layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014144759A JP6312134B2 (en) 2014-07-15 2014-07-15 Method for manufacturing substrate with germanium layer and substrate with germanium layer

Publications (2)

Publication Number Publication Date
JP2016021503A JP2016021503A (en) 2016-02-04
JP6312134B2 true JP6312134B2 (en) 2018-04-18

Family

ID=55266169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014144759A Active JP6312134B2 (en) 2014-07-15 2014-07-15 Method for manufacturing substrate with germanium layer and substrate with germanium layer

Country Status (1)

Country Link
JP (1) JP6312134B2 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3933793B2 (en) * 1998-06-16 2007-06-20 富士通株式会社 Method for forming silicon oxide film and method for manufacturing thin film magnetic head
JP2000299473A (en) * 1999-04-02 2000-10-24 Sharp Corp Selection type silicide thin film transistor and manufacture thereof
JP4302357B2 (en) * 2001-04-06 2009-07-22 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP4326734B2 (en) * 2001-11-16 2009-09-09 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP2010232401A (en) * 2009-03-27 2010-10-14 Hiroshima Univ Crystal semiconductor manufacturing method and semiconductor device manufacturing method using the same

Also Published As

Publication number Publication date
JP2016021503A (en) 2016-02-04

Similar Documents

Publication Publication Date Title
JP2011142310A5 (en) Method for manufacturing semiconductor device
WO2010096646A3 (en) Graphene processing for device and sensor applications
JP6517678B2 (en) Method of manufacturing electronic device
CN103681776B (en) Low-temperature polysilicon film and preparation method thereof, thin film transistor (TFT) and display device
JP4589295B2 (en) Thin film transistor and manufacturing method thereof
JP2008311621A5 (en)
JP2009004736A5 (en)
TW201138093A (en) Method of manufacturing flexible display device
JP2009010353A5 (en)
JP2009528696A (en) Amorphous Silicon Joule Heating Crystallization Method (Method for Crystallization of Amorphous Silicone Joule Heating)
WO2009066949A3 (en) Fabricating method of polycrystalline silicon thin film, polycrystalline silicon thin film fabricated using the same
TWI567999B (en) Thin film transistor array substrate structure and manufacturing method thereof
JP2010283337A5 (en)
TW201712805A (en) Polycrystalline germanium thin film transistor element and manufacturing method thereof
JP2010103514A5 (en)
JP2010157721A5 (en)
WO2015100827A1 (en) Method for defining growth direction of polysilicon
JP6312134B2 (en) Method for manufacturing substrate with germanium layer and substrate with germanium layer
JP6081689B2 (en) Polycrystalline silicon layer, thin film transistor, and organic electroluminescent display device manufacturing method
WO2015192558A1 (en) Low-temperature polysilicon thin film transistor and manufacturing method thereof, array substrate and display device
EP2741314A3 (en) Method of manufacturing a poly-crystalline silicon layer, method of manufacturing an organic light-emitting display apparatus including the same, and organic light-emitting display apparatus manufactured by using the same
JP2009094490A5 (en)
US9218968B2 (en) Method for forming crystalline thin-film and method for manufacturing thin film transistor
JP2011192908A (en) Method of manufacturing polysilicon film, solar cell, and electronic device
JP2009033144A5 (en)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170428

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20170428

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20171121

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20171205

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180130

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180213

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180314

R150 Certificate of patent or registration of utility model

Ref document number: 6312134

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250