JP6305791B2 - Power supply circuit - Google Patents

Description

  The present invention relates to a power supply circuit.

In a power supply circuit that supplies power output from a solar battery to a load, a circuit is known in which a secondary battery that stores the output of the power supply circuit is provided on the load side (see, for example, Patent Document 1).
Japanese Patent Application Laid-Open No. 2007-089373

  A conventional power supply circuit supplies power to the secondary battery and the load from the same terminal. For this reason, there is a waiting time until the voltage of the secondary battery rises to the load drive voltage and the load is driven. Further, if the capacity of the secondary battery is reduced in order to shorten the waiting time, the operating time of the load when power generation is stopped is shortened.

  In the first aspect of the present invention, a power supply circuit that outputs output power to a load according to input power generated by a power generation device, having a supply terminal, and supplying according to input input power An input / output unit that outputs power from the supply terminal, a power storage terminal connected to a power storage device that stores power from the supply terminal, and a capacity smaller than the capacity of the power storage device, and stores power from the supply terminal Whether to connect the capacitor terminal to which the capacitor is connected, the load terminal to which the supplied power or the stored power stored in the power storage device is input and output the output power to the load, and the storage terminal to the supply terminal and the load terminal And a first switching control unit that switches on / off of the first switch depending on whether or not the voltage of the capacitor terminal exceeds a predetermined power storage device storage start voltage. The first switching control unit includes a first reference voltage generation unit that generates a predetermined first reference voltage corresponding to the storage device storage start voltage, and a first CMOS inverter, and the first reference voltage is that of the first CMOS inverter. A first comparator which is input to the input terminal and the voltage of the capacitor terminal is input to the power supply terminal of the first CMOS inverter. The first comparator determines whether the output of the first CMOS inverter is inverted or not. Provides a power supply circuit that detects whether or not the power storage device storage start voltage has been exceeded.

  The summary of the invention does not enumerate all the features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

An outline of the configuration of the power supply circuit 100 is shown. A specific configuration of the power supply circuit 100 according to the present embodiment is shown. 2 shows an exemplary configuration of a power supply circuit 100. An overview of the configuration of the first switching control unit 310 is shown. An example of the configuration of the one-stage configuration switching control unit 350 is shown. 2 shows an exemplary configuration of an overcharge prevention circuit 200. 2 shows an exemplary configuration of a power supply circuit 100. An example of the configuration of the two-stage configuration switching control unit 360 is shown. The magnitude relationship of the operation threshold voltage is shown. 6 is a flowchart showing an example of the operation of the overcharge prevention circuit 200. FIG. It is a flowchart which shows an example of operation | movement of the 3rd switch F3. It is a flowchart which shows an example of operation | movement of the 1st switch F1. It is a flowchart which shows an example of operation | movement of the 2nd switch F2. An example of the operation of the power supply circuit 100 is shown. 2 shows an exemplary configuration of a power supply circuit 100. An example of the configuration of the switching circuit 400 is shown. An example of the operation of the switching circuit 400 is shown. 2 shows an exemplary configuration of a power supply circuit 100. 2 shows an exemplary configuration of a power supply circuit 100. An example of the operation of the switching control circuit 340 is shown. An example of the configuration of the comparator 50 is shown. 6 shows an example of a configuration for setting a reference voltage of a switching control circuit 340. An outline of a reference voltage detection method in the reference voltage detection mode will be described. The basic circuit with which the reference voltage generation part 20 which concerns on this embodiment is provided is shown. The non-volatile memory element 90 provided with a tunnel oxide film is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. It is a flowchart which shows an example of the setting method of a reference voltage. It is a figure for demonstrating the setting method of a reference voltage. A method for setting the nonvolatile memory element 90 will be described. An example of the operation of the switching control circuit 340 in the reference voltage setting mode is shown. An example of a write operation to the second write MOS transistor M2w will be described. An example of the operation of the switching control circuit 340 in the reference voltage setting mode is shown. A write operation to the first write MOS transistor M1w will be described. An example of the circuit structure of the reference voltage generation part 20 which concerns on this embodiment is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. The change amount of the threshold voltage Vth with respect to the writing time of the first control pulse is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. The change of the threshold voltage Vth in the adjustment sequences (2) and (3) is shown. The change of the threshold voltage Vth when the confirmation sequence is used is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. An example of a circuit configuration of the reference voltage generation unit 20 is shown. The change of the threshold voltage Vth in the adjustment sequences (4) and (5) is shown. It is a figure which shows the example of a connection of the current mirror 71. FIG. An example of the configuration of the switching control circuit 340 in the actual operation mode is shown. Another connection example of the first MOS transistor M1 and the second MOS transistor M2 in the reference voltage generation unit 20 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows an outline of the configuration of a power supply circuit 100 according to the present invention. The power supply circuit 100 outputs the output power Pout to the load 15 according to the input power Pin generated by the power generation device 10. The power supply circuit 100 includes an overcharge prevention circuit 200, a switching control unit 300, a capacitor 500, and a power storage device 550, and is connected to the power generation device 10 and the load 15. The power supply circuit 100 may include the power generation device 10 and the load 15 themselves. The power supply circuit 100 has an input terminal VI to which the input power Pin is input and an output terminal VOUT that outputs the output power Pout.

  The power generation device 10 is an environmental power generation device that generates electric power based on photoelectric conversion such as outdoor light or indoor light, or environmental energy such as a thermoelectric conversion element such as Peltier. The power generation device 10 outputs the generated input power Pin to the overcharge prevention circuit 200. The power generation device 10 may be a dye-sensitized solar cell in addition to a general silicon type solar cell. Further, the power generation device 10 may be a power generation device with a small input power Pin that is configured by a one-cell solar cell or the like. As the ambient light changes, the input power Pin increases or decreases.

  The overcharge prevention circuit 200 controls the voltage of the capacitor 500 within a predetermined range to prevent the capacitor 500 from being overcharged. That is, the overcharge prevention circuit 200 prevents overcharging of the capacitor 500 by switching whether to output the input power Pin from the supply terminal VDDC as the supply power Pddc. Further, the overcharge prevention circuit 200 automatically starts charging the capacitor 500 when the voltage at the capacitor terminal VO becomes lower than a predetermined voltage. The overcharge prevention circuit 200 is an example of an input / output unit, and may have a function other than the overcharge prevention function.

  The switching control unit 300 switches the connection of the connected overcharge prevention circuit 200, the load terminal VOUT, the capacitor terminal VO, and the storage terminal VS. For example, the switching control unit 300 switches independently whether or not to connect the supply terminal VDDC and the load terminal VOUT and whether or not to connect the supply terminal VDDC and the storage terminal VS. In addition, the switching control unit 300 switches whether to connect the power storage terminal VS and the load terminal VOUT. Note that the load 15, the capacitor 500, and the power storage device 550 are connected to the load terminal VOUT, the capacitor terminal VO, and the power storage terminal VS, respectively.

  The load 15 is operated by the output power Pout output from the switching control unit 300. The switching control unit 300 may output the output power Pout to the load 15 when the output power Pout rises above a voltage necessary for the operation of the load 15.

  Capacitor 500 temporarily stores supplied power Pddc until power necessary for operation of load 15 is stored. The capacity of the capacitor 500 is smaller than the capacity of the power storage device 550. A part of the supplied power Pddc output from the overcharge prevention circuit 200 may be stored in the capacitor 500.

  The power storage device 550 stores surplus power that is not consumed by the load 15 and the capacitor 500 out of the supplied power Pddc output from the overcharge prevention circuit 200. The power storage device 550 drives the load 15 as a voltage compensation capacitor when the power generation amount of the power generation device 10 decreases. Capacitor 500 and power storage device 550 may be provided outside power supply circuit 100.

  The switching control unit 300 controls each connection based on the voltages of the supply terminal VDDC, the capacitor terminal VO, the power storage terminal VS, and the load terminal VOUT. For example, the switching control unit 300 outputs the supplied power Pddc to the capacitor terminal VO when the voltage of the supply terminal VDDC exceeds a predetermined capacitor storage start voltage. The switching control unit 300 outputs power from the capacitor 500 and the overcharge prevention circuit 200 to the load terminal VOUT when the capacitor 500 is charged and the voltage of the capacitor terminal VO exceeds a predetermined power supply start voltage. . The power supply start voltage may be smaller than the capacitor storage start voltage.

  The switching control unit 300 outputs the supplied power Pddc to the load terminal VOUT and the storage terminal VS when the voltage of the capacitor terminal VO exceeds the storage device storage start voltage larger than the capacitor storage start voltage and the power supply start voltage. To do. Thereby, the power supply circuit 100 can store the power storage device 550 while supplying the output power Pout to the load 15. Since the power supply circuit 100 of this example does not connect the large-capacity power storage device 550 to the overcharge prevention circuit 200 and starts connecting the small-capacitance capacitor 500 to the overcharge prevention circuit 200 at the start of driving the load 15, Can be shortened.

  When the input power Pin is less than the power necessary for the operation of the overcharge prevention circuit 200, the switching control unit 300 cuts off the supplied power Pddc and outputs the stored power stored in the power storage device 550 to the load terminal VOUT. . As a result, the power supply circuit 100 compensates for the operation of the load 15 when the input power Pin decreases.

  FIG. 2 shows a specific configuration of the power supply circuit 100 according to the present embodiment. The switching control unit 300 switches the supply power Pddc output from the overcharge prevention circuit 200 with a switch and supplies it to the load 15, the capacitor 500, and the power storage device 550. The switching control unit 300 includes a first switch F1, a second switch F2, a third switch F3, a first switching control unit 310, a second switching control unit 320, and a third switching control unit 330.

  The first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 have a power supply terminal VDD and an output terminal OUT, respectively. The first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 output high or low from the output terminal OUT according to the voltage input to the power supply terminal VDD.

  The first switch F1 switches whether the power storage terminal VS is connected to the supply terminal VDDC and the load terminal VOUT. One end of the first switch F1 is connected to the power storage terminal VS, and the other end is connected to the second switch F2 and the third switch F3.

  The first switching control unit 310 controls the first switch F1 so as to prevent the output power Pout output to the load 15 from decreasing. The first switching control unit 310 controls on / off of the first switch F1 based on the voltage of the capacitor terminal VO. The first switching control unit 310 outputs low when the voltage of the capacitor terminal VO is smaller than a predetermined voltage generated in the first switching control unit 310, and when the voltage is higher than the predetermined value. Output high.

  The second switch F2 switches whether to connect the load terminal VOUT to the supply terminal VDDC and the power storage terminal VS. One end of the second switch F2 is connected to the load terminal VOUT, and the other end is connected to the first switch F1 and the third switch F3.

  The second switching control unit 320 controls the second switch F2 so that the output power Pout is output only when the capacitor 500 is sufficiently charged and the output power Pout reaches the voltage at which the load 15 operates. . The second switching control unit 320 controls on / off of the second switch F2 based on the voltage of the capacitor terminal VO. The second switching control unit 320 outputs low when the voltage of the capacitor terminal VO is smaller than a predetermined voltage generated in the second switching control unit 320, and is greater than or equal to the predetermined voltage. Output high.

  The third switch F3 switches whether the supply terminal VDDC is connected to the load terminal VOUT and the power storage terminal VS. One end of the third switch F3 is connected to the supply terminal VDDC, and the other end is connected to the first switch F1 and the second switch F2. The capacitor terminal VO in this example is connected to the other end of the first switch F1, the second switch F2, and the third switch F3.

  The third switching control unit 330 controls the third switch F3 so as to stabilize the output of the power generation device 10. Specifically, the output voltage of the power generation apparatus 10 is prevented from decreasing and the power generation efficiency is increased. Further, the third switching control unit 330 prevents the power stored in the capacitor 500 and the power storage device 550 from flowing back to the power generation device 10 side when the power generation device 10 is not sufficiently irradiated with light. The third switching control unit 330 controls the third switch F3 based on the voltage of the supply terminal VDDC. The third switching control unit 330 outputs low when the voltage of the supply terminal VDDC is smaller than a predetermined voltage generated in the third switching control unit 330, and in a case where the voltage is higher than the predetermined value. Output high.

  FIG. 3 shows an exemplary configuration of the power supply circuit 100. The power supply circuit 100 of this example further includes an overdischarge prevention circuit 250. The overcharge prevention circuit 200 of this example includes an overcharge prevention switching control unit 210, a shunt circuit 220, and an overcharge prevention switching unit 230. The first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 are provided with a common power supply terminal VDD.

  The overcharge prevention switching control unit 210 controls the shunt circuit 220 and the overcharge prevention switching unit 230 so as to prevent the capacitor 500 from being overcharged. The overcharge prevention switching control unit 210 detects the voltage of the capacitor terminal VO and outputs a signal according to whether or not the voltage of the capacitor terminal VO exceeds the overcharge prevention skip start voltage. The overcharge prevention switching control unit 210 outputs the output signal to the shunt circuit 220 and the overcharge prevention switching unit 230. The overcharge prevention switching control unit 210 causes the shunt circuit 220 and the overcharge prevention switching unit 230 to perform complementary operations. The reference terminal VSS of the overcharge prevention switching control unit 210 is connected to the ground 3.

  The shunt circuit 220 switches whether or not to connect the input terminal VI of the power supply circuit 100 to a potential lower than the output voltage of the power generation apparatus 10. The shunt circuit 220 includes an NMOS transistor and a free wheel diode. The output terminal VOU of the overcharge prevention switching control unit 210 is connected to the gate terminal of the NMOS transistor. The drain terminal of the NMOS transistor is connected to the input terminal VI of the power supply circuit 100, and the source terminal is connected to the ground 3. The free-wheeling diode of the shunt circuit 220 is provided in the direction opposite to the output of the power generation device 10.

  The overcharge prevention switching unit 230 switches whether to connect the input terminal VI and the capacitor terminal VO of the power supply circuit 100. The overcharge prevention switching unit 230 includes two PMOS transistors connected in series. The gate terminal of each PMOS transistor is connected to the output terminal VOU of the overcharge prevention switching control unit 210. A source terminal at one end of the overcharge prevention switching unit 230 is connected to the input terminal VI of the power supply circuit 100. Multi-terminal drain terminals of the overcharge prevention switching unit 230 are connected to the capacitor 500 and the power storage device 550, respectively. The PMOS transistor of the overcharge prevention switching unit 230 has a free-wheeling diode provided with a diode opposite in direction.

  For example, the overcharge prevention switching control unit 210 outputs high when the capacitor terminal VO exceeds the overcharge prevention skip start voltage (when overcharge is detected). Then, the NMOS transistor of the shunt circuit 220 is turned on, and the PMOS transistor of the overcharge prevention switching unit 230 is turned off. As a result, overcharging of the capacitor 500 is prevented, and the output of the power generation device 10 is reduced.

  When the overcharge prevention switching unit 230 is turned off, the shunt circuit 220 connects the source terminal of the overcharge prevention switching unit 230 to the ground. That is, even when the output of the power generation device 10 increases, the voltage of the source terminal of the overcharge prevention switching unit 230 is kept constant, so that the overcharge prevention switching unit 230 is reliably turned off.

  Thereafter, when the capacity of the capacitor 500 decreases and becomes smaller than the overcharge prevention skip start voltage, the overcharge prevention switching control unit 210 outputs low. Then, the NMOS transistor of the shunt circuit 220 is turned off, and the PMOS transistor of the overcharge prevention switching unit 230 is turned on. Thereby, charging of the capacitor 500 is started.

  Thus, the overcharge prevention circuit 200 has an overcharge prevention function for preventing overcharge of the capacitor 500 when overcharge is detected. Furthermore, the overcharge prevention circuit 200 has an automatic charging start function that automatically starts charging the capacitor 500 when the voltage at the capacitor terminal VO decreases.

  Overdischarge prevention circuit 250 prevents overdischarge of power storage device 550. The overdischarge prevention circuit 250 includes an overdischarge prevention switching control unit 260 and an overdischarge prevention switching unit 270. The power terminal VDD of the overdischarge prevention switching control unit 260 is connected to the power storage terminal VS, and the output terminal VOU is connected to the overdischarge prevention switching unit 270. The reference terminal VSS of the overdischarge prevention switching control unit 260 is connected between the power storage device 550 and the overdischarge prevention switching unit 270.

  Overdischarge prevention switching unit 270 prevents overdischarge of power storage device 550. The overdischarge prevention switching unit 270 includes an NMOS transistor and a freewheeling diode. The gate terminal of the NMOS transistor is connected to the output terminal VOU of the overdischarge prevention switching control unit 260. For example, the reflux diode of the overdischarge prevention switching unit 270 is provided in the opposite direction to the reflux diode of the first switch F1.

  The first switch F1 of this example includes an NMOS transistor and a free wheel diode. The NMOS transistor and the free wheel diode of the first switch F1 are connected in parallel. The output terminal VOU of the first switching control unit 310 is connected to the gate terminal of the NMOS transistor. One end of the NMOS transistor of the first switch F1 is connected to the NMOS transistor of the overdischarge prevention switching unit 270, the other end is connected to the ground 2, and is connected to the ground 1 through the second switch F2. The free-wheeling diode is provided in a direction to prevent power storage of the power storage device 550 when the first switch F1 is off.

  The second switch F2 of this example includes an NMOS transistor and a free wheel diode. The NMOS transistor and the free wheel diode of the second switch F2 are connected in parallel. The output terminal VOU of the second switching control unit 320 is connected to the gate terminal of the NMOS transistor. One end of the NMOS transistor of the second switch F2 is connected to the first switch F1 and the third switch F3, and the other end is connected to the load 15 and the ground 1. The reflux diode of the second switch F2 is provided in a direction that prevents the load 15 from being charged.

  The third switch F3 of this example has two NMOS transistors connected in series. The output terminal VOU of the third switching control unit 330 is connected to the gate terminal of each NMOS transistor. One end of the third switch F3 is connected to the ground 3, which is the negative side of the power generation apparatus 10, and the other end is connected to the ground 2, and is connected to the load 15 and the ground 1 via the second switch F2. Each NMOS transistor of the third switch F3 has a free-wheeling diode in which the direction of the diode is opposite.

  For example, the overcharge prevention switching control unit 210 turns on the shunt circuit 220 and turns off the overcharge prevention switching unit 230 by outputting high when the voltage of the capacitor terminal VO exceeds 3.4V. Thereafter, when the voltage at the capacitor terminal VO is smaller than 3.3 V, a low is output, thereby turning off the shunt circuit 220 and turning on the overcharge prevention switching unit 230. By repeating such a hysteresis operation, the voltage of the capacitor terminal VO is controlled in the range of 3.3 V to 3.4 V, and overcharging of the capacitor terminal VO is prevented.

  The overdischarge prevention circuit 250 outputs high when the voltage of the power storage terminal VS exceeds 2.3 V, and turns on the overdischarge prevention switching unit 270. Thereafter, when the voltage of the power storage terminal VS is smaller than 2.2 V, low is output, and the overdischarge prevention switching unit 270 is turned off. Thereby, overdischarge prevention circuit 250 prevents overcharge of power storage device 550.

  The first switching control unit 310 outputs high when the voltage at the capacitor terminal VO exceeds 3.2 V, and turns on the first switch F1. Thereafter, when the voltage at the capacitor terminal VO is smaller than 3.1 V, low is output and the first switch F1 is turned off. Thereby, the 1st switching control part 310 prevents the fall of output electric power Pout.

  The second switching control unit 320 outputs high when the voltage at the capacitor terminal VO exceeds 2.5 V, and turns on the second switch F2. Thereafter, when the voltage at the capacitor terminal VO is smaller than 2.2V, a low is output, and the second switch F2 is turned off. Thereby, the 2nd switching control part 320 starts the output to the load 15 of the output electric power Pout, when the capacitor | condenser 500 is electrically charged to the voltage which a system operate | moves.

  The third switching control unit 330 outputs high when the voltage at the supply terminal VDDC exceeds 3.2 V, and turns on the third switch F3. Thereafter, when the voltage of the supply terminal VDDC is smaller than 3.1 V, low is output, and the third switch F3 is turned off. Thereby, the 3rd switching control part 330 prevents the fall of the output voltage of the electric power generating apparatus 10, and raises electric power generation efficiency. Further, the third switching control unit 330 prevents the power stored in the capacitor 500 and the power storage device 550 from flowing back to the power generation device 10 side when the power generation device 10 is not sufficiently irradiated with light.

  FIG. 4 shows an outline of the configuration of the switching control circuit 340. The switching control circuit 340 is a CMOS inverter comparator type switching circuit. The CMOS inverter comparator type switching circuit operates with low power consumption. The switching control circuit 340 includes a reference voltage generation unit 20, an inverter 30, a voltage selection unit 40, a comparator 50, a power supply terminal VDD, and an output terminal VOU. For example, the overcharge prevention switching control unit 210, the overdischarge prevention switching control unit 260, the first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 are examples of the switching control circuit 340.

  The switching control circuit 340 operates in a hysteresis manner and outputs a signal corresponding to the input voltage Vin input to the power supply terminal VDD from the output terminal VOU. The switching control circuit 340 controls whether to output high or low from the output terminal VOU depending on whether or not the input voltage Vin exceeds a predetermined operation threshold voltage. The operation threshold voltage has two different values of the upper operation threshold voltage and the lower operation threshold voltage. The switching control circuit 340 realizes a hysteresis operation by changing the value of the operation threshold voltage to the upper operation threshold voltage and the lower operation threshold voltage.

  The reference voltage generation unit 20 generates a predetermined reference voltage corresponding to the operation threshold voltage (target voltage). The reference voltage generation unit 20 of this example includes an upper reference voltage generation unit 25 and a lower reference voltage generation unit 26 each having a nonvolatile memory element. The reference voltage generation unit 20 adjusts the reference voltage generated by the upper reference voltage generation unit 25 and the lower reference voltage generation unit 26 by adjusting the nonvolatile memory element.

  The upper reference voltage generation unit 25 generates a predetermined upper reference voltage VrefH corresponding to the upper operation threshold voltage and outputs it to the voltage selection unit 40. The lower reference voltage generation unit 26 generates a predetermined lower reference voltage VrefL corresponding to the lower operation threshold voltage and outputs it to the voltage selection unit 40. The lower reference voltage VrefL may be smaller than the upper reference voltage VrefH.

  The voltage selection unit 40 selects either the upper reference voltage VrefH or the lower reference voltage VrefL and outputs the selected voltage to the comparator 50. Specifically, the voltage selection unit 40 selects the lower reference voltage VrefL when the input voltage Vin exceeds a threshold voltage determined by the upper reference voltage VrefH. The voltage selection unit 40 selects the upper reference voltage VrefH when the input voltage Vin is equal to or lower than a threshold voltage determined by the lower reference voltage VrefL. Accordingly, the first switching control unit 310 operates in a hysteresis manner with a voltage between the upper operation threshold voltage and the lower operation threshold voltage.

  The output of the comparator 50 changes depending on whether or not the input voltage Vin exceeds the operation threshold voltage. In this example, when the input voltage Vin is equal to or lower than the operation threshold voltage, the output of the comparator 50 is a reference potential such as a ground potential. In addition, when the input voltage Vin exceeds the operation threshold voltage, the output of the comparator 50 is substantially equal to the voltage input to the power supply terminal VDD. The comparator 50 determines whether the voltage input to the power supply terminal VDD exceeds the operation threshold voltage based on whether the output is inverted. In this specification, the output of the comparator 50 indicates that the output of the comparator 50 changes from the reference potential to the voltage input to the power supply terminal VDD and the voltage input to the power supply terminal VDD changes to the reference potential. Is referred to as “invert”.

  The inverter 30 switches on / off according to the output signal of the comparator 50. In the switching control circuit 340, the inverter 30 outputs the input voltage Vin from the output terminal VOU when the input voltage Vin exceeds the operation threshold voltage. On the other hand, the inverter 30 blocks the output of the input voltage Vin from the output terminal VOU when the input voltage Vin is equal to or lower than the operation threshold voltage.

  Note that the configuration of the switching control circuit 340 of this example is that the overcharge prevention switching control unit 210, the overdischarge prevention switching control unit 260, the first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 are configured. The same applies to the case. In that case, each of the operation threshold voltages may be set to an arbitrary value. For example, the operation threshold voltages of the first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 can be read as the storage device storage start voltage, the power supply start voltage, and the capacitor storage start voltage, respectively.

  FIG. 5 shows an example of the configuration of the one-stage configuration switching control unit 350. The one-stage configuration switching control unit 350 includes a reference voltage generation unit 20, a first voltage selection unit 41, and a first comparator 51. The first voltage selection unit 41 includes switches SWH and SWL and a NOT circuit. In the power supply circuit 100 shown in FIG. 3, the overcharge prevention switching control unit 210, the overdischarge prevention switching unit 270, the first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 are all. A one-stage configuration switching control unit 350 is used.

  The upper reference voltage VrefH output from the upper reference voltage generation unit 25 is input to the switch SWH. On the other hand, the lower reference voltage VrefL output from the lower reference voltage generator 26 is input to the switch SWL. The switches SWH and SWL output the input reference voltage to the positive input terminal of the first comparator 51.

  The switch SWH is turned on / off according to a signal obtained by inverting the output of the first comparator 51 by the NOT circuit. On the other hand, the switch SWL is turned on / off according to the signal output from the first comparator 51. The switches SWH and SWL in this example are controlled so that the on / off state is reversed. For example, when the output of the first comparator 51 is high, SWH is turned off and SWL is turned on. On the other hand, when the output of the first comparator 51 is low, SWH is turned on and SWL is turned off.

  The first inverter 53 is provided between the power supply terminal VDD and the output terminal VOU. The first inverter 53 inverts the output of the first comparator 51 and outputs it to the output terminal VOU. The first inverter 53 includes a one-stage CMOS inverter circuit composed of a PMOS transistor and an NMOS transistor, and a free-wheeling diode is provided in parallel with each transistor. The positive power supply terminal of the CMOS inverter circuit of the first inverter 53 is connected to the power supply terminal VDD, and the negative power supply terminal is connected to the ground. The free-wheeling diode of the first inverter 53 is provided in such a direction as to cut off the current flowing from the power supply terminal VDD when the transistor of the first inverter 53 is turned off.

  For example, when the first comparator 51 outputs high, the one-stage configuration switching control unit 350 outputs a signal input to the reference terminal VSS. The signal input to the reference terminal VSS may be a ground voltage. When the first comparator 51 outputs low, the one-stage configuration switching control unit 350 outputs the signal input to the power supply terminal VDD. That is, the one-stage configuration switching control unit 350 outputs a signal in which high and low are opposite to the signal output from the first comparator 51.

  FIG. 6 shows an example of the configuration of the overcharge prevention circuit 200. The overcharge prevention switching control unit 210 in this example is an example of the switching control circuit 340. The overcharge prevention switching control unit 210 is not limited to the configuration of the low power consumption CMOS inverter comparator type switching control circuit 340, and may be configured by a general comparator.

  For example, when the voltage at the capacitor terminal VO exceeds the upper overcharge prevention skip start voltage, the first comparator 51 outputs low. When low is output to the input terminal of the first inverter 53, the upper PMOS transistor is turned on and the lower NMOS transistor is turned off, so that high is output from the output terminal VOU of the overcharge prevention switching control unit 210. Is output. When the overcharge prevention switching control unit 210 outputs high, the shunt circuit 220 is turned on and the overcharge prevention switching unit 230 is turned off. Thereby, the power storage from the power generation apparatus 10 to the capacitor 500 is cut off.

  On the other hand, when the voltage of the capacitor terminal VO is smaller than the lower overcharge prevention skip start voltage, the first comparator 51 outputs high. When high is output to the input terminal of the first inverter 53, the upper PMOS transistor is turned off and the lower NMOS transistor is turned on, so that the low voltage is output from the output terminal VOU of the overcharge prevention switching control unit 210. Is output. When the overcharge prevention switching control unit 210 outputs low, the shunt circuit 220 is turned off and the overcharge prevention switching unit 230 is turned on. Thereby, power storage from the power generation apparatus 10 to the capacitor 500 is started.

  As described above, the overcharge prevention switching control unit 210 causes the voltage of the capacitor terminal VO to be skipped between the upper overcharge prevention skip start voltage and the lower overcharge prevention skip start voltage. Thereby, the overcharge prevention switching control unit 210 prevents the capacitor 500 from being overcharged.

  FIG. 7 shows an example of the configuration of the power supply circuit 100. The power supply circuit 100 of this example is different from the configuration illustrated in FIG. 3 in that the reference terminal VSS of the first switching control unit 310, the second switching control unit 320, and the third switching control unit 330 is provided in common.

  The first switch F1 and the overdischarge prevention switching unit 270 of this example are connected between the capacitor 500 and the power storage device 550. The second switch F2 and the third switch F3 are connected in series between the power generation device 10 and the load 15. The first switch F1, the second switch F2, the third switch F3, and the overdischarge prevention switching unit 270 of this example include a PMOS transistor instead of the NMOS transistor.

  As described above, the first switch F1, the second switch F2, the third switch F3, and the overdischarge prevention circuit 250 illustrated in FIG. 7 function in the same manner although the configuration and arrangement are different from those of the embodiment illustrated in FIG. To do. That is, the power supply circuit 100 of this example operates in the same manner as the power supply circuit 100 described in FIG.

  FIG. 8 shows an example of the configuration of the two-stage configuration switching control unit 360. The two-stage configuration switching control unit 360 includes a reference voltage generation unit 20, a second voltage selection unit 42, a second comparator 52, and a second inverter 54. The two-stage configuration switching control unit 360 is different from the one-stage configuration switching control unit 350 in that it includes the second inverter 54, but the basic operation is the same as that of the one-stage configuration switching control unit 350.

  The second inverter 54 includes a two-stage CMOS inverter circuit. Each transistor of the CMOS inverter is provided with a free-wheeling diode in parallel. The CMOS inverter of the second inverter 54 of this example is composed of a PMOS transistor and an NMOS transistor.

  In the two-stage configuration switching control unit 360, since the second inverter 54 is configured in two stages, the output signal is opposite to that of the one-stage configuration switching control unit 350. That is, the two-stage configuration switching control unit 360 outputs high when the second comparator 52 outputs high, and outputs low when the second comparator 52 outputs low.

  For example, in the power supply circuit 100 shown in FIG. 7, the first switching control unit 310, the overdischarge prevention circuit 250, the second switching control unit 320, and the third switching control unit 330 are the two-stage configuration switching control unit 360. Composed. The overcharge prevention switching control unit 210 includes a one-stage configuration switching control unit 350. As described above, the switching control circuit 340 is configured by the CMOS inverter comparator method, so that the first switching control unit 310, the second switching control unit 320, the third switching control unit 330, the overcharge prevention switching control unit 210, and the excessive switching control circuit 340 are configured. The discharge prevention circuit 250 operates with extremely low power consumption. That is, the power supply circuit 100 can operate even when the power generation amount of the power generation apparatus 10 is very small. For example, the power supply circuit 100 can charge the capacitor 500 even if it generates about 1 μA.

  FIG. 9 shows the magnitude relation of the operation threshold voltage. The operation threshold voltage includes a capacitor storage start voltage, a storage device storage start voltage, an overcharge prevention skip start voltage, and a power supply start voltage. In FIG. 9, when the voltage of the terminal in the parenthesis exceeds the operation threshold voltage, the operation corresponding to each operation threshold voltage is started. In FIG. 9, the voltage corresponding to each operation threshold voltage is finished by making a voltage lower than each operation threshold voltage by a predetermined minute voltage smaller than the voltage at the terminal in parentheses. The operation threshold voltage in this example increases in the order of power supply start voltage, capacitor storage start voltage, power storage device storage start voltage, and overcharge prevention skip start voltage.

  The capacitor storage start voltage is a voltage at the supply terminal VDDC at which the third switch F3 is turned on and storage of the capacitor 500 is started. The third switching control unit 330 controls on / off of the third switch F3 depending on whether or not the voltage of the supply terminal VDDC exceeds the capacitor storage start voltage. When the voltage at the supply terminal VDDC exceeds the capacitor storage start voltage, the third switch F3 is turned on, and the first switch F1 and the second switch F2 are kept off when the voltage at the capacitor terminal VO is still lower than the target. . As a result, the voltage at the capacitor terminal VO gradually increases.

  The power supply start voltage is a voltage at the capacitor terminal VO that starts power supply to the load 15. The power supply start voltage in this example is smaller than the power storage device storage start voltage. The second switching control unit 320 controls on / off of the second switch F2 depending on whether or not the voltage of the capacitor terminal VO exceeds the power supply start voltage. When the voltage at the capacitor terminal VO exceeds a power supply start voltage smaller than the capacitor storage start voltage, the second switch F2 is turned on. At this time, the first switch F1 maintains an off state. As a result, the electric power stored in the capacitor 500 is output to the load 15.

  The power storage device power storage start voltage is a voltage at the capacitor terminal VO at which the first switch F1 is turned on and power storage to the power storage device 550 is started. When power is supplied to the load 15 and the capacitor 500, when the voltage at the capacitor terminal VO further rises and exceeds the storage device storage start voltage larger than the capacitor storage start voltage, the input power output from the power generation device 10 It can be determined that there is a remainder in Pin. In such a case, the first switching control unit 310 turns on the first switch F1 and supplies power to the power storage device 550 as well. At this time, the second switch is kept on.

  The overcharge prevention skip start voltage is a voltage at the capacitor terminal VO that turns off the overcharge prevention circuit 200. Such an operation prevents the voltage at the capacitor terminal VO from rising too much. The overcharge prevention circuit 200 is turned off when the voltage at the capacitor terminal VO exceeds the overcharge prevention skip start voltage. The overcharge prevention circuit 200 is turned on again when the voltage at the capacitor terminal VO becomes lower than a voltage lower than the overcharge prevention skip start voltage by a predetermined voltage. When the overcharge prevention circuit 200 is turned on, the third switch F3 is controlled to be turned on. Thereby, the voltage of the capacitor terminal VO can be maintained in the vicinity of the overcharge prevention skip start voltage.

  Further, when the power generation device 10 cannot output sufficient input power Pin, the third switch F3 is turned off, and the voltage of the power storage terminal VS is equal to or higher than the minimum voltage that the power storage terminal VS can output to the load 15. When the voltage of VO becomes lower than the voltage of the power storage terminal VS, the first switch F1 and the second switch F2 are turned on to store power in the power storage device 550 via the first switch F1 and the second switch F2. The generated power may be output to the load 15.

  FIG. 10 is a flowchart showing an example of the operation of the overcharge prevention circuit 200. In steps S100 to S140, the overcharge prevention circuit 200 controls on / off based on the voltage of the capacitor terminal VO.

  In step S <b> 100, the power generation device 10 outputs the generated energy harvesting as input power Pin to the overcharge prevention circuit 200. For example, the power generation apparatus 10 may output the overcharge prevention circuit 200 when the voltage is 3.2 V or higher.

  In step S110, the overcharge prevention circuit 200 outputs the input power Pin input from the power generation device 10 to the capacitor terminal VO. At this time, the shunt circuit 220 is turned off and the overcharge prevention switching unit 230 is turned on. The capacitor 500 stores the input power Pin of the power generation apparatus 10 that has been input.

  In step S120, on / off of the overcharge prevention circuit 200 is controlled based on a result of comparison between the voltage of the capacitor terminal VO and the overcharge prevention skip start voltage Vovp. When the voltage at the capacitor terminal VO is equal to or lower than the overcharge prevention skip start voltage Vovp, the capacitor 500 is continuously charged (step S110). On the other hand, when the voltage of the capacitor terminal VO exceeds the overcharge prevention skip start voltage Vovp, the overcharge prevention circuit 200 is turned off and ends the charging of the capacitor 500 (step S130).

  In step S <b> 130, the overcharge prevention circuit 200 disconnects the charging path of the capacitor 500 by turning off the PMOS transistor of the overcharge prevention switching unit 230. The overcharge prevention circuit 200 turns on the NMOS transistor of the shunt circuit 220 to shunt the output of the power generation apparatus 10.

  In step S140, the overcharge prevention circuit 200 is controlled based on the result of comparing the voltage obtained by subtracting the predetermined voltage α from the overcharge prevention skip start voltage Vovp with the voltage of the capacitor terminal VO. Here, α may be an arbitrary voltage value. When the voltage of the capacitor terminal VO is equal to or higher than the overcharge prevention skip start voltage Vovp-α, the overcharge prevention circuit 200 is kept off (step S130). On the other hand, when the voltage at the capacitor terminal VO is smaller than the overcharge prevention skip start voltage Vovp−α, the overcharge prevention circuit 200 is turned on and the charging of the capacitor 500 is resumed (step S130). By such an operation, the voltage of the capacitor terminal VO can be maintained in the range of the overcharge prevention skip start voltage Vovp to the overcharge prevention skip start voltage Vovp−α.

  FIG. 11 is a flowchart showing an example of the operation of the third switch F3. In steps S200 to S230, the voltage of the capacitor terminal VO is boosted by controlling on / off of the first switch F1 based on the voltage of the supply terminal VDDC.

  In step S200, the third switch F3 is in the initial state in which it is turned off. When the third switch F3 is turned off, no electric power is stored in the capacitor 500.

  In step S210, the third switch F3 is controlled based on the result of comparison between the voltage at the supply terminal VDDC and the capacitor storage start voltage Vtarget2. When the voltage of the supply terminal VDDC exceeds the capacitor storage start voltage Vtarget2, the connection of the third switch F3 is turned on (step S220). On the other hand, when the voltage of the supply terminal VDDC is equal to or lower than the capacitor storage start voltage Vtarget2, the third switch F3 is continuously turned off (step S200).

  When the storage of the capacitor 500 is started, the voltage at the supply terminal VDDC may decrease thereafter. In step S230, the third switch F3 is controlled based on the result of comparing the capacitor storage start voltage Vtarget2-β with the voltage of the supply terminal VDDC. Here, β is an arbitrary voltage value. When the voltage of the supply terminal VDDC is equal to or higher than the capacitor storage start voltage Vtarget2-β, the third switch F3 is continuously turned on to store the capacitor 500 (step S220). On the other hand, when the voltage of the supply terminal VDDC is smaller than the capacitor storage start voltage Vtarget2-β, the third switch F3 is turned off to stop the storage of the capacitor 500 (step S200). By repeating Step S200 to Step S230, power is stored in the capacitor 500 while the voltage of the supply terminal VDDC is maintained within a predetermined range, and the voltage of the capacitor terminal VO is boosted.

  FIG. 12 is a flowchart showing an example of the operation of the first switch F1. In steps S300 to S330, the power supply to the power storage terminal VS is controlled by controlling on / off of the first switch F1 based on the voltage of the capacitor terminal VO.

  In step S300, the first switch F1 is in an initial state in which it is turned off. When the first switch F1 is in the OFF state, no power is stored in the power storage device 550.

  In step S310, the first switch F1 is controlled based on the result of comparison between the voltage at the capacitor terminal VO and the power storage device storage start voltage Vtarget3. When the voltage of the capacitor terminal VO exceeds the power storage device power storage start voltage Vtarget3, the connection of the first switch F1 is turned on to start power storage in the power storage device 550 (step S320). On the other hand, when the voltage of the capacitor terminal VO is smaller than the power storage device storage start voltage Vtarget3, the first switch F1 is continuously turned off (step S300).

  When power storage to the power storage device 550 is started, the voltage of the capacitor terminal VO may decrease. In step S330, the first switch F1 is controlled based on the result of comparing the power storage device power storage start voltage Vtarget3-γ and the voltage of the capacitor terminal VO. Here, γ is an arbitrary voltage value. When the voltage at the capacitor terminal VO is equal to or higher than the power storage device storage start voltage Vtarget3-γ, the first switch F1 is continuously turned on (step S320). On the other hand, when the voltage of the capacitor terminal VO is smaller than the power storage device power storage start voltage Vtarget3, the first switch F1 is turned off to stop power storage in the power storage device 550 (step S300). By repeating step S300 to step S330, electric power can be stored in the power storage device 550 while maintaining the voltage output to the load 15 within a predetermined range.

  FIG. 13 is a flowchart showing an example of the operation of the second switch F2. In step S400 to step S450, whether the system power is supplied or not is controlled by controlling on / off of the second switch F2 based on the voltage of the capacitor terminal VO. System power supply refers to supplying power to the load 15.

  In steps S400 and 410, the second switch F2 is turned off to stop the system power supply. For example, the system power supply is stopped in a situation where sufficient power for driving the load 15 is not supplied to the capacitor terminal VO.

  In step S420, on / off of the second switch F2 is controlled based on the result of comparing the voltage of the capacitor terminal VO and the power supply start voltage Vtarget4. When the voltage at the capacitor terminal VO is higher than the power supply start voltage Vtarget4, the second switch F2 is turned on and system power supply is started (steps S430 and 440). On the other hand, when the voltage of the capacitor terminal VO is smaller than the power supply start voltage, the second switch F2 is continuously turned off and the system power supply is stopped (steps S400 and 410).

  When system power supply is started, for example, depending on the amount of power generated in the power generation device 10, the voltage at the capacitor terminal VO decreases. In step S450, on / off of the second switch F2 is controlled based on the result of comparing the voltage of the capacitor terminal VO with the power supply start voltages Vtarget4 and Vtarget4-ε. Here, ε is an arbitrary voltage value. When the voltage at the capacitor terminal VO is smaller than the power supply start voltage Vtarget4-ε, the second switch F2 is turned off (step S400). On the other hand, when the voltage of the capacitor terminal VO is equal to or higher than the power supply start voltage Vtarget4-ε, the second switch F2 is continuously turned on (step S430). Note that α, β, γ, and ε described with reference to FIGS. 10 to 13 may be about 0.1 V or about 1 V.

  FIG. 14 shows an example of the operation of the power supply circuit 100. The horizontal axis indicates time, and the vertical axis indicates the voltage of each terminal (supply terminal VDDC, capacitor terminal VO, power storage terminal VS, load terminal VOUT). Below the graph, the on / off states of the first switch F1 to the third switch F3 are shown. The horizontal axis is divided into sections t <b> 1 to t <b> 12 according to the operation status of the power supply circuit 100.

  A section t1 is a section in which the voltage of the supply terminal VDDC is boosted from zero. In the section t1, the voltage of the supply terminal VDDC is boosted by the overcharge prevention circuit 200 with the first switch F1 to the third switch F3 being turned off.

A section t2 is a section after the voltage of the supply terminal VDDC exceeds the capacitor storage start voltage. In a section t3, the third switch F3 is turned on to store the capacitor 500. In the example of FIG. 14, the overcharge prevention circuit 200 and the third switch are set so that the voltage of the supply terminal VDDC is maintained in the range of the overcharge prevention skip start voltage Vovp to the overcharge prevention skip start voltage Vovp−α. F3 is repeatedly turned on and off. In FIG. 14, the overcharge prevention skip start voltage Vovp is indicated by the upper target voltage V _TGT , and the overcharge prevention skip start voltage Vovp-α is indicated by the lower target voltage V _TGT -ζ.

  A section t3 is a section after the voltage of the capacitor terminal VO exceeds the power supply start voltage Vtarget4. In the section t3, the second switch F2 is turned on. As a result, the power stored in the capacitor 500 and the power from the overcharge prevention circuit 200 are output to the load terminal VOUT, and the load 15 operates. In this case, the voltage at the load terminal VOUT is equal to the voltage at the capacitor terminal VO. In section t3, power is supplied to load 15, but power is not sufficiently stored in power storage device 550.

  A section t4 is a section after the voltage of the capacitor terminal VO and the load terminal VOUT exceeds the power storage device power storage start voltage Vtarget3. In the section t4, the first switch F1 is on / off controlled. Thereby, power storage device 550 stores surplus power that is not consumed by load 15 and capacitor 500 among supplied power Pddc output from overcharge prevention circuit 200. The voltage of the load terminal VOUT can be stored in the power storage device 550 by being controlled within the range of the power storage device power storage start voltage Vtarget3 to the power storage device power storage start voltage Vtarget3-γ.

Sections t5 and t6 are sections indicating a situation in which the input power Pin generated by the power generation apparatus 10 has decreased. In the section t5, when the voltage of the supply terminal VDDC becomes equal to or lower than the capacitor storage start voltage Vtarget2-β, the third switch F3 is turned off. In FIG. 14, the capacitor power storage start voltage Vtarget2-β is indicated by the lower target voltage V _TGT -ζ.

  Further, when the third switch F3 is turned off, the voltage at the capacitor terminal VO decreases. When the voltage at the capacitor terminal VO decreases and becomes equal to or lower than the power storage device storage start voltage Vtarget3-γ, the first switch F1 is turned off. On the other hand, the second switch F2 is kept on and outputs the power stored in the capacitor 500 to the load terminal VOUT. Since the third switch F3 is off, the voltage of the power storage terminal VS is constant.

  In the interval t6, when the voltage of the capacitor terminal VO drops below the voltage of the storage terminal VS, if there is a voltage higher than the voltage that can be output to the load 15 at the storage terminal VS, the first switch remains with the third switch F3 turned off. Turn F1 on. Thereby, the power stored in power storage device 550 is output to load terminal VOUT. In the interval t6, the voltages of the supply terminal VDDC, the capacitor terminal VO, and the load terminal VOUT are equal. Further, the voltage at the power storage terminal VS is apparently higher than the voltages at the supply terminal VDDC, the capacitor terminal VO, and the load terminal VOUT due to the influence of the diode.

  A section t7 is a section in which the voltage of the input power Pin has increased again. In a section t7, the voltage at the supply terminal VDDC increases. In the section t7, the power from the overcharge prevention circuit 200 and the power stored in the capacitor 500 are output to the load terminal VOUT, and the load 15 operates. In the section t7, the third switch F3 is turned off. In this case, the voltage at the load terminal VOUT is equal to the voltage at the capacitor terminal VO.

  In a section t8, the voltage at the capacitor terminal VO and the load terminal VOUT rises gradually. Thereafter, in section t9, the voltage of the capacitor terminal VO exceeds the power storage device power storage start voltage Vtarget3, and power storage in the power storage device 550 is resumed.

  FIG. 15 shows an exemplary configuration of the power supply circuit 100. The power supply circuit 100 of this example is different from the configuration illustrated in FIG. 3 in that it further includes a switching circuit 400. The changeover circuit 400 includes a first changeover switch 410, a charge control unit 420, a second changeover switch 430, and a resistor R2. Switching circuit 400 is provided between power generation device 10 and power storage device 550. In addition, the charging control unit 420 includes a switching control unit 425, a resistor R1, and a capacitor C.

  The switching circuit 400 detects whether the power generation device 10 is generating power and switches whether to store the capacitor 500 and the power storage device 550. In addition, switching circuit 400 prevents power stored in capacitor 500 and power storage device 550 from flowing back to power generation device 10. The switching circuit 400 turns off the first changeover switch 410 when the power generation device 10 does not generate enough power and the voltage output from the power generation device 10 is smaller than the voltage at the capacitor terminal VO and the power storage terminal VS.

  The first changeover switch 410 switches whether the power generation device 10 and the capacitor 500 or the power storage device 550 are connected. The first changeover switch 410 of this example is provided between the third switch F3 and the power generation device 10. However, the first changeover switch 410 may be disposed at any position as long as the connection between the power generation device 10 and the capacitor 500 or the power storage device 550 can be disconnected.

  The charging control unit 420 detects the voltage output from the power generation device 10 and turns off the first changeover switch 410 when the detected voltage of the power generation device 10 is smaller than a predetermined value. Further, the charging control unit 420 may detect the voltage output from the power generation apparatus 10 at a predetermined cycle. The charging control unit 420 turns off the second changeover switch 430 with a time constant determined by the resistor R1 and the capacitor C. Further, the charging control unit 420 turns off the first changeover switch 410 with a time constant determined by the capacity C and the current consumption of the switching control unit 425.

  The second changeover switch 430 switches whether to supply the power input from the power generation apparatus 10 to the capacitor C. The second changeover switch 430 includes a PMOS transistor and a free wheel diode.

  The resistor R1 is connected between the drain terminal of the second changeover switch 430 and the capacitor C. The time constant at which the charging control unit 420 operates may be adjusted by changing the size of the resistor R1.

  The resistor R2 functions as a pull-up resistor in order to reliably turn off the second changeover switch 430. The resistor R2 is connected between the gate terminal and the source terminal of the second changeover switch 430.

  For example, in the second changeover switch 430, when the input power Pin of the power generation device 10 is input to the changeover circuit 400, a voltage difference is generated between the source terminal and the gate terminal by the resistor R2. That is, the second changeover switch 430 supplies the input power Pin to the capacitor C when the PMOS transistor is turned on.

  After that, when a voltage larger than a predetermined voltage is stored in the capacitor C, the switching control unit 425 outputs high to turn off the second switching switch 430 and turn on the first switching switch 410. To do. Thereby, the electrical storage of the capacitor 500 is started.

  Since the switching control unit 425 operates using the power stored in the capacitor C as a power source, the power stored in the capacitor C is consumed. When the voltage at the terminal of the capacitor C becomes smaller than a predetermined voltage, the switching control unit 425 outputs low to turn on the second switching switch 430 and the first switching switch 410. Turn off. Thereby, the capacitor C starts to be charged and the charge to the capacitor 500 is stopped.

  Here, when sufficient input power Pin is not input from the power generation apparatus 10, the second changeover switch 430 is not turned on and the capacity C is not stored. That is, the switching control unit 425 cannot output high. That is, the switching control unit 425 can detect whether or not the power generation apparatus 10 is generating power by detecting whether or not the output is switched from low to high.

  FIG. 16 shows an example of the configuration of the switching circuit 400. The switching circuit 400 of this example further includes a startup circuit 450. The switching control unit 425 in this example is an example of the switching control circuit 340. The switching control unit 425 includes a first reference voltage generation unit 21, a first voltage selection unit 41, a first comparator 51, and an output switching unit 57.

  The output switching unit 57 includes an NMOS transistor and a free wheel diode. The gate terminal of the NMOS transistor of the output switching unit 57 is connected to the output terminal of the first comparator 51. When the first comparator 51 outputs high, the output switching unit 57 is turned on and connected to the ground via the reference terminal VSS. Therefore, low is output from the output terminal VOU, and the second changeover switch 430 is turned on.

  On the other hand, when the first comparator 51 outputs low, the output switching unit 57 is turned off. Therefore, a voltage difference does not occur between the gate terminal and the source terminal of the PMOS transistor of the second changeover switch 430, and the second changeover switch 430 remains off.

  The start-up circuit 450 charges the capacitor C directly from the power generator 10 when the power sufficient for the switching control unit 425 to operate is not accumulated in the capacitor C. The startup circuit 450 is provided between the power generation device 10 and the capacitor C. The start-up circuit 450 is particularly effective when the output of the power generation apparatus 10 becomes very small and the second changeover switch 430 cannot be turned on. In this case, since the start-up circuit 450 directly charges the capacity C from the power generation apparatus 10, the capacity C can be stored with the small input power Pin of the power generation apparatus 10. The startup circuit 450 may be an ultra-low power consumption circuit having the same configuration as the switching control circuit 340.

  FIG. 17 shows an example of the operation of the switching circuit 400. The upper diagram shows the output of the charging control unit 420 during normal operation. The normal operation is when the power generator 10 outputs a sufficient input power Pin. For example, the sufficient input power Pin is the minimum power necessary for the switching circuit 400 to operate. The lower diagram shows the output of charge control unit 420 and the amount of power generated by power generation device 10 when the power storage device is stopped. In this example, when the power storage device stops, the output of the power generation device 10 gradually decreases from the normal operation time, and the power generation of the power generation device 10 stops.

  During normal operation, the output of the charging control unit 420 is high and repeats low at a constant cycle. For example, the section in which the output of the charging control unit 420 is high is determined by a time constant determined by the capacity C and the current consumption of the switching control unit 425. In addition, a section in which the output of the charging control unit 420 is low is determined by a time constant determined by the resistor R1 and the capacitor C.

  When the power storage device stops, when the power generation amount of the power generation device 10 decreases, the second changeover switch 430 is not turned on, so that the capacity C is not stored and the output of the charge control unit 420 does not return from low to high. That is, in order for the charging control unit 420 to output high, it is necessary to store power in the capacitor C. However, if the power generation amount of the power generation device 10 decreases, power is not supplied to the capacitor C. As described above, the switching circuit 400 can detect whether the power generation apparatus 10 is operating normally or stopped.

  FIG. 18 shows an example of the configuration of the power supply circuit 100. The power supply circuit 100 of this example is configured to operate by a combination of an NMOS open drain and a pull-up resistor. That is, the power supply circuit 100 of the present example is different from the configuration described in FIG. 15 in that the switching output unit 426 is provided. In addition, the switching control unit 425 of this example is configured by the one-stage configuration switching control unit 350 shown in FIG.

  The switching output unit 426 is composed of two stages of a CMOS inverter circuit and an NMOS transistor. The CMOS inverter circuit of the switching output unit 426 has a PMOS transistor and an NMOS transistor connected in series, and each includes a freewheeling diode. The input terminal of the CMOS inverter of the switching output unit 426 is connected to the output terminal VOU of the switching control unit 425. The output of the power generation device 10 is input to the power supply terminal of the CMOS inverter. The output of the CMOS inverter of the switching output unit 426 is input to the gate terminal of the subsequent NMOS transistor.

  FIG. 19 shows an example of the configuration of the power supply circuit 100. The power supply circuit 100 of this example includes a level shifter circuit 470 between the source terminal and the gate terminal of the PMOS transistor included in the second changeover switch 430. Further, the switching output unit 426 is different from the switching output unit 426 illustrated in FIG. 18 in that it is configured by a single-stage CMOS inverter circuit. The switching control unit 425 of this example is configured similarly to the one-stage configuration switching control unit 350 described in FIG. The power supply circuit 100 may further include a startup circuit 450.

  The level shifter circuit 470 generates a voltage having a level corresponding to the outputs of the switching control unit 425 and the switching output unit 426. For example, the level shifter circuit 470 changes the output of the switching control unit 425 and the switching output unit 426 to a voltage level that can reliably control the on / off of the PMOS transistor included in the second switching switch 430, thereby turning on / off the second switching switch 430. Improve accuracy. Further, the level shifter circuit 470 includes the gate terminal of the PMOS transistor and the first changeover switch included in the second changeover switch 430 according to whether the voltage of the input power Pin exceeds the voltage of the capacitor C or not. Either 410 outputs a voltage of the input power Pin or a reference potential such as ground.

  The level shifter circuit 470 includes a first upper PMOS transistor 471, a second upper PMOS transistor 472, a first lower NMOS transistor 473, and a second lower NMOS transistor 474. The transistor included in the level shifter circuit 470 is provided with a free-wheeling diode in parallel so as to cut off the current from the input terminal VI. The upper side means a PMOS transistor on the side close to the input terminal VI in the level shifter circuit 470. Further, the lower side means an NMOS transistor far from the input terminal VI in the level shifter circuit 470. The arrangement of the upper and lower transistors is not limited to this example, and may be appropriately changed.

  The source terminal of the first upper PMOS transistor 471 is connected between the input terminal VI and the source terminal of the PMOS transistor included in the second changeover switch 430. The drain terminal of the first upper PMOS transistor 471 is connected to the gate terminal of the PMOS transistor included in the second changeover switch 430 and the gate terminal of the second upper PMOS transistor 472.

  The source terminal of the second upper PMOS transistor 472 is connected between the input terminal VI and the source terminal of the PMOS transistor included in the second changeover switch 430. The drain terminal of the second upper PMOS transistor 472 is connected to the gate terminal of the first upper PMOS transistor 471.

  The first lower NMOS transistor 473 is connected in series with the first upper PMOS transistor 471 between the first upper PMOS transistor 471 and the ground. The drain terminal of the first lower NMOS transistor 473 is connected to the gate terminal of the PMOS transistor included in the second changeover switch 430 and the gate terminal of the second upper PMOS transistor 472. The gate terminal of the first lower NMOS transistor 473 is connected to the output terminal of the switching output unit 426.

  The second lower NMOS transistor 474 is connected in series with the second upper PMOS transistor 472 between the second upper PMOS transistor 472 and the ground. The drain terminal of the second lower NMOS transistor 474 is connected to the gate terminal of the first upper PMOS transistor 471. The gate terminal of the second lower NMOS transistor 474 is connected to the output terminal VOU of the switching control unit 425.

  As described above, the power supply circuit 100 of this example can improve the on / off accuracy of the second changeover switch 430 by the level shifter circuit 470. In addition, since the power supply circuit 100 does not use the resistor R2 that functions as a so-called pull-up resistor, loss of power consumed by the resistor R2 can be reduced.

  Next, a method for setting the reference voltage of the switching control circuit 340 according to the characteristics of the power generation device 10 will be described. In the following, a setting method of the switching control circuit 340 will be described as an example of a setting method of the reference voltage of the ultra-low power consumption control circuit, but the first switching control unit 310, the second switching control unit 320, and the third switching control unit. 330, the overcharge prevention switching control unit 210, the overdischarge prevention switching control unit 260, the one-stage configuration switching control unit 350, the two-stage configuration switching control unit 360, and the switching control unit 425 are set in the same manner. The value of the reference voltage may be changed as appropriate according to the characteristics of the power generation apparatus 10 and the like.

  FIG. 20 shows an example of the operation of the switching control circuit 340. The horizontal axis represents the input voltage Vin [V] input to the switching control circuit 340, and the vertical axis represents the output voltage Vout [V] of the switching control circuit 340.

As described above, the switching control circuit 340 operates in a hysteresis manner at each threshold value of the operation threshold voltage. That is, the target voltage (upper target voltage V _TGT , lower target voltage V _TGT −ζ) varies depending on the output state of the comparator 50. Specifically, the first target voltage when the comparator 50 outputs a reference potential is set to V1, and the second target voltage when the comparator 50 outputs a voltage substantially equal to the input voltage Vin is set to V2. Is done. The target voltage may be changed as appropriate according to the specifications required by the switching control circuit 340.

  When the input voltage Vin increases to the first target voltage V1 while the output voltage Vout of the switching control circuit 340 is at the reference potential, a voltage substantially equal to the input voltage Vin is output as the output voltage Vout of the switching control circuit 340. The When the output voltage Vout of the switching control circuit 340 is substantially equal to the input voltage Vin and the input voltage Vin decreases and becomes the second target voltage V2, the output voltage VOUT of the comparator 50 becomes the reference potential.

  FIG. 21 shows an exemplary configuration of the comparator 50. The comparator 50 includes a CMOS inverter 55 and an output circuit 56.

  The input voltage Vin input to the comparator 50 is input to the power input terminal of the CMOS inverter 55. The reference voltage input to the comparator 50 is input to the input terminal of the CMOS inverter 55. The comparator 50 performs a switching operation according to the input voltage Vin input to the power supply terminal and the reference voltage input to the input terminal. The power supply terminal refers to a terminal connected to the source terminal of the CMOS inverter 55, and the input terminal refers to a terminal connected to the gate terminal of the CMOS inverter 55.

  The CMOS inverter 55 has CMOS transistors (Mp, Mn). The CMOS inverter 55 is a power supply terminal input type CMOS inverter, and the input voltage Vin is input to the positive power supply terminal, and GND is connected to the negative power supply terminal. The positive power supply terminal of the CMOS inverter 55 in this example is a terminal connected to the source of the CMOS transistor Mp, and the negative power supply terminal is a terminal connected to the source of the CMOS transistor Mn. The positive power supply terminal of the CMOS inverter 55 of this example functions as an input voltage terminal to which the input voltage Vin is input. The upper reference voltage VrefH and the lower reference voltage VrefL are input to the input terminal of the CMOS inverter 55. As described above, the input terminal of the CMOS inverter 55 refers to a terminal connected to each gate of the CMOS transistor (Mp, Mn). The input terminal of the CMOS inverter 55 in this example functions as a reference voltage terminal to which a reference voltage is input.

  The output circuit 56 outputs a voltage Voutc corresponding to the output voltage Vouti output from the CMOS inverter 55. For example, the output circuit 56 may include a CMOS inverter circuit that is connected to the CMOS inverter 55 in multiple stages, and may include other general output circuits. For example, the output circuit 56 may include a PMOS switch that switches whether to output the output voltage Vouti of the CMOS inverter 55, and an NMOS circuit in which a source that operates according to the output voltage Vouti of the CMOS inverter 55 is connected to the ground potential. You may have. The output circuit 56 may have a plurality of types of output circuits and output terminals corresponding to the respective output circuits.

  Whether the CMOS inverter 55 outputs a ground potential or a voltage substantially equal to the input voltage Vin is whether the difference between the input voltage Vin and the reference voltage is greater than or equal to the threshold value of the PMOS transistor Mp in the CMOS inverter 55 It depends on. The operating point (target voltage) at which the output of the CMOS inverter 55 is inverted can be adjusted by the reference voltage. In this example, the voltage selection unit 40 selects either the reference voltage VrefH or VrefL according to the output of the output circuit 56, so that the target voltage can be changed according to the output of the output circuit 56. Thereby, the switching control circuit 340 performs a hysteresis operation as shown in FIG.

  The reference voltage to be input to the comparator 50 with respect to the target voltage for the switching control circuit 340 to operate is determined by the characteristics of the CMOS inverter 55 included in the comparator 50. However, since the characteristics of the CMOS inverter 55 have variations, it is preferable to use a reference voltage in consideration of variations in the characteristics of the CMOS inverter 55 in order for the switching control circuit 340 to operate accurately with the target voltage.

  FIG. 22 shows an example of a configuration for setting the reference voltage of the switching control circuit 340. The switching control circuit 340 of this example includes a reference voltage detection mode for detecting a reference voltage for operating the comparator 50 at a set target voltage, and a reference voltage generation unit for outputting the detected reference voltage to the reference voltage generation unit 20 There are three operation modes: a reference voltage setting mode for setting 20 and an actual operation mode for comparing the input voltage Vin with the target voltage using the set reference voltage.

  The switching control circuit 340 further includes a mode selection unit 80, a test circuit 70, and a voltmeter 75 in addition to the configuration shown in FIG. The switching control circuit 340 has terminals VPP, DATA, SCLK, PULSE, GND, VIN, VREF, IREF, VMON, and OUT that electrically connect the inside and the outside of the switching control circuit 340. Note that the Vref terminal and the IREF terminal may be the same terminal.

  The mode selection unit 80 selects an operation mode of the switching control circuit 340. The mode selection unit 80 may select the operation mode based on the voltage input from the VPP terminal. The mode selection unit 80 controls the voltage selection unit 40, the upper reference voltage generation unit 25, and the lower reference voltage generation unit 26 according to the selected operation mode.

  In the actual operation mode, the mode selection unit 80 causes the voltage selection unit 40 to select a reference voltage based on a signal indicating the output state of the comparator 50. Thereby, the hysteresis operation shown in FIG. 20 is realized. The test circuit 70 has a current mirror 71 and an amplifier circuit 72. The test circuit 70 does not operate in the actual operation mode but operates in the reference voltage setting mode. The voltage selection unit 40 of this example is externally input to the upper reference voltage VrefH output from the upper reference voltage generation unit 25, the lower reference voltage VrefL output from the lower reference voltage generation unit 26, and the VREF terminal. Is selected in accordance with the operation mode and input to the comparator 50.

  First, the operation of the switching control circuit 340 in the reference voltage detection mode will be described. In FIG. 22, a line through which a signal mainly flows in the reference voltage detection mode is indicated by a bold line. When the mode selection unit 80 selects the reference voltage detection mode, the mode selection unit 80 causes the voltage selection unit 40 to select the set voltage Vref output from the VREF terminal. In the reference voltage detection mode, a set voltage whose level gradually changes is input to the VREF terminal. The voltage selection unit 40 selects the setting voltage Vref that gradually changes and inputs it to the input terminal of the CMOS inverter 55.

  In the reference voltage detection mode, a target voltage at which the switching control circuit 340 operates is input from the VIN terminal to the comparator 50. In this example, the switching control circuit 340 operates with two target voltages, the first target voltage V1 and the second target voltage V2, in order to perform a hysteresis operation. In this case, the first target voltage V1 and the second target voltage V2 are sequentially input to the VIN terminal. The VIN terminal is connected to the power supply terminal of the comparator 50.

  The comparator 50 operates according to the input set voltage Vref and the target voltage. Since the set voltage Vref gradually changes, the output state of the comparator 50 transitions when the difference between the set voltage Vref and the target voltage becomes equal to or greater than a predetermined value. The output terminal of the comparator 50 is connected to the OUT terminal. The level of the set voltage Vref when the output state of the comparator transitions becomes the level of the reference voltage corresponding to the target voltage. The output state of the comparator 50 may be monitored by an external device connected to the OUT terminal, or may be monitored by an internal circuit of the switching control circuit 340 such as the voltmeter 75.

  FIG. 23 shows an outline of a method for detecting the reference voltages (VrefH, VrefL) in the reference voltage detection mode. The vertical axis indicates the input voltage Vin input from the VIN terminal, the set voltage Vref input to the input terminal of the CMOS inverter 55, and the voltage level [V] of the reference voltage (VrefH, VrefL), and the horizontal axis indicates the time. t is indicated.

  The target voltage input to the VIN terminal gradually increases with the passage of time, and is held constant when it reaches a predetermined target voltage. The set voltage Vref increases with the target voltage to an initial value that is larger than the predicted upper reference voltage VrefH by a predetermined value. After the set voltage Vref reaches the initial value, the set voltage Vref is gradually changed (decreased in this example) to detect the set voltage Vref when the output of the CMOS inverter 55 is inverted. The detected set voltage Vref is a reference voltage for the input target voltage. Such processing is performed on both the first target voltage V1 and the second target voltage V2, and the corresponding reference voltages VrefH and VrefL are detected. The mode selection unit 80 sets the reference voltage generation unit 20 based on the detected set voltage. Note that the manner of change of the input voltage Vin and the set voltage is not limited to the example shown in FIG. The set voltage may be changed so that the output state of the comparator 50 transitions after the input voltage Vin reaches the target voltage.

  FIG. 24 shows a basic circuit provided in the reference voltage generation unit 20 according to the present embodiment. The upper reference voltage generation unit 25 and the lower reference voltage generation unit 26 may each have the same circuit as the reference voltage generation unit 20. As shown in FIG. 24B, the reference voltage generation unit 20 according to the present embodiment generates a reference voltage using an element that can be in two states, an enhancement state and a depletion state.

  FIG. 24A shows a reference voltage generation unit 20 including a depletion type MOS transistor M1 and an enhancement type MOS transistor M2. Each MOS transistor in FIG. 24A functions as a depletion type and an enhancement type, respectively, due to differences in parameters such as the doping amount during manufacturing.

  FIG. 24B shows a reference voltage generation unit 20 having a first MOS transistor M1 that functions as a depletion type and a second MOS transistor M2 that functions as an enhancement type. The first MOS transistor M1 and the second MOS transistor M2 each have a floating gate and a control gate. The first MOS transistor M1 and the second MOS transistor M2 of this example are non-volatile, which controls the state of the charge stored in the floating gate according to the voltage applied to the control gate and exhibits characteristics according to the stored charge amount It functions as a memory element. The state of charge stored in the floating gate refers to, for example, the positive / negative of the charge stored in the floating gate and the amount of charge. In this example, the threshold voltages of the first MOS transistor M1 and the second MOS transistor M2 change according to the state of charge stored in the floating gate. Thereby, each MOS transistor functions as a depletion type or an enhancement type.

  In the first MOS transistor M1, the gate terminal and the source terminal are connected to each other, and the drain terminal is connected to the power supply. The first MOS transistor M1 functions as a depletion type when a positive charge is injected into the floating gate. The depletion type is an element that turns off a transistor when a voltage of 0 V is input to the gate terminal, and refers to a so-called normally-off element.

  In the second MOS transistor M2, the gate terminal and the drain terminal are connected to each other, and the source terminal is grounded. The drain terminal of the second MOS transistor M2 is connected to the source terminal of the first MOS transistor M1. The second MOS transistor M2 functions as an enhancement type when a negative charge is injected into the floating gate. The enhancement type is an element that turns on a transistor when a voltage of 0 V is input to the gate terminal, and refers to a so-called normally-on element. The reference voltage generator 20 outputs a reference voltage from the connection point of the first MOS transistor M1 and the second MOS transistor M2.

  Since the reference voltage generation unit 20 shown in FIG. 24B can change the state of the nonvolatile memory element after manufacture, it can compensate for variations in characteristics between design and after manufacture. Therefore, the reference voltage generation unit 20 can adjust the reference voltage output from the connection point of the first MOS transistor M1 and the second MOS transistor M2. The mode selection unit 80 adjusts the reference voltage by controlling the state of charge stored in the floating gates of the first MOS transistor M1 and the second MOS transistor M2.

  FIG. 25 shows a nonvolatile memory element 90 having a tunnel oxide film. The nonvolatile memory element 90 includes a substrate 91, a tunnel oxide film 94, a floating gate 95, an insulating film 96 and a control gate 97.

  The nonvolatile memory element 90 is an NMOS type element that can be brought into an enhancement state and a depletion state by having the floating gate 95. The substrate 91 in this example is a p-type substrate. The substrate 91 has a source region 92 and a drain region 93. The source region 92 and the drain region 93 are formed using a general CMOS process such as ion implantation. On the substrate 91, a tunnel oxide film 94, a floating gate 95, an insulating film 96 and a control gate 97 are stacked in this order.

  The control gate 97 controls a channel region formed between the source region 92 and the drain region 93 by a voltage applied to the gate terminal of the nonvolatile memory element 90. Thereby, the nonvolatile memory element 90 turns on and off the current flowing between the source region 92 and the drain region 93.

  The insulating film 96 insulates between the floating gate 95 and the control gate 97. The insulating film 96 is formed of a general insulating film used in a CMOS process. The state of the charge accumulated in the floating gate 95 changes according to the voltage applied to the control gate 97. For example, the amount of charge accumulated in the floating gate 95 varies in the positive or negative direction according to the voltage applied to the control gate 97. As a result, the threshold voltage of the nonvolatile memory element 90 varies and is controlled to a depletion state or an enhancement state.

  The tunnel oxide film 94 normally insulates between the substrate 91 and the floating gate 95. However, when a voltage higher than a predetermined value is applied to the control gate 97, the tunnel oxide film 94 becomes conductive due to FN tunneling (Fowler-Nordheim tunneling). FN tunneling refers to a moving state when electrons tunnel through an insulator. The floating gate 95 injects electrons from the source region 92 or emits electrons by FN tunneling. As a result, the state of charge stored in the floating gate 95 is controlled.

FIG. 26 shows an example of the circuit configuration of the reference voltage generation unit 20. In a state where the reference voltage generation unit 20 outputs the reference voltage, the switch (SW) is controlled as follows.
SWl: VDD (VIN)
SW2: VSS
SW3, SW4: OPEN
SW5, SW6, SW7, SW8: SHORT (connection)
SW9, SW10: Arbitrary

  In the state where the switch is controlled as shown in FIG. 26, the reference voltage generation unit 20 generates the reference voltage when the first MOS transistor Ml is in the depletion state and the second MOS transistor M2 is in the enhancement state. The VDD terminal functions as a terminal for applying a power supply voltage as the upper reference voltage generation unit 25 and the lower reference voltage generation unit 26. On the other hand, since the voltage input from the VIN terminal of the switching control circuit 340 is input to the VDD terminal, it corresponds to the VIN terminal of the switching control circuit 340.

  More specifically, the reference voltage generation unit 20 includes a first MOS transistor Ml that has a control gate and a floating gate and functions as a depletion type. The reference voltage generation unit 20 includes a second write MOS transistor M2 that has a control gate and a floating gate and functions as an enhancement type. The second write MOS transistor M2 is connected in series with the first MOS transistor Ml. The first MOS transistor Ml and the second write MOS transistor M2 are nonvolatile memory elements having tunnel oxide films through which charges injected into the floating gate tunnel. As a result, the reference voltage generator 20 outputs a reference voltage from the connection point of the first MOS transistor Ml and the second write MOS transistor M2.

  FIG. 27 shows an example of the circuit configuration of the reference voltage generation unit 20. The upper reference voltage generation unit 25 and the lower reference voltage generation unit 26 may each have the same circuit as the reference voltage generation unit 20 shown in FIG. The reference voltage generator 20 includes a first write MOS transistor M1w having a tunnel oxide film, a first output MOS transistor M1r having no tunnel oxide film, a second write MOS transistor M2w having a tunnel oxide film, and a tunnel A second output MOS transistor M2r having no oxide film is included.

  First write MOS transistor M1w and first output MOS transistor M1r each have a floating gate and a control gate. The floating gate and control gate of first write MOS transistor M1w are electrically connected to the floating gate and control gate of first output MOS transistor M1r, respectively.

  The source terminal of the first write MOS transistor M1w is connected to the drain terminal of the second write MOS transistor M2w. Similarly to the configuration shown in FIG. 26, a switch for switching whether to connect the first write MOS transistor M1w and the second write MOS transistor M2w may be further provided. The switch SW1 selects whether to apply a voltage VPP or a voltage VSS such as a ground potential to the drain terminal of the first write MOS transistor M1w. The switch SW2 selects whether to apply a voltage VPP or a voltage VSS such as a ground potential to the source terminal of the second write MOS transistor M2w.

  A predetermined voltage VDD is applied to the drain terminal of the first output MOS transistor M1r. The source terminal of the first output MOS transistor M1r is connected to the drain terminal of the second output MOS transistor M2r. The voltage at the connection point is output as a reference voltage. The voltage VSS is applied to the source terminal of the second output MOS transistor M2r.

  Second write MOS transistor M2w and second output MOS transistor M2r each have a floating gate and a control gate. The floating gate and control gate of second write MOS transistor M2w are electrically connected to the floating gate and control gate of second output MOS transistor M2r, respectively.

  First write MOS transistor M1w and second write MOS transistor M2w have tunnel oxide films. Therefore, it is possible to control the respective threshold voltages Vth by controlling the state of the charge of the floating gates of the first write MOS transistor M1w and the second write MOS transistor M2w via the tunnel oxide film. As described above, since the floating gate and the control gate of the two first MOS transistors M1w and r are electrically connected to each other, the first output MOS transistor M1r has the same threshold value as the first write MOS transistor M1w. It has a voltage Vth. Similarly, the second output MOS transistor M2r has the same threshold voltage Vth as the second write MOS transistor M2w.

  Since the first output MOS transistor M1r and the second output MOS transistor M2r do not have a tunnel oxide film, even when the power supply voltage VDD is continuously applied, electrons are generated from the tunnel oxide film of the nonvolatile memory element. There is no variation in the threshold voltage Vth due to leaking disturbance. For this reason, the reference voltage can be generated with high accuracy. The first output MOS transistor M1r and the second output MOS transistor M2r form a current path in the reference voltage generator 20, but do not have a switch in the current path. Therefore, the on-resistance of the switch does not affect the reference voltage, and the reference voltage can be generated with high accuracy.

  FIG. 28 is a flowchart illustrating an example of a reference voltage setting method. In step S10, the target voltage input to the power supply terminal of the CMOS inverter 55 is set to a predetermined value.

  In the reference voltage detection mode, the comparator 50 detects a voltage to be input to the input terminal of the CMOS inverter 55 in order to operate according to the target voltage. In step S20, as described in FIG. 23, the reference voltages (VrefH, VrefL) corresponding to the target voltage set in step S10 are detected. The detected reference voltages (VrefH, VrefL) are stored in an external device of the switching control circuit 340. The detected reference voltages (VrefH, VrefL) may be stored in the switching control circuit 340.

  In the reference voltage setting mode, the reference voltages (VrefH, VrefL) detected in step S20 are set in the reference voltage generation unit 20. Step S30 for executing the reference voltage setting mode includes steps S31 to S33. Note that the process of step S30 is performed for each target voltage. The set target voltage is input to the power supply terminal of the CMOS inverter 55.

  In step S31, the state of the charge stored in the floating gate of the first write MOS transistor M1w is set to a predetermined reference state. The reference state in step S31 may refer to a state in which the threshold voltage of the first MOS transistors M1w and r is sufficiently increased so that no current flows from the first MOS transistors M1w and r to the second MOS transistors M2w and r. The reference state may refer to a state where charges stored in the floating gate are erased (that is, a state where the amount of charges in the floating gate is substantially zero). In step S31, the control pulse is applied to the control gate of the first write MOS transistor M1w to adjust the state of the electric charge in the floating gate to the reference state, and the current flows from the first MOS transistor M1w, r to the second MOS transistor M2w, r. Will not flow.

  In step S32, a control pulse is applied to the control gate of the second write MOS transistor M2w with the adjustment current generated by the current mirror 71 applied to the second output MOS transistor M2r. By applying the control pulse, the threshold voltage of the second write MOS transistor M2w is changed in the positive direction. As a result, the two second MOS transistors M2 are set to a predetermined enhancement state. The adjustment current may be supplied with a current substantially equal to the current that should flow through the second output MOS transistor M2r during actual operation. In step S32, a control pulse is applied to the control gate of the second write MOS transistor M2w until the reference voltage output from the reference voltage generation unit 20 is substantially equal to the reference voltage detected in step S20 with respect to the target voltage. Apply.

  Next, in step S33, a control pulse is applied to the control gate of the first write MOS transistor M1w without applying the adjustment current generated by the current mirror 71 to the second output MOS transistor M2r. By applying the control pulse, the threshold voltage of the first write MOS transistor M1w is changed in the negative direction. As a result, the two first MOS transistors M1 are set to a predetermined depletion state. Also in step S33, the control pulse is applied to the control gate of the first write MOS transistor M1w until the reference voltage output from the reference voltage generation unit 20 is substantially equal to the reference voltage detected in step S20 with respect to the target voltage. Apply. Such processing is performed on the upper reference voltage generation unit 25 and the lower reference voltage generation unit 26. Thereby, a voltage equal to the reference voltage detected in step S20 can be output to the upper reference voltage generation unit 25 and the lower reference voltage generation unit 26. In step S30, the upper reference voltage VrefH may be set before the lower reference voltage VrefL, or the lower reference voltage VrefL may be set first.

  FIG. 29 is a diagram for explaining a reference voltage setting method. FIG. 29A shows a method of setting the second MOS transistors M2w and r that function as an enhancement type. First, the charge charged in the floating gate of the first write MOS transistor Mlw is set to the reference state. For example, by applying a control pulse that sufficiently increases the threshold voltage of the first write MOS transistor Mlw to the control gate, the charge state is set to the reference state. The polarity of the voltage applied to the control gate can be controlled by switching the switches SW1 and SW9. This prevents current from flowing through the first MOS transistors Mlw and r when setting the second MOS transistors M2w and r that function as an enhancement type.

  Next, in a state where the adjustment current Iref is applied to the second output MOS transistor M2r, a control pulse is applied to the control gate of the second write MOS transistor M2w to charge the floating gate. At this time, charges are charged to the floating gate of the second write MOS transistor M2w so that the reference voltage output from the reference voltage generator 20 becomes a predetermined voltage.

  FIG. 29B shows a method of setting the first MOS transistors M1w and r that function as a depletion type. When setting the first MOS transistors M1w and r, the adjustment current Iref is stopped. Then, a control pulse is applied to the control gate of the second write MOS transistor M2w to charge the floating gate so that the current flowing through the second output MOS transistor M2r is substantially the same as the adjustment current Iref. . In this example, instead of detecting the current flowing through the second output MOS transistor M2r, the second write MOS transistor M2w is floated so that the reference voltage output from the reference voltage generation unit 20 becomes the predetermined voltage described above. Charge the gate.

  FIG. 30 shows a method for setting the nonvolatile memory element 90. The nonvolatile memory element 90 corresponds to the first write MOS transistor M1w and the second write MOS transistor M2w described above. The nonvolatile memory element 90 is an NMOS type element having a control gate and a floating gate. In the nonvolatile memory element 90, the threshold voltage is adjusted by accumulating charges in the floating gate by FN tunneling.

  FIG. 30A shows a bias condition when the threshold voltage of the nonvolatile memory element 90 is changed in the positive direction. FIG. 30B shows a bias condition when the threshold voltage of the nonvolatile memory element 90 is changed in the negative direction. Under these bias conditions, the threshold voltage of the nonvolatile memory element 90 is controlled by applying a control pulse to the control gate.

  When the threshold voltage is changed in the positive direction, as shown in FIG. 30A, the voltage VPP is applied to the control gate terminal, the source terminal is grounded, and the drain terminal is brought into a floating state. As a result, electrons are injected into the floating gate of the nonvolatile memory element 90 by FN tunneling, and the threshold voltage Vth of the nonvolatile memory element 90 increases. The voltage VPP is a voltage necessary for FN tunneling in the tunnel oxide film of the nonvolatile memory element 90.

  When the threshold voltage is changed in the positive direction, as shown in FIG. 30B, the control gate terminal is grounded, the voltage VPP is applied to the source terminal, and the drain terminal is brought into a floating state. As a result, the nonvolatile memory element 90 emits electrons from the floating gate by FN tunneling, and the threshold voltage Vth of the nonvolatile memory element 90 decreases. By combining the operations described in FIGS. 30A and 30B, the threshold voltage of the nonvolatile memory element 90 can be adjusted to a predetermined voltage. As described above, if the threshold voltages of the first write MOS transistor M1w and the second write MOS transistor M2w are adjusted, the threshold voltages of the first output MOS transistor M1r and the second output MOS transistor M2r are similarly adjusted. .

  FIG. 31 shows an example of the operation of the switching control circuit 340 in the reference voltage setting mode. The switching control circuit 340 of this example shows a state in which writing to the second write MOS transistor M2w of the upper reference voltage generation unit 25 is performed. The configuration used in this example is mainly indicated by a bold line.

  The mode selection unit 80 applies a control pulse to the second write MOS transistor M2w of the upper reference voltage generation unit 25. The mode selection unit 80 causes the voltage selection unit 40 to select the Vref terminal. In this case, no voltage is input from the outside to the Vref terminal. The current mirror 71 generates an adjustment current Iref smaller than the external current IREF based on the external current IREF, and outputs it to the upper reference voltage generation unit 25. For example, the current mirror 71 generates the adjustment current Iref having a magnitude 1 / n times the external current IREF (where n> 1). Thereby, a minute adjustment current Iref can be generated with high accuracy. When the switching control circuit 340 does not have the current mirror 71, a minute adjustment current Iref may be input from the outside of the switching control circuit 340.

  The amplifier circuit 72 receives the output of the upper reference voltage generation unit 25 via the voltage selection unit 40, and outputs a signal obtained by amplifying the output to the VMON terminal. The amplified signal output from the amplifier circuit 72 is input to the voltmeter 75. Thereby, the signal-to-noise ratio in the measuring device connected to the VMON terminal is improved. The voltmeter 75 detects the voltage of the amplified signal output from the amplifier circuit 72. Further, a voltmeter 75 may be provided outside the switching control circuit 340. The mode selection unit 80 applies a control pulse to the second write MOS transistor M2w of the upper reference voltage generation unit 25 so that the voltage output from the amplifier circuit 72 becomes a voltage corresponding to the reference voltage to be set.

  The upper reference voltage generation unit 25 of this example sets the upper reference voltage VrefH using adjustment sequences (1) to (5) described later. Further, when the reference voltage VrefL is set in the lower reference voltage generation unit 26, the same configuration as that of the upper reference voltage generation unit 25 of the present example is set.

  FIG. 32 shows an example of a write operation to the second write MOS transistor M2w. The vertical axis indicates the monitor voltage [V], and the horizontal axis indicates time t. A control pulse is input from the mode selection unit 80 to the second write MOS transistor M2w.

  First, a first control pulse is applied to the control gate of the second write MOS transistor M2w to set the state of charge accumulated in the floating gate of the second write MOS transistor M2w to a predetermined initial state. . As a result, the monitor voltage Vmon obtained by monitoring the voltage output from the reference voltage generator 20 increases. The control pulse is applied to the control gate of the second write MOS transistor M2w until the monitor voltage Vmon of the reference voltage generation unit 20 becomes sufficiently higher than the end voltage to be set.

  Next, a second control pulse is applied to the control gate of the second write MOS transistor M2w to control the charge state of the floating gate of the second write MOS transistor M2w. The second control pulse is a pulse having a polarity opposite to that of the first control pulse. In this example, the monitor voltage Vmon of the reference voltage generation unit 20 decreases by applying the second control pulse. The second control pulse is applied so that the monitor voltage Vmon of the reference voltage generation unit 20 gradually approaches the end voltage.

  When the pulse width of the control pulse is wide or the pulse voltage is large, the amount of fluctuation of the charge stored in the floating gate per pulse becomes large. When the amount of change in charge is large, the monitor voltage tends to greatly exceed the end voltage. Therefore, the mode selection unit 80 decreases the intensity of the second control pulse by adjusting at least one of the pulse width or voltage of the second control pulse as the monitor voltage Vmon approaches the end voltage. Note that the mode selection unit 80 may input the first control pulse to the control gate when the second control pulse is applied and the monitor voltage Vmon becomes lower than the end voltage. As a result, the monitor voltage Vmon can be brought close to the end voltage. Such processing is continued until the difference between the monitor voltage Vmon and the end voltage falls within an allowable range.

  Mode selection unit 80 is connected to the VPP terminal, DATA terminal, SCLK terminal, and PULSE terminal. The mode selection unit 80 controls the voltage of the control pulse according to the voltage input from the VPP terminal. In addition, the mode selection unit 80 controls the pulse width of the control pulse by a periodic signal input from the PULSE terminal. The SCLK terminal outputs a clock signal serving as an operation clock for the mode selection unit 80 to the mode selection unit 80. The DATA terminal outputs a data signal related to the test mode to the mode selection unit 80.

  FIG. 33 shows an example of the operation of the switching control circuit 340 in the reference voltage setting mode. The switching control circuit 340 of this example shows a state in which writing to the first write MOS transistor M1w of the upper reference voltage generation unit 25 is performed. The configuration used in this example is indicated by a bold line.

  Writing to the first write MOS transistor M1w differs from writing to the second write MOS transistor M2w shown in FIG. 31 in that the output of the current mirror 71 is not input to the upper reference voltage generation unit 25. . Other configurations are basically the same as those in FIG.

  FIG. 34 shows a write operation to the first write MOS transistor M1w. The vertical axis indicates the monitor voltage [V], and the horizontal axis indicates time t. A control pulse is input from the mode selector 80 to the first write MOS transistor M1w.

  First, a first control pulse is applied to the control gate of the first write MOS transistor M1w to set the state of charge accumulated in the floating gate of the first write MOS transistor M1w to a predetermined initial state. . As a result, the monitor voltage Vmon of the reference voltage generator 20 decreases. The first control pulse is applied to the control gate of the first write MOS transistor M1w until the monitor voltage Vmon of the reference voltage generator 20 becomes sufficiently smaller than the end voltage.

  Next, a second control pulse is applied to the control gate of the first write MOS transistor M1w to control the state of charge accumulated in the floating gate of the first write MOS transistor M1w. The second control pulse is a pulse having a polarity opposite to that of the first control pulse. In this example, the monitor voltage Vmon of the reference voltage generation unit 20 is increased by applying the second control pulse. The second control pulse is adjusted so that the monitor voltage Vmon of the reference voltage generation unit 20 gradually approaches the end voltage.

  Also in the case of the write operation to the first write MOS transistor M1w, the mode selection unit 80 adjusts at least one of the pulse width or voltage of the second control pulse as the monitor voltage Vmon approaches the end voltage, Reduce the intensity of the control pulse. The reference voltage setting mode ends when the monitor voltage Vmon substantially matches the end voltage. The monitor voltage Vmon substantially coincides with the end voltage, but it does not necessarily need to be completely coincident and may be considered to be substantially coincident depending on the use situation.

FIG. 35 shows an example of a circuit configuration of the reference voltage generation unit 20 according to the present embodiment. Each configuration is the same as the circuit configuration of the reference voltage generation unit 20 shown in FIG. In the state where the reference voltage generator 20 outputs the reference voltage in the actual operation mode, the switch is controlled as follows as shown in FIG.
SWl: VSS
SW2: VSS
SW3, SW4: OPEN
SW5, SW7: SHORT (connection)
SW9, SW10: Arbitrary

  The reference voltage generation unit 20 uses the first MOS transistors M1w, r set to the depletion state and the second MOS transistors M2w, r set to the enhancement state with the switches controlled as in this example, A reference voltage is generated.

The reference voltage output from the reference voltage generator 20 is adjusted using the adjustment sequences (1) to (5).
<Adjustment sequence (1)>
FIG. 36 shows an example of the circuit configuration of the reference voltage generation unit 20. The mode selection unit 80 applies a control pulse to the control gate of the first MOS transistor M1w, thereby setting the state of the charge stored in the floating gates of the first MOS transistors M1w and r as a reference state. In this example, control is performed so that the threshold voltage of the first MOS transistors M1w and r is sufficiently higher than the reference voltage to be set in the reference voltage generation unit 20. In the adjustment sequence (1), the switch is controlled as follows. As a result, no current flows from the first MOS transistor M1 to the second MOS transistor M2.
SWl: VSS
SW2: VSS
SW3: SHORT
SW4: OPEN
SW5, SW7: OPEN
SW9: VPP
SW10: Optional

<Adjustment sequence (2)>
FIG. 37 shows an example of the circuit configuration of the reference voltage generation unit 20. The mode selection unit 80 sets the second MOS transistors M2w and r to the initial state described with reference to FIG. 32 by applying the first control pulse to the control gate of the second write MOS transistor M2w. In the adjustment sequence (2), the switch is controlled as follows.
SWl: VSS
SW2: VSS
SW3: OPEN
SW4: SHORT
SW5, SW7: OPEN
SW9: Arbitrary SW10: VPP

<Confirmation sequence>
The states of the second MOS transistors M2w and r in the adjustment sequence (2) and the adjustment sequence (3) to be described later can be determined by monitoring the reference voltage output from the reference voltage generation unit 20.
FIG. 38 shows an example of the circuit configuration of the reference voltage generation unit 20. The switching control circuit 340 of this example checks the reference voltage output by the reference voltage generation unit 20 by flowing the adjustment current Iref through the second output MOS transistor M2r. In the confirmation sequence, the switch is controlled as follows.
SW1, SW2: VSS
SW3, SW4, SW5: OPEN
SW7: SHORT
SW9, SW10: Arbitrary

  FIG. 39 shows the change amount of the threshold voltage Vth with respect to the writing time of the first control pulse in the adjustment sequence (2). The vertical axis represents the threshold voltage Vth of the second MOS transistors M2w and r, and the horizontal axis represents the writing time of the first control pulse to the second MOS transistors M2w and r.

  The threshold voltage Vth of the second MOS transistors M2w and r changes with time as shown in FIG. 39 as the writing time of the first control pulse increases. The mode selection unit 80 generates the first control pulse until the initial state described with reference to FIG.

<Adjustment sequence (3)>
FIG. 40 shows an example of the circuit configuration of the reference voltage generation unit 20. The mode selection unit 80 applies the second control pulse to the control gate of the second write MOS transistor M2w, thereby setting the reference voltage output from the reference voltage generation unit 20 to a predetermined end voltage as described in FIG. Move closer to. In the adjustment sequence (3), the second control pulse is applied while supplying the adjustment current Iref to the second output MOS transistor M2r. In the adjustment sequence (3), the switch is controlled as follows. When the reference voltage is too lower than a predetermined voltage, the first control pulse may be applied to the control gate of the second write MOS transistor M2w to increase the reference voltage.
SWl: VSS
SW2: VPP
SW3: OPEN
SW4: SHORT
SW5, SW7: OPEN
SW9: Arbitrary SW10: VSS

  FIG. 41 shows changes in the threshold voltage Vth in the adjustment sequences (2) and (3). The vertical axis represents the threshold voltage Vth of the second MOS transistors M2w and r, and the horizontal axis represents time.

  In the configuration according to FIG. 40, the threshold voltage Vth of the second MOS transistors M2w and r decreases according to the writing time of the second control pulse as shown in the adjustment sequence (3) of FIG. By adjusting the writing time, the threshold voltage Vth of the second MOS transistors M2w and r is adjusted to be the reference voltage.

  FIG. 42 shows changes in the threshold voltage Vth when the adjustment sequence (3) and the confirmation sequence are alternately performed. In the confirmation sequence, no control pulse is applied to the control gate of the second write MOS transistor M2w, so the reference voltage does not change. The mode selection unit 80 may control the pulse width and voltage of the second control pulse generated in the adjustment sequence (3) according to the reference voltage confirmed in the immediately preceding confirmation sequence.

  The adjustment sequence (3) ends when the reference voltage output from the reference voltage generator 20 reaches a predetermined value. Thereby, the adjustment of the second MOS transistors M2w and r ends. Next, the first MOS transistors M1w and r are adjusted.

<Adjustment sequence (4)>
FIG. 43 shows an example of a circuit configuration of the reference voltage generation unit 20. The mode selection unit 80 sets the first MOS transistors M1w and r to the initial state described with reference to FIG. 34 by applying a first control pulse to the control gate of the first write MOS transistor M1w. In the adjustment sequence (4), the switch is controlled as follows.
SWl: VPP
SW2: VSS
SW3: SHORT
SW4, SW5, SW7: OPEN
SW9: VSS
SW10: Optional

<Adjustment sequence (5)>
FIG. 44 shows an example of a circuit configuration of the reference voltage generation unit 20. The mode selection unit 80 applies the second control pulse to the control gate of the first write MOS transistor M1w, thereby setting the reference voltage output from the reference voltage generation unit 20 to a predetermined end voltage as described in FIG. Move closer to. In adjustment sequences (4) and (5), adjustment current Iref is not applied from the outside. However, the first MOS transistors M1w and r generate a current corresponding to the adjustment current Iref. In the adjustment sequence (5), the switch is controlled as follows.
SW1, SW2: VSS
SW3, SW4: OPEN
SW5, SW7: SHORT
SW9, SW10: Arbitrary

  FIG. 45 shows changes in the threshold voltage Vth in the adjustment sequences (4) and (5). The vertical axis represents the threshold voltage Vth of the first MOS transistors M1w and r, and the horizontal axis represents time. In the adjustment sequence (4), the threshold voltage Vth of the first MOS transistors M1w and r decreases with time as shown in FIG. 45 as the writing time of the first control pulse increases. The mode selection unit 80 generates the first control pulse until the initial state described with reference to FIG.

  In the adjustment sequence (5), the threshold voltage Vth of the first MOS transistors M1w and r increases according to the writing time of the second control pulse. By adjusting the writing time, the threshold voltage Vth of the first MOS transistors M1w and r is adjusted to be the reference voltage. In the confirmation sequence, the control pulse is not applied to the control gate of the first write MOS transistor M1w, so the reference voltage does not change. The mode selection unit 80 may control the pulse width and voltage of the second control pulse generated in the adjustment sequence (5) according to the reference voltage confirmed in the immediately preceding confirmation sequence.

  The adjustment sequence (5) ends when the reference voltage output from the reference voltage generation unit 20 reaches a predetermined value. As a result, the adjustment of the first MOS transistors M1w and r ends, and the adjustment of the reference voltage generation unit 20 ends. When checking the reference voltage in the adjustment sequences (4) and (5), each switch may be controlled in the same manner as in actual operation. For example, each switch is controlled similarly to the example shown in FIG.

  FIG. 46 is a diagram illustrating a connection example of the current mirror 71. The mode selection unit 80 of this example includes a write circuit 85 that operates as a gate control unit. The write circuit 85 controls the switches SW1 to SW10 described with reference to FIGS. 26 to 45, thereby controlling the control gates of the first write MOS transistor M1w and the second write MOS transistor M2w of the reference voltage generation unit 20. Input a control pulse to.

  In the reference voltage setting mode, the current mirror 71 generates an adjustment current Iref smaller than the external current IREF based on the external current IREF input from the outside of the switching control circuit 340. For example, the current mirror 71 generates the adjustment current Iref having a magnitude of 1 / n based on the external current IREF input from the outside of the switching control circuit 340. The current mirror 71 of this example is connected to an external terminal common to the first output MOS transistor M1r. The current mirror 71 generates a minute adjustment current Iref smaller than the external current IREF based on the external current IREF input from the external terminal.

  Further, a switch SW0 is provided between the current mirror 71 and the output terminal of the reference voltage generation unit 20. In accordance with each adjustment sequence, the mode selection unit 80 controls the switch SW0. For example, in the adjustment sequence (3), the mode selection unit 80 turns on the switch SW0. In the adjustment sequences (4) and (5), the mode selection unit 80 turns off the switch SW0 and cuts off the adjustment current Iref flowing through the second output MOS transistor M2r.

  In this example, the reference voltage is set by adjusting the charge stored in the floating gates of the first MOS transistors M1w and r in the adjustment sequence (1) to the reference state, and adjusting the second output MOS transistor M2r in the adjustment sequence (3). A current Iref is input. Therefore, when the adjustment current Iref flows through the second output MOS transistor M2r, no current flows from the first output MOS transistor M1r to the second output MOS transistor M2r. For this reason, the setting accuracy of the second MOS transistors M2w and r is improved. Therefore, it is not necessary to provide a switch for blocking the influence of the electric charge accumulated in the depletion type MOS transistor M1r at the drain end of the first output MOS transistor M1r.

  FIG. 47 shows an example of the configuration of the switching control circuit 340 in the actual operation mode. The switching control circuit 340 uses the VIN terminal, the OUT terminal, and the GND terminal when the mode selection unit 80 selects the actual operation mode. The switching control circuit 340 detects whether or not the voltage input from the VIN terminal is equal to or higher than a predetermined target voltage, and outputs the detected voltage to the OUT terminal.

  The upper reference voltage generator 25 outputs the upper reference voltage VrefH. The lower reference voltage generator 26 outputs the lower reference voltage VrefL. The comparator 50 receives the reference voltages (VrefH, VrefL) and the input voltage Vin. The comparator 50 outputs a signal corresponding to the reference voltage (VrefH, VrefL) and the input voltage Vin to the OUT terminal.

  The voltage selection unit 40 selects a reference voltage (VrefH, VrefL) according to the output of the comparator 50. The voltage selection unit 40 inputs the selected reference voltages (VrefH, VrefL) to the comparator 50. Thereby, the target voltage of the CMOS inverter 55 is changed according to the output of the comparator 50 so as to perform a hysteresis operation.

  FIG. 48 shows another connection example of the first MOS transistor M1 and the second MOS transistor M2 in the reference voltage generation unit 20. Note that the first MOS transistor M1 and the second MOS transistor M2 in FIG. 48A are the same elements as the first MOS transistor M1 and the second MOS transistor M2 in FIG. The first MOS transistor M1 and the second MOS transistor M2 in FIG. 48B are nonvolatile memory elements similar to the first MOS transistor M1 and the second MOS transistor M2 in FIG.

  In this example, the gate of the first MOS transistor M1 is connected to the source of the second MOS transistor M2. The source of the first MOS transistor M1, the drain of the second MOS transistor M2, and the gate of the second MOS transistor M2 are connected to each other. The reference voltage generation unit 20 outputs a reference voltage from the connection point.

  In the configuration shown in FIG. 27, the first MOS transistor M1 and the second MOS transistor M2 on the write side and the output side may have the same connection as the first MOS transistor M1 and the second MOS transistor M2 in FIG. Even in this case, the first MOS transistor M1 and the second MOS transistor M2 on the write side and the output side can be set by a method similar to the method described in FIGS.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 ... Power generation device, 15 ... Load, 20 ... Reference voltage generation part, 25 ... Upper reference voltage generation part, 26 ... Lower reference voltage generation part, 30 ... Inverter, 40・ ・ ・ Voltage selection unit 41 ・ ・ ・ First voltage selection unit 42 ・ ・ ・ Second voltage selection unit 50 ・ ・ ・ Comparator 51 ・ ・ ・ First comparator 52 ・ ・ ・ Second comparator 53 ... 1st inverter, 54 ... 2nd inverter, 55 ... CMOS inverter, 56 ... Output circuit, 57 ... Output switching unit, 70 ... Test circuit, 71 ... Current mirror 72 ... Amplifier circuit, 75 ... Voltmeter, 80 ... Mode selection unit, 85 ... Write circuit, 90 ... Non-volatile memory element, 91 ... Substrate, 92 ... Source Region, 93... Drain region, 94 .. tunnel 95 ... Floating gate, 96 ... Insulating film, 97 ... Control gate, 100 ... Power supply circuit, 200 ... Overcharge prevention circuit, 210 ... Overcharge prevention switching control 220, shunt circuit, 230 ... overcharge prevention switching unit, 250 ... overdischarge prevention circuit, 260 ... overdischarge prevention switching control unit, 270 ... overdischarge prevention switching unit, 300 ... Switch control unit, 310 ... First switch control unit, 320 ... Second switch control unit, 330 ... Third switch control unit, 340 ... Switch control circuit, 350 ... 1 Stage configuration switching control unit, 360 ... Two-stage configuration switching control unit, 400 ... Switching circuit, 410 ... First switching switch, 420 ... Charging control unit, 425 ... Switching control unit, 426 ... Switching output unit, 43 ... second changeover switch, 450 ... start-up circuit, 470 ... level shifter circuit, 471 ... first upper PMOS transistor, 472 ... second upper PMOS transistor, 473 ... first lower side NMOS transistor, 474... Second lower NMOS transistor, 500... Capacitor, 550.

Claims (10)

A power supply circuit that outputs output power to a load according to input power generated by a power generation device,
An input / output unit that has a supply terminal and outputs the supply power corresponding to the input power input from the supply terminal;
A power storage terminal connected to a power storage device for storing power from the supply terminal;
A capacitor terminal having a capacity smaller than the capacity of the power storage device, to which a capacitor for storing power from the supply terminal is connected;
A load terminal that receives the supplied power or the stored power stored in the power storage device and outputs the output power to the load;
A first switch for switching whether or not the power storage terminal is connected to the supply terminal and the load terminal; and whether the voltage of the capacitor terminal exceeds a predetermined power storage device power storage start voltage or not. A first switching control unit for switching on and off ;
A second switch for switching whether to connect the load terminal to the supply terminal and the storage terminal;
A second switching control unit that switches on and off the second switch depending on whether the voltage of the capacitor terminal exceeds a power supply start voltage smaller than the power storage start voltage of the power storage device ;
The first switching control unit
A first reference voltage generating unit that generates a predetermined first reference voltage corresponding to the power storage device storage start voltage;
A first comparator having a first CMOS inverter, wherein the first reference voltage is input to an input terminal of the first CMOS inverter, and a voltage of the capacitor terminal is input to a power supply terminal of the first CMOS inverter;
The first comparator detects whether the voltage of the capacitor terminal exceeds the power storage device storage start voltage depending on whether the output of the first CMOS inverter is inverted ,
The second switching control unit
A second reference voltage generator that generates a predetermined second reference voltage corresponding to the power supply start voltage;
A second comparator having a second CMOS inverter, wherein the second reference voltage is input to an input terminal of the second CMOS inverter, and a voltage of the capacitor terminal is input to a power supply terminal of the second CMOS inverter;
Have
The second comparator is a power supply circuit that detects whether the voltage of the capacitor terminal exceeds the power supply start voltage depending on whether the output of the second CMOS inverter is inverted . A third switch for switching whether or not to connect the supply terminal to the capacitor terminal, the load terminal, and the power storage terminal; and a voltage at the supply terminal is smaller than the power storage device power storage start voltage; A third switching control unit for switching on and off of the third switch depending on whether or not a larger capacitor storage start voltage is exceeded,
The third switching control unit
A third reference voltage generator for generating a predetermined third reference voltage corresponding to the capacitor storage start voltage;
A third comparator that includes a third CMOS inverter, the first reference voltage is input to an input terminal of the third CMOS inverter, and a voltage of the supply terminal is input to a power supply terminal of the third CMOS inverter;
2. The power supply circuit according to claim 1 , wherein the third comparator detects whether the voltage of the supply terminal exceeds the capacitor storage start voltage based on whether the output of the third CMOS inverter is inverted. One end of the first switch is connected to the power storage terminal, and the other end is connected to the second switch and the third switch,
One end of the second switch is connected to the load terminal, and the other end is connected to the first switch and the third switch,
One end of the third switch is connected to the supply terminal, and the other end is connected to the first switch and the second switch,
The power supply circuit according to claim 2 , wherein the capacitor terminal is connected to the other end of the first switch, the second switch, and the third switch. When the voltage of the supply terminal exceeds the capacitor storage start voltage,
The first switch and the second switch are in an off state,
Said third switching control unit, the power supply circuit of claim 3, turning on the third switch. When the voltage of the capacitor terminal exceeds the power supply start voltage,
The first switch is turned off and the third switch is turned on;
The power supply circuit according to claim 3 or 4, wherein the second switching control unit turns on the second switch. Wherein the first switching control unit, the voltage of the capacitor terminal, wherein, when it exceeds the power storage device power storage start voltage, the power supply circuit according to claims 3 to any one of 5 to turn on the first switch . Power supply circuit according to any one of claims 1 6 comprising the power storage device and said capacitor. The input / output unit includes an overcharge prevention circuit,
The overcharge prevention circuit is
A fourth switch for switching whether or not to connect the output terminal of the power generator and the terminal of the capacitor;
A fifth switch for switching whether to connect the output terminal of the power generator to a lower potential than the output terminal of the power generator;
The power supply circuit according to any one of claims 1 to 7 , further comprising: a charge control unit configured to complementarily operate the fourth switch and the fifth switch. A switching circuit provided between the power generation device and the power storage device;
The switching circuit is
A changeover switch for switching whether to connect the power generation device and the power storage device;
Said detecting a voltage generating device outputs, any one of claims 1 and a charging control unit that turns off the changeover switch when the detected voltage of said power generating device has a value less than a predetermined 8 one The power supply circuit according to the item. The power supply circuit according to claim 9 , wherein the charging control unit detects a voltage output from the power generation device at a predetermined cycle.

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