JP6301942B2 - Load drive current detection device - Google Patents

Description

  The present invention relates to a load drive current detection method and an apparatus using the same.

  As various control objects are electronically controlled, electric actuators such as motors and solenoids are widely used to convert electrical signals into mechanical motion and hydraulic pressure. In order to drive these electric actuators, it is necessary to detect the current flowing through the load that is the driving target with high accuracy.

  A method for providing a load drive current detection device for detecting a small current flowing in a current detection MOS by connecting a small current detection MOS in parallel to a driver MOS or transistor (hereinafter referred to as MOS) for driving a load (For example, Patent Document 1 and Patent Document 2).

  When a driver MOS connected to drive a load (for example, a solenoid) is driven on and off for, for example, PWM (Pulse Width Modulation) control, the driver MOS is driven by a high frequency component of the output voltage of the driver MOS. Electro Magnetic Interference) noise is generated.

  A method for reducing the EMI noise by providing a sufficient rise time and fall time (hereinafter also referred to as slope or slope) of the load drive voltage waveform is known.

JP 2011-69809 A JP 2006-203415 A

  As an example of a conventional load drive current detection device, a description will be given using the configuration of FIG. 13 and the timing chart of FIG.

  The load drive current detection device 100 shown in FIG. 13 is electrically connected in parallel with the high-side driver MOS 11 and the high-side driver MOS 11 that cause the drive current Iout to flow through the electromagnetic load 4 such as a solenoid or inductor connected to the ground GND. A high-side current detection circuit 12, a low-side driver MOS 21 that causes the drive current Iout to flow through the electromagnetic load 4 and is electrically connected in series with the high-side driver MOS 11, and an output current IcurH of the high-side current detection circuit 12 A resistor 3 for converting to a voltage value and a voltage measuring circuit 5 for the voltage value converted by the resistor 3 are provided.

  FIG. 14 shows an example of a timing chart of the conventional load drive current detection device of FIG.

  The gate drive signal HGATE of the high-side driver MOS 11 and the high-side current detection circuit, the gate drive signal LGATE of the low-side driver MOS 21, the voltage of the OUT terminal that is an output terminal to the electromagnetic load 4, and the high-side drive MOS 11 FIG. 14 shows the output current ImH, the output current IcurH of the high-side current detection circuit 12, the drain-source voltage VDSH of the high-side driver MOS 11, and the power loss PdH of the high-side driver MOS 11 obtained by ImH × VDSH. .

  To reduce the EMI of the high side driver, as shown in FIG. 14, by providing a slope, the power loss PdH increases particularly when the high side driver falls.

  Due to the difference in characteristics of the high-side driver MOS 11 and the high-side current detection circuit 12 with respect to heat generation, there is an error in the relationship between the high-side driver drive current IoutH assumed when detecting the current and the output current IcurH of the high-side current detection circuit. Occurs, and a current detection error occurs.

  Therefore, the present invention provides a load drive current detection device that enables both EMI reduction of a high-side driver and high accuracy of a current detection function.

In order to solve the above-described problems, the present invention provides a high-side driver MOS for supplying a driving current to an electromagnetic load connected to a ground, and a high-side current detection circuit electrically connected in parallel with the high-side driver MOS. A low-side driver MOS that supplies a driving current to the electromagnetic load and is electrically connected in series with the high-side driver MOS; and a low-side current detection circuit that is electrically connected in parallel with the low-side driver MOS; A resistor for converting the output current of the high-side current detection circuit into a voltage value, a voltage measurement circuit for the voltage value converted by the resistor, and driving of the low-side driver MOS based on the output current of the low-side current detection circuit A current detection circuit for detecting a current, and the low side based on a current detection signal of the current detection circuit; Detecting a MOS reflux for current drivers, the period from the falling edge to the start of the return current of the MOS gate drive signal for the high-side driver, using an enable signal which is an output signal of the enable signal generating circuit, wherein The load driving current detecting device is characterized in that the detection of the driving current of the high side driver MOS based on the output current of the high side current detecting circuit by the voltage measuring circuit is stopped.

  ADVANTAGE OF THE INVENTION According to this invention, the load drive current detection apparatus which enables coexistence of EMI reduction of a high side driver and the high precision of a current detection function can be provided.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is a block diagram which shows the structure of the load drive current detection apparatus which is the 1st Embodiment of this invention. It is an example of the electromagnetic load of the Example shown in FIG. It is an example of the electromagnetic load of the Example shown in FIG. It is an example of the electromagnetic load of the Example shown in FIG. It is an Example by another form of the Example shown in FIG. It is an Example by another form of the Example shown in FIG. It is an Example by another form of the Example shown in FIG. It is the Example which applied the load drive current detection apparatus shown in FIG. 5 to electromagnetic load drive. It is an example of the timing chart of the Example shown in FIG. It is an example of the enable signal generation circuit of the Example shown in FIG. It is an example of the falling edge detection circuit of the Example shown in FIG. 7 is an example of a timing chart for generating an enable signal EN in the embodiment shown in FIG. 6. It is a block diagram which shows the structure of the load drive current detection apparatus which is the 2nd Embodiment of this invention. FIG. 12 is an embodiment in which the load driving current detecting device shown in FIG. 11 is applied to electromagnetic load driving. It is a block diagram which shows the structure of the prior art example of a load drive current detection apparatus. It is an example of the timing chart of the prior art example shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the first embodiment of the present invention, the configuration and operation of a load drive current detection device capable of achieving both EMI reduction of a high side driver and high accuracy of a current detection function will be described.

  FIG. 5 shows the overall configuration of the load drive current detection device according to the embodiment of the present invention.

  The load drive current detection device 100 shown in FIG. 5 is configured to generate a gate drive signal HGATE for the high side driver MOS 11 and a low side driver MOS signal in accordance with the PWM signal so that the high side driver MOS 11 and the low side driver MOS 21 are not turned on simultaneously. The pre-driver circuit 9 that generates the gate drive signal LGATE of the MOS 21 and the falling edge detection circuit 10 of the PWM signal are detected, the falling edge timing of the PWM signal is detected, and based on the current detection signal DCURL of the current detection circuit 6. In the period from the falling edge timing of the PWM signal to the start of the return current, the enable signal EN that is the output signal of the enable signal generation circuit 7 is used to detect the return current of the low-side driver MOS 21 and the voltage measurement circuit 5 Of the high-side current detection circuit 12 by Characterized by stopping the detection of the driving current IoutH of MOS11 for high-side driver based on the force current IcurH.

  In FIG. 6, as an example in which the embodiment shown in FIG. 5 is applied to a linear solenoid driver, the driver MOS 11 and current detection circuit 12 of the high side driver 1, the driver MOS 12 and current detection circuit 22 of the low side driver 2, and the current Specific block examples or circuit examples of the detection circuit 6, the enable signal generation circuit 7, the pre-driver circuit 9, and the falling edge detection circuit 10 are shown, and the operation is performed using the timing charts in FIGS. explain.

The linear solenoid driver shown in FIG. 6 includes a power supply VB, a VCP booster circuit 125 that outputs a higher potential than the power supply VB, an electromagnetic load 4 to be driven connected between the ground GND and the OUT terminal, and a power supply VB. A high-side driver MOS 11 that is connected between the electromagnetic loads 4 and drives the electromagnetic load 4; a high-side current detection circuit 12 that is connected in parallel with the high-side driver MOS 11 and detects the high-side drive current IoutH; A low-side driver MOS 21 connected between the electromagnetic load 4 and the ground GND to drive the electromagnetic load 4; a low-side current detection circuit 22 connected in parallel with the low-side driver MOS 21 to detect the low-side drive current IoutL; A detection resistor 3 for converting the output current IcurH of the side current detection circuit 12 into a voltage, and an input; A low side pre-charge that generates a gate voltage HGATE for driving the high-side drive MOS 11 and the detection MOS 121 from the signal PWM and a gate voltage LGATE for driving the low-side drive MOS driver 21 and the detection MOS 221 from the input signal PWM. A driver circuit 9 is provided.

  For example, as shown in FIG. 6, the high-side current detection circuit 12 uses the high-side driver MOS 11, the source terminal, and the gate terminal in common, and the drain terminal uses the drain terminal of the high-side driver MOS 11, the operational amplifier 122, and the MOS 123. A high-side current detection MOS 121 connected so as to be equipotential in a negative feedback circuit, and a current copy circuit that outputs the current IcurH proportional to the input to the ground with the drain current IsH of the high-side current detection MOS 121 as an input 124 is provided. For example, the current copy circuit 124 sets output current = input current / RcH, that is, IcurH = IsH / RcH, as a constant current copy ratio RcH with respect to the input current.

  For example, as shown in FIG. 6, the low-side current detection circuit 22 is a negative feedback circuit using the source terminal of the low-side driver MOS 21, the operational amplifier 222, and the MOS 223 with the drain terminal and the gate terminal shared with the low-side driver MOS 21. A current detection NMOS 221 connected to be equipotential, and a current copy circuit 224 that outputs the current IcurL proportional to the input to the ground with the source current IsL of the low-side current detection MOS 21 as an input. As the current copy circuit 224, for example, output current = input current / RcL, that is, IcurL = IsL / RcL, as a constant current copy ratio RcL with respect to the input current.

The high-side driver MOS 11 and the detection MOS 121 are MOSs on the same silicon substrate, and are preferably arranged in the vicinity, and the ratio of driving current is determined by the ratio of gate width / gate length. For example, when the gate lengths of the high-side driver MOS 11 and the detection MOS 121 are the same, and the gate width of the high-side driver MOS 11 / the gate width of the detection MOS 121 = NH (NH> 1), the high-side driver MOS 11 The drive current ImH and the drive current IsH of the detection MOS 121 are ImH = NH × IsH
Since the output current IoutH of the high side driver is IsH + ImH, the current IsH of the detection MOS 121 is
IsH = IoutH / (NH + 1)
It becomes. The current IsH of the detection NMOS 121 is output as the output current IcurH of the high-side current detection circuit 12 by the current copy circuit 123 having the current copy ratio RcH. That is,
IcurH = IsH / RcH = IoutH / ((NH + 1) × RcH)
The high side current detection circuit 12 outputs a current obtained by multiplying the load current IoutH of the high side driver by 1 / ((NH + 1) × RcH). Here, for example, by setting NH> 1 and RcH> 1, IcurH can have a smaller current value than IoutH.

  For example, as shown in FIG. 2A, the electromagnetic load 4 includes a linear solenoid or inductor 41 connected between the OUT output and the ground GND. Alternatively, as shown in FIG. 2B, in addition to the linear solenoid or the inductor 41, a capacitor 42 may be connected between the OUT output and the ground GND.

The voltage measurement circuit 5 has a function of measuring a voltage value such as an AD converter circuit. Here, the voltage measurement circuit 5 operates when the enable signal EN is H and stops when the enable signal EN is L.
For example, as shown in FIG. 6, the current detection circuit 6 includes a comparator 61, a resistor 62, and a reference voltage source 63. As a result, after the output current IcurL of the low-side current detection circuit 22 is converted into a voltage value by the resistor 62, the current detection signal DCURL that is the output signal of the comparator 61 becomes H level when the voltage level is equal to or higher than the voltage level of the reference voltage source 63. .

  For example, as shown in FIG. 8, the enable signal generation circuit 7 includes a reset priority reset set-flip-flop and an RS-FF 71. Here, the reset priority RS-FF can be composed of an inverter gate 711 and a NAND gate 712.

  The falling edge detection circuit 10 can be constituted by, for example, a rising edge trigger type flip-flop 101 of the clock signal CLK, an inverter gate 102, and an AND gate 103 as shown in FIG. As shown in FIG. 10, during the period from the H → L falling edge of the INH0 signal corresponding to the PWM signal to the next rising edge of the clock signal CLK, as the output signal DET of the falling edge detection circuit 10, An H pulse signal can be generated. In order to adjust the H pulse width, for example, the frequency or duty of the clock signal CLK or a plurality of flip-flops 101 may be connected. The reset priority RS-FF 71 shown in FIG. 8 enables the period from L → H signal change of the DET signal to L → H of the current detection signal DURL which is the output signal of the current detection circuit 6 as shown in FIG. The signal EN can be set to L level.

  For example, as shown in FIG. 6, the pre-driver circuit 9 includes a gate drive signal generation circuit 91, a level shift circuit 92, a high-side pre-driver 93H, and a low-side driver 93L. In response to the PWM input signal, the gate drive signal generation circuit 91 generates periods TA and TB between the output signal INH0 and the output signal INL as shown in FIG. 7, and the high-side driver MOS 11 and the low-side driver are generated. Dead time periods THL and TLH are generated between the gate drive signal HGATE of the high-side driver MOS 11 and the gate drive signal LGATE of the low-side driver MOS 21 so that the MOS MOS 21 does not conduct simultaneously. Here, the dead time period is a period in which the gates of the high-side driver MOS 11 and the low-side driver MOS 21 are both turned off and no through current flows.

  FIG. 7 shows an example of a timing chart of the load drive current detection device of the embodiment of FIG.

  PWM input signals, INH0, INH1, and INL signals in the pre-driver circuit 9, gate drive signals HGATE for the high-side driver MOS 11 and current detection MOS 121, and gate drive signals LGATE for the low-side driver MOS 21 and current detection MOS 221 The voltage of the OUT terminal, which is the output terminal to the electromagnetic load 4, the output current ImH of the high-side drive MOS 11, the output current IcurH of the high-side current detection circuit 12, and the drain-source voltage of the high-side driver MOS 11 The power loss PdH of the high-side driver MOS 11 obtained by VDSH, ImH × VDSH, the output current ImL of the low-side drive MOS 21, the output current IcurL of the low-side current detection circuit 22, and the low-side drive MOS 2 Drain-source voltage VDSL, power loss PdL of the low-side driver MOS 21 obtained by ImL × VDSL, a current detection signal DCURL that is an output signal of the current detection circuit 6, and an enable signal that is an output signal of the enable generation circuit 7 EN is shown in FIG.

  Since the output current Iout flows from the high-side driver MOS 11 to the electromagnetic load 4 during the ON period of the high-side driver, if the influence of the leakage current is ignored, the output terminal OUT is switched from the power supply voltage VB to the ON voltage of the high-side driver MOS 11. The voltage drops by VonH. Here, the on-voltage VonH is VonH = ImH × RonH where the on-resistance of the high-side driver MOS 11 is RonH and the driving current is ImH.

Since the source voltage of the high-side driver MOS 11 is the OUT terminal voltage, when the MOS threshold voltage Vth is used, it is preferable that the on-resistance RonH is low in the driver circuit that drives a large current, and ImH × RonH <Vth Become. From this, the voltage of HGATE required to turn on the high-side driver MOS 11 is
HGATE voltage = VB−VonH + Vth = VB−ImH × RonH + Vth> VB
It becomes. Therefore, the HGATE voltage needs to be equal to or higher than the VB voltage. The VCP voltage supplied to the pre-driver 93H that outputs the HGATE voltage must also be higher than the VB voltage.

  The VCP voltage may be supplied from a device external power supply via a terminal, or may be generated from a VB power supply from a charge pump, a DCDC converter, a bootstrap, or the like.

  When the high-side driver MOS 11 is turned off during the transition from the high-side driver on-period to the high-side driver off-period, a flyback voltage of the electromagnetic load 4 is generated, and the body diode of the low-side driver MOS 21 causes the ground GND to The output current Iout flows. If the influence of the leakage current is ignored at this time, the output terminal OUT becomes a voltage obtained by dropping the forward voltage VOFF of the body diode of the low-side driver MOS 21 from the ground GND. The current flowing at this time is called a return current. The return current is detected by the low-side current detection circuit 22 as an IcurH current when the current detection signal DCURL that is the output signal of the current detection circuit 6 changes from L to H.

  As a method of detecting the start of transition from the on period of the high side driver to the off period of the high side driver, for example, a falling edge of the PWM input signal or a signal corresponding to the PWM signal, a gate drive signal as shown in FIGS. The falling edge timing of INH0 that is the output signal of the generation circuit 91 is detected by using the falling edge detection circuit 10.

  As shown in FIG. 7, the enable signal generating circuit 7 sets the enable signal EN to L as shown in FIG. 7 from the time when the falling edge is detected by the falling edge detection circuit 10 until the return current is detected by the current detection circuit 6. Thus, the voltage measurement circuit 5 can be stopped during the falling period of the high side driver.

In order to reduce EMI when the solenoid is driven, it is effective to give a slope or slope to the drive voltage waveform OUT of the high side driver. However, as shown in FIG. 7, the power loss PdH of the high-side driver MOS 11 increases locally and transiently during the falling period of the high-side driver, and local and transient heat generation in the high-side driver MOS 11. Will occur. For this reason,
IcurH = IsH / RcH = IoutH / ((NH + 1) × RcH)
If the solenoid drive current IoutH of the high-side driver is detected on the assumption of the proportional relationship, the difference in characteristics with respect to heat generation between the high-side driver MOS 11 and the detection MOS 121 during the falling period of the drive voltage waveform OUT of the high-side driver Therefore, in the following relationship between the current ImH of the high-side driver MOS 11 and the current IsH of the detection MOS 121 assumed when the current is detected:
ImH = NH × IsH
An error occurs in the proportional coefficient NH. As the proportionality coefficient NH is larger, a larger current detection error occurs.

By stopping the voltage measurement circuit 5 by the enable signal EN during the falling period of the high side driver, local and transient due to the power loss PdH of the high side driver MOS 11 during the falling period of the driving voltage waveform OUT of the high side driver. The detection error of the high side driver drive current due to the heat generation can be eliminated, and the current detection accuracy can be improved.
As described above, it is possible to provide a load drive current detection device capable of achieving both EMI reduction of the high side driver and high accuracy of the current detection function.

As described above, as an example applied to a linear solenoid driver, the electromagnetic load 4 includes a linear solenoid or inductor 41 connected between the OUT output and the ground GND as shown in FIG. 2A or 2B. However, as shown in FIG. 2C, a non-insulated DC-DC converter configuration in which an inductor 41 and a capacitor 42 are connected to the OUT output may be used. Here, the load 43 is supplied by a DC-DC converter. For example, a hard disk drive HDD, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), an expansion card (PCI CARD).
), Memory (DDR memory, DRAM (Dynamic RAM), flash memory, etc.), CPU
(Central Processing Unit).

  In the configuration of FIGS. 5 and 6, the pre-driver circuit 9 and the falling edge detection circuit 10 shown in FIGS. 5 and 6 are used to start the stop period of the voltage measurement circuit 5 using the enable signal EN. However, the configuration of the load drive current detection device 100 shown in FIG. 1, FIG. 3, or FIG. 4 may be used.

  FIG. 1 shows an overall configuration of a load drive current detection device according to another embodiment of the present invention.

  A load drive current detection device 100 shown in FIG. 1 is electrically connected in parallel with a high-side driver MOS 11 and a high-side driver MOS 11 that cause a drive current Iout to flow through an electromagnetic load 4 such as a solenoid or inductor connected to the ground GND. A high-side current detection circuit 12, a low-side driver MOS 21 that causes the drive current Iout to flow through the electromagnetic load 4 and that is electrically connected in series to the high-side driver MOS 11, and an electrical parallel connection to the low-side driver MOS 21 The low-side current detection circuit 22, the resistor 3 that converts the output current IcurH of the high-side current detection circuit 12 into a voltage value, the voltage measurement circuit 5 for the voltage value converted by the resistor 3, and the output current of the low-side current detection circuit 22 Based on IcurL, the drive of MOS21 for low side driver Based on the current detection circuit 6 that detects the current IoutL and the current detection signal DCURL of the current detection circuit 6, the return current of the low-side driver MOS 21 is detected. During the period until the start of the return current, the enable signal generation circuit 7 Using the enable signal EN which is an output signal, the detection of the drive current IoutH of the high-side driver MOS 11 based on the output current IcurH of the high-side current detection circuit 12 by the voltage measurement circuit 5 is stopped.

  FIG. 3 shows the overall configuration of a load drive current detection device according to another embodiment of the present invention.

Load drive current detection device 100 shown in FIG. 3, in response to the enable signal EN, rather than stopping the voltage measurement circuit 5 for although the voltage measuring circuit 5 is operated at all times the current detection result, the enable signal Corresponding to EN, there is provided a current value correction means 8 for correcting in advance the detection error of the high side driver drive current due to local and transient heat generation due to the power loss PdH of the high side driver MOS 11. And

  FIG. 4 shows the overall configuration of a load drive current detection device according to another embodiment of the present invention.

  4 converts the sum current Icur, which is the sum of the output current IcurH of the high-side current detection circuit 12 and the output current IcurL2 of the low-side current detection circuit 22, into a voltage by the resistor 3. Features.

As a result, not only the driving current of the high side driver but also the driving current of the low side driver can be detected using the voltage measurement circuit 5 .

  In the second embodiment of the present invention, the dead time period when the high side driver transitions from the on period of the high side driver to the off period of the high side driver, in addition to the compatibility of the high side driver EMI reduction and the high accuracy of the current detection function. The configuration and operation of a load drive current detection device capable of optimally controlling THL will be described.

  FIG. 11 shows one form of the second embodiment of the present invention, and the difference from FIG. 5 which is one form of Example 1 will be described below. The operation will be described with reference to the timing chart in FIG.

  As shown in the timing chart of FIG. 12, the load current detection device 100 shown in FIG. 11 can detect the generation of the return current due to the high-side driver being turned off by changing the current detection signal DCURL of the current detection circuit 6 from L → H. Then, by controlling the pre-driver circuit 9 so as to turn on the gate drive signal LGATE of the low-side driver 2, the dead time period THL can be shortened and optimally controlled.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  In addition, control lines and signal lines are those that are considered necessary for the explanation, and not all control lines and signal lines are necessarily shown in the product.

DESCRIPTION OF SYMBOLS 1 High side driver 2 Low side driver 3 Resistance 4 Electromagnetic load 5 Voltage measurement circuit 6 Current detection circuit 7 Enable signal generation circuit 8 Current value correction means 9 Pre-driver circuit 10 Falling edge detection circuit 100 Load drive current detection device HGATE, LGATE gate Drive signal PWM PWM signal DCURL Current detection signal EN Enable signal DET Falling edge detection signal CLK Clock signal VB Power supply GND Ground

Claims (10)

A high-side driver MOS for flowing a drive current to an electromagnetic load connected to ground, a high-side current detection circuit electrically connected in parallel to the high-side driver MOS, a drive current to flow to the electromagnetic load, and the A low-side driver MOS electrically connected in series with the high-side driver MOS, a low-side current detection circuit electrically connected in parallel with the low-side driver MOS, and an output current of the high-side current detection circuit as a voltage A resistor for converting to a value, a voltage measuring circuit for a voltage value converted by the resistor, a current detecting circuit for detecting a driving current of the low-side driver MOS based on an output current of the low-side current detecting circuit,
With
Based on the current detection signal of the current detection circuit, the return current of the low-side driver MOS is detected, and the period from the falling edge of the gate drive signal of the high-side driver MOS to the start of the return current is enabled A load that uses an enable signal that is an output signal of a signal generation circuit to stop detection of the drive current of the high-side driver MOS based on the output current of the high-side current detection circuit by the voltage measurement circuit; Drive current detection device. A high-side driver MOS for flowing a drive current to an electromagnetic load connected to ground, a high-side current detection circuit electrically connected in parallel to the high-side driver MOS, a drive current to flow to the electromagnetic load, and the A low-side driver MOS electrically connected in series with the high-side driver MOS, a low-side current detection circuit electrically connected in parallel with the low-side driver MOS, and an output current of the high-side current detection circuit as a voltage A resistor for converting to a value, a voltage measuring circuit for a voltage value converted by the resistor, a current detecting circuit for detecting a driving current of the low-side driver MOS based on an output current of the low-side current detecting circuit,
With
Based on the current detection signal of the current detection circuit, the return current of the low-side driver MOS is detected, and the period from the falling edge of the gate drive signal of the high-side driver MOS to the start of the return current is: A load drive current detection device further comprising current value correction means for correcting a current detection result which is an output signal of the voltage measurement circuit in accordance with an enable signal which is an output signal of the enable signal generation circuit. The load drive current detection device according to claim 1, wherein the high side driver MOS gate drive signal and the low side driver MOS are not turned on at the same time, according to a PWM signal, the high side driver MOS gate drive signal, A pre-driver circuit for generating a gate drive signal for the low-side driver MOS ;
The current detection signal is used for dead time generation in which both the gate drive signal of the low-side driver MOS generated by the pre-driver circuit and the gate drive signal of the high-side driver MOS are turned off. A load driving current detecting device. The load drive current detection device according to claim 2, wherein the high side driver MOS gate drive signal and the low side driver MOS are not turned on at the same time according to a PWM signal, A pre-driver circuit for generating a gate drive signal for the low-side driver MOS ;
The current detection signal is used for dead time generation in which both the gate drive signal of the low-side driver MOS generated by the pre-driver circuit and the gate drive signal of the high-side driver MOS are turned off. A load driving current detecting device.   4. The load drive current detection device according to claim 3, comprising: the pre-driver circuit; and a falling edge detection circuit of the PWM signal or a signal corresponding to the PWM signal, the PWM signal or a signal corresponding to the PWM signal. The falling edge timing of the low-side driver MOS is detected based on the current detection signal of the current detection circuit, and the PWM signal or the falling edge timing of the signal corresponding to the PWM signal is detected. During the period until the start of the return current, the enable signal that is the output signal of the enable signal generation circuit is used, and the high-side driver MOS is driven based on the output current of the high-side current detection circuit by the voltage measurement circuit A load driving current detecting device characterized in that detection of current is stopped.   5. The load drive current detection device according to claim 4, comprising the pre-driver circuit and a falling edge detection circuit for the PWM signal or a signal corresponding to the PWM signal, and the PWM signal or a signal corresponding to the PWM signal. The falling edge timing of the low-side driver MOS is detected based on the current detection signal of the current detection circuit, and the PWM signal or the falling edge timing of the signal corresponding to the PWM signal is detected. In a period until the start of the return current, an enable signal that is an output signal of an enable signal generation circuit is used, and the current value correction means is applied to the current detection result of the high-side current detection circuit by the voltage measurement circuit. Is applied to the load drive current detection device.   2. The load drive current detection device according to claim 1, wherein a sum current that is a sum of the output current of the high-side current detection circuit and the output current of the low-side current detection circuit is converted into a voltage by the resistor. A load drive current detection device. The load drive current detection device according to claim 1,
The high-side current detection circuit has a common source terminal and gate terminal with the high-side driver MOS, and the drain terminal is equipotential with a negative feedback circuit using the drain terminal of the high-side driver MOS and an operational amplifier. A high-side current detection MOS that is connected, and a current copy circuit that outputs a current proportional to the input to the ground using the drain current of the high-side current detection MOS as an input;
The low-side current detection circuit has a drain terminal and a gate terminal in common with the low-side driver MOS, and the source terminal is connected to the source terminal of the low-side driver MOS and a negative feedback circuit using an operational amplifier so as to be equipotential. A load drive current detection device comprising: a detection MOS; and a current copy circuit that receives a source current of the low-side current detection MOS and outputs a current proportional to the input to ground.   2. The load drive current detection device according to claim 1, wherein at least the high-side driver MOS and the high-side current detection circuit are formed on the same silicon substrate.   The load drive current detection device according to claim 1, wherein the electromagnetic load is connected from an inductor to a ground via a capacitor and a load.

Images