JP6292281B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having local wiring.

  There is a method in which local wiring (local interconnect) formed by a conductive layer below the first metal wiring layer is used as wiring for connecting between impurity diffusion regions formed on a semiconductor substrate and lead-out wiring from the impurity diffusion region. is there. As a method for forming local wiring, a method is known in which a groove reaching an impurity diffusion region is formed in an interlayer insulating film covering the gate electrode, and a wiring material is buried in this groove.

Japanese Patent Laid-Open No. 08-330314 Japanese Patent Laid-Open No. 11-345887 JP 2000-114481 A

  However, in the above-described local wiring formation method, a photolithography technique is used when a groove is formed in the interlayer insulating film. In the photolithography technique, alignment is performed using an alignment mark of a base pattern (active layer or gate layer), and thus a positional shift may occur with respect to the gate electrode. Further, when forming a contact connected to the gate electrode, it is required to consider a positional deviation between the gate electrode and the local wiring. For this reason, it is necessary to set a wide range of allowable contact misalignment, which has been a hindrance to integration.

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing a decrease in electrical characteristics and yield due to misalignment.

According to one aspect of the embodiment, a first wiring extending in a plane parallel to the surface of the semiconductor substrate, a first wiring extending in the plane, and adjacent to the first wiring on the semiconductor substrate. Forming a second wiring disposed on the first wiring, forming a first sidewall insulating film on the sidewall of the first wiring, and forming a second sidewall insulating film on the sidewall of the second wiring; Forming a conductive film on the semiconductor substrate on which the first wiring, the first sidewall insulating film, the second wiring, and the second sidewall insulating film are formed; and The conductive film on the wiring and the second wiring is selectively removed, and the first wiring extends in the plane in a region between the first wiring and the second wiring. And a portion extending in parallel with the second wiring, and the first wiring and the second sidewall insulating film are formed by the first sidewall insulating film and the second sidewall insulating film. Forming a third wiring made of the conductive film and separated from the second wiring and having a height lower than the height of the first wiring and the height of the second wiring. A manufacturing method is provided.

According to another aspect of the embodiment, on the semiconductor substrate, the first wiring extending in a plane parallel to the surface of the semiconductor substrate, and the first wiring extending in the plane Forming a second wiring disposed adjacent to the first wiring, and forming a first side wall insulating film on the side wall of the first wiring, and forming a second side wall insulating film on the side wall of the second wiring Forming a sacrificial film on the semiconductor substrate on which the first wiring, the first sidewall insulating film, the second wiring, and the second sidewall insulating film are formed, A step of forming an opening in a wiring formation region of the sacrificial film between the first wiring and the second wiring; and on the semiconductor substrate on which the sacrificial film having the opening is formed. Forming a conductive film; selectively removing the conductive film on the sacrificial film leaving the conductive film in the opening; A portion extending in parallel to the first wiring and the second wiring, and the first sidewall insulating film and the second sidewall insulating film provide the first wiring. Forming a third wiring made of the conductive film and having a height lower than the height of the first wiring and the height of the second wiring and separated from the wiring and the second wiring. A method for manufacturing a semiconductor device is provided.

  According to the disclosed method for manufacturing a semiconductor device, the third wiring can be formed without being displaced with respect to the first wiring and the second wiring. As a result, it is possible to eliminate a decrease in electrical characteristics and yield due to the positional deviation. In addition, it is possible to relax the allowable range of displacement of the contact hole connected to the first to third wirings, and it is possible to relax the design rule.

FIG. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the first embodiment. 3A and 3B are a plan view and a cross-sectional view (No. 1) showing the method for manufacturing the semiconductor device according to the first embodiment. 4A and 4B are a plan view and a cross-sectional view (No. 2) showing the method for manufacturing the semiconductor device according to the first embodiment. 5A and 5B are a plan view and a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B are a plan view and a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 7A and 7B are a plan view and a cross-sectional view (part 5) showing the method for manufacturing the semiconductor device according to the first embodiment. 8A and 8B are a plan view and a cross-sectional view (No. 6) showing the method for manufacturing the semiconductor device according to the first embodiment. 9A and 9B are a plan view and a cross-sectional view (No. 7) showing the method for manufacturing the semiconductor device according to the first embodiment. 10A and 10B are a plan view and a cross-sectional view (No. 8) showing the method for manufacturing the semiconductor device according to the first embodiment. 11A and 11B are a plan view and a cross-sectional view (No. 9) showing the method for manufacturing the semiconductor device according to the first embodiment. 12A and 12B are a plan view and a cross-sectional view (No. 10) showing the method for manufacturing the semiconductor device according to the first embodiment. 13A and 13B are a plan view and a cross-sectional view (No. 11) showing the method for manufacturing the semiconductor device according to the first embodiment. 14A and 14B are a plan view and a cross-sectional view (No. 12) showing the method for manufacturing the semiconductor device according to the first embodiment. 15A and 15B are a plan view and a cross-sectional view (No. 13) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 16 is a plan view and a cross-sectional view (No. 14) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 17 is a plan view and a cross-sectional view (No. 15) showing the method for manufacturing the semiconductor device according to the first embodiment. 18A and 18B are a plan view and a cross-sectional view (No. 1) showing the method for manufacturing the semiconductor device according to the second embodiment. 19A and 19B are a plan view and a cross-sectional view (No. 2) showing the method for manufacturing a semiconductor device according to the second embodiment. 20A and 20B are a plan view and a cross-sectional view (part 3) showing the method for manufacturing the semiconductor device according to the second embodiment. 21A and 21B are a plan view and a cross-sectional view (No. 4) showing the method for manufacturing a semiconductor device according to the second embodiment. 22A and 22B are a plan view and a cross-sectional view (No. 5) showing the method for manufacturing a semiconductor device according to the second embodiment. 23A and 23B are a plan view and a cross-sectional view (No. 6) showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 24 is a plan view and a cross-sectional view (No. 7) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 25 is a plan view (part 1) illustrating the structure of a semiconductor device according to a modified embodiment. FIG. 26 is a plan view (part 2) illustrating the structure of a semiconductor device according to a modified embodiment. FIG. 27 is a plan view (part 3) illustrating the structure of a semiconductor device according to a modified embodiment.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

  FIG. 1 is a plan view showing the structure of the semiconductor device according to the present embodiment. FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 3 to 17 are a plan view and a cross-sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS. 2A is a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG.

  An element isolation insulating film 14 that defines active regions 12n and 12p is formed on the silicon substrate 10. A plurality of gate electrodes 20 arranged in parallel are provided on the silicon substrate 10 on which the element isolation insulating film 14 is formed. In the drawing, the central gate electrode 20 is formed so as to extend on the active region 12 n and the active region 12 p through the gate insulating film 18. A P-type source / drain region 24 and an N-type source / drain region (not shown) are formed in the active region 12 n and the active region 12 p on both sides of the gate electrode 20. Thus, an N-type transistor 50 having a gate electrode 20 and source / drain regions is formed in the active region 12p. A P-type transistor 52 having a gate electrode 20 and source / drain regions 24 is formed in the active region 12n. A metal silicide film 26 is formed on the gate electrode 20 and the source / drain regions 24 and the like.

  In the region between the gate electrodes 20, local wirings 38a, 38b, and 38c are formed in alignment with the gate electrode 20. The local wiring 38 a is connected to the source region of the N-type transistor through the metal silicide film 26. The local wiring 38 b connects the drain region of the N-type transistor and the source region of the P-type transistor through the metal silicide film 26. The local wiring 38 c is connected to the drain region of the N-type transistor through the metal silicide film 26. The local wiring is generally a wiring formed in a layer lower than the first metal wiring layer, and corresponds to a wiring connecting between the impurity diffusion regions, a lead wiring from the impurity diffusion region, or the like. . In this specification, “local wiring” may be simply referred to as “wiring”.

  An interlayer insulating film 40 is formed on the silicon substrate 10 on which the N-type transistor 50, the P-type transistor 52, and the local wirings 38a, 38b, and 38c are formed. In the interlayer insulating film 40, contact plugs 44a, 44b, 44c connected to the local wirings 38a, 38b, 38c, respectively, and a contact plug 44d connected to the gate electrode 20 of the N-type transistor 50 and the P-type transistor 52 are provided. Embedded.

  The contact plug 44a is connected to a reference voltage line (not shown). The contact plug 44c is connected to a power supply voltage line (not shown). An input signal line (not shown) is connected to the contact plug 44d. Further, an output signal line (not shown) is connected to the contact plug 44b.

  As described above, the semiconductor device according to the present embodiment is an inverter circuit in which the N-type transistor 50 is a driver transistor and the P-type transistor 52 is a load transistor.

  In the semiconductor device according to the present embodiment, the local wirings 38 a, 38 b, 38 c formed between the gate electrodes 20 are formed in alignment with the gate electrode 20 as described above. Being formed in alignment with the gate electrode 20 means that it is formed at a constant interval from the gate electrode 20 and no misalignment with respect to the gate electrode 20 occurs. By using the manufacturing method described later, the local wirings 38a, 38b, and 38c can be formed in a self-aligned manner with respect to the gate electrode 20 without being positioned with respect to the gate electrode 20 by lithography.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. In each figure, (a) is a plan view showing a portion of a region 60 in FIG. 1, (b) is a cross-sectional view taken along the line AA 'in (a), and (c) is a cross-sectional view along B- in (a). It is B 'sectional view.

  First, the element isolation insulating film 14 that defines the active regions 12n and p is formed on the silicon substrate 10 by, eg, STI (Shallow Trench Isolation).

  Next, a P well (not shown) is formed in each active region 12n by ion implantation, and an N well 16 is formed in the active region 12p (FIGS. 3A, 3B, and 3C). When forming the P well and N well 16, predetermined channel ion implantation is also performed.

  Next, a gate insulating film 18 of, eg, a silicon oxide film is formed on the active regions 12n, 12p by, eg, thermal oxidation.

  Next, a polysilicon film is deposited on the entire surface by, eg, CVD.

  Next, the polysilicon film is patterned by photolithography and dry etching to form the gate electrode 20 (FIGS. 4A, 4B, and 4C). For example, in a 22 nm generation semiconductor device, the gate electrodes 20 having a gate length of 22 nm are arranged in a stripe shape with a pitch of 90 nm, for example.

  In the semiconductor device of the present embodiment, the gate electrode 20 actually used is only the central gate electrode 20 of the three gate electrodes 20 shown in the figure. The gate electrodes 20 on both sides are so-called dummy electrodes. By arranging the gate electrodes 20 at a fixed pitch, the dimensions of the gate electrodes 20 can be made uniform. Such a layout has been standardized in semiconductor devices of the 28 nm generation and later.

  Next, ion implantation is performed on the active region 12n using the gate electrode 20 as a mask to form an impurity diffusion region serving as an extension region.

  Next, after depositing a silicon nitride film by, for example, the CVD method, the silicon nitride film is etched back, and a sidewall insulating film (first insulating portion / third insulating portion) 22 is formed on the sidewall portion of the gate electrode 20.

  Next, ion implantation is performed on the active region 12n using the gate electrode 20 and the sidewall insulating film 22 as a mask to form an impurity diffusion region to be a source / drain region.

  Next, the implanted impurities are activated to form source / drain regions 24 in the active regions 12n on both sides of the gate electrode 20 (FIGS. 5A, 5B, and 5C).

  Thus, the N-type transistor 50 is formed in the active region 12p, and the P-type transistor 52 is formed in the active region 12n.

  Next, a metal silicide film 26 is selectively formed on the gate electrode 20 and the source / drain regions 24 by a salicide process (FIGS. 6A, 6B, and 6C).

  Next, a silicon oxide film 28 is formed on the entire surface by, eg, CVD (FIGS. 7A, 7B, and 7C). For example, in a 22 nm generation semiconductor device, a silicon oxide film 28 having a film thickness of, for example, about 15 nm is formed. Instead of the silicon oxide film 28, another film of a material that can be selectively etched with respect to the sidewall insulating film 22, the metal silicide film 26, and the local wirings 38a, 38b, and 38c to be formed later is formed. Good.

  Next, the silicon oxide film 28 is etched back, and a sidewall insulating film (second insulating portion / fourth insulating portion) 30 of the silicon oxide film 28 is formed on the sidewall portion of the gate electrode 20 on which the sidewall insulating film 22 is formed. It forms (FIG. 8 (a), (b), (c)).

  Next, after depositing a tungsten film by, for example, the CVD method, the surface of the tungsten film is polished by, for example, the CMP method to form a tungsten film 32 having a planarized surface (FIGS. 9A, 9B, 9C). )). For example, in a 22 nm generation semiconductor device, a tungsten film 32 having a thickness of, for example, about 35 nm is formed.

  The tungsten film 32 is a film for forming the local wirings 38a, 38b, and 38c. The material for forming the local wirings 38a, 38b, and 38c is not limited to tungsten, and another conductive film may be formed instead of the tungsten film 32.

  Next, the tungsten film 32 is etched back, and the tungsten film 32 is selectively left in the region between the gate electrodes 20 (FIGS. 10A, 10B, and 10C). For example, in a 22 nm generation semiconductor device, the tungsten film 32 is etched back until the film thickness reaches, for example, about 15 nm.

  Next, after depositing a silicon oxide film by, for example, the CVD method, the surface of the silicon oxide film is polished by, for example, the CMP method to form a silicon oxide film 34 having a planarized surface (FIGS. 11A and 11B). (C)). For example, in a 22 nm generation semiconductor device, for example, a silicon oxide film 34 having a thickness of about 20 nm is formed. Instead of the silicon oxide film 34, another film that can be selectively etched with respect to the sidewall insulating film 22, the metal silicide film 26, and the local wirings 38a, 38b, and 38c to be formed later may be formed. Good. The silicon oxide film 34 is a sacrificial film that is selectively etched with respect to these films in a later step. Further, although the silicon oxide film 34 is not necessarily flattened, the flattening is advantageous in performing high-definition photolithography in a later process.

  Next, a photoresist film 36 is formed on the silicon oxide film 34 by photolithography to cover the regions where the local wirings 38a, 38b, and 38c are to be formed (FIGS. 12A, 12B, and 12C). Sides of the photoresist film 36 (longitudinal sides in the drawing) along the extending direction of the gate electrode 20 are arranged on the gate electrode 20 in consideration of misalignment.

  Next, the silicon oxide film 34 is etched using the photoresist film 36 as a mask, and the pattern of the photoresist film 36 is transferred to the silicon oxide film 34.

  Next, the photoresist film 36 is removed by, for example, ashing (FIGS. 13A, 13B, and 13C).

  Next, the tungsten film 32 is etched using the silicon oxide film 36 as a mask to form local wirings 38a, 38b, and 38c of the tungsten film 32 (FIGS. 14A, 14B, and 14C).

  The local wirings 38a, 38b, and 38c formed in this way are not positioned by lithography with respect to the gate electrode 20, but are automatically positioned by a processing process. For this reason, misalignment does not occur between the local wirings 38 a, 38 b, 38 c and the gate electrode 20. As described above, in the semiconductor device manufacturing method according to the present embodiment, the local wirings 38 a, 38 b, 38 c can be formed in a self-aligned manner with respect to the gate electrode 20.

  The wiring width of the local wirings 38a, 38b, and 38c is defined by the distance between the gate electrodes 20, the thickness of the side wall insulating films 22 and 30, the etching conditions when forming the side wall insulating films 22 and 30, and the like. Therefore, local wirings 38a, 38b, and 38c having an arbitrary wiring width can be formed by appropriately setting these values. Among these, in particular, the sidewall insulating film 30 does not affect the impurity profile and the like of the source / drain region 24, so that the degree of freedom of setting is large.

  In addition, the wiring thickness of the local wirings 38a, 38b, and 38c can be appropriately set according to the etch back amount of the tungsten film 32. As a result, the resistance values of the local wirings 38a, 38b, and 38c and the inter-wiring capacitance can be adjusted as necessary.

  Next, the sidewall insulating film 30 and the silicon oxide film 34 are removed as necessary by, for example, wet etching using a hydrofluoric acid aqueous solution (FIGS. 15A, 15B, and 15C).

  Note that the sidewall insulating film 30 and the silicon oxide film 34 are not necessarily removed. However, when the interlayer insulating film 40 to be formed later is formed of a material different from the sidewall insulating film 30 and the silicon oxide film 34, such as a low dielectric constant film, in view of prevention of increase in the dielectric constant and ease of contact etching. It is desirable to remove.

  Next, a silicon oxide film is deposited on the entire surface by, eg, CVD, and an interlayer insulating film 40 of silicon oxide film is formed (FIGS. 16A, 16B, and 16C).

  Next, contact holes 42 reaching the interlayer insulating film 40, the metal silicide film 36 on the gate electrode 20, the metal silicide film 36 on the source / drain region 24, and the local wirings 38 a, 38 b, and 38 c by photolithography and dry etching. (FIGS. 17A, 17B, and 17C).

  At this time, since the local wirings 38a, 38b, and 38c are formed in alignment with the gate electrode 20, in forming the contact hole 42, only positional deviation with respect to the gate electrode 20 needs to be considered. It is not necessary to consider the positional deviation with respect to the local wirings 38a, 38b, and 38c.

  Next, after a conductive film is deposited on the entire surface, the conductive film is etched back to form contact plugs 44G and 44L embedded in the contact hole 42 (FIGS. (A), (b), and (c)).

  Thereafter, predetermined wiring layers connected to the contact plugs 44G, 44L, etc. are formed, and the semiconductor device according to the present embodiment is completed.

  Thus, according to the present embodiment, local wiring can be formed without being displaced with respect to the gate electrode. As a result, it is possible to eliminate a decrease in electrical characteristics and yield due to the positional deviation. In addition, it is possible to relax the allowable range of displacement of the contact hole connected to the gate electrode and the local wiring, and it is possible to relax the design rule.

[Second Embodiment]
A method for fabricating a semiconductor device according to the second embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 17 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  18 to 24 are a plan view and a cross-sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.

  In the present embodiment, another method for manufacturing the semiconductor device according to the first embodiment shown in FIGS. 1 to 3 will be described. The method of the first embodiment is a manufacturing method using a remaining pattern, whereas the method of the present embodiment is a manufacturing method using a blank pattern. A lithography-friendly process can be selected as appropriate.

  First, for example, the N-type transistor 50, the P-type transistor 52, the metal silicide film 26, and the sidewall insulating film 30 are formed on the silicon substrate 10 in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. Etc.

  Next, after depositing an amorphous carbon film by, for example, a plasma CVD method, the surface of the amorphous carbon film is polished by, for example, a CMP method to form an amorphous carbon film 70 having a planarized surface (FIGS. 18A and 18B). ), (C)). For example, in a 22 nm generation semiconductor device, an amorphous carbon film 70 having a thickness of, for example, about 35 nm is formed.

The amorphous carbon film 70 is formed by carbonization of CH ₄ , C ₂ H ₆ , C ₃ H ₈ , C ₄ H ₁₀ , C ₂ H ₂ , C ₃ H ₆ , C ₃ H ₄ or the like as a source gas by, for example, plasma CVD. Hydrogen gas can be deposited at a temperature of 350 ° C. to 400 ° C. using an inert gas such as He or Ar as a carrier gas. Further, as the polishing conditions for the amorphous carbon film 70, conditions similar to the conditions used as the polishing conditions for the silicon oxide film can be applied.

  Instead of the amorphous carbon film 70, the sidewall insulating films 22 and 30, the metal silicide film 26, and other films that can be selectively etched with respect to the local wirings 38a, 38b, and 38c to be formed later are formed. May be. The amorphous carbon film 70 is a sacrificial film that is selectively etched with respect to these films in a later step. Further, the amorphous carbon film 70 does not necessarily need to be flattened, but the flattening is advantageous in performing high-definition photolithography in a subsequent process.

  Next, a photoresist film 36 is formed on the amorphous carbon film 70 to expose the regions where the local wirings 38a, 38b, and 38c are to be formed by photolithography (FIGS. 19A, 19B, and 19C). Sides of the photoresist film 36 (longitudinal sides in the drawing) along the extending direction of the gate electrode 20 are arranged on the gate electrode 20 in consideration of misalignment.

Next, the amorphous carbon film 70 is etched using the photoresist film 36 as a mask to remove the amorphous carbon film 70 in the regions where the local wirings 38a, 38b, and 38c are to be formed. The amorphous carbon film 70 can be etched by reactive ion etching using, for example, O ₂ and HBr.

  Next, the photoresist film 36 is removed by, for example, ashing (FIGS. 20A, 20B, and 20C).

  Next, after depositing a tungsten film by, for example, the CVD method, the surface of the tungsten film is polished by, for example, the CMP method to form the tungsten film 32 embedded in the amorphous carbon film 70 (FIGS. 21A and 21B). (C)). For example, in a 22 nm generation semiconductor device, a tungsten film 32 having a thickness of, for example, about 35 nm is formed.

  Next, the tungsten film 32 is etched back, and the tungsten film 32 is selectively left in the region between the gate electrodes 20. For example, in a 22 nm generation semiconductor device, the tungsten film 32 is etched back until the film thickness reaches, for example, about 15 nm. Thereby, the local wirings 38a, 38b, and 38c of the tungsten film 32 are formed (FIGS. 22A, 22B, and 22C).

  The local wirings 38a, 38b, and 38c formed in this way are not positioned by lithography with respect to the gate electrode 20, but are automatically positioned by a processing process. For this reason, misalignment does not occur between the local wirings 38 a, 38 b, 38 c and the gate electrode 20. As described above, in the semiconductor device manufacturing method according to the present embodiment, the local wirings 38 a, 38 b, 38 c can be formed in a self-aligned manner with respect to the gate electrode 20.

  The wiring width of the local wirings 38a, 38b, and 38c is defined by the distance between the gate electrodes 20, the thickness of the side wall insulating films 22 and 30, the etching conditions when forming the side wall insulating films 22 and 30, and the like. Therefore, local wirings 38a, 38b, and 38c having an arbitrary wiring width can be formed by appropriately setting these values. Among these, in particular, the sidewall insulating film 30 does not affect the impurity profile and the like of the source / drain region 24, so that the degree of freedom of setting is large.

  In addition, the wiring thickness of the local wirings 38a, 38b, and 38c can be appropriately set according to the etch back amount of the tungsten film 32. As a result, the resistance values of the local wirings 38a, 38b, and 38c and the inter-wiring capacitance can be adjusted as necessary.

Next, the amorphous carbon film 70 is removed by reactive ion etching using, for example, O ₂ and HBr (FIGS. 23A, 23B, and 23C).

  Thereafter, the semiconductor device is completed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 16 to 17, for example.

  Thus, according to the present embodiment, local wiring can be formed without being displaced with respect to the gate electrode. As a result, it is possible to eliminate a decrease in electrical characteristics and yield due to the positional deviation. In addition, it is possible to relax the allowable range of displacement of the contact hole connected to the gate electrode and the local wiring, and it is possible to relax the design rule.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, although the example applied to the inverter circuit has been described in the above embodiment, the present invention is not limited to the inverter circuit, and can be applied to various semiconductor devices having local wiring in a region between gate electrodes. For example, the present invention can be applied to a semiconductor device having a planar layout as shown in FIGS.

  FIG. 25 is a plan view showing an example of the layout of the buffer circuit. FIG. 26 is a plan view showing an example of the layout of the 2-input NAND circuit. FIG. 27 is a plan view showing an example of the layout of the exclusive OR circuit. In any layout, the local wiring 38 is formed in the region between the gate electrodes 20, and the local wiring 38 can be formed in alignment with the gate electrode 20 in the same manner as in the above embodiment.

  In addition to these, the present invention can be applied to various circuit layouts such as a 2-input NOR circuit, an adder circuit, and a flip-flop circuit.

  In the above embodiment, the case where the gate electrodes 20 are arranged at a constant pitch in order to improve the dimensional uniformity of the gate electrodes 20 has been described. However, the interval between the gate electrodes 20 is not necessarily constant. Absent.

  Moreover, although the case where the local wiring 38 is formed in the region between the gate electrodes 20 has been described in the above embodiment, the present invention may be applied to the case where the local wiring is formed in a region between other wirings other than the gate electrode.

  In the above embodiment, the sidewall insulating films 22 and 30 having the two-layer structure are formed on the sidewall portions of the gate electrode 20, but the sidewall insulating film having the two-layer structure is not necessarily formed. If the dielectric strength between the gate electrode 20 and the local wiring 38 can be sufficiently secured only by the sidewall insulating film 22, the sidewall insulating film 30 may not be formed. Further, a sidewall insulating film having a three-layer structure or more may be formed.

  In addition, the structure, constituent materials, manufacturing conditions, and the like of the semiconductor device described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art.

  Regarding the above embodiment, the following additional notes are disclosed.

(Supplementary Note 1) Forming a first wiring and a second wiring disposed adjacent to the first wiring on a semiconductor substrate;
Forming a first sidewall insulating film on the sidewall of the first wiring and a second sidewall insulating film on the sidewall of the second wiring;
Forming a conductive film on the semiconductor substrate on which the first wiring, the first sidewall insulating film, the second wiring, and the second sidewall insulating film are formed;
The conductive film on the first wiring and the second wiring is selectively removed, and the conductive film is formed in the region between the first wiring and the second wiring by the conductive film. Forming a first wiring and a third wiring separated from the second wiring by the first side wall insulating film and the second side wall insulating film. .

(Additional remark 2) In the manufacturing method of the semiconductor device of Additional remark 1,
The step of selectively removing the conductive film on the first wiring and the second wiring includes a step of planarizing the conductive film and a step of etching back the planarized conductive film. A method for manufacturing a semiconductor device.

(Additional remark 3) In the manufacturing method of the semiconductor device of Additional remark 1,
After the step of forming the third wiring, the method further includes a step of patterning the third wiring so that the third wiring remains between the first wiring and the second wiring. A method of manufacturing a semiconductor device.

(Additional remark 4) In the manufacturing method of the semiconductor device of Additional remark 3,
After the step of forming the third wiring and before the step of patterning the third wiring, a step of forming a sacrificial film on the third wiring and a step of flattening the surface of the sacrificial film And
In the step of patterning the third wiring, the third wiring is etched using the sacrificial film as a mask.

(Supplementary Note 5) Forming a first wiring and a second wiring disposed adjacent to the first wiring on a semiconductor substrate;
Forming a first sidewall insulating film on the sidewall of the first wiring and a second sidewall insulating film on the sidewall of the second wiring;
Forming a sacrificial film on the semiconductor substrate on which the first wiring, the first sidewall insulating film, the second wiring, and the second sidewall insulating film are formed;
Forming an opening in a wiring formation region of the sacrificial film between the first wiring and the second wiring;
Forming a conductive film on the semiconductor substrate on which the sacrificial film is formed;
The conductive film on the sacrificial film is selectively removed, the conductive film is formed in the opening by the conductive film, and the first wiring and the second sidewall insulating film are formed by the first sidewall insulating film and the second sidewall insulating film. Forming a third wiring separated from the second wiring. A method for manufacturing a semiconductor device, comprising:

(Appendix 6) In the method for manufacturing a semiconductor device according to Appendix 5,
The method of selectively removing the conductive film on the sacrificial film includes a step of planarizing the conductive film and a step of etching back the conductive film.

(Supplementary note 7) In the method for manufacturing a semiconductor device according to supplementary note 6,
In the step of etching back the conductive film, the conductive film is etched back so that the film thickness of the conductive film becomes the film thickness of the third wiring to be formed. Production method.

(Appendix 8) In the method for manufacturing a semiconductor device according to any one of appendices 5 to 7,
The step of forming the sacrificial film includes a step of depositing the sacrificial film and a step of planarizing the sacrificial film.

(Appendix 9) In the method for manufacturing a semiconductor device according to any one of appendices 5 to 8,
The method of manufacturing a semiconductor device, wherein the sacrificial film is an amorphous carbon film.

(Appendix 10) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 9,
The first side wall insulating film has a first insulating part formed on the side wall of the first wiring, and a second insulating part formed on the first insulating part,
The second side wall insulating film has a third insulating portion formed on the side wall of the second wiring and a fourth insulating portion formed on the third insulating portion. A method for manufacturing a semiconductor device.

(Additional remark 11) In the manufacturing method of the semiconductor device of Additional remark 10,
After the step of forming the third wiring,
The method of manufacturing a semiconductor device, further comprising a step of removing the second insulating portion of the first sidewall insulating film and the fourth insulating portion of the second sidewall insulating film.

(Appendix 12) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 11,
The method for manufacturing a semiconductor device, wherein the first wiring and the second wiring are arranged in parallel.

(Supplementary note 13) In the method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 12,
The first wiring and the second wiring are gate electrodes;
The method for manufacturing a semiconductor device, wherein the third wiring is a wiring for connecting between active regions formed on the semiconductor substrate or a lead-out wiring from the active region.

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12n, 12p ... Active region 14 ... Element isolation insulating film 16 ... N well 18 ... Gate insulating film 20 ... Gate electrode 22, 30 ... Side wall insulating film 24 ... Source / drain region 26 ... Metal silicide film 28, 34 ... Silicon oxide film 32 ... Tungsten film 36 ... Photoresist films 38a, 38b, 38c ... Local wiring 40 ... Interlayer insulating film 42 ... Contact holes 44a, 44b, 44c, 44d ... Contact plug 50 ... N-type transistor 52 ... P-type transistor 60 ... Area 70 ... Amorphous carbon film

Claims (12)

A first wiring extending on a semiconductor substrate in a plane parallel to the surface of the semiconductor substrate; a second wiring extending in the plane and disposed adjacent to the first wiring; Forming a step;
Forming a first sidewall insulating film on the sidewall of the first wiring and a second sidewall insulating film on the sidewall of the second wiring;
Forming a conductive film on the semiconductor substrate on which the first wiring, the first sidewall insulating film, the second wiring, and the second sidewall insulating film are formed;
The conductive film on the first wiring and the second wiring is selectively removed, and extends in the plane in a region between the first wiring and the second wiring. A portion extending in parallel with the first wiring and the second wiring, and separated from the first wiring and the second wiring by the first side wall insulating film and the second side wall insulating film. Forming a third wiring made of the conductive film and having a height lower than the height of the first wiring and the height of the second wiring. Method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a step of forming an element isolation region for defining a plurality of active regions in the semiconductor substrate is provided before the step of forming the first wiring and the second wiring. The method of manufacturing a semiconductor device, further comprising: the third wiring extending and contacting on at least two active regions separated by the element isolation region. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The step of selectively removing the conductive film on the first wiring and the second wiring includes a step of planarizing the conductive film and a step of etching back the planarized conductive film. A method for manufacturing a semiconductor device. A first wiring extending on a semiconductor substrate in a plane parallel to the surface of the semiconductor substrate; a second wiring extending in the plane and disposed adjacent to the first wiring; Forming a step;
Forming a first sidewall insulating film on the sidewall of the first wiring and a second sidewall insulating film on the sidewall of the second wiring;
Forming a sacrificial film on the semiconductor substrate on which the first wiring, the first sidewall insulating film, the second wiring, and the second sidewall insulating film are formed;
Forming an opening in a wiring formation region of the sacrificial film between the first wiring and the second wiring;
Forming a conductive film on the semiconductor substrate on which the sacrificial film having the opening is formed;
The conductive film on the sacrificial film is selectively removed leaving the conductive film in the opening, and extends in the plane and extends in parallel with the first wiring and the second wiring. A height of the first wiring and the second wiring separated from the first wiring and the second wiring by the first side wall insulating film and the second side wall insulating film. Forming a third wiring made of the conductive film and having a height lower than the height of the wiring. 5. The method of manufacturing a semiconductor device according to claim 4 , wherein a step of forming an element isolation region for defining a plurality of active regions in the semiconductor substrate is provided before the step of forming the first wiring and the second wiring. The method of manufacturing a semiconductor device, further comprising: the third wiring extending and contacting on at least two active regions separated by the element isolation region. In the manufacturing method of the semiconductor device according to claim 4 or 5 ,
The method of selectively removing the conductive film on the sacrificial film includes a step of planarizing the conductive film and a step of etching back the conductive film. The method of manufacturing a semiconductor device according to claim 6 .
In the step of etching back the conductive film, the conductive film is etched back so that the film thickness of the conductive film becomes the film thickness of the third wiring to be formed. Production method. In the manufacturing method of the semiconductor device according to any one of claims 4 to 7 ,
The step of forming the sacrificial film includes a step of depositing the sacrificial film and a step of planarizing the sacrificial film. In the manufacturing method of the semiconductor device of any one of Claims 1 thru / or 4,
The first side wall insulating film has a first insulating part formed on the side wall of the first wiring, and a second insulating part formed on the first insulating part,
The second side wall insulating film has a third insulating portion formed on the side wall of the second wiring, and a fourth insulating portion formed on the third insulating portion,
After the step of forming the third wiring, the method further includes the step of removing the second insulating portion and the fourth insulating portion. In the manufacturing method of the semiconductor device according to any one of claims 4 to 8 ,
The first side wall insulating film has a first insulating part formed on the side wall of the first wiring, and a second insulating part formed on the first insulating part,
The second side wall insulating film has a third insulating portion formed on the side wall of the second wiring, and a fourth insulating portion formed on the third insulating portion,
After the step of forming the third wiring, the method further includes the step of removing the second insulating portion and the fourth insulating portion. In the manufacturing method of the semiconductor device according to claim 9 ,
After removing the second insulating portion and the fourth insulating portion, between the first insulating portion and the third wiring, and between the third insulating portion and the third wiring, A method of manufacturing a semiconductor device, further comprising: embedding an interlayer insulating film having a dielectric constant lower than that of the second insulating portion and the fourth insulating portion. The method of manufacturing a semiconductor device according to claim 10 .
After removing the second insulating portion and the fourth insulating portion, between the first insulating portion and the third wiring, and between the third insulating portion and the third wiring, A method of manufacturing a semiconductor device, further comprising: embedding an interlayer insulating film having a dielectric constant lower than that of the second insulating portion and the fourth insulating portion.

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