JP6258412B2 - Oxide-nitride-oxide stack having multilayer oxynitride layer - Google Patents

Description

CROSS REFERENCE TO RELATED APPLICATIONS This invention is based on the priority of US Provisional Patent Application No. 60 / 931,947, filed May 25, 2007, based on 35 U.S.C119 (e). A continuation-in-part of co-pending US application Ser. No. 11 / 811,958 filed on June 13, 2007, alleging benefit, both of which are incorporated herein by reference. To do.

The present invention relates to semiconductor manufacturing technology, and more particularly, to an oxide-nitride-oxide stack having an improved oxide-nitride layer or oxynitride layer and the manufacture thereof.

Nonvolatile semiconductor memories such as split gate flash memories typically use stacked floating gate field effect transistors. In this type of field effect transistor, electrons are induced in the floating gate of the memory cell to be programmed by biasing the control gate of the memory cell and grounding the body region of the substrate on which the memory cell is formed.

Oxide-nitride-oxide (ONO) stacks are used as charge storage layers in silicon-oxide-nitride-oxide-silicon (SSON) transistors, and in split gate flash memories, floating gates and control Used as an insulating layer between the gate.

FIG. 1 is a sectional view of a semiconductor device 100 such as a memory device.
Has a structure 102 that includes a SONOS gate stack, ie, a conventional ONO stack 104 formed according to conventional methods on the surface of a silicon substrate 108. In addition, the device 100 typically includes one or more diffusion regions 110 such as a source and drain that are aligned with the gate stack and separated by a gate channel region 112. In brief, SO
The NOS structure 102 includes a polysilicon gate layer 114 formed on and in contact with the ONO stack 104. The poly gate layer 114 is separated from the substrate 108 by the ONO stack 104 and is electrically insulated. The ONO stack 104 generally includes a bottom oxide layer 116, a nitride or oxynitride layer 118 that acts as a charge storage layer or memory layer of the device 100,
And an upper high temperature oxide (HTO) layer 120 covering the nitride or oxynitride layer.

One problem associated with the conventional SONOS structure 102 and its fabrication method is that the data retention performance of the nitride or oxynitride layer 118 is poor and due to leakage current leaking through this layer,
The lifetime of the device 100 and / or its use in some applications is limited.

Another problem associated with the SONOS structure 102 and its method of manufacture is that the stoichiometric composition of the oxynitride layer 118 is not uniform and optimal across the thickness of the layer. In particular, the oxynitride layer 118 has traditionally been a single process gas mixture and fixed or constant processing conditions to obtain a uniform layer having high nitrogen and high oxygen concentrations over a relatively thick layer thickness. Is formed or deposited in a single step. But for the top and bottom effects,
This method results in nitrogen, oxygen and silicon concentrations that vary throughout the thickness of the conventional oxynitride layer 118. The top effect is due to the order in which process gases are shut off after deposition. In particular, typically a silicon-containing process gas such as silane is shut off first, so that oxygen and / or nitrogen is high and silicon is low in the top portion (top) of the oxynitride layer 118. Similarly, the bottom effect is due to the order in which process gases are introduced to initiate deposition.
In particular, since the deposition of the oxynitride layer 118 is typically after an annealing step, a peak or a relatively high concentration of ammonia (NH ₃ ) occurs at the start of the deposition process, resulting in a bottom portion (bottom portion) of the oxynitride layer. ), Oxygen and silicon recon are low and nitrogen is high. Furthermore, the bottom effect is also attributed to a surface nucleation phenomenon where usable oxygen and silicon in the initial process gas mixture react preferentially with silicon on the surface of the substrate and do not contribute to the formation of oxynitrides. Accordingly, the memory device 100 comprising the ONO stack 104 is adversely affected by charge storage characteristics, particularly programming and erasing speed and data retention performance.

Accordingly, there is a need for a memory device having an ONO stack that includes an oxynitride layer that exhibits improved programming and erase speed and data retention performance as a memory layer. Furthermore,
What is needed is a method or process for forming an ONO stack having an oxynitride layer exhibiting improved oxynitride stoichiometry.

A semiconductor device including a silicon-oxide-nitride-oxide-silicon structure and a method for manufacturing the same are provided. In one embodiment, the structure comprises a tunnel oxide layer on a surface of a silicon-containing substrate and an oxygen-rich first layer having a stoichiometric composition on the tunnel oxide layer and causing little trapping. A multilayer charge storage layer including an oxynitride layer and an oxygen lean second oxynitride layer on the first oxynitride layer and having a stoichiometric composition that produces a high density of traps; A blocking oxide layer on the second oxynitride layer, and a silicon-containing gate layer on the blocking oxide layer.

In one embodiment, the method comprises the steps of (i) forming a tunnel oxide layer over the silicon-containing layer of the substrate; and (ii) a stoichiometry that generates little traps over the tunnel oxide layer. Depositing an oxygen-rich first oxynitride layer having a stoichiometric composition and having a stoichiometric composition that produces a high density of traps on the first oxynitride layer. Forming a multilayer charge storage layer by depositing a material layer; (iii) forming a blocking oxide layer on the second oxynitride layer; and (iv) on the blocking oxide layer. Forming a silicon-containing gate layer.

These and various other features and advantages of the structure and method of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings and the appended claims.

1 is a block diagram illustrating a cross-section of an intermediate structure during manufacture of a memory device having an oxide-nitride-oxide (ONO) stack formed according to a conventional method. FIG. 1 is a block diagram illustrating a cross-section of a portion of a semiconductor device having a silicon-oxide-nitride-oxide-silicon structure including a multilayer charge storage layer according to an embodiment of the present invention. FIG. 3 is a flow diagram of a method for forming an oxide-nitride-oxide structure including a multilayer charge storage layer, according to one embodiment of the invention. 6 is a graph showing an improvement in data retention performance of a memory device using a memory layer formed according to the present invention compared to a memory device using a conventional memory layer. 4 is a flow diagram of a method for forming an oxide-nitride-oxide structure including a multilayer charge storage layer according to another embodiment of the invention. FIG. 3 is an energy band diagram of a programmed conventional memory device having an ONO structure. 7A and 7B are energy band diagrams before and after programming a memory device including a multilayer charge storage layer according to an embodiment of the present invention.

The present invention is generally directed to a device comprising a silicon-oxide-oxynitride-oxide-silicon gate structure including a multilayer charge storage layer and a method of manufacturing the same. This gate structure and manufacturing method is particularly useful for forming memory layers of memory devices such as memory transistors.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the structure and method of the present invention may be practiced without these specific details. Furthermore, well-known structures and techniques are shown in block diagram form, rather than in detail, in order to avoid unnecessarily obscuring an understanding of the present disclosure.

As used herein, “an embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, references to “one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, “coupled” as used herein means both directly connected and indirectly connected by one or more intervening elements.

Briefly, the method comprises the steps of forming a multilayer charge storage layer comprising a multilayer oxynitride layer such as silicon oxynitride (Si ₂ N ₂ O) with different concentrations of oxygen, nitrogen and / or silicon. Including. These oxynitride layers are formed at higher temperatures than nitrides or oxynitrides in conventional ONO structures, and each layer is formed using different process gas mixtures and / or different flow rates. Generally, these oxyoxide layers include at least a top oxynitride layer and a bottom oxynitride layer. In certain embodiments, the stoichiometric composition of these layers is such that the bottom or bottom oxynitride layer has a high oxygen and silicon content and the top oxynitride layer has a high silicon and high nitrogen concentration and low. Adjusted or selected to produce oxygen lean, silicon rich nitride or oxynitride having an oxygen concentration. Silicon-rich and oxygen-rich bottom oxynitride layers reduce stored charge loss without reducing device speed or the difference between the initial (early life) programming and erase voltages. The silicon-rich, oxygen-lean top oxynitride layer increases the difference between the programming voltage and erase voltage of the memory device, thereby increasing device speed, increasing device retention performance, and extending device operating life. In some embodiments, the silicon-rich, oxygen-lean top oxynitride layer can further include a concentration of carbon selected to increase the number of traps in the layer.

Optionally, a silicon-oxide-oxynitride-oxide-silicon gate structure tunnel by dry or wet oxidation or an oxynitride layer on the first oxide layer after formation of the first oxide layer In order to facilitate the formation, the ratio of the thickness of the top oxynitride layer to the bottom oxynitride layer can be selected.

A silicon-oxide-oxynitride-oxide-silicon structure and method for fabricating the same according to various embodiments of the present invention will be described in detail below with reference to FIGS.

FIG. 2 is a block diagram illustrating a cross-section of a portion of a semiconductor memory device 200 having a silicon-oxide-oxynitride-oxide-silicon gate structure including a multilayer charge storage layer, according to one embodiment of the invention. . Referring to FIG. 2, a memory device 200 includes a silicon-oxide-oxynitride-oxide-silicon that includes a multilayer charge storage layer 204 formed on a surface 206 of a silicon layer on a substrate or silicon substrate 208. A gate stack 202 is provided. In addition, device 200 is aligned with gate stack 202 and gate channel region 212.
One or more diffusion regions 210, such as source and drain regions or structures separated by. In general, the silicon-oxide-oxynitride-oxide-silicon gate structure 202 is a silicon-containing gate layer formed on and in contact with the multilayer charge storage layer 204, such as polysilicon or polygate layer 214 and silicon layer or A portion of the substrate 208 is included. Poly gate layer 214
Is separated from the silicon layer or substrate 208 by the multilayer charge storage layer 204 and is electrically isolated. The silicon-oxide-oxynitride-oxide-silicon structure is a thin bottom oxide or tunnel oxide layer 216, top or blocking oxide layer that isolates or electrically isolates the gate stack 202 from the channel region 212. 218 and a multilayer charge storage layer 204. As described above and shown in FIG. 2, the multilayer charge storage layer 204 includes at least two oxynitride layers, such as a top oxynitride layer 220A and a bottom oxynitride layer 220B.

The substrate 208 can comprise a known silicon-based semiconductor material, such as silicon, silicon-germanium, silicon-on-insulator, or system-on-sapphire substrate. Alternatively, the substrate 208 can include a silicon layer formed on a non-silicon based semiconductor material such as gallium arsenide, germanium, gallium nitride, or aluminum phosphide. In particular embodiments, substrate 208 is a doped or undoped silicon substrate.

The lower oxide layer or tunnel oxide layer 216 of the silicon-oxide-oxynitride-oxide-silicon structure is typically about 15 Å to about 22 Å, and in some embodiments about 18 Å dioxide. It includes a relatively thin layer of silicon (SiO ₂ ). The tunnel oxide layer 216 can be formed or deposited by any suitable means, for example, thermally grown or deposited using chemical vapor deposition (CVD). In general, the tunnel oxide layer is formed or grown using thermal oxidation in an oxygen atmosphere. In one embodiment, the process uses a dry oxidation process in which the substrate 208 is placed in a deposition or processing chamber and heated to a temperature of about 700 ° C. to about 850 ° C. Exposure to oxygen for a predetermined period selected based on the desired thickness. In another embodiment, the tunnel oxide layer is formed by radical oxidation using a reaction of oxygen (O ₂ ) and hydrogen (H ₂ ) at a temperature of at least 1000 ° C. in an ISSG (In-Situ Stream Generation) chamber. Grown on the substrate. An exemplary processing time is about 10-100 minutes. Oxidation can be carried out at atmospheric or low pressure.

As described above, the multilayer charge storage layer generally includes at least two oxynitride layers having different compositions of silicon, oxygen, and nitrogen, and is about 70 to 150 inches (in certain embodiments, 100
Ii) can have a total thickness. In one embodiment, the oxynitride layer is a silane (
SiH ₄ ), chlorosilane (SiH ₄ Cl), dichlorosilane (SiH ₄ Cl ₂ ) or D
Silicon sources such as CS (SiH ₂ Cl ₂ ), tetrachlorosilane (SiCl ₄ ), or binary butylamine silane (BTBAS), nitrogen (N ₂ ), ammonia (NH ₃ )
, Nitrogen sources such as nitric oxide (NO ₃ ) or nitrous oxide (N ₂ O), and oxygen (O ₂ ) or N
Formed or volume at low pressure CVD process using oxygen-containing gas, such as _{2 O.} instead of,
A gas in which hydrogen is replaced with deuterium can also be used. For example, deuterated ammonia (ND ₃ ) can be used instead of NH ₃ . Replacing hydrogen with deuterium deactivates the Si dangling bonds at the silicon-oxide interface, and thus the NB of the device
TI (Negative Bias Temperature Instability) life is increased.

For example, the bottom or bottom oxynitride layer 220B places the substrate 208 in the deposition chamber and maintains the chamber at a pressure of about 5 millitorr (mT) to about 500 mT for a period of about 2.5 minutes to about 20 minutes. And introducing a process gas comprising N ₂ O, NH ₃ and DCS while maintaining the substrate at a temperature of about 700 ° C. to about 850 ° C. (in certain embodiments at least about 760 ° C.). It can be deposited on the oxide layer 216. In particular, the process gas comprises a first gas mixture of N ₂ 0 and NH ₃ mixed in a ratio of about 8: 1 to 1: 8 and DCS and NH mixed in a ratio of about 7: 1 to 1: 7. ₃ second gas mixtures can be included and introduced at a flow rate of about 5-200 cubic centimeters per minute (sccm). An oxynitride layer produced or deposited under these conditions has been found to yield a silicon-rich, oxygen-rich bottom oxynitride layer 220B, which has a charge loss rate after programming and erasing. To reduce the voltage shift in the hold state.

The upper oxynitride layer 220A uses a process gas including N ₂ O, NH ₃ and DCS,
The bottom acid by a CVD process at a chamber pressure of about 5 mT to about 500 mT and a temperature of about 700 ° C. to about 850 ° C. (in certain embodiments, at least about 760 ° C.) for a period of about 2.5 minutes to about 20 minutes. A nitride layer 220B can be deposited. In particular, the process gas comprises a first gas mixture of N ₂ 0 and NH ₃ mixed in a ratio of about 8: 1 to 1: 8 and about 7:
1 to 1: The second gas mixture of 7 DCS and NH ₃ were mixed in a ratio of can include, it can be introduced at a flow rate of about 5～200Sccm. An oxynitride layer produced or deposited under these conditions has been found to yield a silicon-rich, nitrogen-rich and oxygen-lean upper oxynitride layer 220A, which is a silicon-oxide-acid. Without compromising the charge loss rate of a memory manufactured using a nitride-oxide-silicon structure, it provides increased speed and increased initial differences in programming and erase voltages, thus extending the operating life of the device. Bring.

In some embodiments, the silicon-rich, nitrogen-rich, and oxygen-lean top oxynitride layer 220A contains about 7: to contain a selected concentration of carbon to increase the number of traps in the layer. It can be deposited on the bottom oxynitride layer 220B by CVD using a process gas containing BTBAS and ammonia (NH ₃ ) mixed in a ratio of 1: 1: 7. The selected concentration of carbon in the second oxynitride layer can include a carbon concentration of about 5% to about 15%.

In certain embodiments, the top nitride layer 220A is continuously deposited in the same tool used to form the bottom oxynitride layer 20B, substantially without breaking the deposition chamber vacuum. In certain embodiments, the upper oxynitride layer 220A is a lower oxynitride layer 220.
The deposition is continuously performed with almost no change in the temperature of the substrate 208 heated during the deposition of B.
In one embodiment, the top oxynitride layer 220A is N ₂ 0 / NH ₃ relative to the DCS / NH ₃ gas mixture so that silicon-rich, nitrogen-rich and oxygen-lean top oxynitride 220A is produced. By depositing the gas mixture at the desired ratio by reducing the gas mixture flow rate, it is continuously deposited immediately after deposition of the bottom oxynitride layer 220A.

In certain embodiments, another oxide or oxide layer (not shown in these figures) is formed by vapor oxidation in different regions or devices on the substrate 208 after the gate stack 202 is formed. The In this embodiment, the silicon-oxide-oxynitride-oxide-silicon top oxynitride layer 220A and top or blocking oxide layer 218 are beneficially vapor annealed during the steam oxidation process. In particular, vapor annealing improves the quality of the blocking oxide layer 218 and reduces the number of traps formed near the top surface of the blocking oxide layer 218 and near the top surface of the bottom oxynitride layer 220A. This can reduce or substantially eliminate the electric field across the blocking oxide layer that can occur (which creates a backflow of charge carriers and adversely affects the data or charge retention performance of the charge storage layer).

A suitable thickness for the bottom oxynitride layer 220B is about 10 mm to about 80 mm, and the ratio of the thickness of the bottom oxynitride layer to the top oxynitride layer is about 1: 6 to 6: 1 In this embodiment, it was confirmed to be at least about 1: 4.

The top or blocking oxide layer 218 of the silicon-oxide-oxynitride-oxide-silicon structure includes a relatively thick SiO ₂ layer of about 30 to about 70 inches, and in certain embodiments about 45 inches. The top or blocking oxide layer 218 can be grown or deposited using any suitable means, such as thermal growth or CVD. In one embodiment, the top or blocking oxide layer 218
Is high temperature oxide (HTO) deposited using a CVD process. In general, the deposition process involves maintaining the substrate 208 at a temperature of about 650 ° C. to about 850 ° C. in a deposition chamber at a pressure of about 50 mT to about 1000 mT for a period of about 10 minutes to about 120 minutes. Exposing to a silicon source such as silane, chlorosilane or dichlorosilane and an oxygen containing gas such as O ₂ or N ₂ O.

In certain embodiments, the top or blocking oxide layer 218 is an oxynitride layer 220A, 22
Deposited continuously in the same tool used to form 0B. In certain embodiments,
The oxynitride layers 220A, 220B and the top or blocking oxide layer 218 are formed by the tunnel oxide layer 2
Formed or deposited in the same tool used for 16 growths. Suitable tools are, for example, ONO, AVP available from AVIZA Technology, Inc., Scotts Valley, California
It is.

A method of forming or manufacturing a silicon-oxide-oxynitride-oxide-silicon stack according to one embodiment is described below with reference to the flowchart of FIG.

Referring to FIG. 3, the method includes a first oxide layer, such as a tunnel oxide layer 216 of a silicon-oxide-oxynitride-oxide-silicon gate stack 202, on the surface of the substrate 208. Begin by forming on the silicon-containing layer (300). Next, a first or bottom oxynitride layer 220B of the multilayer charge storage layer 204 comprising oxynitride is formed on the surface of the first oxide layer (302). As described above, the first or bottom oxynitride layer 220B is N ₂ 0 / NH ₃ at a ratio and flow rate adjusted to obtain a silicon-rich and oxygen-rich oxynitride layer.
And can be formed or deposited by CVD using a process gas comprising a DCS / NH ₃ gas mixture. Next, a second or top oxynitride layer 220A of the multilayer charge storage layer 204 is formed on the surface of the first or bottom oxynitride layer 220B (304). The second or top oxynitride layer 220A has a different stoichiometric composition of oxygen, nitrogen and / or silicon than the first or bottom oxynitride layer 220B. In particular, as described above, the second or upper oxynitride layer 220A is
DC at a ratio and flow rate adjusted to obtain a silicon-rich, oxygen-lean oxynitride layer
It can be formed or deposited by CVD using a process gas comprising a S / NH ₃ and N ₂ 0 / NH ₃ gas mixture. Finally, the top of the silicon-oxide-oxynitride-oxide-silicon structure or blocking oxide layer 218 is formed on the surface of the second layer of the multilayer charge storage layer (
306). As noted above, this top or blocking oxide layer 218 can be formed or deposited by any suitable means, but in some embodiments is deposited by a CVD process.
In one embodiment, the top or blocking oxide layer 218 is a high temperature oxide deposited by an HTO CVD process. Alternatively, the top or blocking oxide layer 218 can be grown thermally. However, in this embodiment, the thickness of the upper oxynitride layer 220A is adjusted because a portion of the oxynitride is effectively consumed or oxidized during the thermal growth process of the upper or blocking oxide layer 218. Or it can be increased.

Optionally, the method includes the step of forming or depositing a silicon-containing layer on the top or surface of the blocking oxide layer 218 to form a silicon-oxide-oxynitride-oxide-silicon stack or structure. Further (308) can be included. This silicon-containing layer may be used, for example, to form a control or polygate layer 214 of the transistor or device 200, for example C
It can be a polysilicon layer deposited by a VD process.

Here, referring to FIG. 4, the data retention performance of a memory device using a memory layer formed according to one embodiment of the present invention is compared with the data retention performance of a memory device using a conventional memory layer. I do. In particular, FIG. 4 illustrates a memory in an electrically erasable read only memory (EEPROM) using a conventional ONO structure and a silicon-oxide-oxynitride-oxide structure having a multi-layered oxynitride layer of the present invention. Fig. 6 shows the change in threshold voltage (VTP) during programming and threshold voltage (VTE) during erasing of the device during device lifetime. In data collection for this figure, both devices were pre-circulated for 100K cycles at an ambient temperature of 85 ° C.

Referring to FIG. 4, a graph or line 402 is an EEP using a conventional ONO structure with a single oxynitride layer that does not refresh the memory after initial write (program or erase).
The time-dependent change of VTP with respect to ROM is shown. The actual data points on line 402 are indicated by white circles,
The remainder of this line represents the extrapolated value of VTP up to the end of the specified lifetime of the EEPROM (EOL). A graph or line 404 shows the change in VTE over time for an EEPROM using a conventional ONO structure. The actual data points on line 404 are indicated by black circles and the rest of this line is EEPROM
The extrapolated value of VTE up to the specified EOL is shown. In general, EEPROM V in EOL
The specified difference between TE and VTP is 0.5V or more in order to be able to identify or detect the difference between the programmed state and the erased state. As is apparent from this figure, an EEPROM using a conventional ONO structure has a difference between VTE and VTP of about 0.35 V at a 20 year specified EOL. Therefore, an EEPROM using a conventional ONO structure does not meet the specified operating life in at least about 17 years when operated under the above conditions.

In contrast, the time course of VTP and VTE of the EEPROM using a silicon-oxide-oxynitride-oxide-silicon structure having a multi-layered oxynitride layer is shown by lines 406 and 408, respectively.
And shows the difference between VTE and VTP of at least 1.96V at the specified EOL. Thus, an EEPROM using a silicon-oxide-oxynitride-oxide-silicon structure according to one embodiment of the present invention exceeds the specified operating life of 20 years. In particular, the graph or line 4
06 shows the time course of VTP of the EEPROM using the silicon-oxide-oxynitride-oxide-silicon structure according to one embodiment of the present invention. The actual data points on line 406 are shown as white squares, and the remainder of this line shows the extrapolated value of VTP up to the specified EOL. Graph or line 4
08 shows the change in VTE over time for EEPROM, the actual data points on line 408 are shown as black squares, and the remainder of this line shows the extrapolated value of VTE up to the specified EOL of the EEPROM.

Next, a method of forming or manufacturing a semiconductor device according to another embodiment will be described with reference to FIG.

Referring to FIG. 5, the method begins by forming a tunnel oxide layer 216 on the substrate (500). Next, the oxygen-rich first or bottom oxynitride layer 2 of the multilayer charge storage layer 204
20B is formed on the surface of tunnel oxide layer 216 (502). As described above, this oxygen-rich first or bottom oxynitride layer 220B is dichlorosilane (SiH ₂ Cl ₂ ) / ammonia (NH ₃ ) mixed in a ratio ranging from about 5: 1 to 15: 1. Mixture and about 2: 1
A process gas comprising a nitrous oxide (N ₂ O) / NH ₃ mixture mixed in a ratio in the range of ˜4: 1 is tuned to obtain a silicon-rich and oxygen-rich, almost trap-free oxynitride layer. Can be formed or deposited by CVD using different flow rates. That is, the stoichiometric composition of the first or bottom oxynitride layer 220B includes a high concentration of oxygen selected to increase the retention performance of the multilayer charge storage layer, and the second or top oxynitride layer 220A includes It acts as a barrier between the trapped charge and the substrate 208. The selected oxygen concentration in the first or bottom oxynitride layer 220B is about 15% to about 40% oxygen concentration, and in certain embodiments about 3%.
5%.

Next, the oxygen-lean second or upper oxynitride layer 220A is replaced by the first or lower oxynitride layer 220.
Formed on the surface of B (504). The second or upper oxynitride layer 220A has a different stoichiometric composition of oxygen, nitrogen and / or silicon than the first oxynitride layer. In particular, as described above, the second or upper oxynitride layer 220A has a range of about 1: 6 to 1: 8 in order to obtain a high trap density oxynitride layer having an oxygen concentration of about 5% or less. N ₂ 0 / NH mixed in the ratio
_{The three} mixtures can be formed or deposited by CVD using a process gas comprising a SiH ₂ Cl ₂ / NH ₃ mixture mixed in a ratio ranging from about 1.5: 1 to 3: 1. Thus, the second or top oxynitride layer 220A includes a charge trap density that is 1000 times or more that of the first or bottom oxynitride layer 220B.

Finally, an upper or blocking oxide layer 218 is formed on the second or upper oxynitride layer 220A of the multilayer charge storage layer 204. As described above, this top or blocking oxide layer 218 is a second layer.
Alternatively, the second oxynitride layer 220A may be thinned to a predetermined thickness by oxidation of a portion of the upper oxynitride layer 220A. Finally, as described with reference to FIG. 4, the endurance (EOL) of the semiconductor device at the specified difference between the program voltage (VTP) and the erase voltage (VTE) is improved by the improvement in the retention performance of the multilayer charge storage layer 204. 2
Extend to 0 years or more.

In another aspect, the multilayer charge storage layer of the present invention has a bandgap energy designed to generate an electric field in a direction opposite to that generated by the stored charge in the charge storage layer in the programmed state. As a result, the data retention performance is improved without affecting the program voltage and / or the erase voltage. An energy band diagram of a programmed conventional device including a channel in a silicon substrate 602, a tunnel oxide layer 604, a homogeneous nitride or oxynitride field storage layer 606, a blocking oxide layer 608 and a polysilicon control gate 610 is shown. It is shown in FIG. Referring to FIG. 6, a large number of trapped charges located near the center of the charge storage layer 608 generate a large electric field from the tunnel oxide layer 604 toward the trapped charge, which reduces the stored charge loss. Note that this can happen.

In contrast, in the memory device including the multilayer charge storage layer of the present invention, the band gap energy generated in the multilayer charge storage layer is inwardly opposite to the electric field generated by the stored charge (from the charge storage layer toward the tunnel oxide). Direction) to enhance the charge retention performance. An unprogrammed memory device including a multilayer charge storage layer 706 is shown in FIG. 7A. The device includes a channel in a silicon substrate 702, a tunnel oxide layer 704, an oxygen lean oxynitride layer 706A, an oxygen rich bottom oxynitride layer 706B, a blocking oxide layer 708, and a polysilicon control gate 710. Referring to FIG. 7A, the trap sites in the oxygen lean upper oxynitride layer 706A generate an electric field in the opposite direction to that generated by the trapped charge in the programmed device. A bandgap diagram of a device including a multilayer charge storage layer 706 obtained in a programmed state is shown in FIG. 7B.

Although the multilayer charge storage layer has been illustrated and described as having two oxynitride layers, a top and a bottom layer, the present invention is not so limited and includes any number of oxynitride layers, one of them. Parts or all may have different stoichiometric compositions of oxygen, nitrogen and / or silicon. In particular, a multilayer charge storage layer having five oxynitride layers, each having a different chemical composition, was fabricated and tested. However, as will be apparent to those skilled in the art, it is generally preferable to use as few layers as possible to achieve the desired result, providing a simpler and more robust process. In addition, using as few layers as possible makes the yield even higher because the control of the stoichiometric composition and dimensions of the few layers is easier.

Further, although the silicon-oxide-oxynitride-oxide-silicon structure has been illustrated and described as part of the silicon-oxide-oxynitride-oxide-silicon stack of a memory device, the present invention describes this structure and its structure. This silicon-oxide-oxynitride-oxide- is not limited to manufacturing
The silicon structure may be any semiconductor technology or any device that requires a charge storage or insulating layer or stack without departing from the scope of the invention, such as split gate flash memory, TaNOS stack, IT (transistor) SNOS type cell. It can be used for or in conjunction with 2T SONOS type cells, 3T SNOS type cells, localized 2-bit cells, multi-level programming cells, and / or 9T or 12T non-volatile semiconductor memory (NVSM) and the like. 8A-8E show schematic diagrams of exemplary memory cell structures in which the multilayer charge storage layer of the present invention is particularly useful.

The advantages of the structure and its manufacturing method according to an embodiment of the present invention over the prior art or the prior art are:
(i) Ability to improve the device retention performance of memory devices using a structure formed by dividing the oxynitride layer into multiple films or layers and adjusting the oxygen, nitrogen and silicon profiles of each layer, (ii) Data retention performance (Iii) using silicon-oxide-oxynitride-oxide-silicon according to an embodiment of the present invention above about 125 ° C. and Ability to meet or exceed speed specifications, and (iv) 100
, With the ability to provide heavy duty program erase cycles of over 00 cycles.

Although this disclosure has described certain exemplary embodiments, it will be apparent that various changes and modifications can be made to these embodiments without departing from the scope of this disclosure. The specification and drawings are accordingly to be regarded in an illustrative rather than a restrictive sense.

37C requesting a summary that allows readers to quickly identify the characteristics of technical disclosure.
A summary is provided pursuant to FR § 1.72 (b). It should be understood that the abstract is not used to interpret or limit the scope or meaning of the claims. Furthermore, in the detailed description given above, it can be seen that various features are grouped together in one embodiment to organize the present disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as subject to the following claims, the subject matter of the invention resides in less than all features of one disclosed embodiment. Accordingly, the following claims are
It is incorporated in the detailed description of the invention, with each claim standing on a separate embodiment.

In the foregoing description, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the multilayer charge storage layer of the present disclosure and the method of making the same. However, it will be apparent to those skilled in the art that the devices and methods of the present invention may be practiced without these specific details. Furthermore, well-known structures and techniques are shown in block diagram form, rather than in detail, in order to avoid unnecessarily obscuring an understanding of the present disclosure.

As used herein, “an embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, references to “one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, “coupled” as used herein means both directly connected and indirectly connected by one or more intervening elements.

Claims (6)

A tunnel oxide layer on the surface of the substrate comprising silicon;
Oxygen-rich first oxynitride layer having a stoichiometric composition on the tunnel oxide layer that hardly generates traps and high density traps on the first oxynitride layer A multilayer charge storage layer comprising an oxygen lean second oxynitride layer having a stoichiometric composition;
A blocking oxide layer on the second oxynitride layer;
A silicon-containing gate layer on the blocking oxide layer;
With
The second oxynitride layer includes a charge trap density of 1000 times or more of the first oxynitride layer;
The second oxynitride layer further includes carbon and has a silicon-oxide-oxynitride-oxide-silicon structure having a carbon concentration of about 5% to about 15%.   The structure of claim 1, wherein the concentration of oxygen in the first oxynitride layer is about 15% to about 40%.   The structure of claim 1, wherein the concentration of oxygen in the second oxynitride layer is less than about 5%. A substrate comprising silicon having laterally spaced source and drain regions;
A tunnel oxide layer on the surface of the substrate;
Oxygen-rich first oxynitride layer having a stoichiometric composition on the tunnel oxide layer that hardly generates traps and high density traps on the first oxynitride layer A multilayer charge storage layer comprising an oxygen lean second oxynitride layer having a stoichiometric composition;
A blocking oxide layer on the second oxynitride layer;
A silicon-containing gate layer on the blocking oxide layer;
With
The second oxynitride layer includes a charge trap density of 1000 times or more of the first oxynitride layer;
The second oxynitride layer further includes carbon, and the carbon concentration is about 5% to about 15%.   The semiconductor device of claim 4, wherein the concentration of oxygen in the first oxynitride layer is about 15% to about 40%.   The semiconductor device of claim 4, wherein the concentration of oxygen in the second oxynitride layer is less than about 5%.

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