JP6248066B2 - Switching power supply circuit - Google Patents

Description

  The present invention relates to a switching power supply circuit, and is particularly useful when applied to processing of residual charges when current supplied to a load such as a processor is interrupted by a synchronous rectification method.

  With the demand for low power consumption of electronic devices, the operating voltage of processing processors has been reduced. As a power supply for such a processor, a switching power supply circuit having a DC / DC converter that operates in a synchronous rectification method is widely used. The DC / DC converter is a technique generally used as a power source, and has a feature that power loss during voltage conversion is smaller than that of a linear regulator or the like. Therefore, it is optimal as a power supply application for a processor that requires a low voltage and a large current during operation.

  In the device, in addition to the low-voltage system for the processor, several power systems are provided for memory, analog parts, and machine parts. The voltages of these power supply systems are generated by individually generating a predetermined voltage from one original power supply or by stepping down from a higher voltage to a lower voltage. Some parts used in the device require a plurality of power supply systems having different voltage values.

  When a component requiring a plurality of power supplies is a semiconductor element, if the order of the power supply system to be applied is not appropriate, there is a risk that a parasitic element existing in the semiconductor element operates unintentionally and damages the component. Therefore, in a device having a plurality of power supply systems, a power-on sequence / off sequence for applying / cutting off voltage to each power supply system is determined. Here, the power-on sequence is generally started from a power supply system with a high voltage, and the power-off sequence is generally shut off from a power supply system with a low voltage.

  The power-on sequence is achieved by the timing of starting the operation of the power supply components that generate and output each power supply system and the time until these power supplies output a required voltage value. The power-off sequence is achieved by the timing of stopping the operation of the power supply components that generate and output each power system and the time until the voltage value of each power system decreases.

  In the power-off sequence, the operation of the load under each power supply system is stopped in advance before stopping the output operation of the power supply components. Therefore, when the power supply component stops operating, the current consumed from each power supply system is a very small current due to a high resistance load, a leakage current, or the like. Capacitors are provided between each power supply system and ground to stabilize the voltage.If the load of each power supply system is in a low current consumption state after the operation of the power supply parts stops, the voltage of these power supply systems It takes time to decrease. For this reason, some power supply components are provided with a mechanism for discharging electric charge remaining in the output power supply system. As a mechanism for discharging, for example, as disclosed in Patent Document 1, there is a mechanism including a dedicated discharge circuit in a power supply. However, additional cost is required to add a dedicated circuit. Thus, for example, Patent Document 2 proposes a method of using a switching transistor built in a DC / DC converter in order to perform predetermined discharge while avoiding an increase in cost. In Patent Document 2, when a stop signal is given to the power supply component, the transistor for switching between the coil and the ground is turned on to discharge the output charge.

  However, in the technique disclosed in Patent Document 2, when the capacitance value of the stabilizing capacitor is large, the charge stored in the capacitor also increases. Therefore, an excessive current flows at the time of discharge, and the coil in the discharge path and the switching The transistor may be damaged.

  As a technique for solving this problem, a technique disclosed in Patent Document 3 has been proposed. In Patent Document 3, the discharge current is observed, and when the current value exceeds a certain value, the switching transistor on the ground side is changed from the conductive state to the non-conductive state to prevent an excessive current from flowing.

Japanese Patent No. 4383936 JP 2008-113696 A JP 2008-160967 A

  By the way, as disclosed in Patent Document 3, if the ground-side transistor is turned off when the current value of the discharge current exceeds a predetermined threshold, the non-ground-side transistor between the primary power supply and the coil Alternatively, through a parasitic diode having the drain of the transistor as an anode and a back gate as a cathode, an output stabilizing capacitor is connected to a coil and the non-grounded switching transistor or a parasitic diode to A discharge path may be formed to the next power source. In this case, the electric charge is discharged while alternately going back and forth between a phase for forming a discharge path called ground from the output stabilization capacitor and a phase for forming a discharge path called a primary power source from the output capacitor. .

  Here, when the load is a processor, a highly accurate voltage supply is required both statically and dynamically to prevent malfunctions due to power supply fluctuations, and to cope with power supply voltage fluctuations caused by steep drive currents. In addition, a stabilizing capacitor having a large capacitance value is provided on the output side. As the output capacitance value of the stabilizing capacitor increases, the amount of electric charge that is discharged increases, and the frequency of the discharge path of the primary power supply from the output capacitor increases. The primary power supply of the power supply component is also provided with a capacity for stabilization, but the primary voltage rises as the amount of charge applied increases as the frequency of discharge to the primary side increases. . If the primary voltage increased by the discharge exceeds the rated voltage of the power supply component, the power supply component may be damaged. As a result, in order to prevent an excessive increase in the primary voltage, when the output capacitance value of the power supply component is large, it is necessary to increase the capacitance value of the primary side capacitor, which causes an increase in cost.

  In view of the above-described prior art, the present invention provides a switching power supply circuit capable of performing predetermined discharge safely and smoothly in a discharge mode without incurring an increase in cost even when a capacitor provided at an output has a large capacity. The purpose is to provide.

The first aspect of the present invention for achieving the above object is as follows:
In the switching mode, output signals output from the respective pre-drivers are alternately turned on / off by a synchronous rectification method, and one end side is a switching element connected to the primary power source, and one end side is grounded A predetermined transistor obtained via a coil and an output terminal from between the first transistor and the second transistor connected in series via the other ends. A switching power supply circuit for applying an output voltage to a load,
A discharge control circuit that operates based on a discharge control signal indicating the discharge mode and controls the second transistor to flow a predetermined constant current in a discharge mode in which the output residual charge is discharged after the switching mode ends. And having
The discharge control circuit is configured such that the second transistor flows a predetermined constant current by forming a current mirror circuit with the second transistor,
Further, a first switch means is provided between the pre-driver that outputs an output signal to the second transistor of the pre-drivers and the second transistor, and the transistor of the discharge control circuit and the second driver The second switch means is provided between the pre-driver and the pre-driver that outputs an output signal to the second transistor by opening the first switch means with the discharge control signal in the discharge mode. The mirror circuit is formed by the second transistor by shutting off the supply of the output signal to the second transistor and simultaneously turning on the second switch means with the discharge control signal. The switching power supply circuit is characterized by the following.

According to this aspect, since the second transistor forms a discharge circuit, there is no need to provide a separate circuit or element for discharging, and the current discharged through the second transistor is set to a constant value by the discharge control circuit. Since it is limited, damage to the coils and transistors forming the discharge circuit can be prevented. Further, since only the discharge circuit having a path from the output terminal to the ground is used, there is no charge transfer to the primary power source or the like, and the means for suppressing the fluctuation of the primary voltage can be simplified. Further, in this aspect, since the mirror circuit is used, the second transistor can be formed easily and with high accuracy so that a predetermined constant current flows.

The second aspect of the present invention is:
In the switching power supply circuit described in the first aspect ,
In the switching power supply circuit, a variable current source is connected to the current mirror circuit.

  According to this aspect, the predetermined constant current flowing through the second transistor can be easily adjusted. As a result, the limit value of the discharge current can be dynamically controlled by dynamically setting a constant current.

The third aspect of the present invention is:
In the switching power supply circuit described in the first aspect ,
In the switching power supply circuit, the current mirror circuit can select a plurality of mirror ratios.

  According to this aspect, the limit value of the discharge current that flows through the second transistor can be controlled by selecting the mirror ratio.

The fourth aspect of the present invention is:
In the switching power supply circuit described in the first aspect ,
The current mirror circuit is a switching power supply circuit including a plurality of current mirror circuits connected in series.

  According to this aspect, the limit value of the discharge current flowing through the second transistor can be adjusted by appropriately setting the mutual mirror ratio.

  According to the present invention, among the switching transistors, the second transistor connected between the coil and the ground has a constant discharge current flowing from the output capacitor to the ground through the second transistor. The function of limiting the value can be realized by the discharge control circuit. That is, the second transistor also serves as a discharge circuit for the output capacitor.

  As a result, it is not necessary to add a circuit or an element for causing a separate discharge, which can contribute to a reduction in cost. In addition, when discharging the output capacitor to the ground, the discharge current is kept constant. Since the value is limited to the value, the discharge current does not reach an excessive value, and damage to the coil, the switching transistor, and the like constituting the discharge circuit at this time can be prevented well.

  Further, a discharge path from the output capacitor to the primary power supply is not formed. As a result, the primary power supply voltage does not rise due to the discharge.

1 is a circuit diagram showing a switching power supply circuit according to a first embodiment of the present invention. It is a wave form diagram which shows the waveform of each part of the circuit diagram shown in FIG. It is a circuit diagram which shows the switching power supply circuit which concerns on the modification of the 1st Embodiment of this invention. It is a circuit diagram which shows the switching power supply circuit which concerns on the modification of the 1st Embodiment of this invention. It is a circuit diagram which shows the switching power supply circuit which concerns on the 2nd Embodiment of this invention. FIG. 6 is a waveform diagram showing waveforms at various parts of the circuit diagram shown in FIG. 5.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a circuit diagram showing a switching power supply circuit according to the first embodiment of the present invention. As shown in the figure, the switching power supply circuit according to this embodiment constitutes a synchronous rectification DC / DC converter. More specifically, the first transistor 8 as a switching element is a P-type MOS transistor, and the source on one end side is connected to the primary power source 1. A voltage stabilizing capacitor 2 is connected to the primary power source 1 in parallel. The second transistor 9 as another switching element is an N-type MOS transistor, and the source on one end side is grounded. The transistors 8 and 9 are connected in series via the drains on the other end side. A predetermined voltage generated by the switching operation of the transistors 8 and 9 is applied to the external load 5 from between the transistors 8 and 9 via the coil 3 and the output terminal Vout. A voltage stabilizing capacitor 4 is connected in parallel with the load 5 to the output terminal Vout.

  The voltage information at the output terminal Vout is fed back to the switching control circuit 7. The output voltage Vo of the output terminal Vout fed back to the switching control circuit 7 is a feedback voltage signal defined by the dividing resistors 71 and 72 and the division ratio determined by the output voltage Vo and the resistance value of the dividing resistors 71 and 72. To the amplifier 73. A reference voltage Vref from a reference voltage source 74 is applied to the amplifier 73 together with a feedback voltage signal defined by the dividing resistors 71 and 72. Thus, the amplifier 73 applies the amplified signal obtained by amplifying the difference between the voltage values of the two supplied voltage signals to the inverting input terminal of the comparator 75. A triangular wave signal generated by the triangular wave generator 76 is applied to the non-inverting input terminal of the comparator 75. Thus, the comparator 75 compares the voltage value of the amplified signal, which is the output of the amplifier 73, with the voltage value of the triangular wave signal, which is the output of the triangular wave generator 76. If the voltage value of the triangular wave signal is high, the Hi signal is output. When the voltage value of the amplified signal is high, the Lo signal is output. The output signal of the comparator 75 is supplied to the pre-driver circuit 10 via the switch logic 77.

  The pre-driver circuit 10 includes a pre-driver 101 for driving the transistor 8 and a pre-driver 102 for driving the transistor 9. The output of the pre-driver 101 is connected to the gate of the transistor 8, and the output of the pre-driver 102 is connected to the gate of the transistor 9, and drives the transistors 8 and 9 according to signals supplied from the switching control circuit 7.

  A switch 12 is provided between the pre-driver 102 and the transistor 9. The switch 12 is opened and closed by a discharge control signal DISCHG. The discharge control signal DISCHG is supplied to the switch logic 77, the switch 12, and the switch 13. When the discharge control signal DISCHG is at the Lo level, the switch logic 77 supplies a signal having the same logic as the output signal of the comparator 75 to the pre-driver circuit 10, and closes the switch 12 and opens the switch 13. That is, when the discharge control signal DISCHG is at the Lo level, the DC / DC converter 6 operates as a step-down DC / DC converter that maintains the output terminal Vout at a predetermined voltage value.

  On the other hand, when the discharge control signal DISCHG is at the Hi level, the switch logic 77 supplies the predriver 101 with a logic signal that causes the transistor 8 to become non-conductive regardless of the output signal of the comparator 75, and the switch 12 opens. The switch 13 is closed. At this time, the transistor 8 is nonconductive regardless of the voltage value of the output terminal Vout, and the gate of the transistor 9 is driven by the discharge control circuit 11.

  Here, the discharge control circuit 11 includes a current source 111 and a transistor 112 which is an N-type MOS transistor, and a constant current Idis is applied from the current source 111 to the drain-gate common terminal of the diode-connected transistor 112. Yes.

  The transistor 112 has a channel width and a channel length so that the drain current is 1: N (N is a mirror ratio) when the mirror circuit is configured with the transistor 9. Thus, when the discharge control signal DISCHG is Hi, the transistor 8 is in an off state, and the transistor 9 and the transistor 112 constitute a mirror circuit. Therefore, the drain current of the transistor 9 is N × Idis.

  Next, waveforms of respective parts accompanying the operation of the switching power supply circuit according to this embodiment having the above-described configuration will be described with reference to the drawings. 2A and 2B are waveform diagrams showing waveforms of respective parts representing the operation of the switching power supply circuit shown in FIG. 1. FIG. 2A is a gate voltage of the transistor 8, FIG. 2B is a gate voltage of the transistor 9, and FIG. 73, the output signal of the triangular wave generator 76, (d) is the output signal of the comparator 75, (e) is the current of the coil 3 (the direction toward the output terminal Vout is positive), and (f) is the output. Voltages Vo and (g) are discharge control signals, and (h) is the drain current of the transistor 9 (the direction from the drain to the coil 3 is positive).

  FIG. 2 shows a waveform from an equilibrium state immediately before the discharge operation of the output-side capacitor 4 is started and the load current is zero. Here, a period in which the discharge control signal DISCHG shown in FIG. 2G is at the Lo level is a normal operation period, and a period in which the Hi level is at is an output discharge operation period.

<Normal operation period>
During the normal operation period, the voltage at the output terminal Vout is determined by the resistance values of the dividing resistors 71 and 72 and the reference voltage Vref provided by the reference voltage source 74. Here, when the resistance value of the dividing resistor 71 is R71 and the resistance value of the dividing resistor 72 is R72, the output voltage Vo of the output terminal Vout is Vref × (R71 + R72) / R72. That is, the output voltage Vo at the output terminal Vout is divided by the dividing resistors 71 and 72 and supplied to the amplifier 73. The amplifier 73 is also supplied with a reference voltage Vref from a reference voltage source 74. As a result, the amplifier 73 amplifies the difference between both voltages and outputs it to the comparator 75.

  The comparator 75 compares the output signal of the amplifier 73 with the triangular wave generated by the triangular wave generator 76, that is, compares the input voltage values of both, and outputs a Hi level signal when the voltage value of the triangular wave is high. When the voltage value of the output signal of the amplifier 73 is high, a Lo level signal is output (see FIG. 2C).

なる関係が成立する。 Here, the output signal of the comparator 75 (see FIG. 2D) is substantially equal to the switching duty of the DC / DC converter 6, the input voltage is Vin, the Hi period of the output signal of the comparator 75 is T_Hi, and the comparator 75. When the Lo period of the output signal is T_Lo,
[Equation 1]

This relationship is established.

  The output signal of the comparator 75 is given as a duty signal to the pre-drivers 101 and 102 via the switch logic 77. The pre-drivers 101 and 102 generate the pulse signals shown in FIGS. 2A and 2B in accordance with the given duty signal and supply them to the switching transistors 8 and 9 to perform a predetermined switching operation. Make it. That is, when the output signal of the comparator 75 is at the Lo level, the pre-driver 101 drives the gate of the transistor 8, which is a PMOS transistor, to the Lo level to bring the transistor 8 into a conductive state. The pre-driver 102 drives the gate of the transistor 9, which is an NMOS transistor, to the Lo level to make the transistor 9 nonconductive. When the transistor 8 is conductive and the transistor 9 is nonconductive, the voltage Vin is applied to the terminal of the coil 3 commonly connected to the drains of the transistors 8 and 9. Here, since one terminal of the coil 3 is connected to the output terminal Vout and Vin> Vo, the current flowing to the output terminal Vout through the coil 3 increases (charge phase (see FIG. 2E)). .

  When the output signal of the comparator 75 is at the Hi level, the pre-driver 101 drives the gate of the transistor 8 to the Hi level to make the transistor 8 nonconductive, and the pre-driver 102 drives the gate of the transistor 9 to the Hi level. Thus, the transistor 9 is turned on. When the transistor 8 is in a non-conductive state and the transistor 9 is in a conductive state, a ground potential is applied to the terminal of the coil 3 commonly connected to the drains of the transistors 8 and 9 and flows through the coil 3 to the output terminal Vout. The current decreases (transfer phase (see FIG. 2 (e))).

  In an equilibrium state and no load state, the amount of increase in the coil current in the charge phase is equal to the amount of decrease in the coil current in the transfer phase, and the average value of the coil current is 0. There is no exchange.

  The polarities of the input terminals of the amplifier 73 and the comparator 75 are set so that the DC / DC converter 6 forms a negative feedback circuit using the output voltage Vo of the output terminal Vout. For example, when the output voltage Vo at the output terminal Vout rises from the balanced state due to external disturbance, the output level of the amplifier 73 falls from the balanced state, and the period T_Lo of the Lo signal output from the comparator 75 becomes shorter than the balanced state. Therefore, the charge phase is shorter and the transfer phase is longer than in the balanced state, and the amount of power supplied from the primary side to the output side is reduced from the balanced state. As a result, the action of lowering the output voltage Vo works. As the voltage value of the output voltage Vo approaches the value in the equilibrium state, the output level of the amplifier 73 and the Hi level output period of the comparator 75 also approach the values in the equilibrium state. Ultimately, it will be the value at equilibrium.

<Output discharge operation period>
During the output discharge operation period, the discharge control signal DISCHG is at the Hi level as shown in FIG. The Hi level signal is supplied to the switch logic 77 and the switches 12 and 13. The switch logic 77 gives the output signal of the comparator 75 to the pre-drivers 101 and 102 when the discharge control signal DISCHG is at the Lo level, and pre-regardless of the output signal of the comparator 75 when the discharge control signal DISCHG is at the Hi level. A signal is output to make the output of the driver 101 high. When the output of the pre-driver 101 is at Hi level, the gate of the transistor 8 which is a PMOS transistor is also driven to Hi level, so that the transistor 8 is turned off.

  The switch 12 is closed when the discharge control signal DISCHG is at the Lo level, and is open when the discharge control signal DISCHG is at the Hi level. On the other hand, the switch 13 is open when the discharge control signal DISCHG is at the Lo level, and is closed when the discharge control signal DISCHG is at the Hi level. Therefore, the gate of the transistor 112 is connected to the gate of the transistor 9 during the discharge period.

  Since the transistor 112 and the transistor 9 have the same gate potential and the source is also the ground potential, the gate-source voltage of the transistor 112 is equal to the gate-source voltage of the transistor 9, and the transistor 112 and the transistor 9 form a mirror circuit. Configure. At this time, since the transistor 8 is in a non-conductive state and the transistor 9 is in a conductive state, a discharge circuit from the output terminal Vout to the ground is formed via the coil 3 and the transistor 9. When the discharge circuit is formed, a discharge current flows through the discharge circuit to discharge the electric charge of the output terminal Vout to the ground. At this time, the current flowing through the coil 3 is equal to the drain current of the transistor 9.

  Since the discharge circuit includes a coil, the discharge current gradually increases in proportion to the time from the formation of the circuit. The discharge current value after t seconds at this time is represented by (Vo × t) ÷ L, where L is the inductance of the coil 3.

  The gradually increasing discharge current is limited at a certain level (see FIG. 2 (e)). The limit value at this time is determined by the constant current Idis supplied from the current source 111 and the mirror ratio of the transistor 9 and the transistor 112. In this embodiment, since the channel width and the channel length of the transistor 9 are set so that the drain current ratio of the transistor 112 and the transistor 9 is 1: N, the discharge current limit value is Idis × N.

  During the discharge period, a circuit that discharges the electric charge of the output terminal Vout to the ground is formed, while a circuit that supplies electric charge to the output terminal Vout is not formed, so that as shown in FIG. The output voltage Vo at the terminal Vout gradually decreases. As the output voltage Vo decreases, the duty signal output from the comparator 75 has a longer Lo time T_Lo and a shorter Hi time T_Hi, but the switch logic 77 outputs the duty signal during the discharge period. Since the pre-driver circuit 10 is not applied, the transistor 8 is non-conductive regardless of the modulation of the duty signal. On the other hand, the transistor 9 forms a discharge circuit.

  As described above, in the present embodiment shown in FIG. 1, since the switching transistor 9 forms a discharge circuit, it is not necessary to provide a separate circuit or element for discharging. Also, as shown in FIG. During the discharge operation period, the current discharged through the transistor 9 is limited to Idis × N, so that it is possible to prevent damage to the coils and transistors forming the discharge circuit. Furthermore, since only the discharge circuit having a path from the output terminal Vout to the ground is used, there is no charge transfer to the primary power source 1 or the like, and it is not necessary to take means for suppressing fluctuations in the primary voltage.

  In FIG. 1, the switching control circuit 7 shows a circuit example of a PWM modulation system, but this can be replaced by a PFM modulation system or other means for generating a switching duty signal.

  Further, although the transistor 8 is a PMOS transistor, it can be replaced by an NMOS transistor. Further, the MOS transistor may be replaced with a bipolar transistor.

  In this embodiment, the discharge control signal DISCHG is given from the outside of the DC / DC converter 6, but this can also be a signal generated internally. For example, when the input low voltage protection function is provided, the DC / DC converter 6 may stop the output operation and start the operation of discharging the output charge at the same time when the input voltage is lowered to a level where the protection operation is necessary. it can. Further, when the DC / DC converter 6 starts / stops operation according to a signal supplied from the outside, the discharge control signal DISCHG can also be used with this signal.

  The pre-driver 101 has been described as outputting a Hi level signal during the discharge operation. However, the pre-driver 101 is a three-state buffer that is used as an output float during the discharge operation, and a discharge is provided by providing a switch between the source and drain of the transistor 8. A structure in which the transistor 8 is sometimes turned off may be employed.

  The pre-driver 102 outputs a Lo / Hi level signal even during the discharge operation to open the switch 12 to insulate the gate of the transistor 9 from the output of the pre-driver 102. However, during the discharge operation, the pre-driver 102 If the three-state buffer is used as the output float, the output of the pre-driver 102 and the gate of the transistor 9 do not need to be insulated, and the switch 12 can be omitted.

  Furthermore, in the above embodiment, the current source 111 is a constant current source, but this may be a variable current source.

  By using a variable current source, the constant current Idis can be set dynamically to control the discharge current limit value dynamically. Similarly, by controlling the discharge current limit value by changing the mirror ratio between the discharge control circuit and the transistor 9, or by connecting a mirror circuit different from the mirror circuit composed of the transistor 112 and the transistor 9 in series. The control circuit 11 can be configured.

  FIG. 3 shows an example of a discharge control circuit that controls the limit value of the discharge current by changing the mirror ratio with the transistor 9. The discharge control circuit 11A in FIG. 3 includes a transistor 112 and a transistor 113 connected in parallel with the transistor 112. Similarly to the transistor 112, the transistor 113 has a common gate and drain connection. A switch 114 is disposed between the gate-drain connection of the transistor 113 and the gate-drain connection of the transistor 112, and a switch 115 is disposed between the gate-drain connection of the transistor 113 and the ground. Yes. The switches 114 and 115 are complementarily opened / closed.

  The transistor 112 is set to have a channel width and a channel length such that the drain current is 1: N (N is a mirror ratio) when the mirror circuit is configured with the transistor 9, and the transistor 113 has the same channel width as the transistor 112. The channel length is set.

  When the switch 114 is in the open state and the switch 115 is in the closed state, the constant current Idis provided by the current source 111 flows to the transistor 112, and the transistor 9 and the transistor 112 constitute a mirror circuit in which the mirror ratio is 1: N. Therefore, the limit value of the current flowing through the transistor 9 is Idis × N.

  When the switch 114 is closed and the switch 115 is open, the constant current Idis provided by the current source 111 flows through the transistors 112 and 113.

  In this case, since the transistors 112 and 113 having the same channel width and channel length are connected in parallel, the mirror ratio of the discharge control circuit 11A and the transistor is 2: N. The mirror ratio can be expressed as 1: (1/2) × N, and the limit value of the current flowing through the transistor 9 is (1/2) × Idis × N.

  As described above, the limit value of the transistor 9 can be controlled by changing the mirror ratio between the discharge control circuit 11A and the transistor 9. By providing a plurality of transistors connected in parallel with the transistor 112, the limit value of the transistor 9 can be set in several stages.

  FIG. 4 shows an example of a discharge control circuit in which a mirror circuit different from the mirror circuit composed of the transistor 112 and the transistor 9 is connected in series. The discharge control circuit 11B of FIG. 4 has a configuration in which a mirror circuit composed of a transistor 9 and a transistor 112 and a mirror circuit composed of a transistor 116 and a transistor 117 are connected in series to the mirror circuit. According to this, the mirror ratio can be increased relatively easily. For example, the mirror ratio of the mirror circuit composed of the transistor 9 and the transistor 112 is 1: N, and the mirror circuit composed of the transistor 116 and the transistor 117. When the mirror ratio is 1: M, the limit value of the transistor 9 is Idis × N × M. By adding the mirror circuit in series, it is possible to set the Idis value required for setting the limit value of the transistor 9 to be as small as the mirror ratio of the circuit to which the circuit is added, so that the current consumption of the circuit can be reduced. it can.

  In addition, when the capacitance value of the output stabilizing capacitor 4 is large, it is necessary to consider heat generated during discharge. During the discharge period, a power loss represented by P = Vo × Idis occurs in the discharge circuit in a unit time, and the DC / DC converter 6 is burned out due to a temperature rise caused by the amount of heat, or in peripheral components. In order to prevent the deterioration of the characteristics of certain capacitors 2 and 4 and coil 3, the overheat protection function that the DC / DC converter normally has is made effective during the discharge operation, and the temperature of the DC / DC converter reaches the protection level. In some cases, it is necessary to take measures such as lowering the discharge current value to lower the amount of heat generated per unit time.

<Second Embodiment>
FIG. 5 shows a switching power supply circuit according to the second embodiment of the present invention. As shown in the figure, the present embodiment is different from the first embodiment shown in FIG. 1 only in the configuration of the discharge control circuit 21. Therefore, the same parts as those in FIG.

The discharge control circuit 21 in this embodiment includes a transconductance amplifier 211, a resistor 212, a reference voltage source 213, and an amplifier 214. The transconductance amplifier 211 amplifies the potential difference between the drain and source of the transistor 9, converts this to a current, and outputs the current. The current output from the transconductance amplifier 211 is converted into a voltage by the resistor 212 and applied to the amplifier 214. The amplifier 214 is applied with the converted voltage signal and a predetermined reference voltage Vref ₂ that is the output of the reference voltage source 213. The output of the amplifier 214 is connected to the gate of the transistor 9 through the switch 13. Here, since the switch 12 is open and the switch 13 is closed during the discharging operation, the gate of the transistor 9 is controlled by the output voltage of the amplifier 214. In the mode in which the amplifier 214 is driving the transistor 9, the discharge control circuit 21 and the transistor 9 constitute a feedback circuit. The polarities of the input terminals of the transconductance amplifier 211 and the amplifier 214 are set so that the feedback circuit becomes a negative feedback circuit. When the output current of the transconductance amplifier 211 and the voltage generated by the resistor 212 are Vdis, the resistance value of the resistor 212 is R212, the transconductance of the transconductance amplifier 211 is Gm, and the on-resistance of the transistor 9 is Ron, the discharge current limit value Idis ₂ is expressed as Idis ₂ = Vdis / (Ron × Gm × R212) from Idis ₂ × Ron × Gm × R212 = Vdis. Here, when the discharge control circuit 21 and the transistor 9 are stable as a negative feedback circuit and are limited to the discharge current limit value Idis ₂ , the reference voltage Vref ₂ and the voltage Vdis given by the reference voltage source 213 are equal. , Idis ₂ = Vref ₂ / (Ron × Gm × R212).

  Next, the operation of the switching power supply circuit according to this embodiment configured as described above will be described with reference to the drawings. FIG. 6 is a waveform diagram showing waveforms at various parts accompanying the operation of the switching power supply circuit shown in FIG. The waveforms of the respective parts shown in FIG. 2 are different from each other in the waveform of the gate voltage of the transistor 9 during the output discharge operation period due to the difference in the configuration of the discharge control circuit. In FIG. 6, (a) is the gate voltage of the transistor 8, (b) is the gate voltage of the transistor 9, (c) is the current of the coil 3 (the direction toward the output terminal Vout is positive), and (d) is the output. The voltage Vo, (e) is the discharge control signal, (f) is the voltage generated by the current output from the transconductance amplifier 211 in the discharge control circuit 21 and the resistor 212, and (g) is the drain current (drain) of the transistor 9. The direction from 1 to the coil 3 is positive).

  As shown in the figure, the waveform during the normal operation period is the same as the operation waveform shown in FIG.

On the other hand, during the output discharge operation period, the negative feedback circuit composed of a discharge control circuit 21 and the transistor 9, transistor 9 drain - a gate voltage when the source current IDS is limit Idis ₂ smaller than transistor 9 The on-resistance of the transistor 9 is reduced and the drain-source current IDS is increased. When the drain-source current IDS is larger than the limit value Idis ₂ , the gate voltage of the transistor 9 is lowered, the on-resistance is increased, and the drain-source current IDS is reduced.

More specifically, immediately after the start of the discharge operation, the discharge current flowing through the coil 3 increases in proportion to the time from 0 A, so that the drain-source current IDS of the transistor 9 becomes smaller than the limit value Idis ₂ and the discharge control circuit 21 raises the gate voltage of the transistor 9 to the Hi level. As a result, the gate voltage rises, the transistor 9 becomes conductive, and a discharge circuit is formed, so that discharge is started from the output terminal Vout.

As the discharge current increases and gradually approaches the limit value Idis ₂ , the gate voltage of the transistor 9 also gradually decreases to a certain value. When the discharge current is the limit value Idis ₂ and the gate voltage of the transistor 9 is VGS, the following relationship is established.

但し、Ｌはトランジスタ９のチャネル長、Ｗはチャネル幅、μｎはトランジスタ９のキャリア移動度、Ｃｏｘはトランジスタ９の単位面積あたりのゲート容量、Ｖｔｈはトランジスタ９の閾値である。 [Equation 2]

However, L is the channel length of the transistor 9, W is the channel width, μn is the carrier mobility of the transistor 9, Cox is the gate capacitance per unit area of the transistor 9, and Vth is the threshold value of the transistor 9.

  From this, the gate voltage VGS is obtained as follows.

[Equation 3]

  Thus, in the embodiment shown in FIG. 5, the discharge current is limited by observing the discharge current and driving the gate of the transistor 9 in the discharge path.

  In the embodiment shown in FIG. 5, the discharge current value is observed from the potential difference between the drain and the source of the transistor 9, but the current value is observed anywhere in the discharge path between the output terminal Vout and the ground. May be. The current observation means can be replaced with other means. For example, if a current sense resistor is provided in the discharge path, the voltage similar to that shown in FIG. 5 can be realized by amplifying and outputting the voltage between the sense resistors to the gate of the transistor 9 via the amplifier circuit. .

  INDUSTRIAL APPLICABILITY The present invention can be effectively used in the industrial field in which a power supply device having a processor or the like as a load is manufactured and sold.

1 Primary power supply 2, 4 Capacitor 3 Coil 5 Load 8, 9, 112, 113, 116, 117 Transistors 11, 21 Discharge control circuit 12, 13 Switch Vout Output terminal Vo Output voltage DISCHG Discharge control signal

Claims (4)

In the switching mode, output signals output from the respective pre-drivers are alternately turned on / off by a synchronous rectification method, and one end side is a switching element connected to the primary power source, and one end side is grounded A predetermined transistor obtained via a coil and an output terminal from between the first transistor and the second transistor connected in series via the other ends. A switching power supply circuit for applying an output voltage to a load,
A discharge control circuit that operates based on a discharge control signal indicating the discharge mode and controls the second transistor to flow a predetermined constant current in a discharge mode in which the output residual charge is discharged after the switching mode ends. And having
The discharge control circuit is configured such that the second transistor flows a predetermined constant current by forming a current mirror circuit with the second transistor,
Further, a first switch means is provided between the pre-driver that outputs an output signal to the second transistor of the pre-drivers and the second transistor, and the transistor of the discharge control circuit and the second driver The second switch means is provided between the pre-driver and the pre-driver that outputs an output signal to the second transistor by opening the first switch means with the discharge control signal in the discharge mode. The mirror circuit is formed by the second transistor by shutting off the supply of the output signal to the second transistor and simultaneously turning on the second switch means with the discharge control signal. A switching power supply circuit. In the switching power supply circuit according to claim 1,
A switching power supply circuit, wherein a variable current source is connected to the current mirror circuit. In the switching power supply circuit according to claim 1,
A switching power supply circuit characterized in that the current mirror circuit can select a plurality of mirror ratios. In the switching power supply circuit according to claim 1,
The switching power supply circuit, wherein the current mirror circuit includes a plurality of current mirror circuits connected in series.

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