JP6247169B2 - Optical receiver circuit and optical receiver - Google Patents

Description

  The present invention relates to an optical receiver circuit and an optical receiver equipped with the optical receiver circuit, for example, an optical receiver circuit including a chip capacitor constituting a bias separation circuit.

  Generally, in an optical communication system, an optical receiver that converts an optical signal into an electric signal is used. The optical receiver includes, for example, an optical receiver circuit including a photodiode (PD) that performs optical-current conversion on an optical signal transmitted from a transmission path (optical fiber), and a voltage obtained by converting the current signal converted by the optical receiver circuit. A transimpedance amplifier (hereinafter referred to as “TIA: Transimpedance Amplifier”) that converts the signal into a signal, amplifies the signal, and outputs the signal is included. For example, the following Patent Document 1 discloses a conventional optical receiver.

FIG. 4 is a diagram showing a configuration of a conventional optical receiver disclosed in Patent Document 1. In FIG.
As shown in the figure, in an optical receiving circuit 500 in a conventional optical receiver, one electrode (for example, an anode) of a photodiode 501 formed on a semiconductor chip 506 is connected to a load LD such as TIA (in the figure, a load LD). In the case of connecting the LD to the resistor RL through the electric line 502, it is necessary to connect the bias separation circuit 504 to the other electrode (for example, cathode) of the photodiode 501. Here, the bias separation circuit 504 is a circuit for grounding the AC component of the signal of the photodiode 501 and guiding the DC component to the external bias application terminal 503, and is realized by combining a capacitor, a capacitor, and a resistor. .

  On the other hand, as disclosed in Patent Document 2 and Non-Patent Document 1, an optical receiver that converts a multi-channel optical signal into a multi-channel electrical signal is also well known. In such a multi-channel optical receiver, it is necessary to provide a bias separation circuit for each photodiode constituting each channel.

  Many conventional multi-channel optical receivers use a PIN photodiode as a light receiving element. In such a multi-channel optical receiver, the reverse bias voltage (about 2 to 10 V) of the PIN structure photodiode and the withstand voltage (about 5 V to 10 V) required for the capacitor and resistor for the bias separation circuit are relatively high. Since the values are close to each other, the capacitor and the resistor for the bias separation circuit are formed on the same semiconductor substrate as the photodiode as described in Patent Document 1, or the same semiconductor as that of the TIA chip as described in Non-Patent Document 2. It was possible to reduce the size of the optical receiver by forming it on the substrate.

JP 2012-244293 A JP 2013-5014 A

S. Tsunashima et al., “Silica-based, compact and variable-optical attenuator integrated coherent receiver with stable optoelectronic coupling system” 2012, Optics Express, Vol. 20, Issue 24, pp. 27174-27179. TEXAS INSTRUMENTS data sheet, “11.3-Gbs Limiting Transimpedance Amplifier With RSSI”, Internet <URL: http://www.tij.co.jp/product/jp/onet8551t>.

  Incidentally, in recent years, in order to increase the capacity of an optical communication system and improve the communication speed, light using an avalanche photodiode (hereinafter referred to as “APD: avalanche photodiode”) instead of a PIN structure photodiode as a light receiving element. The number of receivers is increasing. An APD is an element that has higher light reception sensitivity and can operate at a higher speed than a photodiode having a PIN structure.

However, when APD is used for an optical receiver, there are the following problems.
As described above, the photodiode having the PIN structure requires a reverse bias voltage of about 2 to 10 V, but the APD needs a reverse bias voltage of about 20 V to 50 V, which is higher than that. For this reason, it is not easy to form a capacitor and a resistor for a bias separation circuit on the same semiconductor substrate as that of APD or TIA as in the case of a photodiode having a PIN structure.

  For example, in order to manufacture a high-capacity capacitor with a smaller area on the same semiconductor substrate as the APD, it is necessary to thin the insulating layer between the electrodes of the capacitor. However, if the insulating layer is thinned, the withstand voltage is lowered. . Conversely, if the insulating layer between the capacitor electrodes is made thick to withstand the reverse bias voltage of the APD, the chip area must be increased in order to obtain a high-capacity capacitor, which is not practical.

  Moreover, even if a capacitor for a bias separation circuit or the like is formed in the TIA chip as in Non-Patent Document 1, since the withstand voltage of the capacitor or the like is about 5 to 10V, the reverse of the APD of about 20V to 50V. A bias voltage cannot be applied to the TIA chip.

  Therefore, when a photodiode having a high reverse bias voltage such as an APD is used in an optical receiver circuit, a high-breakdown-voltage chip capacitor or chip for a bias separation circuit is provided separately from the semiconductor chip or TIA chip on which the photodiode is formed. It is necessary to provide resistance.

  However, as described above, in a multi-channel optical receiver, the number of bias separation circuits increases with the number of APDs. Therefore, if the bias separation circuit is realized by a chip capacitor or a chip resistor, the mounting area of the optical receiver is reduced. It gets bigger. For example, as shown in FIG. 5, in a conventional multi-channel optical receiver, a plurality of chip capacitors 606 for bias separation circuits are provided together with a semiconductor chip 601 and a TIA chip 602 on which a photodiode 603 is formed. Since it is mounted on the mounting surface 700, there is a problem that the area of the mounting surface 700 is increased and it is difficult to reduce the size of the optical receiver.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce the size of an optical receiver including a chip capacitor constituting a bias separation circuit.

  An optical receiver circuit (10) according to the present invention includes a submount (11) and a first wiring pattern (10C) extending from a first main surface (10A) of the submount to a side surface (10C) of the submount. 101_1 to 101_4) and second wiring patterns (102_1 to 102_5), third wiring patterns (103_1 to 103_4) formed on the first main surface of the submount, and the first main surface of the submount. Photodiodes (PD1 to PD4) disposed on the anode electrode (A_1 to A_4) are connected to the first wiring pattern, and cathode electrodes (K_1 to K_4) are connected to the third wiring pattern; It is disposed on the first main surface of the mount, one electrode is connected to the third wiring pattern, and the other electrode is connected to the second wiring pattern. Characterized in that it comprises a chip capacitor (CB1 to CB4) that.

  The optical receiving circuit includes a resistor (Rb1 to Rb4) formed in a thin film on a second main surface (10B) opposite to the first main surface of the submount, and the second main surface of the submount. A second wiring pattern (108_1 to 108_4) formed on the surface and connected to one end of the resistor, and the second main pattern of the submount from the side surface on which the first wiring pattern of the submount is formed. A fifth wiring pattern (109_1 to 109_4) extending on the surface and connected to the other end of the resistor, and formed through the submount, the fourth wiring pattern and the third wiring pattern Further, through vias (105_1 to 105_4) to be connected may be further provided.

  In the optical receiver circuit, a plurality of the photodiodes are arranged, a plurality of the first wiring patterns, the second wiring patterns, and the third wiring patterns are formed corresponding to the photodiodes, and the chip capacitor is formed. A plurality of corresponding third wiring patterns are arranged.

  In the optical receiver circuit, the plurality of photodiodes may be formed on one semiconductor chip (17), and the semiconductor chip may be flip-chip mounted on the first main surface of the submount.

  The optical receiver circuit includes a plurality of resistors (Rb1 to Rb1) formed on the second main surface (10B) opposite to the first main surface of the submount so as to correspond to the photodiodes. Rb4), a plurality of fourth wiring patterns (108_1 to 108_4) formed on the second main surface of the submount and respectively connected to one end of the corresponding resistor, and the first wiring of the submount A fifth wiring pattern (109_1 to 109_4) extending from the side surface on which the pattern is formed to the second main surface of the submount and connected to the other end of the corresponding resistor, and the submount And a plurality of through vias (105_1 to 105_4) that connect the fourth wiring pattern and the corresponding third wiring pattern, respectively.

  In the optical receiver circuit, the plurality of photodiodes are arranged along the first side (11A) of the first main surface on the first main surface, and the plurality of second wiring patterns are arranged on the first main surface. The main surface and the side surface are formed along the first side, and the plurality of first wiring patterns are formed between the second wiring patterns on the first main surface and the side surface, respectively. The three wiring patterns are formed on the first main surface between the second wiring patterns so as to face the first wiring pattern, and the chip capacitor is disposed on the other electrode of the plurality of chip capacitors. The second wiring patterns sandwiching the third wiring pattern may be connected to each other via bonding wires (107).

  In the optical receiver circuit, the photodiode may be an avalanche photodiode.

  An optical receiver according to the present invention is supported by a plate-shaped first member (20) made of metal, a second member (50) provided on the first member, and the second member. An optical signal output unit (60) that outputs an optical signal in a direction (Q) parallel to the plane of one member, the optical receiver circuit, and an optical output surface (60A) from which the optical signal of the optical output unit is output A fixing member (14) for fixing the optical receiver circuit to the optical output unit so as to face the first main surface of the submount; and a third member (30) provided on the first member; A TIA chip (40) supported by the third member and having a transimpedance amplifier formed thereon, and the TIA chip has a plurality of electrodes on a surface (40A) opposite to the surface in contact with the third member. A pattern (41) is formed, and the optical receiver circuit is connected to the submount. The surface (10B) opposite to the first main surface faces the side surface (40C) of the TIA chip, and the side surface (10C) on which the first wiring pattern and the second wiring pattern of the submount are formed. ) Are arranged in the same direction as the surface (40A) on which the electrode pattern of the TIA chip is formed, and the first wiring pattern and the second wiring pattern of the optical receiver circuit are bonded wires (70). Are connected to the electrode patterns of the TIA chip, respectively.

  In the above description, the reference numerals with parentheses merely exemplify what are included in the concept of the constituent elements with the reference numerals in the drawings.

  According to the present invention, it is possible to reduce the size of the optical receiver.

FIG. 1 is a diagram showing a circuit configuration of an optical receiver circuit according to an embodiment of the present invention. FIG. 2A is a diagram schematically illustrating a planar structure of the optical receiver circuit according to the present embodiment. FIG. 2B is a diagram schematically illustrating a planar structure of the optical receiver circuit according to the present embodiment. FIG. 2C is a diagram schematically illustrating a planar structure of the optical receiver circuit according to the present embodiment. FIG. 3A is a diagram schematically illustrating a planar structure of an optical receiver including the optical receiver circuit according to the present embodiment. FIG. 3B is a diagram schematically illustrating a planar structure of an optical receiver including the optical receiver circuit according to the present embodiment. FIG. 4 is a diagram illustrating a circuit configuration example of a conventional optical receiving circuit. FIG. 5 is a diagram schematically showing a planar structure of a conventional multi-channel optical receiver.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

≪Circuit configuration of optical receiver circuit≫
FIG. 1 is a diagram showing a circuit configuration of an optical receiver circuit according to an embodiment of the present invention.
The optical receiver circuit 10 shown in the figure converts an optical signal sent from a transmission line (optical fiber) into an electric signal and supplies it to an amplifier circuit such as TIA. The optical receiver circuit 10 can be realized as an optical receiver by combining with an optical output unit such as a planar lightwave circuit (PLC), a TIA, or the like.

  Specifically, the optical receiving circuit 10 includes a plurality of photodiodes PD1 to PD4, a plurality of capacitors Cb1 to Cb4, resistors Rb1 to Rb4, signal electrodes SP_1 to SP_4, ground electrodes GP_1 to GP_5, and a bias electrode BP_1. To BP_4.

  The photodiodes PD1 to PD4 are light receiving elements that perform optical-current conversion on an optical signal output from a planar lightwave circuit or the like. For example, the photodiodes PD1 to PD4 are APDs. The photodiodes PD <b> 1 to PD <b> 4 are formed as an array on one semiconductor substrate, for example, and are configured as one semiconductor chip 17.

  In the present embodiment, the case where the optical receiver circuit 10 includes four photodiodes PD1 to PD4 will be described as an example, but the number of photodiodes included in the optical receiver circuit 10 is not particularly limited.

  The signal electrodes SP_1 to SP_4 are external electrodes for outputting electric signals generated by the photodiodes PD1 to PD4 to TIA or the like. As shown in FIG. 1, the signal electrode SP_1 is connected to the anode electrode A_1 of the photodiode PD1. Similarly, the signal electrodes SP_2 to SP_4 are connected to the anode electrodes A_2 to A_4 of the corresponding photodiodes PD2 to PD4, respectively.

  The ground electrodes GP_1 to GP_5 are external electrodes for connecting to the ground potential. As shown in FIG. 1, the ground electrodes GP_1 to GP_5 are commonly connected to the ground wiring 13.

  The bias electrodes BP_1 to BP_4 are electrodes for inputting a bias voltage supplied to the photodiodes PD1 to PD4.

  Capacitors Cb1 to Cb4 and resistors Rb1 to Rb4 constitute a bias separation circuit for grounding the AC component of the signal from photodiodes PD1 to PD4 and guiding the DC component to the bias application terminal. Specifically, as shown in FIG. 1, one end of the capacitor Cb1 is connected to the cathode electrode K_1 of the photodiode PD1 and one end of the resistor Rb1, and the other end of the capacitor Cb1 is connected to the ground wiring 13. The other end of the resistor Rb1 is connected to the bias electrode BP_1. Thereby, the capacitor Cb1 and the resistor Rb1 function as a bias separation circuit that grounds the cathode electrode K_1 of the photodiode PD1 in an alternating manner and determines the DC potential of the cathode electrode K_1 according to the potential of the bias electrode BP. Similarly, the capacitor Cb2 and the resistor Rb2, the capacitor Cb3 and the resistor Rb3, the capacitor Cb4 and the resistor Rb4 are also connected to the cathode electrode K_1, the bias electrodes BP_2 to BP_4, and the ground wiring 13 of the photodiode PD1, and the corresponding photodiodes are connected. Each functions as a bias separation circuit for PD2 to PD4.

≪Specific structure of optical receiver circuit≫
2A to 2C show the structure of the optical receiver circuit 10 according to the present embodiment.
2A schematically illustrates a planar structure of the optical receiver circuit 10 as viewed from the first main surface 10A side, and FIG. 2B illustrates a plane of the side surface 10C of the optical receiver circuit 10 as viewed from the direction P of FIG. 2A. The structure is schematically shown, and FIG. 2C schematically shows a planar structure viewed from the second main surface 10B side of the optical receiver circuit 10. In the following description, the first main surface 10A of the optical receiver circuit 10 may also be referred to as “front surface 10A”, and the second main surface 10B of the optical receiver circuit 10 may also be referred to as “back surface 10B”.

  2A to 2C, the optical receiver circuit 10 includes a semiconductor chip 17 in which a plurality of photodiodes PD1 to PD4 are formed on a submount 11 on which various wiring patterns and resistors Rb1 to Rb4 are formed. And a plurality of capacitors Cb1 to Cb4 are mounted.

The submount 11 is a substrate for mounting various components for optical communication. The submount 11 is made of, for example, a ceramic substrate. Examples of the ceramic material for the substrate include aluminum nitride (AIN) and aluminum oxide (Al ₂ O ₃ ). The submount 11 may be a multilayer substrate or a single layer substrate.

  A plurality of wiring patterns are formed on the front surface 10A, the back surface 10B, and the side surface 10C of the submount 11. Each wiring pattern is made of, for example, a metal material containing gold (Au) as a main component.

  Specifically, as shown in FIG. 2A, wiring patterns 101_1 to 101_4, wiring patterns 102_1 to 102_5, and wiring patterns 103_1 to 103_4 are formed on the surface 10A of the submount 11. Further, as illustrated in FIG. 2B, wiring patterns 101_1 to 101_4, wiring patterns 102_1 to 102_5, and wiring patterns 109_1 to 109_4 are formed on the side surface 10C of the submount 11. Further, as shown in FIG. 2C, wiring patterns 108_1 to 108_4, wiring patterns 109_1 to 109_4, and a wiring pattern 102_6 are formed on the back surface 10B of the submount.

  The wiring patterns 102_1 to 102_4 are formed in parallel to each other along the side 11A on the surface 10A and the side surface 10C of the submount 11. Each of the wiring patterns 102_1 to 102_4 is formed to extend from the surface 10A of the submount 11 to the side surface 10C. In other words, the wiring patterns 102_1 to 102_4 extend on the surface 10A of the submount 11 from the side 11A of the surface 10A toward the side 11B in a direction orthogonal to the side 11A, and the side 11A is shared with the surface 10A. The side 11C extends from the side 11A toward the side 11C on the side surface 10C of the submount 11. The wiring patterns 102_1 to 102_5 function as the ground wiring 13 described above.

  In addition, a part of the wiring patterns 102_1 to 102_5 formed on the side surface 10C forms electrodes (pads) to be connected to TIA chips and the like to be described later by bonding wires, and functions as the above-described ground electrodes GP_1 to GP_5, respectively. . Furthermore, the wiring patterns 102_1 to 102_5 are connected to the wiring pattern 102_6 on the back surface 10B through through vias (through holes) 103 that penetrate the submount 11 from the front surface 10A to the back surface 10B.

  Note that the through via 103 and through vias 105_1 to 105_4 described later may be filled with a metal material (for example, gold) so as to fill the through hole, or a metal material may be formed only on the side surface of the through hole. good.

  The wiring patterns 101_1 to 101_4 are respectively formed between the wiring patterns 102_1 to 102_5 in a plan view on the surface 10A and the side surface 10C on the submount 11. Each of the wiring patterns 101_1 to 101_4 is formed to extend from the surface 10A of the submount 11 to the side surface 10C. In other words, the wiring patterns 102_1 to 102_4 extend on the surface 10A of the submount 11 from the side 11A of the surface 10A toward the side 11B, and the side 11A is a side common to the surface 10A. The side surface 10C extends from the side 11A toward the side 11C. The length in the Y direction on the surface 10A of the wiring patterns 101_1 to 101_4 is shorter than the length in the Y direction of the wiring patterns 102_1 to 102_5.

  In addition, part of the wiring patterns 101_1 to 101_4 formed on the side surface 10C forms electrodes (pads) for connecting to TIA chips and the like to be described later by bonding wires, and functions as the above-described signal electrodes SP_1 to SP_4. .

  The wiring patterns 103_1 to 103_4 are formed between the wiring patterns 102_1 to 102_5 on the surface 10A so as to face the wiring patterns 101_1 to 101_4, respectively. As shown in FIG. 2A, the length of each wiring pattern 102_1 to 102_4 in the Y direction is shorter than the length of each wiring pattern 102_1 to 102_5 in the Y direction.

  As shown in FIG. 2A, the semiconductor chip 17 on which the photodiodes PD1 to PD4 are formed, the capacitors Cb1 to Cb4, and the fixing member 14 are mounted on the surface 10A of the submount 11.

  The fixing member 14 is a member for fixing the optical receiving circuit 10 to an optical output unit described later, and is made of, for example, a transparent glass material. The fixing member 14 only needs to fix the optical receiving circuit 10 to the optical output unit, and the position on the submount 11 on which the fixing member 14 is mounted is not particularly limited.

  The photodiodes PD1 to PD4 are formed in an array along the longitudinal direction (X direction) of the semiconductor chip 17. As shown in FIG. 2A, the semiconductor chip 17 is arranged on the surface 10A so as to overlap with a part of each of the wiring patterns 101_1 to 101_4 and a part of each of the wiring patterns 103_1 to 103_4 in a plan view. . Specifically, the semiconductor chip 17 has the wiring patterns 101_1 to 101_4 and 103_1 to 103_4 corresponding to the anode electrodes A_1 to A_4 and the cathode electrodes K_1 to K_4 of the photodiodes PD1 to PD4 formed on the back surface. By being connected to each other via solder (bump), flip chip mounting is performed on the surface 10A of the submount 11. At this time, the anode electrode A_1 of the photodiode PD1 is connected to the wiring pattern 101_1, and the cathode electrode K_1 of the photodiode PD1 is connected to the wiring pattern 103_1. Similarly, the anode electrodes A_2 to A_4 of the photodiodes PD2 to PD4 are respectively connected to the corresponding wiring patterns 101_2 to 101_4, and the cathode electrodes K_2 to K_4 of the photodiodes PD2 to PD4 are respectively connected to the corresponding wiring patterns 103_2 to 103_4. ing.

  The capacitors Cb1 to Cb4 are arranged on the wiring patterns 103_1 to 103_4 in a plan view on the surface 10A of the submount 11, respectively. The capacitors Cb <b> 1 to Cb <b> 4 are, for example, chip capacitors (chip capacitors) having an upper and lower surface electrode structure in which electrodes are formed on one surface and a surface opposite to the one surface. The capacitors Cb1 to Cb4 have a withstand voltage that can withstand the reverse bias voltage of the photodiodes PD1 to PD4. For example, when the photodiodes PD1 to PD4 are APDs, the capacitors Cb1 to Cb4 have a withstand voltage that can withstand a reverse bias voltage of about 20V to 40V.

  As shown in FIG. 2A, the capacitor Cb1 has one surface on which an electrode is formed facing the wiring pattern 103_1 and connected via solder, and the other surface on which the electrode is formed via a bonding wire 107. The wiring pattern 102_1 and the wiring pattern 102_2 sandwiching the wiring pattern 103_1 are connected to each other. Similarly, in the capacitors Cb2 to Cb4, one surface on which the electrodes are formed is connected to the corresponding wiring patterns 103_2 to 103_4 via solder, and the other surface on which the electrodes are formed corresponds to the corresponding wiring pattern 102_2. -102_5 and the bonding wire 107, respectively.

  The bonding wire 107 is made of, for example, a metal material whose main component is gold. 2A shows a case where the wiring patterns 102_1 to 102_4 and the capacitors Cb1 to Cb4 are connected by two bonding wires 107, respectively, the wiring patterns 102_1 to 102_4 and the capacitors Cb1 to Cb4 are respectively connected. There is no particular limitation on the number of bonding wires 107 to be connected.

  The resistors Rb1 to Rb4 are formed on the back surface 10B of the submount 11 as shown in FIG. 2C. The resistors Rb1 to Rb4 are thin film resistive elements formed on the back surface 10B, for example, and are formed by patterning a material mainly composed of tantalum nitride into a thin film on the back surface 10B, for example.

  The wiring patterns 108_1 to 108_4 are formed on the back surface 10B of the submount 11. For example, as illustrated in FIG. 2C, the wiring pattern 108_1 is connected to one end of the resistor Rb1, and is connected to the wiring pattern 103_1 through the through via 105_1. Similarly, the wiring patterns 108_2 to 108_4 are respectively connected to one ends of the corresponding resistors Rb2 to Rb4, and are connected to the wiring patterns 103_2 to 103_4 through the through vias 105_2 to 105_4, respectively.

  The wiring pattern 109_1 is formed to extend from the side surface 10C of the submount 11 to the back surface 10B, and is connected to the other end of the resistor Rb1. Specifically, as shown in FIGS. 2B and 2C, the wiring pattern 109_1 extends from the side facing the side 11C toward the side 11C on the back surface 10B of the submount 11, and the side 11C. Is formed extending from the side 11C toward the side 11A on the side surface 10C of the submount 11 having a side common to the back surface 10B. The same applies to the wiring patterns 109_2 to 109_4.

  In addition, part of the wiring patterns 109_1 to 109_4 formed on the side surface 10C functions as the above-described bias electrodes BP_1 to BP_4.

<< Optical Receiver with Optical Receiver Circuit According to the Present Invention >>
3A and 3B show an example of the configuration of an optical receiver including the optical receiver circuit according to the present embodiment. 3A schematically shows a planar structure of the optical receiver 1 on which the optical receiver circuit 10 is mounted, and FIG. 3B schematically shows a planar structure of the side surface of the optical receiver 1 viewed from the direction S in FIG. 3A. Has been shown.

  As shown in FIGS. 3A and 3B, the optical receiver 1 includes a base material 20, a supporting member 30, a supporting member 50, an optical output unit 60, an optical receiving circuit 10, a TIA chip 40, and a TIA. Chip capacitors Ct1 to Ct4 for the chip 40 are provided. In FIG. 3B, illustration of the chip capacitors Ct1 to Ct4 for the TIA chip 40 is omitted.

  The base material 20 is formed of a metal material whose main component is, for example, a copper tungsten alloy (Cu—W alloy), nickel (Ni), or the like. The base material 20 is formed as a box-shaped housing, for example, and the support members 30 and 50 are mounted on a plate-shaped bottom surface in the housing. 3A and 3B, a part of the base material 20 corresponding to the plate-like bottom surface of the housing is illustrated, and illustration of the side surface and the like of the housing is omitted.

  The support member 30 and the support member 50 are fixed to the bottom surface of the base material 20. The support member 30 is a member for supporting the TIA chip 40 and is made of a metal material having a high thermal conductivity such as a copper tungsten alloy. The support member 50 is a member for supporting the light output unit 60, and is made of, for example, a metal material.

  The TIA chip 40 is a semiconductor integrated circuit (IC) realized by forming an amplifier circuit such as a TIA for inputting an electric signal generated by an optical receiver circuit and other peripheral circuits, for example, on one semiconductor substrate. It is. The TIA chip 40 is fixed on the support member 30.

  A plurality of electrodes (pads) 41 are formed on the upper surface 40A opposite to the surface of the TIA chip 40 that contacts the support member 30. As shown in FIGS. 3A and 3B, the plurality of electrodes 41 are connected to the corresponding signal electrodes SP_1 to SP_4 and ground electrodes GP_1 to GP_5 of the optical receiving circuit 10, chip capacitors for TIA, and the like by bonding wires 70, respectively. Yes. Similar to the bonding wire 107, the bonding wire 70 is made of, for example, a metal material containing gold as a main component.

  The optical output unit 60 guides an optical signal to the photodiodes PD <b> 1 to PD <b> 4 of the optical receiving circuit 10. The light output unit 60 includes, for example, a planar lightwave circuit (PLC) 61 and a microlens array 62. The optical signal transmitted through the optical waveguide 610 in the planar lightwave circuit (PLC) 61 is collected by the microlens array 62 and guided to the photodiodes PD1 to PD4. As shown in FIG. 3B, the light output unit 60 is fixed on the support member 50 so that, for example, the direction Q in which the optical signal is output and the bottom surface of the base member 20 are parallel.

  The optical receiver circuit 10 is disposed between the optical output unit 60 and the TIA chip 40 in plan view. Specifically, as shown in FIGS. 3A and 3B, the front surface 10A of the submount 11 and the light output surface 60A of the microlens array 62 face each other, and the back surface 10B of the submount 11 and the side surface 40C of the TIA chip 40. And the side surface 10C of the submount 11 and the upper surface 40A of the TIA chip 40 are fixed to the light output unit 60 via the fixing member 14 so that they face the same direction.

  The back surface 10B of the optical receiver circuit 10, the TIA chip 42, and the support member 30 can be brought close to the extent that the back surface 10B of the optical receiver circuit 10, the side surface 40C of the TIA chip 42, and the support member 30 do not contact each other.

  Further, the heights of the support members 30 and 50 in the Z direction are adjusted so that the wiring patterns 101_1 to 101_4 and the like on the side surface 10C of the optical receiving circuit 10 can be bonded to the electrode 41 on the TIA chip 40. Yes. For example, the heights in the Z direction of the support members 30 and 50 are adjusted so that the heights of the side surface 10C of the optical receiver circuit 10 and the upper surface 40C of the TIA chip 40 are equal.

As described above, like the optical receiver circuit according to the present embodiment, the photodiode and the chip capacitor for the bias separation circuit are mounted on the surface of the submount, and various electrodes for bonding to the TIA chip are mounted on the side surface of the submount. The mounting area of the optical receiver can be reduced by forming the optical receiver.
That is, in the optical receiver circuit according to the present embodiment, the back surface of the submount faces the side surface of the TIA chip, the front surface of the submount faces the light output surface of the light output unit, and various electrodes of the submount FIG. 5 shows an example of mounting the optical output unit and the TIA chip on the base (housing) of the optical receiver so that the formed side surface and the upper surface on which the TIA chip electrode is formed are oriented in the same direction. Compared to the case where the mounting surface on which the semiconductor chip and the chip capacitor on which the photodiode is formed and the mounting surface of the TIA chip are mounted in the same direction as in the conventional optical receiver, the optical receiver The mounting area of the optical receiver can be reduced, and the optical receiver can be downsized.

  In particular, in the multi-channel optical receiver circuit using an APD having a high reverse bias voltage as described above, even when a high-breakdown-voltage chip capacitor or the like for a bias separation circuit is used, the optical receiver circuit according to the present invention is used. Therefore, an increase in mounting area can be suppressed, and downsizing of the optical receiver can be expected.

  Furthermore, according to the optical receiver circuit according to the present embodiment, even when a resistor for the bias separation circuit is required, the resistor is formed on the back surface instead of the front surface of the submount. It becomes possible to form. In addition, since the thickness of the optical receiving circuit can be suppressed by realizing the resistance for the bias separation circuit with a thin film resistor formed on the submount, the resistance for the bias separation circuit is necessary. However, there is no risk of hindering downsizing of the optical receiver.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, in the above embodiment, the case where a plurality of photodiodes (multi-channel optical receiver circuit) are mounted on the optical receiver circuit is illustrated, but the present invention is not limited to this, and the photodiode mounted on the optical receiver circuit is as follows. One piece may be sufficient. In this case, the capacitors (Cb1 to Cb4) and the resistors (Rb1 to Rb4) for the bias separation circuit are also one.

  In the above embodiment, the photodiodes PD1 to PD4 are APDs. However, the present invention is not limited to this, and the photodiodes PD1 to PD4 may be PIN structure photodiodes or other structure photodiodes. The same action and effect are exhibited.

  In the above embodiment, the photodiodes PD1 to PD4 are formed on one semiconductor chip 17, but the photodiodes PD1 to PD4 may be formed on separate semiconductor chips. A plurality of semiconductor chips on which the photodiodes are formed may be mounted on the submount.

  Further, in the above embodiment, the case where the resistors Rb1 to Rb4 are provided as the bias separation circuit is illustrated, but only the capacitors Cb1 to Cb4 are provided as the bias separation circuit, and the resistors Rb1 to Rb4 may not be provided. In this case, the wiring pattern 108_1 and the wiring pattern 109_1 shown in FIG. 2C may be formed as one continuous wiring pattern. The same applies to the wiring patterns 108_2 to 108_4 and the wiring patterns 109_2 to 109_4.

  Further, in the above embodiment, the case where the wiring patterns 102_1 to 102_5 are formed with a constant width is illustrated (see FIGS. 2A and 2B). The wiring width of a part of the formed wiring patterns 102_1 to 102_5 may be larger than the wiring width of other parts.

  DESCRIPTION OF SYMBOLS 10 ... Optical receiver circuit, PD1-PD4 ... Photodiode, Cb1-Cb4 ... Bias separation circuit capacitor, Rb1-Rb4 ... Bias separation circuit resistor, 11 ... Submount, 10A ... First main surface of optical receiver circuit (Front surface), 10B: second main surface (back surface) of optical receiver circuit, 10C: side surface of optical receiver circuit, 11A, 11B ... side of submount, 13 ... ground wiring, 14 ... fixing member, 17 ... semiconductor chip, BP_1 to BP_4 ... bias electrode, GP_1 to GP_5 ... ground electrode, SP_1 to SP_4 ... signal electrode, A_1 to A_4 ... anode electrode, K_1 to K_4 ... cathode electrode, 101_1 to 101_4, 102_1 to 102_6, 103_1 to 103_4, 108_1 to 108_4 , 109_1 to 109_4 ... wiring patterns, 103, 105_ ~ 105_4 ... through via, 107, 70 ... bonding wire, 20 ... substrate, 40 ... TIA chip, 41 ... electrode, 40A ... top surface of TIA chip, 40C ... side surface of TIA chip, 60 ... light output section, 61 ... PLC 610: Optical waveguide 62: Micro lens array 60A: Light output surface 30, 50: Support member

Claims (6)

A submount,
A first wiring pattern and a second wiring pattern extending from the first main surface of the submount to the side surface of the submount;
A third wiring pattern formed on the first main surface of the submount;
A photodiode disposed on the first main surface of the submount, an anode electrode connected to the first wiring pattern, and a cathode electrode connected to the third wiring pattern;
A chip capacitor disposed on the first main surface of the submount, having one electrode connected to the third wiring pattern and the other electrode connected to the second wiring pattern;
In an optical receiving circuit comprising:
A resistor formed in a thin film on a second main surface opposite to the first main surface of the submount;
A fourth wiring pattern formed on the second main surface of the submount and connected to one end of the resistor;
A fifth wiring pattern extending from the side surface on which the first wiring pattern of the submount is formed to the second main surface of the submount and connected to the other end of the resistor;
An optical receiver circuit, further comprising a through via formed through the submount and connecting the fourth wiring pattern and the third wiring pattern. A submount,
A first wiring pattern and a second wiring pattern extending from the first main surface of the submount to the side surface of the submount;
A third wiring pattern formed on the first main surface of the submount;
A photodiode disposed on the first main surface of the submount, an anode electrode connected to the first wiring pattern, and a cathode electrode connected to the third wiring pattern;
A chip capacitor disposed on the first main surface of the submount, having one electrode connected to the third wiring pattern and the other electrode connected to the second wiring pattern;
In an optical receiving circuit comprising:
A plurality of the photodiodes are arranged,
A plurality of the first wiring pattern, the second wiring pattern, and the third wiring pattern are formed corresponding to each of the photodiodes,
A plurality of the chip capacitors are arranged for each corresponding third wiring pattern ,
A plurality of resistors formed in a thin film shape corresponding to each of the photodiodes on a second main surface opposite to the first main surface of the submount;
A plurality of fourth wiring patterns formed on the second main surface of the submount and respectively connected to one end of the corresponding resistor;
A fifth wiring pattern extending from the side surface on which the first wiring pattern of the submount is formed to the second main surface of the submount and connected to the other end of the corresponding resistor,
An optical receiver circuit , further comprising: a plurality of through vias formed through the submount and respectively connecting the fourth wiring pattern and the corresponding third wiring pattern . The optical receiver circuit according to claim 2 ,
The plurality of photodiodes are formed on one semiconductor chip,
The optical receiver circuit, wherein the semiconductor chip is flip-chip mounted on the first main surface of the submount. The optical receiver circuit according to claim 2 or 3 ,
The plurality of photodiodes are arranged along the first side of the first main surface in the first main surface,
The plurality of second wiring patterns are formed along the first side on the first main surface and the side surface,
The plurality of first wiring patterns are respectively formed between the second wiring patterns on the first main surface and the side surface,
The plurality of third wiring patterns are respectively formed on the first main surface between the second wiring patterns so as to face the first wiring patterns,
The other electrode of the plurality of chip capacitors is connected to two second wiring patterns sandwiching the third wiring pattern on which the chip capacitors are disposed via bonding wires, respectively. circuit. In the optical receiver circuit according to any one of claims 1 to 4 ,
The optical receiving circuit, wherein the photodiode is an avalanche photodiode. A plate-shaped first member made of metal;
A second member provided on the first member;
An optical signal output unit that is supported by the second member and outputs an optical signal in a direction parallel to the plane of the first member;
An optical receiver circuit according to any one of claims 1 to 5 ;
A fixing member that fixes the optical receiving circuit to the optical output unit by making the optical output surface of the optical signal output unit from which the optical signal is output face the first main surface of the submount;
A third member provided on the first member;
A TIA chip supported by the third member and having a transimpedance amplifier formed thereon,
The TIA chip has a plurality of electrode patterns formed on a surface opposite to a surface in contact with the third member,
In the optical receiver circuit, a surface opposite to the first main surface of the submount is opposed to a side surface of the TIA chip, and the first wiring pattern and the second wiring pattern of the submount are formed. The side surface is oriented in the same direction as the surface on which the electrode pattern of the TIA chip is formed,
The optical receiver, wherein the first wiring pattern and the second wiring pattern of the optical receiving circuit are respectively connected to the electrode pattern of the TIA chip via bonding wires.

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