JP6238660B2 - THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR - Google Patents

Description

  The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor.

Conventionally, a ferroelectric material (for example, BLT (Bi _{4 -X} La _X Ti ₃ O ₁₂ ), PZT (Pb (Zr _X , Ti ₁ )) is used as a gate insulating layer for the purpose of high-speed switching with a low driving voltage. _{-X) O} 3)) adopted TFTs is disclosed. On the other hand, for the purpose of increasing the carrier concentration, an oxide conductive material (for example, indium tin oxide (ITO), zinc oxide (ZnO), or LSCO (La _X Sr _1-X CuO ₄ )) is used as a channel. An adopted thin film transistor is also disclosed (Patent Document 1).

  Here, looking at the manufacturing method of the above-described thin film transistor, first, a laminated film of Ti and Pt is formed by electron beam evaporation as a gate electrode. On the gate electrode, a gate insulating layer made of the above-described BLT or PZT is formed by a sol-gel method. Further, a channel made of ITO is formed on the gate insulating layer by RF sputtering. Subsequently, Ti and Pt are formed on the channel by an electron beam evaporation method, thereby forming a source electrode and a drain electrode. Thereafter, the element region is separated from other element regions by the RIE method and the wet etching method (mixed solution of HF and HCl) (Patent Document 1). Moreover, some means are disclosed about selection and the combination of the oxide which exhibits the function as a thin-film transistor appropriately (for example, patent documents 2 and 3, nonpatent literature 1).

JP 2006-121029 A International Publication No. 2011/138958 Pamphlet International Publication No. 2013/076031 Pamphlet

Phan Thong Tue, 6 others, "High-Performance Solution-Processed ZrInZnO Thin-Film Transistors", IEEE Transactions on Elecron Devons. 60, no. 1, January 2013

  However, there are several examples of a conventional thin film transistor in which a gate insulating layer or a channel is formed of a complex oxide. However, selection of a material that realizes high characteristics as a thin film transistor and an appropriate manufacturing method therefor has not been possible. Halfway. In addition to improving the performance of each of the gate insulating layer and / or the channel, improving the performance of the stacked layers as a whole is one of the technical problems to be solved for improving the performance of the thin film transistor. One.

  In addition, in the prior art, a process that requires a relatively long time and / or expensive equipment such as a vacuum process or a process using a photolithography method is generally used, so that the use efficiency of raw materials and manufacturing energy is very poor. Become. When the manufacturing method as described above is adopted, many processes and a long time are required to manufacture the thin film transistor, which is not preferable from the viewpoint of industrial property or mass productivity. In addition, there is a problem in the prior art that it is relatively difficult to increase the area.

  The present invention solves at least one of the above-described problems, thereby improving the performance of a thin film transistor in which an oxide is applied to at least a gate insulating layer and a channel, or simplification and energy saving of a manufacturing process of such a thin film transistor. To realize. As a result, the present invention greatly contributes to the provision of a thin film transistor excellent in industrial property or mass productivity.

The inventors of the present application have conducted extensive research and analysis on selection and combination of oxides that can appropriately function as a gate insulating layer and / or a channel from a large number of oxides. As a result, it is possible to appropriately control the content ratio of carbon (C) and hydrogen (H) contained in the oxide as the gate insulating layer with respect to the whole oxide. It has been found that it can contribute to the improvement of field effect mobility (μ _FE ). Usually, in a thin film transistor, carbon (C) is considered to be an element to be removed as much as possible. However, in a thin film transistor in which an oxide is applied to at least a gate insulating layer and a channel, as described above, the contents of carbon (C) and hydrogen (H) contained in the oxide fall within a certain range. The inventors have found that excellent electrical characteristics (particularly, field effect mobility) can be exhibited.

  Further, by selecting and contriving the channel material, processing at a relatively low temperature in the thin film transistor manufacturing process has been realized.

  Any of the above findings is the result of many trials and errors and detailed analysis by the inventors of the present application. In the process of trial and error, focusing on elements that have not been noted as useful elements in the gate insulating layer of a specific oxide so far led to the realization of high-performance thin film transistors. In addition, the inventors of the present application have found that these oxides can be produced by a process that can be greatly simplified or energy-saving as compared with the prior art and can be easily increased in area. The present invention has been created based on the above viewpoints.

  One thin film transistor of the present invention includes an oxide of lanthanum (La) and zirconium (Zr) (which may include inevitable impurities) or lanthanum (La) and tantalum (Ta) between a gate electrode and a channel. A gate insulating layer that is an oxide (which may include inevitable impurities). Here, the carbon (C) content in the gate insulating layer is 0.5 atom% or more and 15 atom% or less, and the hydrogen (H) content in the gate insulating layer is 2 atom% or more and 20 atom%. It is as follows. Furthermore, in this thin film transistor, the above-mentioned channel is an oxide made of indium (In) (can contain unavoidable impurities), an oxide made of indium (In) and tin (Sn) (can contain unavoidable impurities), Oxides of indium (In) and zinc (Zn) (can contain unavoidable impurities) and oxides of indium (In), zirconium (Zr) and zinc (Zn) (can contain unavoidable impurities) One channel oxide layer selected from the group.

By adopting this thin film transistor, very high field effect mobility (μ _FE ) can be obtained. Although the cause is not yet clear at present, the field effect mobility (μ _FE ) is increased by setting the contents of carbon (C) and hydrogen (H) contained in the gate insulating layer to predetermined values. It is very interesting to know that it can be done. As a result, this thin film transistor can exhibit good electrical characteristics.

  In addition, a method of manufacturing a thin film transistor according to the present invention includes a precursor solution containing a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) or a precursor containing lanthanum (La) and tantalum (Ta). And lanthanum (La) by heating a gate insulating layer precursor layer starting from a gate insulating layer precursor solution, which is a precursor solution containing a precursor containing) in an oxygen-containing atmosphere. A gate insulating layer which is an oxide (which may include unavoidable impurities) made of zirconium (Zr) or an oxide (which may contain unavoidable impurities) which consists of lanthanum (La) and tantalum (Ta), The carbon (C) content in the gate insulating layer is not less than 0.5 atom% and not more than 15 atom%, and the hydrogen (H) content in the gate insulating layer is 2 The gate insulating layer forming step of forming the gate insulating layer that is greater than or equal to 20% and less than or equal to 20 atom% so as to be in contact with the gate electrode layer includes the step of forming the gate electrode layer and a channel oxide (which may include inevitable impurities). ) To form a channel. Further, in this thin film transistor manufacturing method, the above-described channel forming step includes a first oxide made of indium (In) (which may contain inevitable impurities), a second made of indium (In) and tin (Sn). An oxide (which may contain inevitable impurities), a third oxide (which may contain inevitable impurities) made of indium (In) and zinc (Zn), or indium (In), zirconium (Zr) and zinc (Zn) And forming a channel oxide which is a fourth oxide (which may contain inevitable impurities).

In this thin film transistor manufacturing method, the precursor layer for a gate insulating layer starting from the precursor solution for a gate insulating layer described above is heated in an oxygen-containing atmosphere, thereby containing carbon (C) and hydrogen (H). Forming a gate insulating layer having a predetermined rate. Therefore, if this thin film transistor manufacturing method is adopted, it is possible to provide a very high electric field by providing a channel forming step for forming a channel oxide made of the specific oxide described above together with such a gate insulating layer forming step. A thin film transistor having favorable electrical characteristics typified by effective mobility (μ _FE ) can be manufactured.

  By the way, in the above-described thin film transistor manufacturing method, in the above-described channel forming step, the first precursor solution containing a precursor containing indium (In) as a solute, the precursor containing indium (In), and tin (Sn) are used. A second precursor solution containing a precursor containing solute, a third precursor solution containing a precursor containing indium (In) and a precursor containing zinc (Zn) as a solute, or a precursor containing indium (In), A precursor containing zirconium (Zr) and a fourth precursor solution having a precursor containing zinc (Zn) as a solute is used as a starting material, and at least selected from the group consisting of acetylacetonate, urea, and ammonium acetate The above-described channel oxide is formed by heating a channel precursor layer containing one kind of co-firing agent and an oxidizing agent in an oxygen-containing atmosphere. Even degree can be adopted as a preferred embodiment. By adopting such a channel formation process, the gate insulating layer and the channel can be formed by a relatively simple process (for example, an ink jet method, a screen printing method, an intaglio / letter printing method, or a nanoimprint method) without using a photolithography method. Can be formed. In addition, it is easy to increase the area. Furthermore, the formation of the oxide of the channel at a lower temperature can be realized by including a co-firing agent. Therefore, according to the method for manufacturing a thin film transistor, a method for manufacturing a thin film transistor excellent in industrial property or mass productivity can be provided. In the present application, as described above, a method of forming a gate insulating layer or a channel oxide layer by firing a precursor solution as a starting material is also referred to as a “solution method” for convenience.

  In the present application, “embossing” is sometimes called “nanoimprint”. Furthermore, in the present application, the “co-firing agent” refers to a chemical substance that mainly plays a role in helping to decompose organic substances in the “pre-firing” step in each embodiment described later.

  According to one thin film transistor of the present invention, a high performance thin film transistor in which a gate insulating layer and a channel are both formed of an oxide is realized. In addition, according to one thin film transistor manufacturing method of the present invention, a high performance thin film transistor in which a gate insulating layer and a channel are both formed of an oxide can be manufactured. In addition, according to the method for manufacturing a thin film transistor, an oxide is formed by a relatively simple process, and thus a method for manufacturing a thin film transistor excellent in industrial property or mass productivity can be provided.

It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the whole structure of the thin-film transistor in the 1st Embodiment of this invention, and its manufacturing method. It is a graph which shows the Vg-Id characteristic of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows the whole structure of the thin-film transistor in the 2nd Embodiment of this invention. It is a graph which shows the Vg-Id characteristic of the thin-film transistor in the 2nd Embodiment of this invention. It is a graph which shows the Vg-Id characteristic of the thin-film transistor in the 2nd Embodiment of this invention. It is a graph which shows the analysis result of the oxide which consists of a lanthanum (La) and a zirconium (Zr) in case the gate insulating layer by the FT-IR measuring apparatus in the 1st and 2nd embodiment of this invention is a LZO layer. . It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the whole structure and the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention.

  Embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this description, common parts are denoted by common reference symbols throughout the drawings unless otherwise specified. In the drawings, elements of the present embodiment are not necessarily described with each other kept to scale. Further, some symbols may be omitted to make each drawing easier to see.

<First Embodiment>
1. Overall Configuration of Thin Film Transistor According to this Embodiment FIGS. 1 to 8 are schematic cross-sectional views showing one process of a method of manufacturing a thin film transistor 100, respectively. FIG. 9 is a schematic cross-sectional view showing one process and the entire configuration of the method of manufacturing the thin film transistor 100 according to this embodiment. As shown in FIG. 9, in the thin film transistor 100 according to this embodiment, the gate electrode 20, the gate insulating layer 34, the channel 44, the source electrode 58, and the drain electrode 56 are stacked in this order on the substrate 10 from the lower layer. .

  The thin film transistor 100 employs a so-called bottom gate structure, but this embodiment is not limited to this structure. Therefore, a person skilled in the art can form a top gate structure by changing the order of the steps by referring to the description of the present embodiment with ordinary technical common sense. Moreover, the display of the temperature in this application represents the surface temperature of the heating surface of the heater which contacts a board | substrate. Further, in order to simplify the drawing, description of patterning of the extraction electrode from each electrode is omitted.

Examples of the substrate 10 include a high heat-resistant glass, a SiO ₂ / Si substrate (that is, a substrate in which a silicon oxide film is formed on a silicon substrate; hereinafter, also simply referred to as “substrate”), an alumina (Al ₂ O ₃ ) substrate, Includes STO (SrTiO) substrate, semiconductor substrate (for example, Si substrate, SiC substrate, Ge substrate, etc.) such as an insulating substrate in which an STO (SrTiO) layer is formed on the surface of Si substrate via SiO ₂ layer and Ti layer Various insulating base materials can be applied.

Examples of the material of the gate electrode 20 include metal materials such as refractory metals such as platinum, gold, silver, copper, aluminum, molybdenum, palladium, ruthenium, iridium, and tungsten, or alloys thereof, or indium tin oxide. (ITO) or ruthenium oxide (RuO ₂ ) can be applied.

  In the thin film transistor 100 according to the present embodiment, the gate insulating layer 34 includes an oxide composed of lanthanum (La) and zirconium (Zr) (however, it may contain unavoidable impurities. The same applies to the oxide of the material.) Or an oxide composed of lanthanum (La) and tantalum (Ta).

  Here, the atomic ratio of lanthanum (La) and zirconium (Zr) in the gate insulating layer 34 is not particularly limited. For example, when lanthanum (La) is set to 1, zirconium (Zr) is about 0. .43 or more and about 2.33 or less is preferable because a good transistor performance effect (typically high field-effect mobility) can be obtained. In addition, regarding the atomic ratio between lanthanum (La) and zirconium (Zr), when lanthanum (La) is set to 1, zirconium (Zr) is 1 or more and 2.33 or less. Since an effect (typically, high field effect mobility) can be achieved with high accuracy, it is particularly preferable. In the gate insulating layer 34, an oxide made of lanthanum (La) and zirconium (Zr) is also referred to as an LZO layer. In the gate insulating layer 34, lanthanum (La) and tantalum (Ta) are used. The resulting oxide is also called the LTO layer. In the present application, various atomic composition ratios were obtained by performing elemental analysis using Rutherford backscattering spectroscopy (RBS method) or the like. In particular, regarding the content of carbon (C) and hydrogen (H), using Pelletron 3SDH manufactured by National Electrostatics Corporation, Rutherford Backscattering Spectroscopy (RBS analysis), Hydrogen Forward Scattering (Hydrogen Forward) It was determined by conducting elemental analysis using scattering spectroscopy (HFS analysis method) and nuclear reaction analysis method ((Nuclear Reaction Analysis: NRA analysis method)).

  Further, the atomic ratio of lanthanum (La) and tantalum (Ta) in the gate insulating layer 34 is not particularly limited.

  The thickness of the gate insulating layer 34 of this embodiment is preferably 50 nm or more and 300 nm or less. The upper limit of the thickness of the gate insulating layer 34 is not particularly limited, but, for example, if it exceeds 300 nm, it is not preferable because it may affect channel interface characteristics. On the other hand, it is not preferable that the thickness is less than 50 nm from the viewpoints of an increase in leakage current and deterioration of the coating property of the film on the substrate.

  The relative dielectric constant of the gate insulating layer 34 is preferably 3 or more and 100 or less. When the relative dielectric constant of the gate insulating layer 34 exceeds 100, the time constant becomes large, which hinders high-speed operation of the transistor. On the other hand, when the relative dielectric constant is less than 3, the amount of charge induced by the gate insulating film increases. This is not preferable because there is a possibility that the device characteristics may deteriorate due to the reduction. From the above viewpoint, the relative dielectric constant is more preferably 15 or more and 30 or less.

The channel 44 of this embodiment is four types of channel oxides shown in the following (A1) to (D1).
(A1) Channel oxide made of indium (In) (also referred to as “first oxide” or “InO” in this embodiment)
(B1) Channel oxide made of indium (In) and tin (Sn) (also referred to as “second oxide” or “ITO” in this embodiment)
(C1) Channel oxide made of indium (In) and zinc (Zn) (also referred to as “third oxide” or “IZO” in this embodiment)
(D1) Channel oxide composed of indium (In), zirconium (Zr), and zinc (Zn) (in this embodiment, also referred to as “fourth oxide” or “ZIZO”)

  In the second oxide of the present embodiment, for example, the channel oxide is tin (Sn) having an atomic ratio of 0.001 or more and 0.03 or less when indium (In) is 1. Including.

  In the third oxide of the present embodiment, for example, the channel oxide is made of zinc (Zn) having an atomic ratio of 0.001 or more and 0.75 or less when indium (In) is 1. Including.

  Further, in the fourth oxide of the present embodiment, for example, the channel oxide is zinc (Zn) having an atomic ratio of 0.001 or more and 0.75 or less when indium (In) is 1. Zirconium (Zr) having an atomic ratio of 0.015 to 0.075 is included.

  It was also confirmed that the channel oxide of this embodiment was an amorphous phase or a nanocrystalline phase. Therefore, it is considered that a favorable interface state with the gate insulating layer 34 which is an amorphous phase in contact with the channel 44 can be obtained. As a result, a thin film transistor having good electrical characteristics can be formed. Note that the layer of the channel 44 made of indium (In) is also called an InO layer. The layer of the channel 44 made of a channel oxide made of indium (In) and tin (Sn) is also called an ITO (Indium Tin Oxide) layer. The layer of the channel 44 made of a channel oxide made of indium (In) and zinc (Zn) is also called an IZO layer. A layer of the channel 44 made of a channel oxide containing indium (In), zinc (Zn), and zirconium (Zr) is also called a ZIZO layer.

  A thin film transistor in which the thickness of the channel 44 is 5 nm or more and 80 nm or less is a preferable embodiment from the viewpoint of covering the gate insulating layer 34 and the like with high accuracy and facilitating modulation of channel conductivity.

In addition, the material of the source electrode 58 and the drain electrode 56 of the present embodiment is not particularly limited. For example, ITO (Indium Tin Oxide) or ruthenium oxide (RuO _2).
).

2. 1. Manufacturing Method of Thin Film Transistor 100 (1) Formation of Gate Electrode First, as shown in FIG. 1, an SiO ₂ / Si substrate (hereinafter also simply referred to as “substrate”) in which the gate electrode 20 is a base material by a known sputtering method. 10 is formed.

(2) Formation of Gate Insulating Layer Next, as shown in FIG. 2, a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) are soluted on the gate electrode 20 by a known spin coating method. A precursor for a gate insulating layer starting from a precursor solution for a gate insulating layer, or a precursor solution for a gate insulating layer containing a precursor containing lanthanum (La) and a precursor containing tantalum (Ta) as a solute Layer 32 is formed.

Here, in the present embodiment, the carbon (C) content in the finally formed gate insulating layer is 0.5 atom% or more and 15 atom% or less, and hydrogen (H) in the gate insulating layer is formed. The precursor solution for the gate insulating layer is adjusted so that the content of is not less than 2 atom% and not more than 20 atom%. A specific adjustment method is as shown in the following (1) to (3).
(1) By heating at 110 ° C. for 30 minutes, lanthanum acetate is dissolved in propionic acid to obtain a 0.2 mol / kg solution.
(2) By heating at 110 ° C. for 30 minutes, zirconium butoxide is dissolved in propionic acid to obtain a 0.2 mol / kg solution.
(3) The above solutions (1) and (2) are mixed at room temperature.
Note that, from the viewpoint of further improving the electrical characteristics of the thin film transistor, the carbon (C) content is 1 atom% or more and 10 atom% or less, and the hydrogen (H) content in the gate insulating layer is 5 atoms. % To 18 atom% is more preferable.

  In addition, when the carbon (C) content in the gate insulating layer is less than 0.5 atom%, the field-effect mobility of the transistor is low. On the other hand, if the content of carbon (C) in the gate insulating layer exceeds 15 atom%, there is a possibility that the problem of poor insulation may occur. In addition, when the hydrogen (H) content in the gate insulating layer is less than 2 atom%, there is a possibility that the field-effect mobility of the transistor is lowered. On the other hand, if it exceeds 20 atom%, there is a possibility that the problem of poor insulation may occur.

  An example of a precursor containing lanthanum (La) for the oxide for the gate insulating layer in the present embodiment is lanthanum acetate. As other examples, lanthanum nitrate, lanthanum chloride, or various lanthanum alkoxides (for example, lanthanum isopropoxide, lanthanum butoxide, lanthanum ethoxide, lanthanum methoxyethoxide) may be employed. An example of a precursor containing zirconium (Zr) for the oxide for the gate insulating layer in the present embodiment is zirconium butoxide. As other examples, zirconium nitrate, zirconium chloride, or various other zirconium alkoxides (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide) may be employed. An example of the precursor containing tantalum (Ta) for the oxide for the gate insulating layer in the present embodiment is tantalum butoxide. As other examples, tantalum nitrate, tantalum chloride, or various other tantalum alkoxides (eg, tantalum isopropoxide, tantalum butoxide, tantalum ethoxide, tantalum methoxide) can be employed.

  Then, it heats at 80 degreeC or more and 250 degrees C or less for predetermined time as preliminary baking. By this preliminary baking, the solvent in the precursor layer 32 for the gate insulating layer is sufficiently evaporated, and in order to develop a characteristic that enables future plastic deformation (before thermal decomposition, the organic chain Is considered to remain. From the viewpoint of realizing the above-described viewpoint with higher accuracy, the pre-baking temperature is preferably 100 ° C. or higher and 250 ° C. or lower. This temperature range is also a preferred temperature range for pre-baking in other materials.

  This pre-baking is performed in an oxygen atmosphere or in the air (hereinafter also collectively referred to as “oxygen-containing atmosphere”). In the present embodiment, in order to finally obtain a sufficient thickness of the gate insulating layer 34 (for example, about 125 nm), the formation of the gate insulating layer precursor layer 32 and the preliminary baking are repeated a plurality of times by the above-described spin coating method. . After that, as the main baking, the gate insulating layer precursor layer 32 is placed in an oxygen atmosphere (for example, 100% by volume, but is not limited to this. The same applies to the following “oxygen atmosphere”) for a predetermined time of 250. By heating and heating in the range of not less than 500 ° C. and not more than 500 ° C., an oxide of lanthanum (La) and zirconium (Zr) or lanthanum (La) and tantalum (as shown in FIG. A gate insulating layer 34 which is an oxide composed of Ta) is formed.

  By the way, the gate insulating layer 34 in this embodiment is a precursor solution for a gate insulating layer containing a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) as a solute, or a precursor containing lanthanum (La). It is formed by firing a precursor solution for a gate insulating layer having a body and a precursor containing tantalum (Ta) as a solute.

(3) Formation of Channel Then, as shown in FIG. 4, a channel precursor layer 42 is formed on the gate insulating layer 34 by a known spin coating method. In the present embodiment, the channel precursor layer 42 is formed using the channel precursor solutions shown in the following (A2) to (D2) having four types of precursors as solutes.
(A2) Channel precursor solution having a precursor containing indium (In) as a solute (also referred to as “first precursor solution” in this embodiment)
(B2) A channel precursor solution having a precursor containing indium (In) and a precursor containing tin (Sn) as solutes (also referred to as “second precursor solution” in this embodiment)
(C2) A channel precursor solution having a precursor containing indium (In) and a precursor containing zinc (Zn) as a solute (also referred to as a “third precursor solution” in this embodiment)
(D2) A channel precursor solution containing a precursor containing indium (In), a precursor containing zirconium (Zr), and a precursor containing zinc (Zn) as a solute (in this embodiment, “fourth precursor Also called “solution”)

  In addition, the channel precursor solution described above further includes at least one co-firing agent selected from the group of acetylacetonate, urea, and ammonium acetate, and an oxidizing agent. An example of the oxidizing agent is nitrate, peroxide, or perchlorate.

  Thereafter, as preliminary firing, the channel precursor layer 42 is heated in a range of 80 ° C. or more and 300 ° C. or less for a predetermined time. After that, as the main firing, the channel precursor layer 42 is heated in a range of 180 ° C. or more and 500 ° C. or less in an oxygen atmosphere for a predetermined time, as shown in FIG. A channel 44 made of the above four types of channel oxides (A1) to (D1) is formed.

  Here, an example of a precursor containing indium (In) for the channel 44 in this embodiment is indium nitrate. As other examples, indium acetylacetonate, indium acetate, indium chloride, or various indium alkoxides (for example, indium isopropoxide, indium butoxide, indium ethoxide, indium methoxyethoxide) may be employed. An example of a precursor containing zinc (Zn) for the channel 44 in this embodiment is zinc chloride. As other examples, zinc nitrate, zinc acetate, or various zinc alkoxides (for example, zinc isopropoxide, zinc butoxide, zinc ethoxide, zinc methoxyethoxide) may be employed. An example of a precursor containing tin (Sn) for the channel 44 in this embodiment is tin chloride. As other examples, tin nitrate, tin acetate, or various tin alkoxides (for example, tin isopropoxide, tin butoxide, tin ethoxide, tin methoxyethoxide) may be employed. An example of a precursor containing zirconium (Zr) for the channel 44 in this embodiment is zirconium butoxide. As other examples, zirconium nitrate, zirconium chloride, or various other zirconium alkoxides (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide) may be employed.

(4) Formation of Source Electrode and Drain Electrode Further, as shown in FIG. 6, after a resist film 90 patterned by a known photolithography method is formed on the channel 44, the channel 44 and the resist film 90 are formed. Then, the ITO layer or the RuO ₂ layer 50 is formed by a known sputtering method. The ITO layer target material of this embodiment is ITO containing 5 wt% tin oxide (SnO ₂ ), and is formed at room temperature. The target material in the case of the RuO ₂ layer is ruthenium oxide (RuO ₂ ) which is itself. Thereafter, when the resist film 90 is removed, a drain electrode 56 and a source electrode 58 made of an ITO layer or RuO ₂ layer 50 are formed on the channel 44 as shown in FIG.

  Thereafter, a resist film 90 patterned by a known photolithography method is formed on the drain electrode 56, the source electrode 58, and the channel 44, and then the resist film 90, a part of the drain electrode 56, and the source electrode 58 are formed. Using the part as a mask, the exposed channel 44 is removed using a known dry etching method using argon (Ar) plasma. As a result, the patterned channel 44 is formed, whereby the thin film transistor 100 is manufactured.

3. Characteristics of Thin Film Transistor 100 Next, Example 1 will be described in order to describe the first embodiment in more detail, but the present embodiment is not limited to this example. For Example 1, the characteristics of the thin film transistor 100 were examined by the following method.

[Example 1]
In Example 1, first, a 200 nm thick platinum (Pt) layer was formed on the substrate 10 as the gate electrode 20. The platinum layer was formed by a known sputtering method. In Example 1, a TiO _X film (not shown) having a thickness of about 10 nm is formed on SiO ₂ .

  Next, a gate insulating layer precursor solution containing a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) as a solute is formed on the gate electrode layer by a known spin coating method. Insulating layer precursor layer 32, or gate insulating layer precursor layer 32 using a precursor solution containing lanthanum (La) and a precursor solution containing tantalum (Ta) as a solute as a starting material. Form. The precursor containing lanthanum (La) is lanthanum acetate. The precursor containing zirconium (Zr) is zirconium butoxide. The precursor containing tantalum (Ta) is tantalum butoxide. Then, it heats to 250 degreeC for about 5 minutes as preliminary baking. In Example 1, the formation of the precursor layer by spin coating and the preliminary firing were repeated 5 times.

Further, after that, as the main firing, the gate insulating layer 34 was obtained by heating the precursor layer at 400 ° C. for about 20 minutes in an oxygen atmosphere. When the gate insulating layer 34 is an LZO layer, the following three types of gate insulating layers 34 were formed with respect to the atomic ratio of lanthanum (La) and zirconium (Zr) in the gate insulating layer 34.
(1) Zirconium (Zr) is 7 when lanthanum (La) is 3 (that is, zirconium (Zr) is about 2.33 when lanthanum (La) is 1)
(2) Zirconium (Zr) is 5 when lanthanum (La) is 5 (that is, zirconium (Zr) is 1 when lanthanum (La) is 1)
(3) Zirconium (Zr) is 3 when lanthanum (La) is 7 (that is, zirconium (Zr) is about 0.43 when lanthanum (La) is 1)

  On the other hand, when the gate insulating layer 34 is an LTO layer, the atomic ratio of lanthanum (La) and tantalum (Ta) in the gate insulating layer 34 is 1: 1.

  The thickness of the gate insulating layer 34 was about 125 nm. In addition, the film thickness of each layer calculated | required the level | step difference of each layer and the board | substrate 10 with the stylus method. In the present embodiment, the carbon (C) content in the gate insulating layer 34 is not less than 0.5 atom% and not more than 15 atom%. In addition, the hydrogen (H) content in the gate insulating layer was 2 atom% or more and 20 atom% or less.

Thereafter, on the gate insulating layer 34, a precursor for a channel using as a starting material the channel precursor solution shown in (A2) to (D2) having the above-mentioned four kinds of precursors as a solute by a known spin coating method. Layer 42 was formed. This channel precursor solution contains acetylacetonate as a co-firing agent. Further, this channel precursor solution contains, as an oxidizing agent, indium nitrate as a raw material for forming nitrate ions (NO ₃ ⁻ ). In addition, this channel precursor solution is further added with ammonium acetate in order to further enhance the firing property of the channel precursor solution in the main firing. In this way, by adding two or more types of the co-firing agents described above, it is possible to adjust the calcinability (specifically, the calcining temperature and the strength of the calcining). It has been confirmed by the inventors of this application.

  Further, indium nitrate was employed as a precursor containing indium (In) for the channel precursor layer 42. Further, zinc chloride was adopted as a precursor containing zinc (Zn) for the channel precursor layer 42. Further, tin chloride was adopted as a precursor containing tin (Sn). Further, zirconium butoxide was adopted as a precursor containing zirconium (Zr).

  Next, as a preliminary firing, the channel precursor layer is heated to 250 ° C. for about 30 minutes. After forming the source and drain electrodes and separating the elements (patterning of the channel), as the main firing, the channel precursor layer is heated in an oxygen atmosphere at 250 ° C. or higher and 400 ° C. or lower for about 10 minutes, thereby The four types of channel oxide layers (channel 44) shown in (A1) to (D1) were formed. The thickness of the channel oxide layer was about 20 nm. Thereafter, as in the first embodiment, a source electrode and a drain electrode were formed.

  In this embodiment, when the channel 44 is an ITO layer, the atomic ratio between indium (In) and tin (Sn) is such that when the indium (In) is 1, tin (Sn) is It was about 0.01. When the channel 44 is an IZO layer, the atomic ratio between indium (In) and zinc (Zn) is approximately 0.5 when zinc (Zn) is 1 when indium (In) is 1. It was. When the channel 44 is a ZIZO layer, the atomic ratio of indium (In), zinc (Zn), and zirconium (Zr) is approximately equal to that of zinc (Zn) when indium (In) is 1. 0.5 and zirconium (Zr) was about 0.025.

(1) Current-Voltage Characteristics Tables 1 and 2 show threshold voltage (V), subthreshold characteristic (SS), field effect mobility (μ _FE ), and ON / OFF ratio in a typical thin film transistor 100. Yes. Table 1 also shows the atomic ratio between lanthanum (La) and zirconium (Zr) and the channel firing temperature when the gate insulating layer is an LZO layer. Table 2 shows that the atomic ratio of lanthanum (La) to tantalum (Ta) is 1: 1 when the gate insulating layer is an LTO layer.

FIG. 10 is a graph showing Vg-Id characteristics of the thin film transistor 100 having the combination of “LZO / IZO” in Table 1 as a representative example. Note that V _D in FIG. 10 is a voltage (V) applied between the source electrode 58 and the drain electrode 56 of the thin film transistor 100.

As shown in Table 1, Table 2, and FIG. 10, when the Vg-Id characteristics of the thin film transistor 100 in the first embodiment were examined, the field effect mobility (μ _FE ) was 127 cm ² / Vs or more. In particular, in all examples except LZO / ZIZO, it is worthy of special mention that the field effect mobility (μ _FE ) was an extremely high value of 500 cm ² / Vs or more. Also, ON / OFF ratio were both on the order of greater than 10 ^6. Accordingly, the thin film transistor 100 can sufficiently function as a thin film transistor even when the gate insulating layer and the channel that form the thin film transistor 100 are an oxide layer and are formed by employing a solution method. It was confirmed.

Although not shown in Table 1, in the atomic ratio of lanthanum (La) and zirconium (Zr), zirconium (Zr) was about 0.43 when lanthanum (La) was set to 1. In the example of LZO / InO (solution method), when the firing temperature of the channel 44 is 300 ° C., in addition to good Vg-Id characteristics, a high field effect mobility (μ _FE ) of 437 cm ² / Vs or more is confirmed. It was done. The ON / OFF ratio at that time is 10 ⁷ or more, and the SS value is 100 mV / dec. Met.

  In particular, in the formation of the channel 44, a thin film transistor having high electrical characteristics as described above was realized in spite of the treatment at a low firing temperature of 400 ° C. or lower.

<Second Embodiment>
1. FIG. 11 is a schematic cross-sectional view illustrating the entire configuration of the thin film transistor 200 according to the present embodiment.

  In this embodiment, the channel 244 of the thin film transistor 200 is a channel oxide made of indium (In) or a channel oxide made of indium (In) and tin (Sn) formed by sputtering. Except for this, it is the same as the first embodiment. Therefore, the description which overlaps with 1st Embodiment is abbreviate | omitted. In the channel oxide composed of indium (In) and tin (Sn), the content of tin (Sn) was about 1 atom% of the whole.

  As shown in FIG. 11, in the thin film transistor 200 according to the present embodiment, the gate electrode 20, the gate insulating layer 34, the channel 244, the source electrode 58 and the drain electrode 56 are stacked on the substrate 10 from the lower layer. . Note that the thickness of the channel 244 in this embodiment is about 10 nm or more and 60 nm or less.

The channel 244 is a channel oxide made of indium (In) or a channel oxide made of indium (In) and tin (Sn). The film forming conditions by the sputtering method in this embodiment are as shown in the following (1) to (3).
(1) Under a pressure of 0.5 Pa of argon and 0.04 Pa of oxygen, 35 W is applied in a mixed gas atmosphere of the argon and the oxygen.
(2) The temperature of the substrate is room temperature.
(3) The processing time by the sputtering method is 10 minutes to 40 minutes.
In addition, after the above-mentioned (1) to (3), the processes shown in the following (4) and (5) are also performed as necessary.
(4) After the treatment by the sputtering method, heating is performed at 250 ° C. in the atmosphere for 30 minutes.
(5) After channel patterning, as a post-annealing treatment, heating is performed at 250 ° C. or higher and 400 ° C. or lower for 10 minutes.

3. Characteristics of Thin Film Transistor 200 Next, Example 2 will be described in order to describe the second embodiment in more detail, but the present embodiment is not limited to this example. For Example 2, the characteristics of the thin film transistor 200 were examined by the following method.

[Example 2]
In the second embodiment, only the oxide layer of the channel 244 is different from the thin film transistor of the first embodiment. Therefore, the overlapping description is omitted.

Table 3 shows the threshold voltage (V), subthreshold characteristic (SS), field-effect mobility (μ _FE ), and ON / OFF ratio of a typical thin film transistor 200. Table 3 also shows the atomic ratio between lanthanum (La) and zirconium (Zr) when the gate insulating layer is an LZO layer.

FIGS. 12 and 13 are representative examples of Vg-Id characteristics of the thin film transistor 200 having a combination of “LZO / InO (sputtering method)” or a combination of “LZO / ITO (sputtering method)” in Table 3. It is a graph which shows. Note that V _D in FIGS. 12 and 13 is a voltage (V) applied between the source electrode 58 and the drain electrode 56 of the thin film transistor 1200.

(4) Analysis of gate insulating layer oxide by FT-IR measurement device (measurement device by infrared absorption spectrum method) FIG. 14 shows an FT-IR measurement device (manufactured by Bruker) in the first and second embodiments described above. It is a graph which shows the analysis result of the oxide which consists of a lanthanum (La) and a zirconium (Zr) in case the gate insulating layer by a ALPHA, type | mold is an LZO layer. In FIG. 14, (a) is about 2.33 of zirconium (Zr) when the lanthanum (La) is 1 in the atomic ratio of lanthanum (La) and zirconium (Zr). In FIG. 14B, zirconium (Zr) was about 1 when the lanthanum (La) was 1 in the atomic ratio of lanthanum (La) and zirconium (Zr). Further, in FIG. 14C, in the atomic ratio of lanthanum (La) and zirconium (Zr), zirconium (Zr) was about 0.43 when lanthanum (La) was 1.

As shown in FIG. 14, it is very interesting that both (a) and (b) in FIG. 14 show the bond between carbon (C) and hydrogen (H) or carbon (C ) and oxygen (O) and about 1300 cm ^-1 ~ absorption peak at about 1600 cm ^-1 based on the binding of (range Y in Figure 14) is relatively strongly observed. Further, in FIG. 14 (a) and (b) are both in the infrared absorption spectrum method, the absorption peak at about 2500 cm ^-1 ~ about 3750cm ^-1 based on the binding of oxygen (O) and hydrogen (H) (Range of X in FIG. 14) was observed quite strongly.

On the other hand, (c) in FIG. 14 shows about 1300 cm ⁻¹ to about 1300 cm ⁻¹ to about 1300 cm ⁻¹ based on the bond of carbon (C) and hydrogen (H) or the bond of carbon (C) and oxygen (O) in the infrared absorption spectrum method. with absorption peaks of 1600 cm ^-1 is relatively weakly observed, the absorption peak at about 2500 cm ^-1 ~ about 3750cm ^-1 based on the binding of oxygen (O) and hydrogen (H) was hardly observed.

  Here, according to the research and analysis of the present inventors so far, the difference between (a) and (b) in FIG. 14 and (c) is the electrical characteristics of the thin film transistor manufactured in the first embodiment. It is thought that it affects the physical characteristics. For example, (c), that is, a gate insulating layer in which zirconium (Zr) is about 0.43 when lanthanum (La) is 1 in the atomic ratio of lanthanum (La) and zirconium (Zr) is adopted. In particular, it has been confirmed that the Vg-Id characteristics of the thin film transistor are deteriorated particularly when the baking temperature is 350 ° C. or higher. On the other hand, when a gate insulating layer in which the number of atoms of zirconium (Zr) is 1 or more and 2.33 or less when the number of atoms of lanthanum (La) is 1, it is relatively independent of the firing temperature. Excellent Vg-Id characteristics can be obtained. Therefore, it is very interesting that the atomic ratio of lanthanum (La) to zirconium (Zr) has been confirmed to affect the manufacturing process of the thin film transistor or a part of the electrical characteristics of the thin film transistor.

As described above, it has become clear that the thin film transistors 100 and 200 of the present embodiment can achieve good electrical characteristics as thin film transistors. In particular, according to the manufacturing method of the thin film transistor 100 of the present embodiment, the gate insulating layer and the channel are made of an oxide and are formed by using a solution method. The area can be easily increased, and the industrial property or mass productivity can be remarkably improved.
<Third Embodiment>

  The present embodiment is the same as the first embodiment except that the embossing process is performed in the formation process of a part of the layers in the first embodiment. Therefore, the description which overlaps with 1st Embodiment is abbreviate | omitted.

1. Manufacturing Method of Thin Film Transistor 300 FIGS. 15 to 20 are schematic cross-sectional views illustrating one process of the manufacturing method of the thin film transistor 300. FIG. FIG. 21 is a schematic cross-sectional view showing one process and the entire configuration of the method of manufacturing the thin film transistor 300 in the present embodiment. In order to simplify the drawing, the description of the patterning of the extraction electrode from each electrode is omitted.

(1) Formation of Gate Electrode First, as shown in FIG. 15, the gate electrode 20 is formed on the substrate 10 by a known sputtering method, photolithography method, and etching method. Note that the material of the gate electrode 20 of the present embodiment is platinum (Pt).

(2) Formation of Gate Insulating Layer Next, on the substrate 10 and the gate electrode 20, as in the first embodiment, a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) are used as solutes. A gate insulating layer precursor layer 32 starting from a gate insulating layer precursor solution, or a gate insulating layer precursor solution having a lanthanum (La) -containing precursor and a tantalum (Ta) -containing precursor as a solute. Form. Thereafter, pre-baking is performed in an oxygen-containing atmosphere while being heated to 80 ° C. or higher and 200 ° C. or lower.

  In the present embodiment, the stamping process is performed on the gate insulating layer precursor layer 32 that has been pre-fired only. Specifically, in order to perform patterning of the gate insulating layer, as shown in FIG. 16, the mold is used at a pressure of 1 MPa or more and 20 MPa or less using the gate insulating layer mold M1 while being heated to 80 ° C. or more and 300 ° C. or less. Apply pressing. As a result, the gate insulating layer precursor layer 32 having a thickness of about 50 nm to about 300 nm is formed by the gate insulating layer mold M1 of the present embodiment.

  Thereafter, the entire gate insulating layer precursor layer 32 is etched to remove the gate insulating layer precursor layer 32 from regions other than the region corresponding to the gate insulating layer as shown in FIG. Etching step for the entire surface of the precursor layer 32 for use). In addition, although the etching process of the precursor layer 32 for gate insulating layers of this embodiment was performed using the wet etching technique which does not use a vacuum process, it is etched by what is called dry etching technique using plasma. Not disturb.

  Thereafter, heating is performed in a range of 250 ° C. or more and 500 ° C. or less for a predetermined time in an oxygen atmosphere (for example, 100% by volume, but is not limited thereto. The same applies to the following “oxygen atmosphere”). As shown in FIG. 18, a gate insulating layer which is an oxide made of lanthanum (La) and zirconium (Zr) or an oxide made of lanthanum (La) and tantalum (Ta) is formed on the substrate 10 and the gate electrode 20. 34 is formed.

(3) Formation of channel A die pressing process is performed on the channel precursor layer 42 that has been pre-fired only. First, the channel precursor which is the first precursor solution, the second precursor solution, the third precursor solution, or the fourth precursor solution shown in the first embodiment is formed on the gate insulating layer 34 and the substrate 10. A channel precursor layer 42 starting from the body solution is formed. Thereafter, as in the first embodiment, as the preliminary firing, the channel precursor layer 42 is heated in a range of 80 ° C. or higher and 180 ° C. or lower for a predetermined time.

  Next, as shown in FIG. 20, in the state heated to 80 ° C. or higher and 250 ° C. or lower, the channel precursor layer 42 is subjected to a die pressing process at a pressure of 1 MPa or higher and 20 MPa or lower using the channel mold M2. Apply. As a result, a channel precursor layer 42 having a layer thickness of about 50 nm or more and about 300 nm or less is formed. Thereafter, the entire surface is etched in the same manner as the gate insulating layer precursor layer 32. After that, as the main firing, the channel precursor layer 42 is heated in a range of 180 ° C. or more and 500 ° C. or less in an oxygen atmosphere for a predetermined time, as shown in FIG. Channels 44 made of the four types of channel oxides shown in (A1) to (D1) shown in the first embodiment are formed.

(4) Formation of Source Electrode and Drain Electrode Next, as in the first embodiment, after a resist film patterned by a known photolithography method is formed on the channel 44, the channel 44 and the resist film are formed. Then, an ITO layer is formed by a known sputtering method. Thereafter, when the resist film is removed, a drain electrode 56 and a source electrode 58 made of an ITO layer are formed on the channel 44 as shown in FIG.

  In this embodiment, embossing is performed on the precursor layer that has obtained high plastic deformation ability. As a result, even when the pressure applied when embossing is a low pressure of 1 MPa or more and 20 MPa or less, each precursor layer comes to deform following the surface shape of the mold, and the desired embossing structure Can be formed with high accuracy. In addition, by setting the pressure in a low pressure range of 1 MPa or more and 20 MPa or less, the mold becomes difficult to be damaged when performing the stamping process, and it is advantageous for increasing the area.

  Here, the reason why the pressure is within the range of “1 MPa or more and 20 MPa or less” is as follows. First, if the pressure is less than 1 MPa, the pressure may be too low to emboss each precursor layer. On the other hand, if the pressure is 20 MPa, the precursor layer can be sufficiently embossed, so that it is not necessary to apply more pressure. From the viewpoint described above, it is more preferable to perform the embossing process at a pressure in the range of 2 MPa to 10 MPa in the embossing process in the third embodiment.

  In the third embodiment, the embossing process is performed on the gate insulating layer 34 and the channel 44 of the first embodiment, but the object of the embossing process is not limited thereto. For example, it is possible to form an embossed structure by embossing the gate insulating layer 34 of the second and second embodiments.

  As described above, in this embodiment, the “embossing process” is employed, in which the embossing structure is formed by embossing the gate insulating layer 34 and the channel 44. By adopting this embossing process, a process that requires a relatively long time and / or expensive equipment such as a vacuum process, a process using a photolithography method, or an ultraviolet irradiation process becomes unnecessary. Therefore, the thin film transistor 300 and the manufacturing method thereof are extremely excellent in industrial property or mass productivity.

<Other embodiments>
In order to appropriately achieve the effects in the above-described embodiments, the solvent of the precursor solution of the gate insulating layer is acetic acid, propionic acid, octylic acid, ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, It is preferable that it is the mixed solvent of the alcohol by which 1 type or 2 types are selected from the group of 2-butoxyethanol. The solvent for the channel precursor solution is one alcohol solvent selected from the group consisting of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol, or acetic acid, propionic acid, and octyl. A solvent that is one carboxylic acid selected from the group of acids is preferred.

  In the preliminary firing for forming each oxide layer in each of the above embodiments, the preliminary firing temperature is most preferably 100 ° C. or higher and 180 ° C. or lower. This is because the solvent in various precursor layers can be evaporated more accurately. In particular, when the embossing process is performed after that, pre-baking in the above-mentioned temperature range is preferable to develop a property that enables future plastic deformation (before the pyrolysis). It can be considered that the organic chain remains in this state.

  Moreover, in the above-mentioned 3rd Embodiment, it is supposed that a stamping process is performed with respect to the precursor layer which acquired the high plastic deformation capability. As a result, even when the pressure applied when embossing is as low as 1 MPa or more and 20 MPa or less, each precursor layer is deformed following the surface shape of the mold, and a desired embossing structure is obtained. Can be formed with high accuracy. In addition, by setting the pressure in a low pressure range of 1 MPa or more and 20 MPa or less, the mold becomes difficult to be damaged when performing the stamping process, and it is advantageous for increasing the area.

  Furthermore, in the modified example of the third embodiment, after the channel 44 is formed, a source electrode and a drain electrode made of an ITO layer may be formed by applying a stamping process after adopting the solution method. . Specifically, it is as follows.

  First, after the channel 44 is formed, a precursor for a source / drain electrode having a precursor containing indium (In) and a precursor containing tin (Sn) as a solute is formed on the channel 44 by a known spin coating method. A source / drain electrode precursor layer is formed using the body solution as a starting material. Here, examples of the precursor containing indium (In) for the source / drain electrode oxide layer in this embodiment include indium acetate, indium nitrate, indium chloride, or various indium alkoxides (for example, indium isopropoxy). , Indium butoxide, indium ethoxide, indium methoxyethoxide) may be employed. Examples of the precursor containing tin (Sn) for the source / drain electrode oxide layer in the present embodiment include tin acetate, tin nitrate, tin chloride, or various tin alkoxides (for example, tin isopropoxy). , Tin butoxide, tin ethoxide, tin methoxyethoxide) may be employed.

  In this case, as the pre-baking, for example, after the source / drain electrode precursor layer is heated to 150 ° C. in the atmosphere for about 5 minutes, the source / drain electrode is patterned, for example, at 200 ° C. in order to perform patterning. Then, using a source / drain electrode mold (not shown), embossing is performed at a pressure of 5 MPa. Thereafter, as the main baking, the source / drain electrode precursor layer is heated in the atmosphere to, for example, about 5 minutes to 250 ° C. or more and 400 ° C. or less to form the source / drain electrode oxide layer. Furthermore, as the main firing, heating in an atmosphere of nitrogen, for example, at 450 ° C. for about 15 minutes causes oxygen in the ITO to be deficient, and this deficiency becomes a conductive oxygen deficient carrier. It becomes possible to plan.

  Further, in each of the above-described embossing steps, in advance, a mold release treatment for the surface of each precursor layer and / or a mold release surface for the mold pressing surface, which the mold pressing surface comes into contact with, is performed. Thereafter, it is preferable to perform a stamping process on each precursor layer. By performing such treatment, it is possible to reduce the frictional force between each precursor layer and the mold, and therefore it is possible to perform the stamping process with higher accuracy on each precursor layer. . Examples of the release agent that can be used for the release treatment include surfactants (for example, fluorine surfactants, silicon surfactants, nonionic surfactants, etc.), fluorine-containing diamond-like carbon, and the like. can do.

  Moreover, each precursor layer (for example, source electrode and drain precursor layer) subjected to the stamping process between the stamping step and the main firing step for each precursor layer in each of the embodiments described above. It is a more preferable aspect that a step of etching the precursor layer as a whole is included under the condition that the precursor layer is removed in the region where the layer thickness is the thinnest. This is because unnecessary regions can be removed more easily than etching after each precursor layer is finally fired. Therefore, in each of the above-described embodiments, a more preferable aspect described above can be adopted instead of the step of performing the entire etching after the main baking.

  As described above, the disclosure of each of the embodiments described above is described for explaining the embodiments, and is not described for limiting the present invention. In addition, modifications within the scope of the present invention including other combinations of the embodiments are also included in the claims.

DESCRIPTION OF SYMBOLS 10 Substrate 20,224 Gate electrode 32 Gate insulating layer precursor layer 34 Gate insulating layer 42 Channel precursor layer 44 Channel 56 Drain electrode 58 Source electrode 100, 200, 300 Thin film transistor 50 ITO layer or RuO ₂ layer 90 Resist film M1 Gate insulation layer type M2 channel type

Claims (12)

Between the gate electrode and the channel, an oxide composed of lanthanum (La) and zirconium (Zr) (can contain inevitable impurities) or an oxide composed of lanthanum (La) and tantalum (Ta) (including inevitable impurities) And the content of carbon (C) in the gate insulating layer is not less than 0.5 atom% and not more than 15 atom%, and the content of hydrogen (H) in the gate insulating layer The rate is 2 atom% or more and 20 atom% or less,
The channel is
Indium (In) oxide (may contain inevitable impurities), Indium (In) and tin (Sn) oxide (may contain inevitable impurities), Indium (In) and zinc (Zn) One type of channel oxide layer selected from the group of oxides (which may contain unavoidable impurities) and oxides (which may contain unavoidable impurities) consisting of indium (In), zirconium (Zr) and zinc (Zn) Is,
Thin film transistor. When the gate insulating layer is an oxide composed of the lanthanum (La) and the zirconium (Zr) (may contain inevitable impurities), and the number of atoms of the lanthanum (La) is 1, the zirconium The number of atoms of (Zr) is 1 or more and 2.33 or less,
The thin film transistor according to claim 1. The gate insulating layer, the infrared absorption spectrum method, having an absorption peak at about 2500 cm ^-1 ~ about 3750cm ^-1 based on the binding of oxygen (O) and hydrogen (H),
The thin film transistor according to 請 Motomeko 2. The gate insulating layer, the infrared absorption spectrum method, carbon (C) and hydrogen (H) and the bond or carbon (C) and oxygen (O) and bonded to the based of about 1300 cm ^-1 ~ about 1600 cm ^-1 of the Having an absorption peak,
The thin film transistor according to 請 Motomeko 2. A precursor solution containing a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) as a solute, or a precursor solution containing a precursor containing lanthanum (La) and a precursor containing tantalum (Ta) as a solute. By heating a gate insulating layer precursor layer starting from a certain gate insulating layer precursor solution in an oxygen-containing atmosphere, an oxide composed of lanthanum (La) and zirconium (Zr) (inevitable impurities are removed). Or an oxide of lanthanum (La) and tantalum (Ta) (which may include inevitable impurities), and the carbon (C) content in the gate insulating layer is 0 The gate insulating layer having a thickness of not less than 5 atom% and not more than 15 atom%, and the hydrogen (H) content in the gate insulating layer is not less than 2 atom% and not more than 20 atom% The gate insulating layer forming step of forming in contact with the gate electrode layer,
Including between the step of forming the gate electrode layer and the step of forming a channel for forming a channel oxide (which may include inevitable impurities),
Forming the channel comprises:
A first oxide made of indium (In) (can contain unavoidable impurities), a second oxide made of indium (In) and tin (Sn) (can contain unavoidable impurities), indium (In) and zinc (Zn Or a fourth oxide composed of indium (In), zirconium (Zr) and zinc (Zn) (may contain inevitable impurities)
A step of forming a channel oxide.
A method for manufacturing a thin film transistor. Forming the channel comprises:
A first precursor solution having a precursor containing indium (In) as a solute, a second precursor solution having a precursor containing indium (In) and a precursor containing tin (Sn) as a solute, and indium (In) A third precursor solution containing a precursor containing zinc and a precursor containing zinc (Zn) as a solute, or a precursor containing indium (In), a precursor containing zirconium (Zr), and a precursor containing zinc (Zn) A channel precursor layer comprising a fourth precursor solution having a solute as a starting material, and further comprising at least one co-firing agent selected from the group consisting of acetylacetonate, urea, and ammonium acetate, and an oxidizing agent By heating in an oxygen-containing atmosphere,
A step of forming a channel oxide that is the first oxide, the second oxide, the third oxide, or the fourth oxide.
A method for manufacturing the thin film transistor according to claim 5. The gate insulating layer precursor solution is a precursor solution having a lanthanum (La) -containing precursor and a zirconium (Zr) -containing precursor as a solute, and in the gate insulating layer, the lanthanum (La) ) When the number of atoms of the zirconium (Zr) is 1 or more and 2.33 or less,
A method for manufacturing the thin film transistor according to claim 5. The gate insulating layer, the infrared absorption spectrum method, having an absorption peak at about 2500 cm ^-1 ~ about 3750cm ^-1 based on the binding of oxygen (O) and hydrogen (H),
Method for producing a serial mounting of the thin film transistor to 請 Motomeko 7. The gate insulating layer, the infrared absorption spectrum method, carbon (C) and hydrogen (H) and the bond or carbon (C) and oxygen (O) and bonded to the based of about 1300 cm ^-1 ~ about 1600 cm ^-1 of the Having an absorption peak,
Method for producing a serial mounting of the thin film transistor to claim 7 or請 Motomeko 8. In the gate insulating layer forming step,
Before forming the gate insulating layer, the gate insulating layer precursor layer is subjected to a stamping process in a state of being heated at 80 ° C. or higher and 300 ° C. or lower in an oxygen-containing atmosphere. Further comprising an embossing step of forming an embossed structure on the precursor layer,
Method for fabricating the thin film transistor according to any one of claims 7乃 Optimum claim 9. In the channel forming step,
Before forming the channel, the channel precursor layer is subjected to an embossing process in a state where the channel precursor layer is heated at 80 ° C. or higher and 250 ° C. or lower in an oxygen-containing atmosphere. Further comprising a stamping step for forming a stamping structure,
The manufacturing method of the thin-film transistor of Claim 6. The heating temperature for forming the gate insulating layer is 250 ° C. or more and 500 ° C. or less,
The heating temperature for forming the channel is 180 ° C. or higher and 500 ° C. or lower.
The manufacturing method of the thin-film transistor of Claim 11.

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