JP6230422B2 - Wafer processing method - Google Patents
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- JP6230422B2 JP6230422B2 JP2014004796A JP2014004796A JP6230422B2 JP 6230422 B2 JP6230422 B2 JP 6230422B2 JP 2014004796 A JP2014004796 A JP 2014004796A JP 2014004796 A JP2014004796 A JP 2014004796A JP 6230422 B2 JP6230422 B2 JP 6230422B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
- B28D5/0011—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing with preliminary treatment, e.g. weakening by scoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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Description
本発明は、半導体ウエーハ等のウエーハの加工方法に関する。 The present invention relates to a method for processing a wafer such as a semiconductor wafer.
半導体デバイス製造プロセスにおいては、略円板形状である半導体ウエーハの表面に格子状に形成された分割予定ライン（ストリート）によって区画された複数の領域にそれぞれＩＣ、ＬＳＩ等のデバイスを形成し、該デバイスが形成された各領域を分割予定ラインに沿って分割することによりデバイスチップを製造している。 In the semiconductor device manufacturing process, devices such as IC and LSI are respectively formed in a plurality of regions partitioned by division lines (streets) formed in a lattice shape on the surface of a semiconductor wafer having a substantially disk shape, A device chip is manufactured by dividing each region in which a device is formed along a planned division line.
半導体ウエーハを個々のデバイスチップに分割する分割装置としては、一般にダイシング装置と呼ばれる切削装置が用いられており、この切削装置は非常に薄い切り刃を有する切削ブレードによって半導体ウエーハを分割予定ラインに沿って切削して半導体ウエーハを個々のデバイスチップに分割する。このようにして分割されたデバイスチップは、パッケージングされて携帯電話やパソコン等の各種電子機器に広く利用されている。 As a dividing device that divides a semiconductor wafer into individual device chips, a cutting device generally called a dicing device is used. This cutting device uses a cutting blade having a very thin cutting edge to cut a semiconductor wafer along a planned dividing line. The semiconductor wafer is divided into individual device chips by cutting. The device chips thus divided are packaged and widely used in various electronic devices such as mobile phones and personal computers.
ところで、例えば厚さ３００μｍ以上等の比較的厚みが厚いウエーハを切削ブレードでダイシングすると、裏面チッピングが大きく発生するという問題がある。そこで、裏面チッピングを抑えるために、例えば特開昭６４−３８２０９号公報に開示された先ダイシング法（ＤＢＧ）やＷＯ２００３−０７７２９５号公報に開示された加工方法（ＳＤＢＧ）を用いることが考えられる。 By the way, for example, when a wafer having a relatively large thickness, such as a thickness of 300 μm or more, is diced with a cutting blade, there is a problem in that backside chipping occurs greatly. Therefore, in order to suppress backside chipping, it is conceivable to use, for example, a tip dicing method (DBG) disclosed in JP-A-64-38209 or a processing method (SDBG) disclosed in WO2003-077795.
先ダイシング法は、半導体ウエーハの表面から分割予定ラインに沿って所定深さ（デバイスチップの仕上がり厚さに相当する深さ）の分割溝を形成し、表面に分割溝が形成された半導体ウエーハの裏面を研削して裏面に分割溝を露出させ個々のデバイスチップに分割する技術であり、デバイスチップの厚さを１００μｍ以下に加工することが可能である。 In the first dicing method, a split groove having a predetermined depth (a depth corresponding to the finished thickness of the device chip) is formed along the planned split line from the surface of the semiconductor wafer, and the semiconductor wafer having the split groove formed on the surface is formed. This is a technique of grinding the back surface to expose the dividing grooves on the back surface to divide the chip into individual device chips, and the device chip can be processed to a thickness of 100 μm or less.
一方、ＳＤＢＧ法はレーザー加工方法と研削方法を組み合わせた技術であり、まずウエーハに対して透過性を有する波長のレーザービームをウエーハに照射して、分割予定ラインに沿って所定深さの位置（ウエーハの表面からデバイスチップの仕上がり厚さに相当する深さ以上の位置）に改質層を形成するとともに改質層からウエーハの表面側に伸長するクラック層を形成し、その後、ウエーハの裏面を研削してウエーハを仕上がり厚みに薄化するとともに研削圧力によりウエーハをクラック層を分割起点に個々のデバイスチップに分割する技術である。 On the other hand, the SDBG method is a technique that combines a laser processing method and a grinding method. First, the wafer is irradiated with a laser beam having a wavelength that is transparent to the wafer, and a position at a predetermined depth ( A modified layer is formed from the wafer surface to a depth equal to or greater than the depth corresponding to the finished thickness of the device chip, and a crack layer extending from the modified layer to the front surface side of the wafer is formed. In this technique, the wafer is finished to a thin thickness by grinding, and the wafer is divided into individual device chips by using a cracking layer as a starting point by a grinding pressure.
しかし、引用文献１に記載された先ダイシング法において、ウエーハの厚みの半分以上の深さのハーフカット溝を形成すると、溝形成後、後の裏面研削時に表面に形成されたデバイスを保護するためのウエーハの表面に保護テープを貼着する必要があるが、保護テープを貼着する際のハンドリング時にウエーハが破損してしまうという問題がある。 However, in the tip dicing method described in Cited Document 1, when a half-cut groove having a depth of more than half of the wafer thickness is formed, the device formed on the surface is protected after the groove is formed after the groove is formed. However, there is a problem that the wafer is damaged during handling when the protective tape is applied.
また、引用文献２に記載されたＳＤＢＧ法でも、一つの改質層から伸長させることのできるクラック層は１５０μｍ程度であるため、抗折強度を悪化させないために研削後のチップ側面に改質層を残存させないようにすると、１５０μｍ以上の厚みのチップの形成は困難であるという問題がある。 Further, even in the SDBG method described in the cited document 2, since the crack layer that can be extended from one modified layer is about 150 μm, the modified layer is formed on the side surface of the chip after grinding in order not to deteriorate the bending strength. If it does not remain, there is a problem that it is difficult to form a chip having a thickness of 150 μm or more.
本発明はこのような点に鑑みてなされたものであり、その目的とするところは、抗折強度を悪化させることなく比較的厚い厚みのチップを形成し得るウエーハの加工方法を提供することである。 The present invention has been made in view of these points, and the object of the present invention is to provide a wafer processing method capable of forming a relatively thick chip without deteriorating the bending strength. is there.
本発明によると、交差する複数の分割予定ラインが設定されたウエーハの加工方法であって、表面チッピングを抑えることができる程度の細粒径の砥粒を含有した切削ブレードをウエーハの表面から該分割予定ラインに沿って切り込ませ、ウエーハの厚みの半分より浅く仕上げ厚みに至らない深さの複数の溝を形成する溝形成ステップと、該溝形成ステップを実施した後、ウエーハの表面に保護テープを貼着する保護テープ貼着ステップと、該保護テープ貼着ステップを実施した後、該保護テープを介してウエーハをチャックテーブルで保持する保持ステップと、該保持ステップを実施した後、ウエーハに対して透過性を有する波長のレーザービームの集光点をウエーハ内部の該仕上げ厚みより裏面側に位置付けて、該レーザービームをウエーハの裏面に向かって該分割予定ラインに沿って照射して、ウエーハ内部に該分割予定ラインに沿う改質層を形成するとともに該改質層から伸長して該溝に達し該分割予定ラインに沿うクラック層を形成するレーザー加工ステップと、該レーザー加工ステップを実施した後、ウエーハの裏面を研削手段で研削して該仕上げ厚みへと薄化するとともに該改質層を除去し、ウエーハを該分割予定ラインに沿ってチップに分割する研削ステップと、を備えたことを特徴とするウエーハの加工方法が提供される。 According to the present invention, there is provided a wafer processing method in which a plurality of intersecting scheduled lines are set, and a cutting blade containing abrasive grains having a fine particle size capable of suppressing surface chipping is provided from the wafer surface. A groove forming step for forming a plurality of grooves having a depth less than half of the wafer thickness and not reaching the finished thickness by cutting along the planned dividing line, and protecting the wafer surface after performing the groove forming step. After carrying out the protective tape attaching step for attaching the tape, the protective tape attaching step, the holding step for holding the wafer with the chuck table via the protective tape, and after the holding step, On the other hand, the condensing point of a laser beam having a wavelength having transparency is positioned on the back surface side of the finished thickness inside the wafer, and the laser beam is placed on the wafer. Toward the back surface of the wafer is irradiated along the dividing lines, reaches the groove extends from the reforming layer to form a along the Hare reforming layer on the dividing lines within the wafer the dividing lines in a laser processing step of forming a along cormorants crack layer, after performing the laser processing step, and grinding the back surface of the wafer with grinding means to remove said modified layer with thinned to the final thickness, the wafer And a grinding step for dividing the wafer into chips along the division line.
本発明の加工方法では、ウエーハの表面に溝を形成した後保護テープを貼着するので、ウエーハ内部に改質層とクラック層が形成されても保護テープにより剛性を保つことができ、ハンドリング性を損なうことがない。 In the processing method of the present invention, since a protective tape is applied after forming a groove on the surface of the wafer, the protective tape can maintain rigidity even if a modified layer and a crack layer are formed inside the wafer, and handling properties Will not be damaged.
さらに、研削により改質層を除去するとともにウエーハを分割予定ラインに沿って分割するので、チップには改質層が残存することがなく抗折強度を悪化させることがない。 Furthermore, since the modified layer is removed by grinding and the wafer is divided along the planned dividing line, the modified layer does not remain on the chip and the bending strength is not deteriorated.
以下、本発明の実施形態を図面を参照して詳細に説明する。図１を参照すると、半導体ウエーハ１１の表面側斜視図が示されている。半導体ウエーハ（以下、単にウエーハと略称することがある）１１の表面１１ａには複数の分割予定ライン（ストリート）１３によって区画された各領域にＩＣ、ＬＳＩ等のデバイス１５が形成されている。ウエーハ１１の外周には、ウエーハの結晶方位を示すマークとしてのノッチ１７が形成されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, a front side perspective view of a semiconductor wafer 11 is shown. On a surface 11a of a semiconductor wafer (hereinafter, sometimes simply referred to as a wafer) 11, devices 15 such as ICs and LSIs are formed in respective regions partitioned by a plurality of division lines (streets) 13. A notch 17 is formed on the outer periphery of the wafer 11 as a mark indicating the crystal orientation of the wafer.
本発明のウエーハの加工方法では、まず、ウエーハ１１の表面１１ａから分割予定ライン１３に沿って仕上げ厚みに至らない深さの複数の溝を形成する溝形成ステップを実施する。図２は溝形成ステップを示す斜視図、図３はその断面図である。図２及び図３において、ウエーハ１１を吸引保持するチャックテーブルが省略されている。 In the wafer processing method of the present invention, first, a groove forming step is performed in which a plurality of grooves having a depth not reaching the finished thickness is formed from the surface 11a of the wafer 11 along the scheduled division line 13. FIG. 2 is a perspective view showing a groove forming step, and FIG. 3 is a sectional view thereof. 2 and 3, the chuck table for sucking and holding the wafer 11 is omitted.
図２において、切削装置の切削ユニット（切削手段）１０は、スピンドルハウジング１２中に回転可能に収容されたスピンドル１４と、スピンドル１４の先端部に装着された切削ブレード１６とを含んでいる。 In FIG. 2, a cutting unit (cutting means) 10 of the cutting apparatus includes a spindle 14 rotatably accommodated in a spindle housing 12, and a cutting blade 16 attached to the tip of the spindle 14.
溝形成ステップでは、矢印Ａ方向に高速回転する切削ブレード１６をウエーハ１１の分割予定ライン１３に所定深さ（ウエーハの仕上げ厚みに至らない深さ）切り込ませ、図示しないチャックテーブルを矢印Ｘ１方向に加工送りしながらウエーハ１１の表面１１ａから分割予定ライン１３に沿って仕上げ厚みに至らない深さの溝１９を形成する。 In the groove forming step, a cutting blade 16 that rotates at high speed in the direction of arrow A is cut into a predetermined division line 13 of the wafer 11 (a depth that does not reach the finished thickness of the wafer), and a chuck table (not shown) is moved in the direction of arrow X1. A groove 19 having a depth that does not reach the finished thickness is formed from the surface 11a of the wafer 11 along the planned dividing line 13 while being fed to the surface.
切削ユニット１０を分割予定ライン１３のピッチずつ割り出し送りしながら、第１の方向に伸長する全ての分割予定ライン１３に沿って溝１９を形成する。次いで、ウエーハ１１を吸引保持した図示しないチャックテーブルを９０°回転し、第１の方向と直交する第２の方向に伸長する分割予定ライン１３に沿って同様な溝１９を形成する。 Grooves 19 are formed along all the division lines 13 extending in the first direction while the cutting unit 10 is indexed and fed by the pitch of the division lines 13. Next, a chuck table (not shown) that sucks and holds the wafer 11 is rotated by 90 °, and a similar groove 19 is formed along the division line 13 that extends in a second direction orthogonal to the first direction.
この溝形成ステップでは、従来の先ダイシング法で形成する溝の深さに比べて浅い溝１９を形成する。このように浅い溝１９を形成するため、細粒径の砥粒を含有した切削ブレード１６が使用可能であり、溝形成時の表面チッピングを抑えることが可能である。 In this groove forming step, a groove 19 that is shallower than the groove formed by the conventional tip dicing method is formed. Since the shallow groove 19 is formed in this way, a cutting blade 16 containing fine abrasive grains can be used, and surface chipping during groove formation can be suppressed.
溝形成ステップを実施した後、ウエーハ１１の表面１１ａに保護テープ２１を貼着する保護テープ貼着ステップを実施する。図４は保護テープ貼着ステップ実施後の断面図を示している。 After performing the groove forming step, a protective tape adhering step for adhering the protective tape 21 to the surface 11a of the wafer 11 is performed. FIG. 4 shows a cross-sectional view after carrying out the protective tape attaching step.
保護テープ貼着ステップを実施した後、図５に示すように、レーザー加工装置のチャックテーブル１８で保護テープ２１を介してウエーハ１１を保持する保持ステップを実施する。この保持ステップを実施すると、ウエーハ１１の裏面１１ｂが露出される。 After performing the protective tape attaching step, as shown in FIG. 5, a holding step of holding the wafer 11 via the protective tape 21 is performed by the chuck table 18 of the laser processing apparatus. When this holding step is performed, the back surface 11b of the wafer 11 is exposed.
保持ステップを実施した後、図６に示すように、ウエーハ１１に対して透過性を有する波長のレーザービームＬＢの集光点Ｐを集光器２０でウエーハ１１内部の仕上げ厚みｔより裏面１１ｂ側に位置付けて、レーザービームＬＢをウエーハ１１の裏面１１ｂに向かって分割予定ライン１３に沿って照射し、分割予定ライン１３に沿った改質層２３を形成するとともに改質層２３から溝１９に向かって伸長する分割予定ライン１３に沿ったクラック層２５を形成するレーザー加工ステップを実施する。仕上げ厚みｔは例えば３００μｍである。 After performing the holding step, as shown in FIG. 6, the condensing point P of the laser beam LB having a wavelength transmissive to the wafer 11 is placed on the back surface 11 b side from the finished thickness t inside the wafer 11 by the condenser 20. The laser beam LB is irradiated along the planned division line 13 toward the back surface 11 b of the wafer 11 to form the modified layer 23 along the planned division line 13 and from the modified layer 23 toward the groove 19. Then, a laser processing step for forming the crack layer 25 along the dividing line 13 that extends is performed. The finished thickness t is, for example, 300 μm.
このレーザー加工ステップは、チャックテーブル１８を分割予定ライン１３のピッチずつ割り出し送りしながら、第１の方向に伸長する全ての分割予定ライン１３に沿って実施した後、チャックテーブル１８を９０°回転してから、第２の方向に伸長する全ての分割予定ライン１３に沿っても同様に実施する。 This laser processing step is performed along all the division lines 13 extending in the first direction while indexing and feeding the chuck table 18 by the pitch of the division lines 13, and then rotating the chuck table 18 by 90 °. After that, the same operation is performed along all the planned division lines 13 extending in the second direction.
このレーザー加工ステップにおける加工条件は、例えば次のように設定されている。 The processing conditions in this laser processing step are set as follows, for example.
光源 ：ＬＤ励起ＱスイッチＮｄ：ＹＶＯ４パルスレーザー
波長 ：１０６４ｎｍ
パルス出力 ：０．２Ｗ
繰り返し周波数 ：８０ｋＨｚ
集光スポット径 ：φ１μｍ
加工送り速度 ：１００ｍｍ／秒
Light source: LD excitation Q switch Nd: YVO 4 pulse laser Wavelength: 1064 nm
Pulse output: 0.2W
Repetition frequency: 80 kHz
Condensing spot diameter: φ1μm
Processing feed rate: 100 mm / sec
レーザー加工ステップを実施した後、ウエーハ１１の裏面１１ｂを研削手段で研削して仕上げ厚みｔへと薄化するとともに改質層２３を除去し、ウエーハ１１を分割予定ライン１３に沿ってデバイスチップ２７に分割する研削ステップを実施する。この研削ステップについて図７を参照して説明する。 After performing the laser processing step, the back surface 11b of the wafer 11 is ground by a grinding means to reduce the thickness to a finished thickness t and the modified layer 23 is removed. A grinding step is performed to divide into two. This grinding step will be described with reference to FIG.
研削ステップでは、図７に示すように、研削装置のチャックテーブル２２でウエーハ１１の表面１１ａ側を保護テープ２１を介して吸引保持し、ウエーハ１１の裏面１１ｂ側を露出させる。 In the grinding step, as shown in FIG. 7, the front surface 11 a side of the wafer 11 is sucked and held through the protective tape 21 by the chuck table 22 of the grinding device, and the back surface 11 b side of the wafer 11 is exposed.
研削装置の研削ユニット（研削手段）２４は、モータにより回転駆動されるスピンドル２６と、スピンドル２６の先端に固定されたホイールマウント２８と、ホイールマウント２８に複数のねじで着脱可能に固定された研削ホイール３０とを含んでいる。研削ホイール３０は、環状のホイール基台３２と、ホイール基台３２の下端外周部に環状に固着された複数の研削砥石３４とから構成される。 The grinding unit (grinding means) 24 of the grinding apparatus includes a spindle 26 that is rotationally driven by a motor, a wheel mount 28 that is fixed to the tip of the spindle 26, and a grinding that is detachably fixed to the wheel mount 28 with a plurality of screws. Wheel 30. The grinding wheel 30 includes an annular wheel base 32 and a plurality of grinding wheels 34 that are annularly fixed to the outer periphery of the lower end of the wheel base 32.
研削ステップでは、チャックテーブル２２を矢印ａ方向に例えば３００ｒｐｍで回転しつつ、研削ホイール３０をチャックテーブル２２と同一方向に、即ち矢印ｂ方向に例えば６０００ｒｐｍで回転させるとともに、図示しない研削ユニット送り機構を作動して、研削砥石３４をウエーハ１１の裏面１１ｂに接触させる。 In the grinding step, while rotating the chuck table 22 in the direction of arrow a at, for example, 300 rpm, the grinding wheel 30 is rotated in the same direction as the chuck table 22, that is, in the direction of arrow b at, for example, 6000 rpm. In operation, the grinding wheel 34 is brought into contact with the back surface 11 b of the wafer 11.
そして、研削ホイール３０を所定の研削送り速度で下方に所定量研削送りして、ウエーハ１１の研削を実施する。研削を続行してウエーハ１１を仕上げ厚みｔへと薄化すると、改質層２３が除去されるとともに分割予定ライン１３に沿ったクラック層２５に研削圧力が作用して、ウエーハ１１は図８に示すように、個々のデバイスチップ２７に分割される。 Then, the grinding wheel 30 is ground by a predetermined amount at a predetermined grinding feed speed, and the wafer 11 is ground. When the grinding is continued and the wafer 11 is thinned to the finished thickness t, the modified layer 23 is removed and a grinding pressure is applied to the crack layer 25 along the scheduled division line 13, so that the wafer 11 is shown in FIG. As shown, it is divided into individual device chips 27.
本実施形態の加工方法によると、デバイスチップ２７の裏面側はクラック層２５による分割であるため、チッピングの発生が抑制される。また、ウエーハ１１の表面１１ａ側に溝１９が形成されているため、研削中に隣接するチップ同士が接触しても、表面チッピングが発生することがなく、デバイス１５は損傷することがない。 According to the processing method of this embodiment, since the back surface side of the device chip 27 is divided by the crack layer 25, occurrence of chipping is suppressed. Further, since the groove 19 is formed on the surface 11a side of the wafer 11, even if adjacent chips come into contact with each other during grinding, surface chipping does not occur and the device 15 is not damaged.
ウエーハ１１の表面１１ａ側に溝１９が形成されるため、ウエーハ１１をチップ２７に分割しチップに分割されたウエーハ１１をダイシングテープに転写した後、洗浄をすることでチップ２７のデバイス１５側を十分に洗浄可能である。 Since the groove 19 is formed on the front surface 11a side of the wafer 11, the wafer 11 is divided into chips 27, and the wafer 11 divided into chips is transferred to a dicing tape, and then cleaned, thereby cleaning the device 15 side of the chip 27. It can be washed sufficiently.
また、本発明のウエーハの加工方法は、ウエーハ１１の分割予定ライン１３に沿ってＴＥＧ（Ｔｅｓｔ Ｅｌｅｍｅｎｔ Ｇｒｏｕｐ）等が形成されているウエーハに対して有効である。 The wafer processing method of the present invention is effective for a wafer in which a TEG (Test Element Group) or the like is formed along the division line 13 of the wafer 11.
１０ 切削ユニット
１１ 半導体ウエーハ
１３ 分割予定ライン
１５ デバイス
１６ 切削ブレード
１９ 溝
２０ 集光器（レーザーヘッド）
２１ 保護テープ
２３ 改質層
２４ 研削ユニット（研削手段）
２５ クラック層
２７ デバイスチップ
DESCRIPTION OF SYMBOLS 10 Cutting unit 11 Semiconductor wafer 13 Scheduled division line 15 Device 16 Cutting blade 19 Groove 20 Condenser (laser head)
21 Protective tape 23 Modified layer 24 Grinding unit (grinding means)
25 Crack layer 27 Device chip
Claims (1)
表面チッピングを抑えることができる程度の細粒径の砥粒を含有した切削ブレードをウエーハの表面から該分割予定ラインに沿って切り込ませ、ウエーハの厚みの半分より浅く仕上げ厚みに至らない深さの複数の溝を形成する溝形成ステップと、
該溝形成ステップを実施した後、ウエーハの表面に保護テープを貼着する保護テープ貼着ステップと、
該保護テープ貼着ステップを実施した後、該保護テープを介してウエーハをチャックテーブルで保持する保持ステップと、
該保持ステップを実施した後、ウエーハに対して透過性を有する波長のレーザービームの集光点をウエーハ内部の該仕上げ厚みより裏面側に位置付けて、該レーザービームをウエーハの裏面に向かって該分割予定ラインに沿って照射して、ウエーハ内部に該分割予定ラインに沿う改質層を形成するとともに該改質層から伸長して該溝に達し該分割予定ラインに沿うクラック層を形成するレーザー加工ステップと、
該レーザー加工ステップを実施した後、ウエーハの裏面を研削手段で研削して該仕上げ厚みへと薄化するとともに該改質層を除去し、ウエーハを該分割予定ラインに沿ってチップに分割する研削ステップと、
を備えたことを特徴とするウエーハの加工方法。 A wafer processing method in which a plurality of intersecting division lines are set,
A cutting blade containing abrasive grains with a fine grain size that can suppress surface chipping is cut from the surface of the wafer along the planned dividing line, and the depth is less than half the wafer thickness and does not reach the finished thickness. Forming a plurality of grooves, and
After performing the groove forming step, a protective tape attaching step of attaching a protective tape to the surface of the wafer;
A holding step of holding the wafer on the chuck table via the protective tape after performing the protective tape attaching step;
After carrying out the holding step, the condensing point of the laser beam having a wavelength that is transparent to the wafer is positioned on the back side of the finished thickness inside the wafer, and the laser beam is divided toward the back side of the wafer. was irradiated along the planned line to form along the Hare crack layer on the dividing line reaches the groove extends from the reforming layer to form a along the Hare reforming layer on the dividing lines within the wafer Laser processing step,
After the laser processing step is performed, the back surface of the wafer is ground by a grinding means to reduce the thickness to the finished thickness, and the modified layer is removed, and the wafer is divided into chips along the division line. Steps,
A wafer processing method characterized by comprising:
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| CN109743877B (en) * | 2016-10-03 | 2022-06-10 | 琳得科株式会社 | Adhesive tape for semiconductor processing and method for manufacturing semiconductor device |
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| WO2020017599A1 (en) * | 2018-07-19 | 2020-01-23 | 東京エレクトロン株式会社 | Substrate treatment system and substrate treatment method |
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| CN109590288B (en) * | 2018-11-28 | 2021-06-04 | 四川大学 | Method for laser cleaning impurities on the transmission surface of light-transmitting medium |
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| CN111987146A (en) * | 2020-09-21 | 2020-11-24 | 上海擎茂微电子科技有限公司 | A kind of wafer for preparing semiconductor device and backside thinning method of wafer |
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| DE60313900T2 (en) * | 2002-03-12 | 2008-01-17 | Hamamatsu Photonics K.K., Hamamatsu | Method for separating substrates |
| JP4440582B2 (en) * | 2003-09-10 | 2010-03-24 | 浜松ホトニクス株式会社 | Semiconductor substrate cutting method |
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