JP6227255B2 - Diode and manufacturing method thereof - Google Patents

Description

  The present invention relates to a diode, and more particularly to a diode applied to a high voltage, high current IGBT module or the like of a vehicle, an industrial device or the like.

  A diode used as a high-current switching element is required to have a high breakdown voltage of several thousand volts or more. In this element, in particular, the thickness of the n− layer and the like are specified and the breakdown voltage is maintained. In this case, the thicker the n− layer, the higher the breakdown voltage.

  However, on the other hand, it is effective to reduce the thickness of the n− layer in order to reduce recovery loss that occurs during recovery of the forward voltage or IGBT module. Therefore, in order to reduce the loss, the n-layer is made thin while ensuring a breakdown voltage.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2010-40562) and Patent Document 2 (Japanese Patent Laid-Open No. 1-258476), a deep nB (n buffer) layer is introduced to reduce the thickness of the n-layer, and the forward direction. It is disclosed to reduce voltage and loss. Patent Document 1 also discloses that the oscillation phenomenon is suppressed by introducing an nB layer in which the impurity concentration gradually decreases. In an IGBT module incorporating a diode, stable operation can be secured by suppressing this oscillation phenomenon.

JP 2010-40562 A JP-A-1-258476

  However, in these prior arts, no consideration is given to the thickness of the Si wafer and the relationship between it and the nB layer. Therefore, it has been difficult to construct a structure or impurity profile structure that can reduce loss while ensuring a breakdown voltage.

  The present invention has been made in consideration of the above-described problems, and an object of the present invention is to provide a diode structure capable of reducing loss while ensuring withstand voltage characteristics.

In order to solve the above problems, a diode according to the present invention has a cathode electrode on one surface and an anode electrode on the other surface of a Si wafer having a wafer thickness of 340 to 380 μm , a p + layer on the anode surface, and a p + layer on the cathode surface. An n + layer is provided, and an n-type dopant having a dose of 5 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻² is diffused from the same plane in a depth range of 50 to 130 μm to form a deep n buffer (nB) layer. Further, a shallow n buffer (nB) layer is formed by diffusing 20 μm or less of n-type dopant from the cathode surface.

  According to the present invention, it is possible to provide a diode with high breakdown voltage and low loss. This makes it possible to increase the operating temperature of the IGBT module.

Sectional drawing of the diode which is Example 1 of this invention. The impurity profile of the diode of FIG. Relationship between nB layer depth and recovery loss (Err). Relationship between nB layer depth and breakdown voltage (Vb). Relationship between nB layer depth and oscillation start power supply voltage (Vring). Relationship between Vb and Vring. Sectional drawing of the diode which is Example 2 of this invention. The impurity profile of the diode of FIG.

  The present inventor has studied a diode having the cross-sectional structure shown in FIG.

  FIG. 2 shows the impurity profile of this diode. The diffusion depth of the nB layer was the distance from the anode at a point where it increased by 10% with respect to the n-concentration of the base. The n-concentration is determined by the resistance value of the wafer. From the viewpoint of ensuring the cosmic ray resistance of the diode, it is set to 200 Ωcm or more.

  First, diffusion depth and recovery loss (Err) were examined. The result of the examination is shown in FIG. From this figure, it can be seen that Err does not depend on the diffusion depth, but decreases as the wafer thickness decreases. If the Err can be reduced by 10% compared to a 400 μm thick wafer diode that does not apply a deep nB layer, the diode module's built-in IGBT module can reduce the heat generated by the diode. Is possible. Therefore, the maximum junction temperature (Tjmax) can be increased from 125 ° C. to 150 ° C., for example. For this reason, the wafer thickness is preferably 380 μm or less. However, the wafer thickness may vary by 10 μm with respect to the specification value. For this reason, it is preferable to secure a withstand voltage characteristic for a wafer thickness of 370 μm.

  FIG. 4 shows the relationship between the diffusion depth and the breakdown voltage (Vb). From this figure, it can be seen that Vb decreases as the wafer thickness decreases. In the case of the same wafer thickness and the same nB dose, Vb tends to decrease as the diffusion depth increases. This tendency has been clarified from the study of the present inventors, and it has been found that the breakdown voltage does not increase simply by introducing a deep nB layer. In addition, from the study by the present inventor, it is also clear that Vb decreases with the dose amount of the nB layer.

  On the other hand, the relationship between the power supply voltage (Vring) at which oscillation starts and the wafer thickness is shown in FIG. Vring increases with increasing wafer thickness. Furthermore, it can be seen that Vring increases with increasing diffusion depth. Further, it has been clarified by the inventors that Vring increases as the dose of the nB layer increases.

  Vb falls about 20% from the room temperature value at -40 ° C. Therefore, Vb at room temperature is set to 3900 V or more for 3300V IGBT module applications. On the other hand, Vring is also set to 2000V or higher, which is about 20% higher than the normal voltage 1650V.

  Therefore, when a 370 μm wafer is applied, the diffusion depth is set to 50 μm or more and 130 μm or less. However, the withstand voltage and oscillation characteristics may be deteriorated by external charges. For this reason, the diffusion depth is more preferably set to 60 μm or more and 110 μm or less.

The wafer dependency of the relationship between Vb and Vring is shown in FIG. The figure also shows the nB dose dependency. From this figure, it can be seen that Vb and Vring satisfy the above conditions at least if the wafer thickness is set to 340 μm or more. As described above, the trade-off between Vb and Vring occurs depending on the dose amount of the nB layer. Therefore, it can be seen that a dose of 1 × 10 ¹² cm ⁻² is preferable for a wafer having a thickness of 340 μm. Also, 8 × 10 ¹¹ to 2 × 10 ¹² cm ^{−2 for} a 350 μm wafer, 6 × 10 ¹¹ to 4 × 10 ¹² cm ^{−2 for} a 360 μm wafer, and 5 × 10 ¹¹ to 1 × 10 ¹³ cm for a 370 μm wafer. A dose of ^-2 is preferred. The wafer thickness may deviate by ± 10 μm from the specification value. For this reason, it is preferable to satisfy the conditions of Vb and Vring with a wafer thickness of 10 μm. However, when the wafer thickness is thinner than the lower limit value, it is possible to sort by the pressure resistance inspection.

Thus, a dose of 5 × 10 ¹¹ to 1 × 10 ¹³ cm ^{−2 for} a 340-380 μm wafer, more preferably a dose of 6 × 10 ¹¹ to 4 × 10 ¹² cm ^{−2 for} a 340-370 μm wafer, and even more. Preferably, by forming an nB layer with a dose of 8 × 10 ¹¹ to 2 × 10 ¹² cm ⁻² on a 340-360 μm wafer, it is possible to form a diode with low loss and high reliability. A lower loss diode can reduce the loss of the IGBT module in which the diode is incorporated, and can expand the operable temperature range.

  When forming this nB layer, it is desirable to use P as a dopant from the viewpoint of influence on other processes and apparatuses. In the case of As, the diffusion coefficient is small and time is required for diffusion. Further, in the case of P, even if it is discharged from the wafer by out-diffusion or the like and contaminates the apparatus or the like, since P is used for the n + layer or the like, the furnace body and the like can be managed together. In the case of other elements, contamination due to out-diffusion is often a problem in line management.

  In the case of P, a relatively long diffusion process is performed to form a deep nB layer. It becomes possible to process within 10 days by diffusing at a diffusion temperature of 1290 ° C. or higher. Therefore, it is desirable to diffuse above this temperature. In addition, when the p layer and the n + layer are formed in the subsequent process, it is possible to perform the treatment below this temperature. For example, when p is formed by diffusing B, a high temperature of 1200 ° C. can be applied, and the diffusion time can be shortened.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view of a main part of a diode according to a first embodiment of the present invention.

A 50 nm oxide film was formed by thermal oxidation on the back surface of the n-type Si wafer 1 having a thickness of 360 μm, and then P was ion-implanted at a concentration of 1 × 10 ¹² cm ⁻² . Thereafter, diffusion is performed at 1300 ° C. for 120 h to form a deep nB layer 2 having a depth of 80 μm.

Subsequently, B is ion-implanted in order to form the p + layer 3 on the surface serving as the anode. In this example, the dose amount of B was 5 × 10 ¹³ cm ⁻² . Thereafter, diffusion is performed at 1200 ° C. in order to diffuse B on the surface.

In order to form the n + layer 4 on the back surface, P is implanted into the back surface at a dose of 1 × 10 ¹⁵ cm ⁻² . Then, heat treatment is performed at 1000 ° C. to activate P. Through the above steps, the diffusion and activation heat treatment temperatures are sequentially lowered from the nB layer formation to the n + layer formation, so that an impurity profile can be formed with high accuracy.

  Next, Al is formed as an anode electrode and processed into an anode electrode pad by a mask process. Further, a polyimide protective film is formed using a photo process. Further, Au / Ni / Ti / AlSi is formed as a cathode electrode.

  The Si wafer on which the plurality of diode chips are formed by the above manufacturing process is diced to cut out the diode chips. An IGBT module in which the diode of this embodiment is combined with an IGBT has improved breakdown voltage and oscillation characteristics, and can make recovery loss extremely small.

  FIG. 7 is a cross-sectional view of an essential part of the diode of the second embodiment of the present invention. FIG. 8 shows the impurity profile of this diode.

An oxide film of 50 nm is formed on the back surface of the n-type Si wafer 1 having a thickness of 370 μm by the same method as in Example 1, and then P is ion-implanted at a dose of 2 × 10 ¹² cm ⁻² . Thereafter, diffusion is performed at 1300 ° C. for 120 h to form a deep nB layer 2 having a depth of 80 μm.

Next, P is ion-implanted into the back surface at a dose of 2 × 10 ¹² cm ⁻² . Thereafter, diffusion is performed to a depth of 15 μm at 1200 ° C. to form a shallow nB layer 5. The shallow nB layer is desirably 20 μm or less so as not to affect the breakdown voltage characteristics. By thus forming the nB layer in two stages, it is possible to prevent breakdown voltage degradation due to n + defects and Al spikes on the back electrode.

Subsequently, B is ion-implanted in order to form the p + layer 3 and the p− layer 6 on the surface serving as the anode. In this embodiment, a mask process is applied and B is implanted in two types of doses. As the dose amount of B, 5 × 10 ¹³ cm ⁻² and 5 × 10 ¹² cm ⁻² are applied. Thereafter, diffusion is performed at 1100 ° C. in order to diffuse B on the surface.

In order to form the n + layer 4 on the back surface, P was implanted into the back surface at a dose of 1 × 10 ¹⁵ cm ⁻² . Then, heat treatment is performed at 1000 ° C. to activate P. Through the above steps, the diffusion and activation heat treatment temperatures are sequentially lowered from the nB layer formation to the n + layer formation, so that an impurity profile can be formed with high accuracy.

  Next, Al is formed as an anode electrode and processed into an anode electrode pad by a mask process. Further, a polyimide protective film is formed using a photo process. Further, Au / Ni / Ti / AlSi is formed as a cathode electrode.

  The Si wafer on which the plurality of diode chips are formed by the above manufacturing process is diced to cut out the diode chips. An IGBT module in which the diode of this embodiment is combined with an IGBT has improved breakdown voltage and oscillation characteristics, and can make recovery loss extremely small.

DESCRIPTION OF SYMBOLS 1 ... n-layer 2 ... nB layer 3 ... p + layer 4 ... n + layer 5 ... nB layer 6 ... p- layer

Claims (4)

In Si wafers 380μm from the wafer thickness 340, a cathode electrode on one surface, has an anode electrode on the other surface, p + layer on the anode surface, comprises an n + layer on the cathode surface, from 5 × 10 ¹¹ from the same surface An n-type dopant having a dose of 1 × 10 ¹³ cm ⁻² is diffused in a depth range of 50 to 130 μm to form a deep n buffer (nB) layer, and further, the n-type dopant is diffused to 20 μm or less from the cathode surface. And a shallow n buffer (nB) layer. In claim 1,
The diode, wherein the n-type dopant is P. In claim 1,
The resistivity of the Si wafer is 200 Ωcm or more. The p + layer, before forming the n + layer, the n-type dopant ions are implanted, diffused 50μm or more at 1290 ° C. or higher to form the deep n buffer (nB) layer, then further injecting n-type dopant 2. The method of manufacturing a diode according to claim 1, wherein the shallow n buffer (nB) layer having a depth of 20 μm or less is formed by diffusion.