JP6204131B2 - Light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a light emitting device and a method for manufacturing the same, and more particularly, a light emitting diode (LED) formed by bonding a semiconductor light emitting layer grown on a growth substrate to a support substrate and then removing the growth substrate. The present invention relates to an element and a manufacturing method thereof.

  In recent years, a semiconductor light-emitting laminate that has been grown on a growth substrate (or temporary substrate) by a vapor phase growth method such as MOCVD (Metal-Organic Chemical Vapor Deposition) is bonded to a conductive support substrate, and then the growth substrate is attached. A removed LED (also referred to as a metal bonding structure or MB structure) is used. For example, Patent Document 1 discloses an LED element having a structure in which a growth substrate is removed, in which an electrode is embedded in a semiconductor layer closer to the light extraction surface than the active layer.

Special table 2010-525585

  However, in the light emitting element as described above, the current is diffused in the horizontal direction (in-plane direction) because the film thickness of the semiconductor layer is thinner than the chip size as compared with the LED fabricated on the conductive growth substrate. Difficult to concentrate current. In particular, in an LED element having a configuration as disclosed in Patent Document 1, current concentrates around an electrode embedded in a semiconductor layer closer to the light extraction surface than the active layer, and the luminous efficiency of the LED element. Decrease in reliability and reliability.

  The present invention has been made in view of the above-described points, and an object thereof is to provide a high-performance light-emitting element having good in-plane current diffusion, high luminous efficiency and high reliability, and a method for manufacturing the same.

  The light-emitting element of the present invention includes a semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked. A light-emitting element having a surface of the semiconductor layer as a light extraction surface, a groove penetrating the second semiconductor layer and the active layer from the second semiconductor layer side and reaching the first semiconductor layer; An insulating layer covering the second semiconductor layer and the active layer exposed from the trench; a first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the trench; A second ohmic electrode formed on the surface of the second semiconductor layer, and the first semiconductor layer is partially formed in the first semiconductor layer in contact with the ohmic electrode And having a lower electrical resistivity than other portions of the first semiconductor layer. Wherein the of containing the low-resistance region.

  In the method for manufacturing a light-emitting element according to the present invention, a semiconductor in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked on a first substrate. Forming a structural layer; forming a groove extending from the second semiconductor layer through the second semiconductor layer and the active layer into the first semiconductor layer; and exposing from the groove Forming an insulating layer covering the second semiconductor layer and the active layer, and forming an opening exposing the first semiconductor layer in the insulating layer at the bottom of the groove, Forming a first ohmic electrode connected to the first semiconductor layer; forming a second ohmic electrode on the second semiconductor layer; and implanting ions into the first semiconductor layer. Go in the first semiconductor layer in the Characterized in that it comprises forming a low resistance region having low electrical resistivity than the rest of the the region in contact with the first ohmic electrode and the first semiconductor layer.

It is sectional drawing of the light emitting element which is Example 1 of this invention. 2A to 2E are cross-sectional views showing respective manufacturing steps of the light emitting device shown in FIG. It is sectional drawing of the light emitting element which is Example 2 of this invention. 4A and 4B are cross-sectional views of light-emitting elements that are modifications of the first embodiment. 5A and 5B are cross-sectional views of light-emitting elements that are modifications of the second embodiment.

  In the examples described below, the case where the semiconductor structure layer is composed of a first semiconductor layer, a light emitting layer, and a second semiconductor layer will be described for ease of explanation and understanding. Each of the second semiconductor layer and the light emitting layer may be composed of a plurality of layers. For example, the semiconductor layer may include a carrier injection layer, a barrier layer for preventing carrier overflow, a current diffusion layer, a contact layer for improving ohmic contact, a buffer layer, and the like. Further, the conductivity types of the first semiconductor layer and the second semiconductor layer may be opposite to those of the following embodiments.

  In the following, preferred embodiments of the present invention will be described, but these may be appropriately modified and combined. In the following description and the accompanying drawings, substantially the same or equivalent parts will be described with the same reference numerals.

FIG. 1 is a cross-sectional view of a light-emitting element 10 that is Embodiment 1 of the present invention. In FIG. 1, the current flowing between the electrodes in the light emitting element 10 is indicated by a one-dot chain arrow. The light-emitting element 10 includes a GaN-based (Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y) having a structure in which the light-emitting element structure 20 and the support 30 are bonded via a bonding layer 35. ≦ 1)) light emitting diode (LED).

  More specifically, the light-emitting element structure (hereinafter, also simply referred to as an element structure) 20 has a first conductivity type first semiconductor layer 11, an active layer 13, and a conductivity opposite to the first conductivity type. The semiconductor structure layer 17 is a light emitting functional layer in which a second semiconductor layer 15 of a second conductivity type is stacked. In this embodiment, a case where the first semiconductor layer 11 is an n-type semiconductor layer and the second semiconductor layer 15 is a p-type semiconductor layer will be described as an example.

The first semiconductor layer 11 is a layer including an n-type semiconductor layer to which an n-type dopant such as Si is added. The active layer 13 has a multiple quantum well structure configured by repeatedly laminating a GaN layer and an In _x Ga _1-x N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) layer. The second semiconductor layer 15 is a p-type semiconductor layer to which a p-type dopant such as Mg is added. The surface 11S of the first semiconductor layer 11 (that is, the upper surface of the semiconductor structure layer 17) functions as a light extraction surface.

  On the lower surface of the semiconductor structure layer 17, a groove 17 </ b> G extending from the second semiconductor layer 15 through the active layer 13 to the first semiconductor layer 11 is formed. On the lower surface of the second semiconductor layer 15, a p-electrode 19 in which, for example, Ti / Ag or ITO / Ag is stacked in this order is formed on the second semiconductor layer 15. The cap layer 21 is formed so as to bury the p-electrode 19 on the lower surface of the second semiconductor layer 15 and is made of, for example, TiW.

The insulating layer 23 is an insulating layer formed so as to cover the surface from which the semiconductor structure layer 17 is exposed and the cap layer 21, and is made of, for example, SiO ₂ or SiN. The insulating layer 23 has an opening 23 </ b> A that exposes the bottom surface of the groove 17 </ b> G, and an opening 23 </ b> B that exposes the cap layer 21 in the end region of the light emitting element 10.

  The n-electrode 25 as an ohmic electrode is connected to the first semiconductor layer 11 exposed from the opening 23A on the bottom surface of the groove 17G, and is formed on the insulating layer 23 formed on the side surface of the groove 17G. A p-feed electrode 27 connected to the cap layer 21 exposed from the opening 23B is formed. The n power supply electrode 29 is formed so as to cover the insulating layer 23 and the n electrode 25 in a region other than the end region where the p power supply electrode 27 is formed. The n power supply electrode 29 is formed away from the p power supply electrode 27 and is electrically insulated from the p power supply electrode 27. Note that the p-feed electrode 27 and the n-feed electrode 29 are each connected to a current supply source outside the light-emitting element 10. That is, in the light emitting element 10, the current is supplied to the semiconductor structure layer 17 from the p feeding electrode 27 and the n feeding electrode 29 through the p electrode 19 and the n electrode 25, respectively.

  In the first semiconductor layer 11, a low resistance region 11 </ b> A having a higher carrier concentration and lower electrical resistivity than the other region of the first semiconductor layer 11 is formed on the n electrode 25 in contact with the n electrode 25. Has been. That is, the low resistance region 11 </ b> A is formed so as to cover the surface where the n electrode 25 is in contact with the first semiconductor layer 11. In other words, the low resistance region 11A is partially provided in the first semiconductor layer 11 in contact with the bottom of each of the grooves 17G. That is, each of the low resistance regions 11A is provided so as to be separated from each other, and there is another region having a higher electrical resistivity than the low resistance region 11A of the first semiconductor layer 11 between the adjacent low resistance regions 11A. doing. The low resistance region 11A is formed from a depth d1 in contact with the n-electrode 25 to a depth d2 that does not reach the surface 11S of the first semiconductor layer 11 (FIG. 2E). That is, the low resistance region 11A is partially formed in the first semiconductor layer 11 both in the in-plane direction and in the depth direction of the first semiconductor layer 11 as described above.

  As shown in FIG. 1, the support 30 has a support substrate 31 with good heat dissipation such as Si, and an insulating layer 33 formed on the surface of the support substrate 31 facing the light emitting element structure 20. The element structure 20 is bonded by a bonding layer 35 which is a metal layer formed on the insulating layer 33. More specifically, the bonding layer 35 is formed in a region facing the region where the bonding layer 35A formed in the region facing the region where the n feeding electrode 29 is formed and the region where the p feeding electrode 27 is formed. It consists of a bonding layer 35B. Note that the bonding layer 35A and the bonding layer 35B are formed apart from each other and are electrically insulated from each other.

  In the light emitting element 10 of Example 1, the low resistance region 11A having a higher carrier concentration than the other regions of the first semiconductor layer 11 is disposed in contact with the n electrode 25. Thereby, the contact resistance between the n-electrode 25 and the first semiconductor layer 11 can be kept low. Therefore, the Joule loss generated between the n electrode 25 and the first semiconductor layer 11 when current is injected from the n electrode 25 to the first semiconductor layer 11 is suppressed, and the current to the semiconductor structure layer 17 is reduced. It is possible to improve injection efficiency and light emission efficiency. Further, since the low resistance region 11A having a low electrical resistivity is formed in the current path, the resistance value of the entire current path of the light emitting element 10 can be lowered, and the operating resistance can be lowered.

  In the light emitting device 10 of Example 1, the current injected from the n-electrode 25 into the first semiconductor layer 11 is first diffused in the low resistance region 11A having a lower electrical resistivity than the other regions. Thereafter, a current is injected into the other region of the first semiconductor layer 11 from the entire surface of the low resistance region 11A having an area larger than the interface between the n-electrode 25 and the first semiconductor layer 11. Therefore, as shown by a one-dot chain line arrow in FIG. 1, the current is diffused well in the first semiconductor layer 11, current concentration in the light emitting element 10 is prevented, and the light emission efficiency of the light emitting element is improved. .

[Method for Manufacturing Light-Emitting Element 10]
The manufacturing method of the light emitting element 10 which is Example 1 is demonstrated in detail below. 2A to 2E are cross-sectional views illustrating each manufacturing process of the light-emitting element 10 of Example 1. FIG.

[Formation of light emitting element structure]
First, crystal growth is performed using a MOCVD (Metal-Organic Chemical Vapor Deposition) method to form the semiconductor structure layer 17. Specifically, the growth substrate 37 such as a sapphire substrate is put into an MOCVD apparatus, and after the thermal cleaning, the first semiconductor layer 11, the active layer 13, and the second semiconductor layer 15 are sequentially formed.

  Next, as shown in FIG. 2A, a p-electrode 19 and a cap layer 21 are formed. The p-electrode 19 is formed by sequentially depositing Ti / Ag or ITO / Ag or the like on the second semiconductor layer 15 to a thickness of about 100 to 300 nm by, for example, sputtering or electron beam (EB) evaporation. It is formed by patterning to the shape. The cap layer 21 is formed by forming a TiW film so as to embed the p-electrode 19 by, for example, a sputtering method or an electron beam (EB) vapor deposition method, and patterning it into a predetermined shape similar to the p-electrode. In order to improve the wiring resistance of the p electrode 19, the cap layer 21 may be formed by depositing TiW / Ti / Pt / Au / Ti on the p electrode 19 in this order.

Next, as illustrated in FIG. 2B, an insulating film 39 is formed so as to cover the surface of the second semiconductor layer 15 and the cap layer 21. The insulating film 39 is formed by forming an insulating material such as SiO ₂ or SiN by, for example, sputtering or CVD (Chemical Vapor Deposition).

Next, as shown in FIG. 2C, a groove is formed in the first semiconductor layer 11, a part of the insulating film 39 is removed to complete the insulating layer 23, and then an n-electrode 25 is formed. . Specifically, first, in the region between each of the p-electrode 19 and the cap layer 21, the first semiconductor layer 11 is exposed through the insulating film 39, the second semiconductor layer 15, and the active layer 13. A groove 17G is formed in the groove. The groove 17G is formed, for example, by dry etching the insulating film 39, the second semiconductor layer 15, and the active layer 13 by reactive ion etching (RIE) or the like. Thereafter, an insulating film made of an insulating material such as SiO ₂ or SiN is formed in the same manner as the insulating film 39 so as to cover the active layer 13 and the second semiconductor layer 15 exposed from the side surface of the groove 17G. 23 is completed. Thereafter, the n-electrode 25 is formed so as to cover the surface of the first semiconductor layer 11 exposed from the opening 23A at the bottom of the groove 17G and to cover the portion formed on the side surface of the groove 17G of the insulating layer 23. . The n electrode 25 is formed by patterning after forming a film in a thickness of, for example, 300 nm or more in the order of Ti / Al or Ti / Ag from the surface of the first semiconductor layer 11.

Next, as shown in FIG. 2D, a p-feed electrode 27 and an n-feed electrode 29 are formed. Specifically, first, an opening 23B that exposes a part of the cap layer 21 in a region where the p-feed electrode 27 is to be formed is formed. The opening 23B is formed by partially removing the insulating layer 23 by wet etching or dry etching. Next, for example, Ti / Pt / Au is deposited in this order by EB vapor deposition or the like so as to cover the insulating layer 23, the n-electrode 25, and the cap layer 21 exposed from the opening 23B, and then patterned into a predetermined shape. A p-feed electrode 27 and an n-feed electrode 29 are formed. At this time, the p-feed electrode 27 and the n-feed electrode 29 are patterned so as to be separated from each other and electrically insulated. The light emitting element structure 20 is completed through the above steps. When a plurality of light emitting element structures 20 are formed on one growth substrate, the light emitting element structures 20 are separated into pieces by, for example, dry etching.
[Formation of support and adhesion to support]
First, the support 30 is formed by forming the insulating layer 33 made of, for example, SiO ₂ or SiN on one surface of the support substrate 31 made of Si or the like. Thereafter, bonding layers 35 </ b> A and 35 </ b> B made of Au are formed as a bonding layer with the light emitting element structure 20 on the insulating layer 33 of the support 30. For forming the bonding layers 35 </ b> A and 35 </ b> B, an appropriate method can be used from, for example, resistance heating, EB vapor deposition, and sputtering.

  Next, the element structure 20 and the support body 30 are joined by, for example, thermocompression bonding. More specifically, so-called Au / Au bonding was performed by thermocompression bonding of Au, which is the outermost layer of the p-feed electrode 27 and the n-feed electrode 29 of the element structure 20, and Au forming the bonding layers 35A and 35B. . Note that the bonding method and materials are not limited to the above-described methods and materials, and for example, bonding using eutectic bonding using AuSn or the like may be performed.

[Removal of growth substrate]
After bonding the element structure 20 and the support 30, the growth substrate 37 is removed. By removing the growth substrate 37, the surface 11S of the first semiconductor layer 11 is exposed and becomes a light extraction surface. The growth substrate 37 was removed using a laser lift-off method. The removal of the growth substrate 37 is not limited to laser lift-off, and may be performed by wet etching / dry etching, mechanical polishing, chemical mechanical polishing (CMP), or a combination including at least one of them.

[Formation of low resistance region]
After removing the growth substrate 37, the low resistance region 11A is formed. The low resistance region 11A is formed by doping impurities (Si) into the first semiconductor layer 11 using, for example, an ion implantation method using a metal mask. By using the ion implantation method, a desired amount (for example, about 10 times the amount that can be doped in a normal semiconductor layer growth step) is added to a desired region of the first semiconductor layer without reducing the crystallinity of the semiconductor structure layer 17. It is possible to dope impurities). In the ion implantation, the acceleration voltage is adjusted so that the region where the n electrode 25 is in contact with the first semiconductor layer 11 is doped with impurities, that is, the low resistance region 11A is formed in contact with the n electrode 25. More specifically, by adjusting the acceleration voltage, a region from the depth d1 in contact with the n electrode 25 to the predetermined depth d2 (FIG. 2E) from the surface 11S of the first semiconductor layer 11 as described above is obtained. The low resistance region 11A can be obtained. In addition, after the low resistance region 11A is formed by ion implantation, annealing, which is an implanted impurity, can be activated to further reduce the resistance of the low resistance region 11A.

  Hereinafter, a light-emitting element 40 that is Embodiment 2 of the present invention will be described with reference to FIG. In FIG. 3, the current flowing between the electrodes of the light emitting element 40 is indicated by a one-dot chain arrow. The light emitting element 40 has the same configuration as that of the light emitting element 10 according to the first embodiment except that the configuration of the low resistance region is different.

  In the light emitting element 40, the low resistance region 41 includes a first low resistance region 41A and a second low resistance region 41B. The first low resistance region 41A is a low resistance region similar to the low resistance region 11A of the light emitting element 10 according to the first embodiment. That is, the first low-resistance region 41A is formed in contact with the surface exposed to the first semiconductor layer 11 of the n-electrode 25, and has more carriers than the other regions of the first semiconductor layer 11. This is a region where the concentration is high and the electrical resistivity is low. The low resistance region 41A is partially formed in a region having a depth where the low resistance region 41A in the first semiconductor layer 11 is formed. That is, the first semiconductor layer 11 includes a low resistance region 41A and another region having a higher electrical resistivity than the low resistance region 41A in the depth region where the low resistance region 41A is formed. .

  The second low resistance region 41B is a region having a higher carrier concentration and a lower electrical resistivity than the portion of the first semiconductor layer 11 excluding the first low resistance region 41A. The surface 11S of the first semiconductor layer 11, that is, the entire surface of the light extraction surface, is formed from the light extraction surface to a depth reaching the upper surface of the first low resistance region 41A. In other words, in the second low resistance region 41B, each of the first low resistance regions 41A is connected to the second low resistance region 41B on the upper surface thereof.

  By forming the low-resistance region 41 having the above-described configuration, the contact resistance between the n-electrode 25 and the first semiconductor layer 11 is kept low, similarly to the light-emitting element 10 according to the first embodiment. It is possible to prevent Joule loss that occurs between the first semiconductor layer 11 and the current injection efficiency into the semiconductor structure layer 17, thereby improving the light emission efficiency. Further, the resistance value of the entire current path of the light emitting element 10 can be lowered, and the operating resistance can be lowered.

  Furthermore, in the light emitting element 40, the current injected from the n electrode 25 into the first low resistance region 41A as shown by the one-dot chain line arrow in FIG. 3 is greater than the other regions from the first low resistance region 41A. First, it flows into the second low-resistance region 41B having low resistance. Thereafter, the current diffuses in the in-plane direction of the light emitting element 40 in the second low resistance region 41B, and the current flows in the semiconductor structure layer 17 from the entire lower surface of the second low resistance region 41B toward the p-electrode 19. . Accordingly, the first semiconductor layer 11 is sufficiently diffused in the in-plane direction, and current diffusion in the semiconductor structure layer 17 is promoted. Note that the second low resistance region 41B is farther from the p electrode 19 than the n electrode 25 and the first low resistance region 41A, and this also causes a semiconductor structure as compared with the light emitting element 10 of Example 1. Current spreading in layer 17 is facilitated. Thereby, according to the light emitting element 40, light emission efficiency improves and it is possible to prevent light emission unevenness on the light extraction surface of the light emitting element.

  The low resistance region 41B is formed after the low resistance region 41A is formed in contact with the n-electrode 25 in the same manner as the low resistance region 11A of the light emitting element 10 of the first embodiment. The low resistance region 41B is formed by implanting impurities into the entire surface of the light extraction surface of the first semiconductor layer 11 from the light extraction surface to the upper surface of the low resistance region 41A by ion implantation. The formation position (depth region) of the low resistance region 41B can be performed by adjusting the acceleration voltage. After forming the low resistance regions 41A and 41B, annealing in the same manner as in the manufacturing method of Example 1 activates the impurities in the low resistance region 41, and the light emitting element 40 is completed.

  In the above embodiment, a concavo-convex structure for improving the light extraction efficiency may be formed on the surface 11S (light extraction surface) of the first semiconductor layer 11. Such a concavo-convex structure is obtained by wet etching the light extraction surface of the first semiconductor layer 11 with TMAH after the growth substrate 37 is removed, before the low resistance regions 11A and 41 are formed, or after the low resistance regions 11A and 41 are formed. Form. In addition, a mask pattern having an artificial periodic structure is formed on the n-clad layer 12 by a method such as photolithography, EB lithography, EB drawing, nanoimprinting, laser exposure, and the lift-off method, followed by dry etching to form a concavo-convex structure. May be.

  In Example 1, the low resistance region 11A is illustrated as being formed only in the region on the surface of the n-electrode 25 that is in contact with the first semiconductor layer 11, but the formation range of the low resistance region 11A is illustrated. It is not limited to the embodiment. For example, as shown in FIG. 4A, the light emitting element 10 extends in the in-plane direction, and in a plane parallel to the first semiconductor layer 11, the surface of the n-electrode 25 is in contact with the first semiconductor layer 11. It may be formed in a wide area. In addition, as shown in FIG. 4B, the low resistance region 11A may extend upward to reach the light extraction surface of the first semiconductor layer 11. As described above, by configuring the low resistance region 11A to extend in the in-plane direction of the light emitting element 10 or the direction perpendicular to the in-plane direction, current diffusion in the semiconductor structure layer 17 can be further improved. is there.

  In the second embodiment, the second low resistance region 41B is illustrated as reaching the light extraction surface in the entire in-plane direction of the light emitting element 40 of the first semiconductor layer 41B. The formation range of the low resistance region 41B is not limited to the illustrated embodiment. The second low resistance region 41B is formed closer to the light extraction surface side of the first semiconductor layer 11 than the first low resistance region 41A, in contact with the first low resistance region 41A. That is, it is only necessary to be formed in a wider area in the plane parallel to the first semiconductor layer 11 than the first low resistance area 41A (viewed from the direction perpendicular to the plane). For example, as shown in FIG. 5A, the second low resistance region 41B may be formed in a depth region separated from the surface 11S (light extraction surface) of the first semiconductor layer 11. Further, as shown in FIG. 5B, the second low resistance regions 41B may be formed discontinuously, that is, separated from each other. Further, the second low resistance region 41B may be formed to a region deeper than the upper surface of the first low resistance region 41A.

  The above-described embodiments can be applied by appropriately combining or modifying them. Moreover, the above-described materials, numerical values, and the like are merely examples.

DESCRIPTION OF SYMBOLS 10, 40 Light emitting element 11 1st semiconductor layer 11A Low resistance area | region 11S Surface 13 Active layer 15 2nd semiconductor layer 17 Semiconductor structure layer 17G Groove 19 P electrode 21 Cap layer 23, 33 Insulating layer 23A, 23B Opening 25 n Electrode 27 p power supply electrode 29 n power supply electrode 30 support 31 support substrate 35 bonding layer 37 growth substrate 39 insulating film 41 low resistance region 41A first low resistance region 41B second low resistance region

Claims (6)

A semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer are sequentially stacked, and the surface of the first semiconductor layer is a light extraction surface; A light emitting element
A groove that penetrates through the second semiconductor layer and the active layer from the second semiconductor layer side and reaches the first semiconductor layer;
An insulating layer covering the second semiconductor layer and the active layer exposed from the groove;
A first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the groove;
A second ohmic electrode formed on the surface of the second semiconductor layer,
It said first semiconductor layer, said partially formed in contact with the first ohmic electrode on the first semiconductor layer, and a low electrical resistivity than the rest of the first semiconductor layer the look including a first low resistance region, the first low resistance region is wider than said first exposed surface on a semiconductor layer of a first of said semiconductor layer parallel to a plane first ohmic electrode A light-emitting element formed in a region . A semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer are sequentially stacked, and the surface of the first semiconductor layer is a light extraction surface; A light emitting element
  A groove that penetrates through the second semiconductor layer and the active layer from the second semiconductor layer side and reaches the first semiconductor layer;
  An insulating layer covering the second semiconductor layer and the active layer exposed from the groove;
  A first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the groove;
  A second ohmic electrode formed on the surface of the second semiconductor layer,
  The first semiconductor layer is partly formed in the first semiconductor layer in contact with the first ohmic electrode, and has a lower electrical resistivity than the other part of the first semiconductor layer. 1. A light-emitting element including one low-resistance region, wherein the first low-resistance region reaches the surface of the first semiconductor layer. A semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer are sequentially stacked, and the surface of the first semiconductor layer is a light extraction surface; A light emitting element
  A groove that penetrates through the second semiconductor layer and the active layer from the second semiconductor layer side and reaches the first semiconductor layer;
  An insulating layer covering the second semiconductor layer and the active layer exposed from the groove;
  A first ohmic electrode formed in contact with the first semiconductor layer exposed from the bottom of the groove;
  A second ohmic electrode formed on the surface of the second semiconductor layer,
  The first semiconductor layer is partly formed in the first semiconductor layer in contact with the first ohmic electrode, and has a lower electrical resistivity than the other part of the first semiconductor layer. 1 low resistance region,
  The first semiconductor layer is formed on the surface side of the first semiconductor layer with respect to the first low resistance region and in contact with the first low resistance region, and is formed on the first semiconductor layer. A second electrode having a lower electric resistance than a portion of the first semiconductor layer excluding the first low-resistance region, which is formed in a region wider than the first low-resistance region in a parallel plane. A light-emitting element including the low-resistance region. 4. The light emitting device according to claim 1, wherein the first low resistance region is formed to a depth that does not reach a surface of the first semiconductor layer. 5.   Forming a semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked on a first substrate;
  Forming a groove extending from the second semiconductor layer through the second semiconductor layer and the active layer into the first semiconductor layer;
  Forming an insulating layer covering the second semiconductor layer and the active layer exposed from the trench;
  Forming an opening exposing the first semiconductor layer in the insulating layer at the bottom of the groove, and forming a first ohmic electrode connected to the first semiconductor layer in the opening;
  Forming a second ohmic electrode on the second semiconductor layer;
  A low resistance region having a lower electrical resistivity than other portions of the first semiconductor layer in a region in contact with the first ohmic electrode in the first semiconductor layer by performing ion implantation in the first semiconductor layer Forming, and
  The low resistance region is formed in a region wider than a surface exposed to the first semiconductor layer of the first ohmic electrode in a plane parallel to the first semiconductor layer. Production method. Forming a semiconductor structure layer in which a first semiconductor layer, an active layer, and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer are sequentially stacked on a first substrate;
Forming a groove extending from the second semiconductor layer through the second semiconductor layer and the active layer into the first semiconductor layer;
Forming an insulating layer covering the second semiconductor layer and the active layer exposed from the trench;
Forming an opening exposing the first semiconductor layer in the insulating layer at the bottom of the groove, and forming a first ohmic electrode connected to the first semiconductor layer in the opening;
Forming a second ohmic electrode on the second semiconductor layer;
A low resistance region having a lower electrical resistivity than other portions of the first semiconductor layer in a region in contact with the first ohmic electrode in the first semiconductor layer by performing ion implantation in the first semiconductor layer look including the steps of: forming a,
A method for manufacturing a light-emitting element, characterized in that the low-resistance region reaches the surface of the first semiconductor layer .

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