JP6199206B2 - Sampling energy meter - Google Patents

Description

  The present invention relates to a watt-hour meter that measures a pulse formed by a sampling method, and more particularly to a device that makes a pulse formation error zero.

  The sampling watt-hour meter converts the input voltage and current into digital signals with an A / D converter, multiplies them to obtain digital power values, and integrates the power values for a predetermined time to calculate the power amount value. To do. Then, the number of pulses corresponding to the calculated electric energy value is output.

  A / D conversion is performed using a sampling clock. As a general-purpose watt-hour meter, a type of watt-hour meter whose sampling clock is not synchronized with an input signal to be measured is used. This type has a simple circuit configuration and is widely used.

  However, if the sampling clock is not synchronized with the input signal, jitter will occur in the formed pulse, and an error will occur in a short time, making it impossible to measure the electric energy with high resolution.

  Therefore, an watt-hour meter serving as a reference device has been provided, in which a sampling clock is generated in synchronization with an input signal for an application that requires high-precision power measurement in a short time.

  FIG. 6 shows a configuration of a conventional high-accuracy watt-hour meter using a sampling clock synchronized with an input signal. This applies an input voltage of f [Hz] to the rectangular wave converter 101, forms a voltage synchronization signal and applies it to the PLL circuit 102, thereby forming a sampling clock of nf [Hz], and an A / D converter 103. , 104.

Thus, the A / D converter 103 digitally converts the voltage signal, and the A / D converter 104 digitally converts the current signal to form a voltage signal v _mk and a current signal i _mk, which are supplied to the multiplier 105 and supplied to the instantaneous power. _Find p _mk [W]. Here, the subscripts m and k indicate k-th data in the m-th cycle of the sample (hereinafter the same).

The instantaneous power p _mk is given to a power calculator 10 having an instantaneous power integrator 106, an averaging circuit 107, and a frequency setter 108, and a frequency setting signal f _m = p _m / r [Hz] corresponding to the measured power is obtained. Formed and applied to the digital oscillator 109.

Here, in the power calculator 10, the frequency setter 108 resets the instantaneous power integrator 106 every cycle in order to measure the power every cycle. Further, the digital oscillator 109 uses the clock signal from the crystal oscillator 110 to form a pulse output F _m [Hz] corresponding to the measured power.

FIG. 7 is a timing chart showing signals at various parts of the circuit shown in FIG. Synchronously with the repetition of a certain period of the voltage signal waveform, instantaneous voltage v _mk [V], instantaneous current i _mk [A], instantaneous power p _mk [W], instantaneous power integrated value Σp _mk [W] and Average power P _m [W] appears.

JP 2000-121679 A JP 2007-306306 A

  However, unlike the general-purpose type, the conventional watt-hour meter shown in FIG. 6 is highly accurate. However, since the reset operation is performed every n samples, the reset operation and the reset operation are not performed. The system cannot cope with sudden input changes that occur in the meantime, and may cause an accumulated error in the number of pulses.

  The present invention has been made in consideration of the above-described points, and an object thereof is to provide a sampling watt-hour meter in which the number of output pulses accurately corresponds to an input signal.

In order to achieve the above object, in the present invention,
An input circuit that digitally converts the voltage and current to be measured by sampling with a voltage synchronization signal extracted from the voltage to form an input voltage and an input current;
A multiplier for calculating instantaneous power from the input voltage and input current;
An energy measuring device that integrates and averages the instantaneous power, and calculates a measured energy by resetting in a cycle based on the voltage synchronization signal;
An integrator for calculating an integrated electric energy given the measured electric energy and the voltage synchronization signal;
An electric energy / pulse number setting device for setting the electric energy / pulse number setting value;
A frequency setter for obtaining a frequency set value according to the integrated power amount and the power amount / pulse number set value;
A primary register that increases a holding value based on the frequency setting value each time a clock is applied, and a secondary register that sequentially stores the holding value of the primary register according to the voltage synchronization signal; A pulse output forming circuit that forms a pulse output while correcting the frequency setting value according to a difference between a holding value of a register and a holding value of the secondary register;
Sampling watt hour meter with
Is to provide.

  In the present invention, as described above, the pulse output is formed while correcting the measured electric energy obtained by sampling synchronized with the input voltage in the period of the voltage, so that a pulse corresponding accurately to the measured electric energy is output. Can do. And even if the input signal changes suddenly, the accumulated error of the number of pulses does not occur.

BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which shows the whole structure of one Example of this invention. The timing chart which showed each part signal in the electric energy measurement operation | movement of this invention. FIG. 2 is a block diagram showing an internal configuration of a feedback digital oscillator 111 in FIG. 1. Explanatory view showing a bit configuration of the primary registers 111 _i and the secondary register 111 _j in FIG. FIG. 4 is a simplified block diagram illustrating a configuration of a pulse output forming circuit illustrated in FIG. 3. The block diagram which shows the structure of the conventional sampling watt-hour meter. The timing chart which showed each part signal in the electric energy measurement operation | movement in the structure of FIG.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, parts common to the circuit shown in FIG. 6 are denoted by the same reference numerals, and different parts are denoted by different numerals. That is, the rectangular wave converter 101, the PLL circuit 102, the A / D converters 103 and 104, the multiplier 105, and the crystal oscillator 110, which are input circuits, have the same configuration as the circuit of FIG.

  1 includes an instantaneous power integrator 106, an averaging circuit 107, and a power amount calculator 113. The power amount measuring device 100 in FIG. Specifically, it is slightly different. A feedback digital oscillator (pulse output circuit) 111 and a clock counter 112 represented by different symbols are elements according to the present invention.

The clock counter 112 receives the clock f _clk [Hz] from the crystal oscillator 110 and counts the number of clocks C _m in one cycle of the input signal, and then resets the count value by the reset signal from the power amount calculator 113. .

The number of clocks C _m that is the output of the clock counter 112 is supplied to the electric energy calculator 113 and used to form the measured electric energy e _{in m} [Ws], and is also supplied to the feedback digital oscillator 111 to calculate the electric energy. Used for.

That is, the period T _{m of the} input signal to be measured is
T _m = C _m / f _clk [s] (1)
Where f _{clk is the} clock frequency.

It is. Therefore, the measured power amount e _{in m} is obtained by multiplying the average power P _m and the time T _m ,
e _{in m} = P _m T _m = C _m P _m / f _clk (2)
It is expressed.

FIG. 2 is a timing chart showing signals at respective parts of the circuit of FIG. The sampling clock nf [Hz] is formed and supplied to the A / D converters 103 and 104 in synchronization with the repetition of the constant periods T ₁ , T ₂ , T ₃ ,. The clock f _clk is given to the digital oscillator 111 and the clock counter 112.

In accordance with the timing of the clock f _clk, C ₁ the number of clocks while the clock counter 112 is repeatedly reset, C _2, C _3, ... and continue to update, the amount of power calculator 113 as a clock number C _m, the feedback type digital This is given to the oscillator 111.

The average power P _m is calculated as P ₁ , P ₂ , P ₃ ,... By the averaging circuit 107 in each period T ₂ , T ₃ , T ₄ ,. Thus, the measured electric energy e _{in m} [Ws] is obtained.

The following two data shown in FIG. 2, the pulse power amount e _{out m} and the integrated power amount _Em will be described later in connection with the pulse output forming circuit shown in FIG.

Feedback digital oscillator 111
FIG. 3 shows the internal configuration of the feedback digital oscillator 111 shown in FIG. 1. This feedback digital oscillator 111 uses a pulse generator A using a primary register 111 _i and a secondary register 111 _j . A pulse output forming circuit (shown by a two-dot chain line) including the corrector B as a main component is provided.

The feedback digital oscillator 111 further includes an integrator 111 _a , a frequency setter 111 _b , an electric energy / pulse setter 111 _c , multipliers 111 _e , 111 _l , 111 _n , an overflow value setter 111 _f and a register as related elements. 111 _i and 111 _j are provided.

In addition, the pulse output forming circuit includes an adder 111 _h and a subtractor 111 _k .

FIG. 4 shows the bit configuration of the primary register 111 _i and the secondary register 111 _j . The total number of bits is (x + y) bits. “X + y−1” bits, the lower side is an x bit width from “0” to “x−1” bits, and the upper side is a y bit width from “x + y−1” bits.

In the present invention, a register value of (x + y) bits is used for counting pulses, the lower x bits of the register are treated as a fractional part of the number of pulses, the upper y bits are treated as an integer part of the number of pulses, and the resolution of the number of pulses is 2 ^x It is improved twice.

In FIG. 3, the feedback digital oscillator 111 has, as input signals, the measured power amount e _{in m} [Ws], the voltage synchronization signal f [Hz], the clock number C _m and the clock f _clk [Hz] shown in FIG. And a pulse generator A (shown by a one-dot chain line) which operates based on a clock f _clk [Hz] given an electric energy r [Ws] per pulse from two setting devices 111 _c and 111 _f and a constant 2 ^x. Then, a pulse is formed, and after correction is made by a corrector B (shown by a one-dot chain line frame) that operates based on the voltage synchronization signal f [Hz], a pulse output F _m is sent as an output signal.

In this feedback digital oscillator 111, the measured electric energy e _{in m} is converted from the electric energy calculator 113 (FIG. 1), the clock number C _m is converted from the clock counter 112 (FIG. 1), and the voltage synchronization signal is converted into a rectangular wave. A clock f _clk is _supplied from a crystal oscillator 110 from the device 101.

Meanwhile, the amount of power r per pulse from the electric energy / pulse setting unit 111 _c, constant 2 ^x is given from the overflow value setting unit 111 _f.

In the feedback digital oscillator 111, the integrator 111a has _a measured power amount e _{in m at} its addition input terminal (+), an output pulse power amount e _{out m at} its subtraction input terminal (−), and a synchronization input terminal. voltage by synchronizing signal f [Hz] is given, on the measurement electric energy e _{in m} and the output pulse power amount e _out integral power consumption corresponding to _m E _m [Ws] together to form the frequency setter 111 _b in .

The frequency setter 111 _b is further provided with a clock f _clk [Hz], an electric energy r [Ws] per pulse, and a clock number C _m ,
E _m [Ws] × f _clk / (rC _m ) [Ws ² ]
Frequency setting value f _m ,
f _m = E _m f _clk / (rC _m ) [Hz]
It calculates and provides the frequency setting value f _m to the multiplier 111 _e of the pulse shaper A.

Pulse former A
The pulse former A includes a multiplier 111 _e , an adder 111 _h, and a primary register 111 _i . In the multiplier _111e , the frequency set value f _m is multiplied by 2 ^x / f _clk obtained by the divider 111 _g dividing the output 2 ^x of the overflow value setter 111 _f by the clock f _clk . The obtained product E _m 2 ^x / (rC _m ) is given to the adder 111 _h .

Here, “x” of the constant 2 ^x is x in the number of bits [(x + y) bits] of the primary register 111 _i and the secondary register 111 _j , which will be described later.

The adder 111 _h adds the output q _{m−1 (Cm−1)} of the primary register 111 _{i to} the product E _m 2 ^x / (rC _{m )} to form a signal q _{m (Cm)} , and the primary register 111 _i To give.

FIG. 5 shows a portion surrounded by a two-dot chain line in FIG. 3, that is, a pulse output forming circuit. This pulse output forming circuit includes a primary register 111 _i and a secondary register 111 _j , and a multiplier 111 _e , an adder 111 _h and a subtractor 111 _k which are related elements.

The primary register 111 _i forms the pulse output F _m of the feedback digital oscillator 111 and is a basic component of the feedback digital oscillator 111 that forms a pulse output in cooperation with the secondary register 111 _j . , A multiplier 111 _e , an adder 111 _h , and a subtractor 111 _k .

In FIG. 5, the primary register 111 _i updates the hold value every time the clock f _clk is given, and the output q _{m (1)} of the adder 111 _h is now given to the input terminal D _A. At this time, the previous hold value q _{m−1 (Cm−1)} is output to the output terminal Q _A.

An adder 111 _h arranged on the input side of the primary register 111 _i is an output (P _m / r) · (2 ^x / f _clk ) of the multiplier 111 _e and a feedback output of the primary register 111 _i , q _{m− 1 (Cm−1)} is added to form an output (x + y) bit width q _{m (1),} which is applied to the input D _A of the primary register 111i. Here, P _m is the average power, which will be described later using the following formula (6).

On the other hand, the feedback at the output terminal Q _A of the primary registers 111 _i output _{q m-1 (Cm-1} ) is also applied to the input terminal D _B of the secondary register 111 _j. Secondary register 111 _j is for updating the held value every given voltage synchronization signal f [Hz], the previous one from the output terminal Q _B until updated value held q _{m-2 (Cm- 2)} is given to the subtractor 111 _k .

Furthermore, subtractor 111 _k which is disposed at the output side of the secondary register 111 _j is, q _m-1 is a primary register 111 _i feedback output from the output of the secondary register _{111 j q m-2 (Cm} -2) _(Cm-1) obtained by subtracting the difference _{(q m-2 (Cm-} 2) -q m-1 (Cm-1)) to form a.

As a result, the primary register 111 _i forms an output q _{m−1 (Cm−1)} having a width of (x + y) bits, of which the (x−1) bits or the most significant bit in the lower x bits is output as the pulse output F _m. and outputs as a feedback to all bits in the adder 111 _h and the secondary register 111 _j.

_{Each time} the clock f [Hz] is given, the secondary register 111 _j gives the stored data q _{m−2 (Cm−2)} to the subtractor 111 _k . Subtractor 111 _k performs subtraction of the secondary register 111 _j of output _{q m-2 (Cm-2} ) and the primary register 111 _i feedback output _{q m-1 (Cm-1} ), the difference (q _{m- 2 (Cm−2)} −q _{m−1 (Cm−1)} ) is obtained and supplied to the multiplier 111 _l (FIG. 3).

First, the stored value update operation of the primary register 111 _i and the secondary register 111 _j is as follows. First, as described above, the held value of the primary register 111 _i at the i-th clock in the m-th cycle is expressed as q _{m (i)} . It represents. The clock speed of one cycle of the m-th cycle is measured by the clock counter 112, the value is expressed in C _m.

Here, when the cycle switches from the (m-2) th cycle to the (m-1) th cycle, and when the voltage synchronization signal synchronized with the cycle is input, the clock is the Cm-2th clock of the (m-2) th cycle. is there. At that time, the primary register 111 _i outputs q _{m−2 (Cm−2)} in synchronization with this clock.

Next, when the voltage synchronization signal is input from the m-1 period to the m period, the secondary register 111 _j outputs the output q _m-2 of the primary register 111 _i in synchronization with the voltage synchronization signal. Copy and output _(Cm-2) . At the same time, the primary register 111 _i is updated to q _{m−1 (Cm−1)} . 3 and 5 show the state at this time.

In this way, the secondary register 111 _j synchronizes the value of the primary register 111 _i with q _{1 (C1)} , q _{2 (C2)} ,..., Q _{m−2 (Cm− 2)} , q _{m-1 (Cm-1)} , q _{m (Cm)} , and so on.

In Figure 5, represents a state in which switching to m-th cycle from m-1-th cycle, this time, the subtracter 111k is the output of, the holding value of the secondary register 111 _j and primary registers 111 _i The difference q _{m−2 (Cm−2)} −q _{m−1 (Cm−1)} represents the increment of the primary register 111 _i during the first period of the m−1 period. Then, the number of pulses output during one period is obtained by the following formula (3) by the multiplier 111 _l .

(q _{m-2 (Cm-2)} -q _{m-1 (Cm-1)} ) / 2 ^x (3)
Normally, the number of output pulses can be counted only in units of one pulse. Therefore, in order to improve the resolution of the pulse count per unit time, it is necessary to increase the pulse frequency.

  However, even a watt-hour meter that outputs a relatively high frequency pulse has a frequency of about 10 [kHz], so the number of pulses output per cycle is about 200, and high resolution cannot be desired.

Therefore, in the present invention, utilizing the value held in the register to the counting of pulses, treats upper y bits of the register integer part of the number of pulses, the lower x bits as the fractional part of the number of pulses, 2 ^x times the resolution of the pulse number It has been improved.

Calculations here integral power consumption, shows a method of calculating the integrated electricity E _m in the m-th cycle below. E _m is obtained by the following equation (4) from the measured power amount e _{in m} and the output pulse power amount e _{out m} .

E _m = E _m-1 + e _{in m} -e _{out m} [Ws] (4)
Here, E _m−1 represents the integrated power amount at the time of the (m−1) cycle, one cycle before.

The output pulse power amount e _{out m} in the m-th cycle is obtained by the following equation (5) obtained by multiplying the number of pulses obtained by the above equation (3) by the multiplier 111 _{n and} the electric energy r [Ws] per pulse. .

e _{out m} = r (q _{m-2 (Cm-2)} -q _{m-1 (Cm-1)} ) / 2 ^x [Ws] (5)
Incidentally, an output pulse power amount e _{out m} (output) and integrated electricity E _m (output of the integrator 111 _a), are shown in FIG.

The average power P _m obtained by dividing the integrated power E _m by the time T _m of one cycle of the input signal is
P _m = E _m / T _m = E _m f _clk / C _m (6)
The frequency setting value f _m is obtained from the average power P _m obtained using the above formula (6) and the power amount r per pulse by the following formula (7):
f _m = P _m / r = E _m f _clk / (rC _m ) (7)
As obtained.

In this way, the output of the primary register 111 _i simply increases by (P _m / r) · (2 ^x / f _clk ) each time a clock is applied. However, each of the registers 111 _i and 111 _j has a (x + y) bit configuration, and the lower x bit width portion has an x bit binary configuration, so the overflow value 2 ^x can be counted up. Overflows when exceeded. The limit number of clocks until it overflows is
2 ^x / {(P _m / r) · (2 ^x / f _clk )} = r / P _m · f _clk
It is.

Therefore, the time to cause overflow is the product of the above limit clock number multiplied by the clock period 1 / f _clk .
r / P _m · f _clk × 1 / f _clk = r / P _m
And the frequency causing the overflow is the reciprocal of it,
P _m / r
And equal to the frequency set value f _m (= P _m / r).

  Note that, as a characteristic of the operation of the binary register in which the holding value simply increases, the most significant bit has a duty ratio of about 50%, and the frequency matches the overflow frequency. For this reason, the most significant (x−1) bits of the lower bits can be used as the pulse output.

Coordinated operation of pulse former A and corrector B Returning to FIG. 3 showing the overall configuration of the embodiment of the present invention, the bit configuration of the primary register 111 _i is (x + y) bits as described above. In this primary register 111 _i , the lower-order x-bit portion is used and the output (P _m / r) · (2 ^x / f _clk ) of the multiplier 111 _e is sequentially increased in synchronism with the clock f _clk to obtain a constant 2 ^{When x} is reached, it overflows.

  The number of overflows is counted in the upper y bits. The numerical value of the higher-order bits thus carried is the number of output pulses.

The output q _{m−1 (Cm−1)} of the primary register 111 _i is sent out as a pulse output F _m , and is given as a feedback signal to the secondary register 111 _j and the subtractor 111 _k .

The bit configuration of the secondary register 111 _j is the same as that of the primary register 111 _i .

In the secondary register 111 _j , the output q _{m−1 (Cm−1)} of the primary register 111 _i is changed to q _{m−2 (Cm−2),} q _{m−1 (Cm− (Cm− 1), q m (Cm)} , and copy as ..., and outputs to the subtractor 111 _k.

The subtracter 111 _k, data q _m-2 data _{q m-1 (Cm-1} ) is subtracted to both data difference from the _(Cm-2) from the primary registers 111 _i from the secondary register 111 _j (q _{m−1 (Cm−1)} −q _{m−2 (Cm−2)} ) is obtained and supplied to the multiplier 111 _l .

The multiplier 111 _l multiplies this difference (q _{m-1 (Cm-1)} -q _{m-2 (Cm-2)} ) by the set value of the 1/2 ^x calculator 111 _m (q _{m- 1 (Cm-1) -q m} -2 (Cm-2)) / 2 x is calculated, giving the multiplier 111 _n. The output of the multiplier _{111 l (q m-1 (} Cm-1) -q m-2 (Cm-2)) / 2 x is the number of pulses outputted in one period of the voltage synchronization signal.

The multiplier 111 _n, the number of the output pulse _{(q m-1 (Cm-} 1) -q m-2 (Cm-2)) / 2 x, the power per pulse from the electric energy / pulse setting unit 111 _c Multiplying the amount r, the output pulse power amount e _{out m} ,
e _{out m} = r (q _{m-1 (Cm-1)} -q _{m-2 (Cm-2)} ) / 2 ^x [Ws]
As determined, the subtraction input terminal of the integrator 111 _a - give ().

In the above-described cooperative operation of the pulse former A and the corrector B, when the increment of the register holding value for one period is q _{m-1 (Cm-1)} -q _{m-2 (Cm-2)} , The number of pulses output to is given by the above equation (3)
(Q _{m-1 (Cm-1)} -q _{m-2 (Cm-2)} ) / 2 ^x
Is represented as

  As described above with reference to FIG. 5, in order to perform high-resolution measurement with the sampling watt-hour meter, it is necessary to improve the resolution of pulse counting per unit time. To that end, it is conceivable to increase the frequency of the generated pulse, but this is not practical.

Therefore, in the present invention, by using the value held in the register for counting pulses, the upper y bits of the register are treated as an integer part of the number of pulses, the lower x bits are treated as a fractional part of the number of pulses, and the resolution of the number of pulses is 2 It is improved ^x times.

Formation and Correction of Output Pulse As described above, the watt-hour meter according to the present invention performs power calculation and period measurement in units of one cycle of the input signal to obtain the measured power amount e _{in m} . At the same time, the number of output pulses is counted to obtain an electric energy e _{out m} corresponding to the number of pulses.

The frequency set value f _m obtained by correcting the measured power amount e _{in m} and the output pulse power amount e _{out m} is set in the feedback digital oscillator 111. This is repeated for each cycle of the input signal according to the voltage synchronization signal f [Hz].

  As a result, if the power and frequency of the input signal are constant, a constant average power amount is obtained for each cycle, and pulses having a constant frequency are output.

  Further, even if the input signal fluctuates, the number of output pulses is counted and fed back, so that there is an advantage that no cumulative error of the number of pulses occurs.

10 power calculator, 100 power meter.
101 rectangular converter, 102 PLL circuit, 103, 104 A / D converter,
105 multiplier, 106 instantaneous power integrator, 107 averaging circuit,
108 frequency setting device, 113 electric energy calculator, 109 digital oscillator,
110 crystal oscillator, 111 feedback digital oscillator,
112 clock counter, 113 electric energy calculator.
111 _a accumulator, 111 _b frequency setting device, 111 _c electric energy / pulse setting device,
111 _e , 111 _l , 111 _k , 111 _n multipliers,
111 _f overflow value setter, 111 _g divider, 111 _h adder,
111 _i , 111 _j registers, 111 _k subtractor, 111 _m 1/2 _x arithmetic unit.
A pulse shaper, B corrector.

Claims (4)

An input circuit that digitally converts the voltage and current to be measured by sampling with a voltage synchronization signal extracted from the voltage to form an input voltage and an input current;
A multiplier for calculating instantaneous power from the input voltage and input current;
An energy measuring device that integrates and averages the instantaneous power, and calculates a measured energy by resetting in a cycle based on the voltage synchronization signal;
An integrator for calculating an integrated electric energy given the measured electric energy and the voltage synchronization signal;
An electric energy / pulse number setting device for setting the electric energy / pulse number setting value;
A frequency setter for obtaining a frequency set value according to the integrated power amount and the power amount / pulse number set value;
A primary register that increases a holding value based on the frequency setting value each time a clock is applied, and a secondary register that sequentially stores the holding value of the primary register according to the voltage synchronization signal; A pulse output forming circuit that forms a pulse output while correcting the frequency setting value according to a difference between a holding value of a register and a holding value of the secondary register;
Sampling watt hour meter with The sampling watt-hour meter according to claim 1,
The primary power register and the secondary register each have an upper bit corresponding to an integer part and a lower bit corresponding to a decimal part. The sampling watt-hour meter according to claim 1,
The sampling watt-hour meter, wherein the primary register updates the stored contents at the period of the clock, and the secondary register updates the stored contents at the period of the voltage synchronization signal. The sampling watt-hour meter according to claim 3,
The difference number of output pulses obtained by dividing the set value 2 ^x of the value held in the holding value and the secondary register of the primary registers is multiplied by one pulse per power amount obtained in advance an output pulse power amount A sampling watt-hour meter characterized by obtaining and correcting the measured power amount by the output pulse power amount.

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