JP6176777B2 - Pixel circuit and imaging device - Google Patents

Description

  The present invention relates to a pixel circuit for imaging an observation object and an image sensor including the pixel circuit.

In recent years, a stimulated Raman scattering (SRS) microscope has been used in the field of molecular imaging (see Non-Patent Document 1 below). In this SRS microscope, imaging is performed by detecting an intensity change amount of excitation light in stimulated Raman scattering. Specifically, when the observation object is excited with light of two different wavelengths (frequency ω ₁ , ω ₂ ), the difference in frequency (ω ₁ −ω ₂ ) is the difference between the molecules in the observation object. Resonance occurs when it matches the natural vibration level energy, and if the excitation light is intensity-modulated, this resonance causes a change in the intensity of the output light output at the frequency ω ₁ according to the intensity modulation. The intensity change is very weak, about 10 ⁻⁵ to 10 ⁻⁴ times compared with the excitation signal, and it is necessary to detect a slight change in a large excitation light component in the SRS microscope. In a conventional SRS microscope, a single point detector such as a photodiode is used as an imaging device.

“Stimulated Raman Scattering Microscope-SRS Microscope” [online], Mitsuhiki Co., Ltd. (Optipedia), [March 15, 2013 search], Internet <URL: http://optipedia.info/microscopy/nonlinear/srs / principle-7 / ＞

  However, it is difficult to detect a weak signal change with high sensitivity in a device that detects a weak signal change such as a conventional SRS microscope. For example, in the detection of stimulated Raman scattering, since a very weak signal component is added to an excitation light component having a relatively high intensity, signal detection is further difficult.

  Therefore, the present invention has been made in view of such a problem, and provides a pixel circuit and an image sensor that can accurately detect a weak intensity change superimposed on a relatively strong signal component. Objective.

In order to solve the above problem, the pixel circuit of the present invention receives first and second clock signals complementary to each other, and outputs first and second optical signals from an observation object excited by an excitation light source. A charge distribution unit that converts and distributes charges according to a clock signal and detects them as first and second current signals; and first and second low-pass filters that receive first and second current signals, respectively. Receiving the third clock signal, the first and second voltage signals of the first and second low-pass filters are detected as the first and second voltage signals at timing synchronized with the third clock signal, respectively. Two sampling circuits, an integration circuit that integrates and outputs the difference between the first and second voltage signals detected by the first and second sampling circuits, and the first and second based on the light intensity of the excitation light source. Clock A first phase adjustment circuit for adjusting the phase of the signal and a second phase adjustment circuit for adjusting the phase of the third clock signal based on the light intensity. The first and second sampling circuits are connected to the first and second sampling circuits at a timing such that the difference between the first voltage signal and the second voltage signal is canceled when an optical signal that is not generated is received. The phase of the third clock signal is adjusted so as to detect the voltage signal .

  According to such a pixel circuit, when intensity modulation is applied to an external optical signal at a predetermined frequency, the first and second clock signals synchronized with the intensity modulation frequency are provided. The charge distributing unit distributes the charges in synchronization with the intensity modulation, and detects the first and second current signals. The first and second low-pass filters output the first and second current signals as voltages, and the first and second sampling circuits output the voltage outputs of the first and second low-pass filters, respectively. 3 is sampled in synchronization with the clock signal 3, and the difference between the output voltages of the first and second sampling circuits is integrated and output. Thereby, even if a weak intensity modulation is applied to an optical signal having a relatively high intensity, the intensity modulation level can be detected with high accuracy.

In addition, if such first and second phase adjustment circuits are provided, the charges are distributed in synchronization with the intensity modulation applied to the optical signal, and the first and second voltages are based on the distributed charges. The signal difference can be integrated and output. As a result, the level of intensity modulation in the optical signal can be detected with high accuracy.

  Further, as the optical signal, an optical signal modulated so as to repeat the first level and the second level at a predetermined repetition frequency is received, and the first phase adjustment circuit is configured to synchronize with the repetition frequency. It is preferable to adjust the phases of the first and second clock signals. In this case, charges can be distributed in synchronization with the intensity modulation applied to the optical signal, and the difference between the first and second voltage signals can be integrated and output based on the distributed charges. As a result, the level of intensity modulation in the optical signal can be detected with high accuracy.

  It is also preferable that the charge distribution unit has a light receiving unit that converts an optical signal into a charge, and has a semiconductor element structure that distributes the charge to two output nodes. For example, the charge distribution unit may include a photogate including two or more electrodes, or the charge distribution unit may include an embedded photodiode as a light receiving unit and two transfer gates. The charge distribution unit may include an embedded photodiode as a light receiving unit and two or more gate electrodes provided so as to sandwich a transfer path forming a part of the embedded photodiode. In this case, when the charge distribution unit is combined with a device formed on a semiconductor element such as an imaging element, the entire circuit can be easily downsized.

  Furthermore, it is also preferable that the first and second sampling circuits have capacitors that sample the voltage outputs of the first and second low-pass filters, respectively. By adopting such a configuration, it is possible to detect the charges distributed by the charge distributing unit at the timing synchronized with the third clock signal by the first and second sampling circuits.

  Furthermore, the integrating circuit has a fully differential amplifier connected to the outputs of the first and second sampling circuits, and two capacitors connected between the input and output of the fully differential amplifier. preferable. With this configuration, the difference between the two voltage signals detected by the first and second sampling circuits can be detected by accumulating them in the two capacitors.

  An imaging device according to the present invention includes the above-described pixel circuit arranged one-dimensionally or two-dimensionally, and a readout circuit that reads a signal from the pixel. According to such an imaging device, the intensity modulation level in the optical signal detected by the plurality of pixel circuits provided for each pixel can be read out by the readout circuit. As a result, the one-dimensional and two-dimensional level distribution of the intensity modulation of the optical signal from the observation object can be detected with high accuracy.

  According to the present invention, a weak intensity change superimposed on a relatively strong signal component can be accurately detected.

1 is a block diagram illustrating a schematic configuration of a measurement system 100 including a pixel circuit 1 according to a preferred embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of a pixel main circuit 3 in FIG. 1. (A) is sectional drawing which shows the specific structure of the distribution light-receiving circuit 13 of FIG. 2, (b), (c) is a figure which shows the potential distribution of the cross-sectional direction of the distribution light-receiving circuit 13 of (a). (A) is sectional drawing which shows the other structure of the distribution light-receiving circuit 13 of FIG. 2, (b), (c) is a figure which shows the potential distribution of the cross-sectional direction of the distribution light-receiving circuit 13 of (a). 2A is a plan view showing another configuration of the sorting light receiving circuit 13 in FIG. 2, and FIGS. 2B and 2C show potential distributions along the VV direction of the sorting light receiving circuit 13 in FIG. FIG. FIG. 3 is a circuit diagram illustrating a detailed configuration of a pixel main circuit 3 in FIG. 2. It is a figure which shows the connection state of the circuit element at the time of sampling operation | movement of the pixel main circuit 3 of FIG. 6, and integration operation. 1 is a block diagram illustrating a configuration of an image sensor 200 according to an embodiment including a pixel circuit 1. FIG. It is a figure which shows the time change of the excitation light handled by the measurement system of FIG. 1, and the output light of observation object. It is a figure which shows the time change of the various signals handled with the measurement system of FIG. It is a graph which shows the simulation result of the voltage difference between differential outputs with respect to the integration time at the time of receiving the output light which does not contain an SRS signal in the pixel circuit. It is a graph which shows the simulation result of the voltage difference between differential outputs with respect to the integration time at the time of receiving the output light containing an SRS signal in the pixel circuit. It is a block diagram which shows schematic structure of measurement system 100A containing the pixel circuit 1A which concerns on the modification of this invention.

  Hereinafter, preferred embodiments of a pixel circuit and an image sensor including the pixel circuit according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted. Each drawing is made for the purpose of explanation, and is drawn so as to particularly emphasize the target portion of the explanation. Therefore, the dimensional ratio of each member in the drawings does not necessarily match the actual one.

  FIG. 1 is a block diagram showing a schematic configuration of a measurement system 100 including a pixel circuit 1 according to a preferred embodiment of the present invention. This measurement system 100 is used for molecular imaging such as SRS imaging targeting the observation object S, and an excitation light source that irradiates the observation object S with laser light modulated at a predetermined frequency (for example, 80 MHz) as excitation light. 101, a half mirror 102 which is provided on the optical path of the laser light irradiated by the light source 101 and transmits the laser light to the observation target, and the output light from the observation target S excited by the laser light The pixel circuit 1 that receives the output light and generates an electrical signal, and the pulse picker 103 that thins out the laser light branched by the half mirror 102 and converts it into an electrical signal and outputs the electrical signal to the pixel circuit 1. It is configured to include. Although only one pixel circuit is shown in the figure for the sake of simplicity, the measurement system 100 includes an imaging device including a plurality of pixel circuits 1 as described later.

The pixel circuit 1 constituting a part of the measurement system 100 receives an electric signal from the pixel main circuit 3 that receives the output light from the observation object S and the pulse picker 103, and adjusts the delay time of the electric signal. The clock signal G to be supplied to the pixel main circuit 3 based on the delay circuits 5 and 7, the frequency divider 6 inserted on the input side of the delay circuit 7, and the electrical signal whose delay time is adjusted by the delay circuit 5. ₁ and G ₂ (first and second clock signals) are supplied to the pixel main circuit 3 on the basis of the phase adjustment circuit 9 for adjusting the phase and the electrical signal whose delay time is adjusted by the delay circuits 5 and 7. The phase adjustment circuit 11 adjusts the phase of the clock signal φ ₁ (third clock signal) and the clock signals φ _1d and φ ₂ . These phase adjustment circuits 9 and 11 are circuits for adjusting the phases of the clock signals G ₁ , G ₂ , φ ₁ , φ _1d , and φ ₂ based on the intensity change of the excitation light that excites the observation object S. It is. The delay circuit 5 also includes a time during which the laser light from the light source 101 passes through the observation object S and is received by the pixel main circuit 3 as output light, and the intensity of the laser light is phased via the pulse picker 103. It is provided to absorb the difference from the time detected by the adjustment circuit 9 until the clock signals G ₁ and G ₂ are supplied to the pixel main circuit 3. Further, the delay circuit 7 takes into account the signal transmission time between the charge distribution timing by the clock signals G ₁ and G ₂ in the pixel main circuit 3 and the sampling timing of the voltage signal generated by the charge distribution. It is provided to generate a time difference. Further, the frequency divider 6 outputs an electric signal with the frequency of intensity modulation of the laser light being 1 / n (n is an integer of 2 or more). The delay circuits 5 and 7 and the phase adjustment circuits 9 and 11 are provided for each of the plurality of pixel circuits 1 in the imaging device, so that a difference in delay time that differs for each pixel can be absorbed. .

FIG. 2 is a block diagram illustrating a schematic configuration of the pixel main circuit 3. The pixel main circuit 3 receives the output light O _in from the observation object S, converts it into electric charges, generates two current signals, and distributes two currents from the distribution light receiving circuit 13. The low-pass filters 15a and 15b that receive the signals, the sampling circuits 17a and 17b that respectively sample the voltage outputs from the low-pass filters 15a and 15b, and the difference between the voltage signals sampled by the sampling circuits 17a and 17b are integrated and output. And an integration circuit 19.

The distribution light receiving circuit 13 has a semiconductor element structure, has a light receiving unit that converts light O _in into electric charges, and has a configuration that can distribute the electric charge from the light receiving unit to two output nodes. 3A shows a cross-sectional view showing a specific configuration of the distributed light receiving circuit 13, and FIGS. 3B and 3C show potential distributions in the cross-sectional direction of the distributed light receiving circuit 13. FIG. The sorting light receiving circuit 13 shown in FIG. 3A has a structure using a photogate. Specifically, in the sorting light receiving circuit 13, a buried channel layer 23 that is an n-type layer is formed on a p-type silicon substrate 21, and storage nodes 25 a and 25 b that are n-type layers are formed at both ends of the buried channel layer 23. Furthermore, gate electrodes 29a and 29b are formed on the storage nodes 25a and 25b side on the buried channel layer 23 via the insulating layer 27, respectively. These storage nodes 25a and 25b are respectively connected to the low-pass filters 15a and 15b in FIG. 2, and the PN junction capacitances of the storage nodes 25a and 25b constitute part of the low-pass filters 15a and 15b in FIG. In order to obtain a sufficient capacitance, the capacitors of the low-pass filters 15a and 15b are preferably configured by connecting MOS type capacitors or the like. The p-type silicon substrate 21 and the buried channel layer 23 constitute a light receiving unit that converts the output light O _in into electric charges.

With such a configuration of the distribution light receiving circuit 13, when a high voltage is applied to the gate electrode 29a and a low voltage is applied to the gate electrode 29b, a potential gradient is formed in the light receiving portion as shown in FIG. The photoelectrons (charges) generated by the photons hν incident on the part are transferred to the storage node 25a side through the buried channel layer 23 and stored in the storage node 25a. On the other hand, when a high voltage is applied to the gate electrode 29b and a low voltage is applied to the gate electrode 29a, as shown in FIG. 3C, photoelectrons (charges) generated by the photons hν incident on the light receiving portion are embedded in the buried channel layer 23. The data is transferred to the storage node 25b and stored in the storage node 25b. Therefore, by alternately applying a high voltage and a low voltage to the two gate electrodes 29a and 29b, the generated charges can be alternately transferred and distributed to the left and right storage nodes 25a and 25b. That is, by receiving the complementary clock signals G ₁ and G ₂ at the gate electrodes 29a and 29b, the light O _in is distributed according to the clock signals G ₁ and G ₂ and the two current signals (first and second current signals). Current signals), the two current signals can be stored in the storage nodes 25a and 25b and output as two voltage signals. Note that the number of gate electrodes formed on the buried channel layer 23 is not limited to two, and may be three or more.

4A is a cross-sectional view showing another configuration example of the distributed light receiving circuit 13, and FIGS. 4B and 4C show potential distributions in the cross-sectional direction of the distributed light receiving circuit 13. FIG. . The sorting light receiving circuit 13 shown in FIG. 4A has a structure using an embedded photodiode. Specifically, in the sorting light receiving circuit 13, an active layer 33 which is an n-type layer is formed on a p-type silicon substrate 31, and a high-concentration p-type layer 35 is formed on the surface of the active layer 33. Storage nodes 37a and 37b, which are high-concentration n-type layers, are provided at both ends of 33, and an insulating layer 39 is provided between the active layer 33 and the storage nodes 37a and 37b on the surface of the p-type silicon substrate 31, respectively. Gate electrodes (transfer gates) 41a and 41b are formed through the gates. These storage nodes 37a and 37b are respectively connected to the low-pass filters 15a and 15b in FIG. 2, and the PN junction capacitances of the storage nodes 37a and 37b constitute part of the low-pass filters 15a and 15b in FIG. In order to obtain a sufficient capacitance, the capacitors of the low-pass filters 15a and 15b are preferably configured by connecting MOS type capacitors or the like. The p-type silicon substrate 31, the active layer 33, and the p-type layer 35 constitute a light receiving unit that converts the output light O _in into electric charges.

Even with such a configuration of the sorting light receiving circuit 13, when a high voltage is applied to the gate electrode 41a and a low voltage is applied to the gate electrode 41b, the photon hν incident on the light receiving portion is generated as shown in FIG. The photoelectrons thus transferred are transferred from the buried photodiode to the storage node 37a and stored in the storage node 37a. On the other hand, when a high voltage is applied to the gate electrode 41b and a low voltage is applied to the gate electrode 41a, as shown in FIG. 4C, the photoelectrons generated by the photons hν incident on the light receiving portion are transferred from the embedded photodiode to the storage node 37b. And stored in the storage node 37b. Therefore, by receiving the clock signals G ₁ and G ₂ complementary to the gate electrodes 41a and 41b, the light O _in is distributed according to the clock signals G ₁ and G ₂ and two current signals (first and second current signals). Current signals), and the two current signals can be stored in the storage nodes 37a and 37b and output as two voltage signals.

  5A is a plan view showing another configuration example of the distribution light receiving circuit 13, and FIGS. 5B and 5C are cross-sectional directions along the line VV of the distribution light reception circuit 13. FIG. Shows the potential distribution. The sorting light receiving circuit 13 shown in FIG. 5A has a structure using an embedded photodiode. Specifically, an embedded photodiode 53 formed on the silicon substrate 51 and storage nodes 55a and 55b formed at both ends of the embedded photodiode 53 are provided. Further, on the silicon substrate 51, the storage node A set of gate electrodes 57a is provided on the 55a side so as to sandwich a part of the transfer path of the embedded photodiode 53, and a set of gate electrodes 57a is provided on the storage node 55b side so as to sandwich a part of the transfer path of the embedded photodiode 53. Gate electrode 57b is provided. These storage nodes 55a and 55b are respectively connected to the low-pass filters 15a and 15b in FIG. 2, and the PN junction capacitances of the storage nodes 55a and 55b constitute part of the low-pass filters 15a and 15b in FIG. In order to obtain a sufficient capacitance, the capacitors of the low-pass filters 15a and 15b are preferably configured by connecting MOS type capacitors or the like.

Even in such a configuration of the distribution light receiving circuit 13, when a high voltage is applied to the set of gate electrodes 57a and a low voltage is applied to the set of gate electrodes 57b, as shown in FIG. Photoelectrons generated by the incident photons hν are transferred from the embedded photodiode 53 to the storage node 55a and stored in the storage node 55a. On the other hand, when a high voltage is applied to the set of gate electrodes 57b and a low voltage is applied to the set of gate electrodes 57a, the photoelectrons generated by the photons hν incident on the light receiving portion are embedded as shown in FIG. The data is transferred from the photodiode 53 to the storage node 55b side and stored in the storage node 55b. Therefore, by receiving the clock signals G ₁ and G ₂ complementary to the gate electrodes 57a and 57b, the light O _in is distributed according to the clock signals G ₁ and G ₂ and two current signals (first and second current signals). Current signals), and the two current signals can be stored in the storage nodes 55a and 55b and output as two voltage signals.

  Next, the circuit configuration of the pixel main circuit 3 will be described with reference to FIG. All circuit elements of the pixel main circuit 3 shown in the figure are integrated on the same semiconductor substrate. In the same figure, the sorting light receiving circuit 13 is shown as an equivalent circuit including two current sources 13a and 13b.

The low-pass filters 15a and 15b of the pixel main circuit 3 are series circuits of a capacitor 61 and a resistance element 63, respectively, and pass the low-frequency components of the current signals I _in and I _ip generated by the sorting light receiving circuit 13 to pass voltage signals. Output as. Sampling circuits 17a and 17b include capacitors 65a and 65b, one end of which is connected to the outputs of low-pass filters 15a and 15b via switches SW1a and SW1b, respectively, and the other end of which is biased via switches SW2a and SW2b. . Further, the terminals on the low-pass filters 15a and 15b side of these capacitors 65a are connected to each other via the switch SW3. These switches SW1a, the SW1b, given clock signal phi _1d by the phase adjusting circuit 11, the switch SW2a, the SW2b, the clock signal phi ₁ is provided by phase adjusting circuit 11, the switch SW3, the phase adjustment circuit 11 provides a clock signal φ ₂ . Such configuration of the sampling circuit 17a, 17b is a low-pass filter 15a, a voltage output of the 15b, the clock signal two voltage signals at a timing synchronized φ to _{1 V} 1, _{V 2} (first and second voltage signals) Sampling to detect.

The integration circuit 19 of the pixel main circuit 3 includes a fully differential operational amplifier (amplifier) 67. Further, the integrating circuit 19 includes a capacitor 69a and a switch SW5a connected in parallel with each other between one output and the inverting input of the fully differential operational amplifier 67, and the other output of the fully differential operational amplifier 67 with the non-output. It includes a capacitor 69b and a switch SW5b connected in parallel with each other between the inverting input. The inverting input and the non-inverting input of the fully differential operational amplifier 67 are connected to the outputs of the sampling circuits 17a and 17b via the switches SW4a and SW4b, respectively. Differential output. These switches SW4a, the SW4b, the clock signal phi ₂ is provided by phase adjusting circuit 11, the switch SW5a, the SW5b, given a reset signal RT for resetting the output of the integration circuit 19 from the phase adjustment circuit 11 . The difference between the _two voltage signals V ₁ and V ₂ is integrated by the integrating circuit 19 having such a configuration and output as a differential output.

  The operation of the pixel main circuit 3 will be described with reference to FIG. FIG. 7 shows a connection state of circuit elements during sampling operation and integration operation of the pixel main circuit 3.

First, after the reset signal RT is set to “1” (on) and the accumulated charges in the capacitors 69a and 69b of the integrating circuit 19 are initialized, the clock signal φ _1d and the clock signal φ ₁ are set to “1” (on). Thus, the connection state as shown in FIG. Then, the voltage outputs of the low-pass filters 15a and 15b are amplified by the capacitors 65a and 65b, respectively. Thereafter, the clock signal φ _1d and the clock signal φ ₁ are set to “0” (off), and the clock signal φ ₂ is set to “1” (on), so that the connection state as shown in FIG. Set to Then, by the action of the integrating circuit 19, charges corresponding to the difference between the _two voltage signals V ₁ and V ₂ sampled by the capacitors 65a and 65b are transferred to and accumulated in the capacitors 69a and 69b. At this time, in order to perform the bottom plate sampling, is set earlier than the clock signal phi _1d to turn off the clock signal phi _1, the low-pass filter 15a, the sampling timing of the output of 15b is determined by the clock signal phi ₁ Is done. As a result, the voltage value of the differential output of the integrating circuit 19 increases by the difference between the voltage signals V ₁ and V ₂ , and the operations of FIG. 7A and FIG. 7B are repeated alternately. Thus, an amplified voltage obtained by integrating the difference between the voltage signals V ₁ and V ₂ a plurality of times can be obtained.

  FIG. 8 is a block diagram showing a configuration of the image sensor 200 of the present embodiment including the pixel circuit 1 described above. The image sensor 200 shown in the figure includes a pixel circuit 1 arranged in a two-dimensional array of 64 in the horizontal direction and 8 in the vertical direction, and a horizontal scanning circuit (reading out) for controlling the horizontal reading position from the pixel circuit 1. Circuit) 201, a multiplexing circuit (reading circuit) 202 that reads and multiplexes output signals from the pixel circuit 1 selected by the horizontal scanning circuit 201, and an output buffer 203 that amplifies the output of the multiplexing circuit 202. Composed. Note that the number of pixel circuits 1 included in the image sensor 200 can be arbitrarily set, and the pixel circuits 1 may be configured by one-dimensionally arranged pixel circuits 1.

Next, the principle of SRS imaging by the measurement system 100 described above will be described. FIG. 9 is a diagram illustrating temporal changes in excitation light and observation target output light handled by the measurement system 100. 10A and 10B are diagrams showing time changes of various signals handled by the measurement system 100. FIG. 10A is a time change of the entire photocurrent _Ip , and FIG. 10B is clock signals G ₁ and G _2. (C) and (d) are photocurrents I _ip and I _in after distribution, (e) and (f) are time variations of the sampled voltage signals V ₁ and V ₂ , (G) shows time changes of the clock signals φ ₁ , φ _1d , and φ ₂ , respectively.

The excitation light having the frequency ω ₁ as shown in FIG. 9A and the intensity-modulated Stokes having the frequency ω ₂ as shown in FIG. 9B from the light source 101 to the observation object S. When the light is combined and irradiated, intensity-modulated output light having a frequency ω ₁ as shown in FIG. 9C is observed in the pixel circuit 1. Specifically, the output light has a waveform that repeats the first level and the second level at a predetermined repetition frequency synchronized with on / off of the Stokes light. In the output light, the change in intensity modulation is as weak as about 10 ⁻⁵ to 10 ⁻⁴ times that of the excitation signal, and in order to detect SRS, a slight change in the large excitation light component is detected. There is a need to.

A total photocurrent generated by receiving the output light in the pixel circuit 1 is _defined as I _p . To this, a large offset current I _b is the background light component are joined by small signal current I _s, which corresponds to the modulation component (FIG. 10 (a)). To retrieve this signal current I _s, a 2-phase clock signals G _1, G _2, as shown in FIG. 10 (b), the pulse signal synchronized with the intensity modulation of the complementary photocurrent I _p each other produce Is done. At this time, average currents I _ip0 and I _in0 of the two currents I _ip and I _in (FIGS. _10C and _10D ) distributed in the pixel circuit 1 are respectively calculated by the following equations.
I _ip0 = I _b / 2 + I _s / 2
I _in0 = I _b / 2
Therefore, the difference between the two by the pixel circuit 1;
I _ip0 −I _in0 = I _s / 2
Is required, the signal current required for the SRS can be obtained.

In the pixel circuit 1, the two current signals distributed by the distribution light receiving circuit 13 are passed through the low-pass filters 15a and 15b to be shaped into triangular wave voltage signals V ₁ and V ₂ (FIG. 10 (e)). ), (F)). Here, the low pass filter 15a, the resistance value of the resistance element 63 of 15b R, the capacitance of the capacitor 61 when the C _1, the time constant RC ₁ is set sufficiently larger than the period T of the intensity modulation of the output light ing. At this time, the amplitude ΔV _pp of the triangular wave is given by
ΔV _pp = I _b T / 4C ₁
Is calculated. On the other hand, the signal component of the triangular wave is
V _s = I _s R / 2
And the ratio between the two is:
ΔV _pp / V _s = (I _b / I _s ) × (T / 2) / (C ₁ R)
Is calculated. From this calculation result, it can be understood that in order to realize SRS imaging, it is necessary to detect and amplify a weak signal component in a very large background light. In other words, _{I b} is very large compared to the _{I s.} As a result, a large triangular wave interference signal ΔV _pp due to background light is mixed into the weak signal voltage V _s , and it is difficult to amplify the signal component. From the above equation, there is obviously to be able to reduce this ratio by greater than the period T of the constant RC ₁ intensity-modulated time but, ^{10-5 to 10-4} times the _{I s} is _{I b} On the other hand, it is difficult to set the time constant of the circuit to 10 ⁴ to 10 ⁵ times T / 2 in consideration of the range of resistance and capacitor values included in the unit pixel circuit.

Therefore, the sampling circuits 17a and 17b of the pixel circuit 1 receive the clock signals φ ₁ and φ _1d (FIG. _10G ) adjusted in timing by the phase adjustment circuit 11 and sample the voltage signals V ₁ and V ₂ . The timing is adjusted, and the difference between the voltage signals V ₁ and V ₂ is integrated and output by the integration circuit 19. The timing of the clock signals φ ₁ and φ _1d is such that the difference between the voltage signals V ₁ and V ₂ is canceled when the output light that does not include the SRS signal component (no intensity modulation occurs) is received. Adjustment is made so as to synchronize with a timing such as 0 (FIG. 10E). Thus, upon receiving an output light including a SRS signal component can be extracted by amplifying a voltage corresponding to the small signal current I _s.

FIG. 11 shows a simulation result of the voltage difference between the differential outputs with respect to the integration time when the pixel circuit 1 receives the output light not including the SRS signal. Here, a case where the timings Δt of the clock signals φ ₁ and φ _1d are variously changed is shown. From this result, it can be seen that when the timing Δt of the clock signals φ ₁ and φ _1d is adjusted and Δt = −400 ps, the background light component hardly changes with respect to the integration time. On the other hand, when the timing Δt is shifted by 20 ps, the background light component increases to about 1 V with an integration time of about 35 ms. In this simulation, the amplitude of the background light component is 100 μA and the SRS signal is zero.

FIG. 12 shows a simulation result of the voltage difference between the differential outputs with respect to the integration time when the pixel circuit 1 receives the output light including the SRS signal. Thus, it can be seen that the signal components linearly increase and change as the integration time becomes longer by the clock signals φ ₁ and φ _1d adjusted so that the background light component does not appear. In this simulation, the amplitude of the background light component is changed at 0~100nA the signal current I _s is a SRS signal to 100 .mu.A.

According to the pixel circuit 1 described above, when the intensity modulation is applied to the optical signal O _in from the outside at a predetermined frequency, the clock signals G ₁ and G ₂ synchronized with the intensity modulation frequency are given. Thus, the charge is distributed by the distribution light receiving circuit 13 in synchronization with the intensity modulation, and the current signal is detected. Then, the low pass filter 15a, a 15b, their current signal is output as a voltage, a sampling circuit 17a, a 17b, a low-pass filter 15a, the voltage output of 15b are respectively the clock signal .phi.1, in synchronization with the phi _1d sampling, the sampling The difference between the output voltages of the circuits 17a and 17b is integrated and output. Thereby, even if a weak intensity modulation is applied to an optical signal having a relatively high intensity, the intensity modulation level can be detected with high accuracy.

  In addition, by providing the delay circuits 5 and 7 and the phase adjustment circuits 9 and 11, charges are distributed in synchronization with the intensity modulation applied to the optical signal, and only signal components such as SRS signals are based on the distributed charges. Can be extracted and the difference between the voltage signals can be integrated and output. As a result, the level of intensity modulation in the optical signal can be detected with high accuracy.

  Further, since the distributed light receiving circuit 13 has a semiconductor element structure, when the distributed light receiving circuit 13 is combined with a device formed on a semiconductor element such as an image sensor, the entire circuit can be easily downsized.

In addition, this invention is not limited to embodiment mentioned above. For example, the configuration of the pixel circuit 1A may be changed as shown in a measurement system 100A according to a modification of the present invention shown in FIG. That is, the measurement system 100 shown in FIG. 1 includes the delay circuits 5 and 7, the frequency divider 6, and the phase adjustment circuits 9 and 11 for each pixel. May be provided in common. Specifically, as shown in FIG. 13, the delay circuits 5 and 7, the frequency divider 6, and the phase adjustment circuit 9 are combined into a plurality of pixel circuits 1 </ b> A, a row unit or a column unit of the pixel circuit 1 </ b> A. Alternatively, only the phase adjustment circuit 11 may be included in the pixel circuit 1A for each pixel circuit 1A. With this configuration, the delay circuits 5 and 7 can roughly adjust the delay time for each of the plurality of pixel circuits, and the phase can be finely adjusted by the phase adjustment circuit 11, so that the voltage signals V ₁ and V ₂ can be adjusted. The sampling timing can be optimized. At the same time, the circuit configuration of the entire pixel circuit is simplified.

  DESCRIPTION OF SYMBOLS 1 ... Pixel circuit, 3 ... Pixel main circuit, 5, 7 ... Delay circuit, 9, 11 ... Phase adjustment circuit, 13 ... Distribution light-receiving circuit (charge distribution part), 15a, 15b ... Low-pass filter, 17a, 17b ... Sampling circuit , 19 ... integration circuit, 21, 31 ... p-type silicon substrate (light receiving part), 23 ... buried channel layer (light receiving part), 25a, 25b, 37a, 37b, 55a, 55b ... storage node (output node), 29a, 29b ... Gate electrode (photogate), 33 ... Active layer (light receiving portion), 35 ... p-type layer (light receiving portion), 41a, 41b ... Gate electrode (transfer gate), 53 ... Embedded photodiode, 57a, 57b ... Gate Electrodes 61 ... Capacitors 65a, 65b ... Capacitors 67 ... Fully differential operational amplifiers (fully differential amplifiers) 69a, 69b ... Capacitors, 2 0 ... imaging element, 201 ... horizontal scanning circuit (readout circuit), 202 ... multiplexing circuit (readout circuit), S ... observation object.

Claims (9)

Receiving the first and second clock signals complementary to each other, the optical signal from the observation object excited by the excitation light source is converted into electric charge according to the first and second clock signals, and distributed. A charge distribution unit that detects the first and second current signals,
First and second low-pass filters for receiving the first and second current signals;
Receiving a third clock signal, and detecting the voltage outputs of the first and second low-pass filters as first and second voltage signals at timings synchronized with the third clock signal, respectively; A second sampling circuit;
An integrating circuit that integrates and outputs the difference between the first and second voltage signals detected by the first and second sampling circuits;
A first phase adjustment circuit for adjusting the phases of the first and second clock signals based on the light intensity of the excitation light source;
A second phase adjustment circuit for adjusting the phase of the third clock signal based on the light intensity;
With
The second phase adjustment circuit has the timing at which the difference between the first voltage signal and the second voltage signal is canceled when an optical signal in which intensity modulation has not occurred is received. Adjusting the phase of the third clock signal so that the first and second sampling circuits detect the first and second voltage signals;
A pixel circuit characterized by that. As the optical signal, an optical signal modulated to repeat the first level and the second level at a predetermined repetition frequency is received,
The first phase adjustment circuit, the repeated in sync with frequency, the pixel circuit according to claim 1, wherein adjusting the phase of said first and second clock signals. The charge distribution unit has a light receiving unit that converts the optical signal into a charge, and has a semiconductor element structure that distributes the charge to two output nodes.
The pixel circuit according to claim 1 or 2, characterized in that. Each of the first and second sampling circuits includes a capacitor that samples the voltage output of the first and second low-pass filters.
The pixel circuit according to any one of claims 1 to 3, characterized in that. The integrating circuit includes a fully differential amplifier connected to the outputs of the first and second sampling circuits, and two capacitors connected between the input and output of the fully differential amplifier.
The pixel circuit according to any one of claims 1 to 4, characterized in that. The charge distribution unit includes a photogate including two or more electrodes.
The pixel circuit according to claim 3 . The charge distribution unit includes:
An embedded photodiode as the light receiving portion;
Including two transfer gates,
The pixel circuit according to claim 3 . The charge distribution unit includes:
An embedded photodiode as the light receiving portion;
Two or more gate electrodes provided so as to sandwich a transfer path forming a part of the embedded photodiode,
The pixel circuit according to claim 3 . The pixel circuit according to any one of claims 1 to 9 , which is arranged in one dimension or two dimensions,
A readout circuit for reading out signals from the pixels;
An image pickup device comprising:

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