JP6148171B2 - Semiconductor device manufacturing method and manufacturing jig - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method and a manufacturing jig. More specifically, the present invention relates to a semiconductor device manufacturing method and a manufacturing jig for performing solder reflow on a semiconductor device on which mounted components are mounted.

  Conventionally, a jig used when soldering a semiconductor chip in a reflow process is known (see, for example, Patent Documents 1 and 2).

  The jig of Patent Document 1 includes an upper jig and a lower jig, and positions a substrate, a semiconductor chip, a solder material, a mounting component, and the like in a semiconductor device by sandwiching them. According to the jig of this patent document 1, even if the distance between the outer surface of the back-side conductive plate and the outer surface of the front-side conductive plate is set to a predetermined value and the thickness of both conductive plates varies, the variation can be suppressed. It is said that.

  Moreover, the jig | tool of patent document 2 is made to penetrate the positioning terminal fixed to the conductive pattern in the through-hole of the board | substrate, and is a structure which provided the change in the hole diameter of the positioning terminal. According to the jig of this patent document 2, it is supposed that the position shift of the semiconductor chip etc. which generate | occur | produces with solidification of a solder material can be absorbed.

JP 2006-278591 A JP 2012-129336 A

  However, along with the recent increase in size of semiconductor devices, soldering deteriorates due to differences in expansion and contraction between members due to the difference in thermal expansion between the jig that holds the semiconductor chip and the case or water jacket in the reflow process. Challenges arise. For example, the jig that holds the semiconductor chip interferes with the case or the water jacket, or the stress increases at the contact portion between the jig holding the semiconductor chip and the case or the water jacket, causing problems in soldering the semiconductor chip. Occur.

  The present invention is for solving the above-described problems, and an object of the present invention is to provide a manufacturing method and a manufacturing jig of a semiconductor device that can be soldered well even when different expansion and contraction occurs between members in a reflow process. It is in.

(1) Manufacture of a semiconductor device that performs solder reflow on a semiconductor device (for example, the semiconductor device 1 in the embodiment) on which mounted components (for example, the substrate 4, the semiconductor chip 5, and the wiring member 6 in the embodiment) are mounted. In the method, a plurality of conical round holes (for example, the round holes 41b in the embodiment) are provided around the substrate (for example, the substrate 4 in the embodiment), and the outer peripheral portion is slightly larger than the substrate. A pair of claws (for example, the pair of claws 41c in the embodiment) for fixing the outer peripheral edge of the substrate is formed below the outer peripheral portion. ) And a semiconductor chip by interposing a solder material (for example, the second solder material 8 in the embodiment) on the substrate (step S7 in the embodiment). (For example, step S9 in the embodiment) for arranging (for example, the semiconductor chip 5 in the embodiment), and a wiring member by interposing a solder material (for example, the third solder material 9 in the embodiment) on the semiconductor chip. (For example, step S11 in the embodiment) for arranging (for example, the wiring member 6 in the embodiment) and a step for arranging the weight jig (for example, the weight jig 50 in the embodiment) on the wiring member (for example, Step S12 in the embodiment, and the semiconductor device is vertically sandwiched between an upper jig (for example, the upper jig 60 in the embodiment) and a lower jig (for example, the lower jig 20 in the embodiment), and the upper jig positioning pins extending out the distal end of ingredients is formed in the cusp-type (e.g., positioning pins 61a in the embodiment) before the surrounding jig By inserting the round hole, the step of positioning the enclosed jig (e.g., step S13 in the embodiment) and is cooled and thereafter heating the semiconductor device in which the surrounding jig is positioned in a reflow furnace And a reflow process (for example, step S14 in the embodiment) in which the solder material (for example, the second solder material 8 and the third solder material 9 in the embodiment) is melted and solidified and soldered. A method for manufacturing a semiconductor device.

  According to the invention of (1), the substrate, the semiconductor chip, and the wiring member to be soldered by the solder material are positioned on the surrounding jig inserted through the positioning pins extended from the upper jig. For this reason, a board | substrate, a semiconductor chip, and a wiring member can be spaced apart and fixed from other members, such as a lower jig and a case. Therefore, even if the expansion and contraction between these members differs due to the difference in thermal expansion between the substrate and other members such as the lower jig and case in the reflow process, the substrate, semiconductor chip and wiring member positioned on the surrounding jig are The horizontal movement is free without interference with other members such as jigs and cases. In addition, the surrounding jig, the substrate positioned on the surrounding jig, the semiconductor chip, and the wiring member do not come into contact with other members such as the lower jig and the case and are not affected. There is no problem in soldering the substrate, the semiconductor chip and the wiring member. Therefore, the semiconductor device can be soldered satisfactorily even when different expansion and contraction occurs between the members in the reflow process.

(2) Manufacture of a semiconductor device that performs solder reflow on a semiconductor device (for example, the semiconductor device 1 in the embodiment) on which mounted components (for example, the substrate 4, the semiconductor chip 5, and the wiring member 6 in the embodiment) are mounted. A jig (for example, a manufacturing jig 10) disposed around a substrate (for example, the substrate 4 in the embodiment) on which the mounting component is mounted , and a plurality of conical round holes (for example, in the embodiment) A round hole 41b) is provided, and an outer peripheral portion that is slightly larger than the substrate is formed. A pair of claws (for example, the pair of claws 41c in the embodiment) that fixes the outer peripheral edge of the substrate below the outer peripheral portion. ) In which the surrounding jig is formed (for example, the surrounding jig 40 in the embodiment) and the solder material (for example, the second solder material 8 and the third solder material 9 in the embodiment) are interposed. A weight jig (for example, weight jig 50 in the embodiment) disposed on the mounting component stacked in the above, an upper jig for sandwiching the semiconductor device vertically (for example, the upper jig 60 in the embodiment), and A lower jig (for example, the lower jig 20 in the embodiment) and a tip extending from the upper jig and inserted into the round hole of the go jig have a pointed end for positioning the go jig. A semiconductor device manufacturing jig comprising: a positioning pin formed in a head shape (for example, the positioning pin 61a in the embodiment), and placed in a reflow furnace together with the semiconductor device.

  According to the invention of (2), there are the same operations and effects as the invention of (1).

  According to the present invention, it is possible to provide a semiconductor device manufacturing method and a manufacturing jig that can be soldered satisfactorily even if different stretching occurs between members in the reflow process.

1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is an exploded perspective view and FIG. 1B is an overall perspective view. It is a disassembled perspective view which shows the manufacturing jig of the semiconductor device which concerns on the said embodiment. It is sectional drawing which shows the use condition of the manufacturing jig of the semiconductor device which concerns on the said embodiment. It is a flowchart which shows the implementation procedure of the reflow in the manufacturing method of the semiconductor device which concerns on the said embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the semiconductor device 1 according to the present embodiment will be described.
1A and 1B are diagrams showing a semiconductor device 1 according to the present embodiment, in which FIG. 1A is an exploded perspective view and FIG. 1B is an overall perspective view.
As shown in FIG. 1, the semiconductor device 1 includes a water jacket 2, a case 3, a substrate 4, a semiconductor chip 5, and a wiring member 6.
In the semiconductor device 1, a semiconductor chip 5 and a wiring member 6 are arranged in this order on a plurality of substrates 4 in a water jacket 2 that constitutes the bottom of the semiconductor device 1 and a case 3 that surrounds the periphery of the water jacket 2. Have stacked.

The water jacket 2 cools the substrate 4 to which the heat generated by the semiconductor chip 5 has been transferred by circulating cooling water therein. The water jacket 2 has a rectangular flat plate shape and forms the bottom of the semiconductor device 1. The water jacket 2 is hollow inside, and has projecting portions 2a and 2b provided with openings of cooling water to be circulated inside at both ends in the lateral direction.
The cooling water flowing through the water jacket 2 flows in from the one protruding portion 2a, absorbs the heat of the substrate 4 when flowing through the water jacket 2, and cools the substrate 4, while the water temperature is increased. Out of the protrusion 2b.

The case 3 surrounds the peripheral portion of the water jacket 2 so as to protect the substrate 4, the semiconductor chip 5, and the wiring member 6.
The case 3 is made of resin, and the outer wall portion 3a erected and connected to the four peripheral edges of the water jacket 2 having a rectangular flat plate shape, and the inside of the outer wall portion 3a are matched to a plurality of stored boards. And a partition part 3b for partitioning. The partition portion 3b includes a main partition portion 3b1 that is connected to both ends in the short direction over the longitudinal direction at the center portion in the short direction of the semiconductor device 1, and a plurality of substrates 4 from the main partition portion 3b1 to both ends in the longitudinal direction of the semiconductor device 1. And a sub-partition portion 3b2 extending between the two.

The substrate 4 has a structure for radiating heat generated from the semiconductor chip 5.
The substrate 4 is divided into a plurality of parts in one semiconductor device 1, is small with respect to the size of the semiconductor device 1, and a plurality of substrates 4 are mounted on the water jacket 2. The substrate 4 has a sandwich structure composed of a metal plate such as Cu and an insulator such as ceramic sandwiching the metal plate, and insulates the water jacket 2 and the semiconductor chip 5 from each other. The substrate 4 is soldered onto the water jacket 2 so that heat can be transferred to the water jacket 2 at the contact surface (lower surface) with the water jacket 2.

The semiconductor chip 5 is a semiconductor switching element such as an IGBT (Insulated Gate Bipolar Transistor) used for vehicle control. One to three semiconductor chips 5 are arranged on one substrate 4.
The semiconductor chip 5 is soldered onto the substrate 4 so as to transfer heat to the metal plate of the substrate 4.

  The wiring member 6 connects the semiconductor chip 5 or the substrate 4 and the conductive portion of the case 3. The wiring member 6 is made of a conductive metal and is disposed on the semiconductor chip 5 or the substrate 4. The wiring member 6 is soldered on the semiconductor chip 5 or the substrate 4.

Next, the semiconductor manufacturing method according to the present embodiment will be described.
In the semiconductor manufacturing method, first, a single inspection of each of the plurality of semiconductor chips 5 is performed. Next, the large-sized semiconductor device 1 on which a plurality of semiconductor chips 5 are mounted is reflowed in a batch. The reflow process for solder reflow is a combination of the soldering joining process of three layers between the water jacket 2 and the substrate 4, between the substrate 4 and the semiconductor chip 5, and between the semiconductor chip 5 and the wiring member 6. It is. After completion of the reflow process of the semiconductor device 1, another gel bonding process is performed on the semiconductor device 1, a control board is assembled to the semiconductor device 1, and a function test of the semiconductor device 1 is performed.

Next, the manufacturing jig 10 used in the reflow process of the semiconductor device 1 according to the present embodiment will be described.
FIG. 2 is an exploded perspective view showing the manufacturing jig 10 of the semiconductor device 1 according to the present embodiment. FIG. 3 is a cross-sectional view showing a usage state of the manufacturing jig 10 of the semiconductor device 1 according to the present embodiment.
The manufacturing jig 10 includes a lower jig 20, a correction jig 30, a surrounding jig 40, a weight jig 50, and an upper jig 60. Further, the manufacturing jig 10 includes a first fixing pin 71 and a second fixing pin 72.
In the manufacturing jig 10, the semiconductor device 1 is disposed on the lower jig 20 and the correction jig 30, the substrate 4 is surrounded by the surrounding member 41, and the weight jig 50 is positioned by the surrounding jig 40 while the semiconductor device 1 is positioned. The semiconductor device 1 is sandwiched up and down by the upper jig 60 and the lower jig 20, and the surrounding jig 40 is positioned by the upper jig 60.

The lower jig 20 is a basic member that is placed on a placement table (not shown).
The lower jig 20 includes a rectangular flat base member 21 on which the semiconductor device 1 is placed. The base member 21 has clamps 22 at four corners.

  The correction jig 30 corrects the posture of the semiconductor device 1 by suppressing the semiconductor device 1 placed on the base member 21 that is the lower jig 20. The correction jig 30 includes a correction member 31.

  The correction member 31 includes a flat plate portion 31b having a rectangular hole portion 31a at the center, and leg portions 31c erected at the four corners of the flat plate portion 31b so as to lift the flat plate portion 31b from the base member 21. The correction member 31 is placed with the leg portion 31 c placed on the base member 21, and the leg portion 31 c is clamped and held by the clamp 22 of the base member 21. The correction member 31 includes a plurality of the semiconductor devices 1 that are stretched over both ends in the short direction of the flat plate portion 31b that suppresses warping of the center of the semiconductor device 1 at a plurality of parallel longitudinal positions in the rectangular hole portion 31a. The thin rod portion 31d. The plurality of thin rod portions 31d are vertically vertically extending from both ends of the flat plate portion 31b of the correction member 31 to the lower side, and from the lower ends of the vertical rod portions on both sides to the center portion in the width direction. And a horizontal bar portion extending horizontally on the side. The correction member 31 has a plurality of depressing bar portions 31 e that extend downward from the lower surface of the flat plate portion 31 b and suppress warping of the outer peripheral portion of the semiconductor device 1. The restraining bar portion 31e includes a shaft that can slide with respect to the flat plate portion 31b, and a spring that is interposed on the shaft.

The correction member 31 is fixed to the base member 21 which is the lower jig 20 by a first fixing pin 71 at one location on the side in the longitudinal center of the flat plate portion 31b and one end in the short direction (FIG. 2, FIG. 3).
The water jacket 2 of the semiconductor device 1 arranged in the manufacturing jig 10 is similarly arranged on the same side as the first fixing pin 71 on the upper surface of the base member 21 in the longitudinal direction central portion and the lateral direction one end portion side. The case 3 is fixed by one second fixing pin 72 (see FIG. 3).
The upper jig 60 and the lower jig 20 are fixed by one first fixing pin 71, and the water jacket 2 and the lower jig 20 are fixed by one second fixing pin 72 in the vicinity of the first fixing pin 71. Thus, the thermal expansion changes of the upper jig 60, the water jacket 2 and the lower jig 20 are allowed. This thermal expansion change causes the upper jig 60, the water jacket 2 and the lower jig 20 to change radially from the first fixing pin 71 and the second fixing pin 72 as starting points.

  The surrounding jig 40 is inserted into a positioning pin 61 a extended from the upper jig 60. The surrounding jig 40 includes a plurality of surrounding members 41.

  The surrounding member 41 has a shape that is slightly larger than each substrate 4. The surrounding member 41 has a vertical hole portion 41 a and a round hole 41 b as a positioning portion. The vertical hole portion 41 a is a rectangular space portion in which the weight member 51 can be arranged, and the semiconductor chip 5 on the substrate 4. The number is set according to the number of. Two round holes 41b are provided in the thick part of the surrounding member 41 so as to be positioned by the two positioning pins 61a. The round hole 41b has a conical shape so that the tip of the positioning pin 61a can be inserted during insertion. The two round holes 41b for each surrounding member 41 are provided at least a predetermined distance apart. The surrounding member 41 is prohibited from rotating by the two round holes 41b being separated by at least a predetermined distance. The surrounding member 41 is supported at two points by inserting the two positioning pins 61a through the round holes 41b, and does not rotate integrally with the upper jig 60 according to the expansion and contraction of the thermal expansion of the upper jig 60. Moving.

As shown in FIG. 3, the outer peripheral portion of the surrounding member 41 has at least one pair of claws 41 c protruding downward in order to fix the outer peripheral edge of the substrate 4 covered with the surrounding member 41. At least one pair of claws 41 c is provided on each side of the substrate 4 so as to hook and fix the opposite sides of the outer peripheral edge of the substrate 4. Since the board | substrate 4 is small and there is little expansion / contraction by thermal expansion, generation | occurrence | production of the crack by thermal expansion is suppressed in the state fixed to the at least 1 pair of nail | claw 41c at the time of reflow.
The distance between the surrounding member 41 and the case 3 is set to be equal to or longer than the extension distance of the upper jig 60 expected at the time of reflow, and the surrounding member 41 and the case 3 do not come into contact with each other even during thermal expansion.

  The weight jig 50 is disposed on the wiring member 6 stacked with a solder material interposed. The weight jig 50 has a plurality of weight members 51 surrounded by the surrounding member 41.

The weight member 51 has a rectangular columnar shape disposed in the vertical hole portion 41 a of the surrounding member 41. The weight member 51 is disposed for each semiconductor chip 5. Therefore, for example, when three semiconductor chips 5 are mounted on the substrate 4, the three weight members 51 are arranged on the wiring members 6 on the three semiconductor chips 5. The Since the weight member 51 is stored in the vertical hole portion 41a of the surrounding member 41 at the lower portion, it is difficult for the weight member 51 to fall down.
The weight member 51 has a cover 52. The cover 52 covers a solder adhesion prohibition region such as a signal pad portion on the surface of the semiconductor chip 5 to prevent solder adhesion during reflow.

  There are two types of weight members 51: a sliding cover weight member 51a and a monoblock cover weight member 51b. The weight member 51 on the left side of FIG. 3 is a sliding cover weight member 51a, and the weight member 51 on the right side of FIG. 3 is a monoblock cover weight member 51b.

  The sliding cover weight member 51 a includes a rectangular parallelepiped main body 53 placed on the wiring member 6, and a sliding cover portion 54 provided in the semiconductor chip 5 region on the side of the main body 53. The slide type cover part 54 includes a shaft part 55 slidable through a bearing 53 a protruding from the side surface of the main body 53, a cover 52 a provided at the lower end part of the shaft part 55, and a drop provided at the upper end part of the shaft part 55. And a stopper 56 for prevention. The cover 52a of the slide type cover portion 54 is pressed against the solder adhesion prohibition region on the surface of the semiconductor chip 5 below the wiring member 6 on which the main body 53 is placed by sliding the shaft portion 55 with respect to the main body 53. .

  The monoblock cover weight member 51 b has a rectangular parallelepiped shape, and has a cover 52 b integrated with the main body 53. The cover 52b protrudes downward from the side of the main body 53 placed on the wiring member 6 so as to face the surface of the semiconductor chip 5 below the wiring member 6 on which the lower surface of the main body 53 is placed. A predetermined gap is set between the surface and the solder adhesion prohibited area so that solder splash does not enter during reflow.

The upper jig 60 sandwiches the semiconductor device 1 with the lower jig 20 up and down. The upper jig 60 is made of a material having the same linear expansion coefficient as that of the lower jig 20.
The upper jig 60 is disposed in the rectangular hole 31a in the center of the correction member 31 and is disposed in the cooperation member 61 having a positioning pin 61a for positioning the surrounding member 41 and the rectangular hole 61b in the center of the cooperation member 61. And a heat shield member 62.

The cooperation member 61 positions the surrounding member 41.
The cooperation member 61 has the shape of the rectangular hole portion 31a of the correction member 31, and is hooked by the step portion 31a1 protruding at the inner wall lower portion of the rectangular hole portion 31a of the correction member 31, thereby closing the rectangular hole portion 31a. The linking member 61 has positioning pins 61a so as to be inserted through the two round holes 41b of each surrounding member 41. The positioning pin 61a is a round bar shape with a pointed tip, and the displacement of the tip when the positioning pin 61a is inserted is within the range of the radial distance of the conical round hole 41b. Correct the position to the center. The cooperation member 61 has a rectangular hole 61b in the center.

The heat shield member 62 prevents the upper surface of the semiconductor device 1 from being overheated by the upper heater in the reflow furnace.
The heat shield member 62 has the shape of the rectangular hole 61b of the linkage member 61, and is hooked on a stepped portion that protrudes at the lower part of the inner surface of the rectangular hole 61b of the linkage member 61, thereby closing the rectangular hole 61b.

Next, details of the reflow procedure in the method for manufacturing the semiconductor device 1 according to the present embodiment will be described.
FIG. 4 is a flowchart showing a reflow execution procedure in the method for manufacturing the semiconductor device 1 according to the present embodiment.

  As shown in FIG. 4, in step S1, the base member 21, which is the lower jig 20, is placed on the mounting table.

  In step S <b> 2, the water jacket 2 is disposed on the base member 21. The water jacket 2 is inserted on the base member 21 by inserting the second fixing pin 72 on the base member 21 into the hole 2c at one central portion in the longitudinal direction of the water jacket 2 and one end in the short direction. Is positioned.

  In step S <b> 3, the case 3 is placed on the water jacket 2. The case 3 inserts the second fixing pin 72 on the base member 21 inserted through the water jacket 2 into one hole 3c on the outer wall 3a of the case 3 in the longitudinal center and one end in the lateral direction. By doing so, it is positioned on the base member 21 and the water jacket 2.

  In step S4, the correction member 31 is arranged so as to surround the periphery of the water jacket 2 in which mounting components of the substrate 4, the semiconductor chip 5 and the wiring member 6 to be arranged later in the case 3 are laminated in this order. At this time, the five thin rod portions 31 d of the correction member 31 are arranged in the space above the wiring member 6. After the correction member 31 is arranged, each of the four legs 31 c of the correction member 31 is clamped by each clamp 22 on the base member 21.

  In step S <b> 5, the first solder material 7 is disposed on the water jacket 2.

  In step S <b> 6, the plurality of substrates 4 are arranged on the water jacket 2 through the first solder material 7 in the spaces between the partition portions 3 b of the case 3.

  In step S7, the surrounding member 41 is covered on the substrate 4 so that the wiring member 6 and the semiconductor chip 5 are stored in the vertical hole portion 41a, and at least one pair of claws 41c of the surrounding member 41 is opposed to the substrate 4. Hang on each side and fix. Since the position of the surrounding member 41 is corrected by the movement of the round hole 41b inserted through the positioning pin 61a, the surrounding member 41 can be arranged roughly without moving the substrate 4. The distance between the surrounding member 41 and the case 3 is a gap equal to or longer than the extension distance of the upper jig 60 such as the correction member 31 expected at the time of reflow.

  In step S <b> 8, the second solder material 8 is disposed on each of the plurality of substrates 4.

  In step S <b> 9, each of the plurality of semiconductor chips 5 is disposed at a corresponding position of each of the plurality of substrates 4 via the second solder material 8.

  In step S <b> 10, the third solder material 9 is disposed on each of the plurality of semiconductor chips 5.

  In step S <b> 11, each of the plurality of wiring members 6 is disposed on each of the plurality of semiconductor chips 5 via the third solder material 9.

  In step S <b> 12, the weight member 51 is disposed in the vertical hole portion 41 a of the surrounding member 41 and on the wiring member 6.

In step S <b> 13, the cooperation member 61 is disposed in the rectangular hole 31 a of the correction member 31. When the cooperation member 61 is disposed in the rectangular hole 31 a of the correction member 31, the plurality of positioning pins 61 a of the cooperation member 61 are inserted into the two round holes 41 b of each of the plurality of surrounding members 41. At this time, the position of the surrounding member 41 is corrected to the center of the round hole 41b within the radius distance of the round hole 41b by the positioning pin 61a inserted through the round hole 41b.
Subsequently, the heat shield member 62 that is the upper jig 60 is disposed in the rectangular hole 61 b of the cooperation member 61.

In step S14, the semiconductor device 1 held by the manufacturing jig 10 is put into a reflow furnace, heated by the upper and lower heaters 81 and 82, and then cooled, whereby the solder materials 7, 8, and 9 are changed. Melt and then solidify. Thus, the three-layer soldering joining process between the water jacket 2 and the substrate 4, between the substrate 4 and the semiconductor chip 5, and between the semiconductor chip 5 and the wiring member 6 is simultaneously performed.
Here, the upper jig 60, the water jacket 2, and the lower jig 20 perform different thermal expansion changes (expansion and contraction) due to the heating of the heaters 81 and 82. In this case, the upper jig 60 and the lower jig 20 are fixed by one first fixing pin 71, and the water jacket 2 and the lower jig 20 are fixed by one second fixing pin 72 in the vicinity of the first fixing pin 71. By fixing, the thermal expansion change (extension / contraction) of each of the upper jig 60, the water jacket 2 and the lower jig 20 is allowed. However, since the upper jig 60 and the lower jig 20 are made of a material having the same linear expansion coefficient, the thermal expansion change (expansion / contraction) is substantially equal. The surrounding member 41 positioned by the positioning pin 61 a via the correction member 31 moves without rotating in the horizontal direction according to the thermal expansion of the upper jig 60. Since the substrate 4 fixed to the surrounding member 41 is divided into a plurality of pieces and is smaller than the size of the semiconductor device 1 and is small in thermal expansion change, it is fixed by at least one pair of claws 41c and the water jacket of the entire lower surface. No cracking occurs due to the solder joint between the two.
In the reflow furnace, molten solder droplets of the solder materials 7, 8, 9 are generated on the surface of the semiconductor chip 5. However, the solder adhesion prohibition region on the surface of the semiconductor chip 5 is covered with the covers 52a and 52b of the sliding cover weight member 51a or the monoblock cover weight member 51b, thereby preventing adhesion of solder splashes.

According to the manufacturing method of the semiconductor device 1 according to the present embodiment, the following effects are exhibited.
The substrate 4, the semiconductor chip 5, and the wiring member 6 to be soldered by the solder materials 7, 8, and 9 are surrounded and fixed by the surrounding member 41 inserted through the positioning pins 61 a extended from the upper jig 60. . For this reason, the substrate 4, the semiconductor chip 5, and the wiring member 6 can be fixed apart from other members such as the lower jig 20 and the case 3. Therefore, a difference in thermal expansion between the water jacket 2 on which the substrate 4 is disposed in the reflow process (step S14) and other members such as the lower jig 20 and the case 3, or the water jacket 2 and the upper jig on which the substrate 4 is disposed. Even if the expansion and contraction between these members differs due to the difference in thermal expansion from 60, the substrate 4, the semiconductor chip 5 and the wiring member 6 fixed to the surrounding member 41 interfere with other members such as the lower jig 20 and the case 3. It is not allowed to move forward and backward in the horizontal direction. Further, since the substrate 4, the semiconductor chip 5, and the wiring member 6 fixed to the surrounding member 41 do not contact and are not affected by other members such as the lower jig 20 and the case 3, the stress is increased due to contact. The trouble of soldering of the semiconductor chip 5 to be generated does not occur. Therefore, the semiconductor device 1 can be soldered satisfactorily even when different expansion and contraction occurs between the members in the reflow process (step S14).

It should be noted that the present invention is not limited to the above-described embodiment, and modifications and improvements within the scope that can achieve the object of the present invention are included in the present invention.
The number of positioning pins for positioning one surrounding member is not limited to two, and may be two or more.
The solder material may be a high-temperature lead-free solder or the like, and may be a bonding material including a brazing material or metal particles such as nano Ag instead of the solder.
The claws may be provided between long regions on the opposite sides of the substrate, may be two or more pairs, or correspond to opposite sides different from the opposite sides to which at least one pair of claws correspond. It may be provided.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 4 ... Board | substrate 5 ... Semiconductor chip 6 ... Wiring member 8 ... 2nd solder material 9 ... 3rd solder material 10 ... Manufacturing jig 20 ... Lower jig 30 ... Surrounding jig 50 ... Weight jig 60 ... Top Jig 61a ... Positioning pin

Claims (2)

A method of manufacturing a semiconductor device for performing solder reflow on a semiconductor device on which a mounting component is mounted,
A plurality of conical round holes are formed around the substrate, an outer peripheral portion that is slightly larger than the substrate is formed, and a pair of claws for fixing the outer peripheral edge of the substrate is formed below the outer peripheral portion. Placing a go jig to be performed ;
Placing a semiconductor chip with a solder material interposed in the substrate;
Arranging a wiring member with a solder material interposed on the semiconductor chip;
Placing a weight jig on the wiring member;
The semiconductor device is vertically sandwiched between an upper jig and a lower jig, and a positioning pin having a pointed tip formed extending from the upper jig is inserted into the round hole of the surrounding jig. , Positioning the go jig,
A reflow process in which the semiconductor device on which the surrounding jig is positioned is heated in a reflow furnace and then cooled, so that the solder material is melted and then solidified and soldered. Manufacturing method. A semiconductor device manufacturing jig for performing solder reflow on a semiconductor device on which mounted components are mounted,
A plurality of conical round holes are formed around the substrate on which the mounting component is mounted, and an outer peripheral portion that is slightly larger than the substrate is formed. A go jig in which a pair of claws for fixing the periphery is formed ;
A weight jig disposed on the mounting component laminated with a solder material interposed therebetween;
An upper jig and a lower jig for sandwiching the semiconductor device vertically;
A positioning pin that extends from the upper jig and is inserted into the round hole of the surrounding jig so that the tip for positioning the surrounding jig is formed into a pointed shape, and
A semiconductor device manufacturing jig, which is put into a reflow furnace together with the semiconductor device.

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