JP6146146B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly to a silicon carbide semiconductor device and a manufacturing method thereof.

  Among semiconductor devices using silicon carbide as a material, for example, whether or not an inversion layer is formed in a channel region with a predetermined threshold voltage as a boundary, such as a MOSFET (Metal Oxide Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). However, in a semiconductor device that conducts and cuts off current, various studies have been made on improving channel mobility and reducing on-resistance.

  In JP-A-9-199724, a groove extending in the <112-0> direction and penetrating through both the n + type source region and the p type silicon carbide semiconductor layer and reaching the n− type silicon carbide semiconductor layer is disclosed. A silicon carbide semiconductor device in which an n-type silicon carbide semiconductor thin film layer is formed on the inner wall by epitaxial growth is described.

JP 9-199724 A

  However, the silicon carbide semiconductor device described in Japanese Patent Laid-Open No. 9-199724 realizes high mobility while suppressing the occurrence of so-called short channel effects such as lowering of the threshold voltage and deterioration of characteristics such as punch-through breakdown of the channel region. Is difficult. Specifically, since the n-type silicon carbide semiconductor thin film layer is formed by epitaxial growth, the silicon carbide semiconductor device has a certain impurity concentration. Therefore, when the thickness of the p-type silicon carbide semiconductor layer is reduced and the impurity concentration of the p-type silicon carbide semiconductor layer is increased to shorten the channel, the entire n-type silicon carbide semiconductor thin film layer is increased in concentration. When formed, it is difficult to suppress the occurrence of the short channel effect. On the other hand, when the entire n-type silicon carbide semiconductor thin film layer is formed at a low concentration, it is difficult to reduce the resistance of the n-type silicon carbide semiconductor thin film layer, and it is difficult to reduce the on-resistance. That is, it has been difficult to obtain a high-performance silicon carbide semiconductor device that can reduce channel resistance while suppressing the occurrence of the so-called short channel effect.

  The present invention has been made to solve the above-described problems. A main object of the present invention is to provide a high-performance silicon carbide semiconductor device and a method for manufacturing the same.

  A silicon carbide semiconductor device according to the present invention includes a first layer having a first conductivity type, a second layer having a second conductivity type provided on the first layer, and a second layer. And a silicon carbide substrate including a third layer having a first conductivity type. The silicon carbide substrate is provided with a trench having a sidewall extending through the third layer and the second layer to reach the first layer, and the sidewall has a surface orientation {0-33-8}. 1 face is included. The first surface is covered with an insulating film, and is in contact with the insulating film on the first surface of the sidewall, and the first impurity implantation region having the first conductivity type from the third layer to the first layer Is further provided.

  According to the present invention, a high-performance silicon carbide semiconductor device can be obtained.

It is sectional drawing of the silicon carbide semiconductor device which concerns on this Embodiment. It is a figure for demonstrating the impurity concentration distribution of the channel region of the silicon carbide semiconductor device which concerns on this Embodiment. It is a flowchart of the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the manufacturing method of the silicon carbide semiconductor device which concerns on this Embodiment. It is sectional drawing for demonstrating the example of a change of the silicon carbide semiconductor device which concerns on this Embodiment. It is a fragmentary sectional view which shows roughly the microscopic structure of the side wall surface which has a special surface. It is a figure which shows the crystal structure of the (000-1) plane in the hexagonal crystal of polytype 4H. It is a figure which shows the crystal structure of the (11-20) plane which follows the line XV-XV of FIG. It is a figure which shows the crystal structure in the surface vicinity of the composite surface of FIG. 13 in (11-20) plane. It is the figure which looked at the compound surface of Drawing 13 from the (01-10) plane. FIG. 5 is a graph showing an example of the relationship between the angle between the channel plane and the (000-1) plane viewed macroscopically and the channel mobility when thermal etching is performed and when it is not performed. It is. It is a graph which shows an example of the relationship between the angle between a channel direction and the <0-11-2> direction, and channel mobility. It is a figure which shows the modification of FIG.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

First, an outline of an embodiment of the present invention will be described.
(1) A first layer having a first conductivity type (drift layer 2) and a second layer having a second conductivity type provided on the first layer (drift layer 2) (body region 3) And a silicon carbide substrate (epitaxial substrate 100) including a third layer (source region 4) provided on the second layer (body region 3) and having the first conductivity type. The silicon carbide substrate (epitaxial substrate 100) has a trench having a side wall that penetrates through the third layer (source region 4) and the second layer (body region 3) to reach the first layer (drift layer 2). The side wall (side wall surface SW) is provided including a first surface (plane S1) having a plane orientation {0-33-8}. The first surface is covered with an insulating film (gate insulating film 8), contacts the insulating film (gate insulating film 8) on the first surface of the side wall (sidewall surface SW), and a third layer (source region). A first impurity implantation region (n-type channel region 7) having the first conductivity type from 4) to the first layer (drift layer 2) is further provided.

  In this way, the first impurity implantation region (n-type channel region 7) and the second impurity are directly below the insulating film (gate insulating film 8) covering each of the sidewall surface SW and the bottom surface BT of the trench TR. Since the layer (body region 3) is bonded, the first impurity implantation region (n-type channel region 7) and the second layer (in the state where a voltage higher than the threshold voltage is not applied to the gate electrode 9) A depletion layer extends from the boundary surface of the junction with the body region 3) toward the first impurity implantation region (n-type channel region 7). When no voltage higher than the threshold voltage is applied, no conduction channel is formed. Further, since the sidewall surface SW of the trench TR has a special surface, the interface state density at the interface between the insulating film (gate insulating film 8) and the first impurity implantation region (n-type channel region 7) is reduced. In addition to the reduction, the mobility of the conduction channel formed in the first impurity implantation region (n-type channel region 7) can be increased.

  (2) The impurity concentration of the first impurity implantation region (n-type channel region 7) may change in a direction along the first surface (surface S1). In this way, even when the second layer (body region 3) is provided with a constant impurity concentration in the thickness direction of the silicon carbide substrate (epitaxial substrate 100), the first impurity implantation region (n-type) In the channel region 7), the depletion layer formed at the junction interface with the second layer (body region 3) spreads differently in the channel extending direction. That is, the first impurity implantation region (n-type channel region 7) can include a region that is easily depleted and a region that has a high impurity concentration. As a result, silicon carbide semiconductor device 200 can suppress the occurrence of a so-called short channel effect such as a decrease in threshold voltage and deterioration of characteristics such as punch-through breakdown of the channel region, and can reduce channel resistance.

  (3) The impurity concentration of the first impurity implantation region (n-type channel region 7) may be lower on the first layer (drift layer 2) side than on the third layer (source region 4) side. . In this way, the first impurity implantation region (n-type channel region 7) is easily depleted on the first layer (drift layer 2) side where the impurity concentration of the first conductivity type is low. . As a result, in silicon carbide semiconductor device 200, the occurrence of a so-called short channel effect such as a decrease in threshold voltage and deterioration in characteristics such as punch-through breakdown of the channel region is effectively suppressed.

  (4) The insulating film (gate insulating film 8) and the third layer (source region 4) may be in direct contact. In this way, silicon carbide semiconductor device 200 generates high-concentration conduction electrons in a region where n source region 4 having a higher impurity concentration than n-type channel region 7 and gate insulating film 8 are in direct contact. be able to. Furthermore, silicon carbide semiconductor device 200 can distribute high-concentration conduction electrons generated in the region to n-type channel region 7.

  (5) A first layer having a first conductivity type (drift layer 2) and a second layer having a second conductivity type provided on the first layer (drift layer 2) (body region 3) And a step of preparing a silicon carbide substrate (epitaxial substrate 100) including a third layer (source region 4) provided on the second layer (body region 3) and having the first conductivity type (S10); Then, a trench having a sidewall extending through the third layer (source region 4) and the second layer (body region 3) to the first layer (drift layer 2) is formed in the silicon carbide substrate (epitaxial substrate 100). Step (S40). The side wall includes a first surface (plane S1) having a plane orientation {0-33-8}. In the step of forming trench TR (S40), the first conductivity from the third layer (source region 4) exposed on the first surface (surface S1) of the sidewall to the first layer (drift layer 2). A first impurity implantation region (n-type channel region 7) having a type is formed.

  In the step (S40), exposed on the side wall surface SW including the first surface (surface S1) having the surface orientation {0-33-8} and bonded to the second layer (body region 3) The first impurity implantation region (n-type channel region 7) can be formed using an ion implantation method. As a result, when the insulating film (gate insulating film 8) is formed so as to cover the sidewall surface SW of the trench TR and the gate electrode 9 is further formed, the first impurity implantation region (n-type channel region 7) is carbonized. It can function as a channel region of the silicon semiconductor device 200. Thereby, generation of so-called short channel effect is suppressed, and high performance silicon carbide semiconductor device 200 capable of reducing channel resistance can be obtained.

  (6) The impurity concentration of the first impurity implantation region (n-type channel region 7) may be changed in the direction along the first surface (surface S1). That is, by controlling the implantation conditions in the step (S40), the first impurity implantation region (n-type channel region 7) including the region that is likely to be depleted and the region having a high impurity concentration can be easily formed. .

  (7) The first impurity implantation region (n-type channel region 7) may be formed before the trench TR. That is, first, as a step (S45) of forming the first impurity implantation region (n-type channel region 7), ions may be implanted using the mask film 16. Thereafter, by performing the step of forming a trench (S46), the first impurity implantation region (n-type channel region 7) can be formed on the side wall surface SW.

  (8) The first impurity implantation region (n-type channel region 7) may be formed after the trench TR. Even in this case, the first impurity implantation region (from the third layer (source region 4) exposed on the first surface (surface S1) of the sidewall surface SW to the first layer (drift layer 2) ( The first impurity implantation region (n-type channel region 7) is exposed on the side wall surface SW by ion implantation using the mask film 16 corresponding to the region where the n-type channel region 7) is to be formed. Can be formed.

Next, embodiments of the present invention will be described in more detail.
First, the structure of the silicon carbide semiconductor device according to the present embodiment will be described with reference to FIG. Silicon carbide semiconductor device 200 according to the present embodiment is configured as a vertical MOSFET. The silicon carbide semiconductor device shown in FIG. 1 includes an epitaxial substrate 100, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 10, a source electrode 12, a source wiring layer 13, a drain electrode 14, and a back surface. And a protective electrode 15. Epitaxial substrate 100 includes base substrate 1, drift layer 2, body region 3 (body region 3), source region 4, contact region 5, and n-type channel region 7. The plane orientation of the upper surface of the epitaxial substrate 100 has an off angle larger than 0 degree and smaller than 8 degrees with respect to {0001}.

Base substrate 1 is made of single-crystal silicon carbide having a crystal system of hexagonal crystal and has a conductivity type of n-type (first conductivity type). Base substrate 1 contains an impurity such as N (nitrogen) at a high concentration. The concentration of impurities such as nitrogen contained in the base substrate 1 is, for example, about 1.0 × 10 ¹⁸ cm ⁻³ .

Drift layer 2 has n-type conductivity. The drift layer 2 is an epitaxial layer formed on the base substrate 1. Drift layer 2 contains an impurity such as nitrogen (N), for example. The impurity concentration of drift layer 2 is lower than the impurity concentration of base substrate 1, and is, for example, 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less.

Body region 3 has a p-type conductivity (second conductivity type). Body region 3 is formed on drift layer 2. Body region 3 contains impurities such as aluminum (Al) and boron (B). The impurity concentration of the body region 3 is 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less, and preferably 1 × 10 ¹⁸ cm ⁻³ . The thickness of the body region 3 is, for example, not less than 0.3 μm and not more than 1.2 μm, and preferably about 0.5 μm.

Source region 4 has n type conductivity. Source region 4 is formed on body region 3. Source region 4 contains an impurity such as N, for example. The impurity concentration of the source region 4 is 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. The thickness of the source region 4 is, for example, not less than 0.1 μm and not more than 0.4 μm, preferably about 0.2 μm.

  Contact region 5 has a p-type conductivity. Contact region 5 is formed to penetrate body region 3 through source region 4. Contact region 5 contains impurities such as aluminum (Al) and boron (B).

  Trench TR is provided by partially removing source region 4, body region 3, and drift layer 2 on the upper surface of epitaxial substrate 100 (the surface opposite to base substrate 1). Trench TR has side wall surface SW and bottom surface BT. Sidewall surface SW passes through source region 4 and body region 3 and reaches drift layer 2. The bottom surface BT is located in the drift layer 2. Bottom surface BT has a flat shape substantially parallel to the top surface of epitaxial substrate 100.

  Sidewall surface SW is inclined with respect to the upper surface of epitaxial substrate 100, whereby trench TR expands in a tapered shape toward the opening. Side wall surface SW has a predetermined crystal plane (also referred to as a special plane) at least on body region 3. Details of the special surface will be described later.

N-type channel region 7 has n-type conductivity. N-type channel region 7 is formed in source region 4, body region 3 and drift layer 2 along side wall surface SW of trench TR. That is, in the present embodiment, the n-type channel region 7 is formed so as to be exposed on the entire side wall surface SW. The n-type channel region 7 is not formed so as to be exposed on the bottom surface BT. The n-type impurity contained in the n-type channel region 7 is, for example, P (phosphorus). The n-type channel region 7 is provided so that the impurity concentration is lower than the impurity concentration of the source region 4 and higher than the impurity concentration of the drift layer 2. The impurity concentration of the n-type channel region 7 is set higher than the impurity concentration of the body region 3, and preferably 1.05 times or more the impurity concentration of the body region 3. For example, the impurity concentration of the n-type channel region 7 is 5 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, preferably 5 × 10 ¹⁸ cm ⁻³ .

FIG. 2 shows the impurity concentration distribution of the n-type channel region 7 in the present embodiment. FIG. 2A is a schematic cross-sectional view of an n-type channel region 7 formed so as to be in contact with the source region 4, the body region 3, and the drift layer 2, and FIG. 2B is shown in FIG. 4 is a graph showing the impurity concentration distribution in the depth direction of trench TR (stacking direction of source region 4, body region 3 and drift layer 2) for n-type channel region 7. Referring to FIG. 2, the impurity concentration of n-type channel region 7 changes in the direction along side wall surface SW in n-type channel region 7, and preferably in the vicinity of the interface between drift layer 2 and body region 3. The n-type channel region 7 has an impurity concentration lower than that of the n-type channel region 7 in the vicinity of the interface between the body region 3 and the source region 4. That is, the impurity concentration of n-type channel region 7 near the interface between drift layer 2 and body region 3 is, for example, 5 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. The impurity concentration of n-type channel region 7 in the vicinity of the interface between body region 3 and source region 4 is, for example, 5 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. At this time, the impurity concentration of the n-type channel region 7 formed on the body region 3 gradually increases from the impurity concentration of the n-type channel region 7 in the vicinity of the interface between the drift layer 2 and the body region 3. 3 and the source region 4 may be provided so as to reach the impurity concentration of the n-type channel region 7 near the interface. In the present embodiment, the impurity concentration of n-type channel region 7 formed on source region 4 (located on the upper surface side of epitaxial substrate 100 from the interface between body region 3 and source region 4) is the same as that of body region 3. And the impurity concentration of the n-type channel region 7 in the vicinity of the interface between the source region 4 and the source region 4.

  Gate insulating film 8 covers each of side wall surface SW and bottom surface BT of trench TR. That is, the gate insulating film 8 directly contacts and covers the n-type channel region 7 on the sidewall surface SW of the trench TR. The gate electrode 9 is provided on the gate insulating film 8. Source electrode 12 is in contact with each of source region 4 and p contact region 5. The source wiring layer 13 is in contact with the source electrode 12. Source wiring layer 13 is, for example, an aluminum layer. The interlayer insulating film 10 insulates between the gate electrode 9 and the source wiring layer 13.

  Next, the operation of the semiconductor device shown in FIG. 1 will be briefly described. Referring to FIG. 1, in a state where a voltage higher than a threshold is not applied to gate electrode 9, that is, in an off state, a conduction channel is formed in n-type channel region 7 provided immediately below gate insulating film 8 and on body region 3. Is not formed. Specifically, in the vicinity of the interface between drift layer 2 and body region 3, the depletion layer expands from the interface of the junction between n-type channel region 7 and body region 3 to the n-type channel region 7 side in the off state. It becomes a non-conductive state. On the other hand, when a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode 9, an accumulation layer is formed in the n-type channel region 7 provided on the body region 3. As a result, the source region 4 and the drift layer 2 are electrically connected. As a result, a current flows between the source electrode 12 and the drain electrode 14.

  Next, with reference to FIGS. 3 to 10, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described.

First, base substrate 1 made of single crystal silicon carbide having a hexagonal crystal system is prepared (step (S10)). Next, referring to FIG. 4, drift layer 2 is formed by epitaxial growth of silicon carbide on base substrate 1 (step (S20)). The surface of the base substrate 1 on which epitaxial growth is performed preferably has an off angle within 8 degrees from the {000-1} plane, and more preferably has an off angle within 8 degrees from the (000-1) plane. . Epitaxial growth can be performed by a CVD method. As the source gas, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) can be used. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.

Next, referring to FIG. 5, body region 3 and source region 4 are formed on drift layer 2 (step (S30)). These can be formed by ion implantation onto the upper surface 2A of the drift layer 2, for example. In ion implantation for forming body region 3, an impurity such as aluminum (Al) for imparting p-type is ion-implanted. In the ion implantation for forming the source region 4, an impurity for imparting n-type, such as phosphorus (P), is implanted. Instead of ion implantation, epitaxial growth may be used with the addition of impurities. Further, contact region 5 is formed on drift layer 2, body region 3 and source region 4. Specifically, a mask film having an opening corresponding to a position where the contact region 5 is to be formed is formed on the source region 4, and the mask film is used to form, for example, Al or the like on the upper surface of the source region 4. A p-type impurity is ion-implanted. The mask film is made of, for example, silicon dioxide (SiO ₂ ). After the contact region 5 is formed, the mask film is removed.

  Next, referring to FIGS. 6 to 8, trench TR is formed (step (S40)). Specifically, the trench TR is formed and the n-type channel region 7 is formed. In the present embodiment, first, referring to FIG. 6, n-type channel region 7 is formed (step (S45)). Specifically, first, mask film 16 having an opening corresponding to a position where bottom surface BT of trench TR is to be formed in the subsequent step (S46) is formed on source region 4. The opening of the mask film 16 is formed wider on the side where the sidewall surface SW of the trench TR is to be formed than the bottom surface BT of the trench TR. The opening of the mask film 16 is defined by the wall surface 16w. The material of the mask film 16, the film thickness, and the shape of the wall surface 16 </ b> W (such as the inclination angle with respect to the upper surface 2 </ b> A) are ion-implanted through the mask film 16 in this step (S <b> 40) under predetermined implantation conditions (such as implantation energy). In this case, the n-type channel region 7 is provided along the side wall surface SW. The film thickness of the mask film 16 covering the position where the n-type channel region 7 is not formed only needs to be sufficient to prevent ion implantation into the source region 4.

  In this step (S45), an n-type impurity is then implanted into the upper surface 2A using the mask film 16. In the present embodiment, the injection direction is a direction perpendicular to the upper surface 2A. At the position where the wall surface 16w of the mask film 16 is formed on the upper surface 2A, n-type impurities are implanted through the wall surface 16w of the mask film 16. The implantation energy of the n-type impurity in this step (S45) is, for example, about 100 keV or more and 500 keV or less. When the implantation energy is less than 100 keV, it is difficult to form the n-type channel region 7 across the source region 4, the body region 3 and the drift layer 2. On the other hand, when the implantation energy exceeds 500 keV, the depth from the top surface 2A is deeper than the position on the drift layer 2 where the bottom surface BT of the trench TR will be formed in the subsequent step (S46). Impurities may be implanted into the region.

  At this time, by controlling the implantation conditions such as the implantation energy and the dose amount, the n-type channel region 7 changes the impurity concentration in the direction along the side wall surface SW formed in the subsequent step (S46). It is formed. Preferably, the impurity concentration of n-type channel region 7 near the interface between drift layer 2 and body region 3 is set lower than the impurity concentration of n-type channel region 7 near the interface between body region 3 and source region 4. It is done. Thus, epitaxial substrate 100 including base substrate 1, drift layer 2, body region 3, source region 4, contact region 5, and n-type channel region 7 is formed.

Next, referring to FIGS. 7 and 8, trench TR is formed (step (S46)). Specifically, referring to FIG. 7, first, after removing mask film 16 shown in FIG. 16, mask layer 17 is formed on the upper surface of source region 4. As the mask layer 17, for example, an insulating film such as SiO ₂ can be used. As a method for forming mask layer 17, an insulating film is formed using, for example, a CVD method. The thickness of the mask layer 17 may be any thickness that can reliably remain when exposed to the etching conditions in this step (S46). Next, a resist film (not shown) having an opening in a region where the bottom surface BT of the trench TR is to be formed is formed on the insulating film using a photolithography method. Using the resist film as a mask, the insulating film exposed from the opening of the resist film is removed, thereby forming an opening pattern in the insulating film. Thereafter, the resist film is removed. As a result, mask layer 17 having an opening in the region where bottom surface BT of trench TR shown in FIG. 7 is to be formed is formed.

Next, referring to FIG. 7, using mask layer 17 as a mask, part of n-type channel region 7 is removed by etching. As an etching method, for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. By such etching, a groove having a side wall substantially perpendicular to the upper surface 2A of the epitaxial substrate 100 (the upper surface of the source region 4) is formed in the region where the trench TR is to be formed. In this way, the structure shown in FIG. 7 is obtained.

Next, referring to FIG. 8, using mask layer 17 as a mask, part of n-type channel region 7 is further removed by thermal etching. The thermal etching can be performed, for example, by heating the substrate in an atmosphere containing a reactive gas having at least one kind of halogen atom. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less. Thereby, trench TR having sidewall surface SW is formed. Side wall surface SW is inclined with respect to the upper surface of epitaxial substrate 100, and n-type channel region 7 is exposed on the entire surface of side wall surface SW. Preferably, side wall surface SW includes a predetermined crystal plane (also referred to as a special plane) on n-type channel region 7 provided on body region 3. Specifically, sidewall surface SW includes a surface having a plane orientation {0-33-8}. Referring to FIG. 9, mask layer 17 is removed by an arbitrary method after obtaining the structure shown in FIG.

  Next, activation annealing for activating the impurities implanted into the epitaxial substrate 100 is performed (step (S50)). Specifically, a heat treatment is performed in which the epitaxial substrate 100 is heated to, for example, about 1700 ° C. and held for about 30 minutes in an inert gas atmosphere such as argon (Ar). As a result, the impurities implanted into the epitaxial substrate 100 are activated.

  Next, referring to FIG. 10, a gate insulating film is formed (step (S60)). Specifically, gate insulating film 8 is formed so as to cover side wall surface SW and bottom surface BT of trench TR and the upper surface of epitaxial substrate 100. The gate insulating film 8 can be formed by thermal oxidation, for example.

  Next, referring to FIG. 11, gate electrode 9 is formed (step (S70)). Specifically, gate electrode 9 is formed so as to fill the region inside trench TR (region surrounded by side wall surface SW and bottom surface BT) with gate insulating film 8 interposed therebetween. First, a conductor film to be a gate electrode is formed on the gate insulating film 8 by using a sputtering method or the like. As a material of the conductor film, any material such as metal can be used as long as it is a conductive material. Thereafter, the portion of the conductor film formed in a region other than the inside of trench TR is removed by using any method such as etch back or CMP. In this way, the structure shown in FIG. 11 is obtained.

  Next, referring to FIG. 12, interlayer insulating film 10 is formed (step (S80)). Specifically, first, an interlayer insulating film 10 is formed on the gate insulating film 8 and the gate electrode 9 so as to cover the upper surface of the gate electrode 9. The material constituting the interlayer insulating film 10 may be any material as long as it has insulating properties. Next, a resist film (not shown) having an opening on the p-type contact region 5 is formed on the interlayer insulating film 10. Using the resist film as a mask, the interlayer insulating film 10 and the gate insulating film 8 are partially removed by etching. As a result, the interlayer insulating film 10 and the gate insulating film 8 are formed with openings in which part of the p-type contact region 5 and the source region 4 are exposed.

  Next, ohmic electrodes (source electrode 12 and drain electrode 14) are formed (step (S90)). Specifically, first, the source electrode 12 is formed by a lift-off method using the resist film formed in the previous step (S80). Source electrode 12 is formed in contact with p-type contact region 5 and source region 4. Furthermore, the drain electrode 14 is formed on the lower surface (the surface opposite to the surface where the trench TR is formed) of the epitaxial substrate 100 in the base substrate 1.

  Next, pad electrodes (not shown) and wirings (not shown) electrically connected to the respective electrodes are formed (step (S100)). By the above procedure, silicon carbide semiconductor device 200 according to the present embodiment can be obtained.

  Next, functions and effects of silicon carbide semiconductor device 200 and the method for manufacturing the same according to the present embodiment will be described.

  In silicon carbide semiconductor device 200 in accordance with the present embodiment, n-type channel region 7 is entirely formed on sidewall surface SW of trench TR formed so as to penetrate source region 4 and body region 3 to reach drift layer 2. It is formed so as to be exposed. That is, the n-type channel region 7 and the body region 3 are joined immediately below the gate insulating film 8 covering each of the sidewall surface SW and the bottom surface BT of the trench TR. Therefore, in a state where a voltage equal to or higher than the threshold voltage is not applied to the gate electrode 9, as described above, the depletion layer is located on the n-type channel region 7 side from the boundary surface of the junction between the n-type channel region 7 and the body region 3. , And no conduction channel is formed in the n-type channel region 7. On the other hand, in a state where a voltage equal to or higher than the threshold voltage is applied to the gate electrode 9, an accumulation layer is formed in the n-type channel region 7 provided on the body region 3. A conduction channel is formed.

  Furthermore, the sidewall surface SW of the trench TR has a special surface. Therefore, the interface state density at the interface between the gate insulating film 8 and the n-type channel region 7 can be reduced, and the mobility of the conduction channel formed in the n-type channel region 7 can be increased.

Since the n-type channel region 7 is formed by ion implantation, the impurity concentration distribution of the n-type channel region 7 can be controlled by controlling the implantation conditions. Therefore, the impurity concentration of n-type channel region 7 near the interface between drift layer 2 and body region 3 is set lower than the impurity concentration of n-type channel region 7 near the interface between body region 3 and source region 4. Can do. In this case, in the vicinity of the interface between drift layer 2 and body region 3, a depletion layer generated at the interface of the junction between n-type channel region 7 and body region 3 in the off state expands to the n-type channel region 7 side. . As a result, even when the body region 3 is formed thin, the short channel effect can be more effectively suppressed. Further, the threshold voltage can be increased by reducing the impurity concentration of the n-type channel region 7. That is, the threshold voltage can be controlled by controlling the impurity concentration of the n-type channel region 7. Further, in this case, the impurity concentration of the n-type channel region 7 in the vicinity of the interface between the body region 3 and the source region 4 is set high, for example, about 5 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ¹⁹ m ^−3. It may be done. In this case, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 9, a conduction channel is formed in the n-type channel region 7 provided immediately below the gate insulating film 8 and on the body region 3. In addition, channel resistance can be reduced and on-resistance can be reduced.

  In the present embodiment, the n-type channel region 7 is formed so as to be exposed on the entire side wall surface SW. However, the present invention is not limited to this. The n-type channel region 7 may be formed at least in a portion on the n-type channel region 7 formed in the body region 3. For example, referring to FIG. 11, n-type channel region 7 may be formed to be in contact with drift layer 2 on the drain electrode 14 side, and preferably extends a relatively long distance in drift layer 2. do not do. In this way, drift layer 2 having a lower impurity concentration and higher mobility than n-type channel region 7 can be used more actively as a current path in silicon carbide semiconductor device 200. As a result, channel mobility of silicon carbide semiconductor device 200 can be further improved. Referring to FIG. 11, n-type channel region 7 may be formed on the source electrode 12 side so as to be in contact with n source region 4. In this case, a region in which the n source region 4 having a higher impurity concentration than the n-type channel region 7 and the gate insulating film 8 are in direct contact with each other is formed. 7 can be distributed.

  In the present embodiment, the step (S46) for forming the trench TR is performed after the step (S45) for forming the n-type channel region 7, but the present invention is not limited to this. For example, after forming the trench TR, the n-type channel region 7 may be formed by performing ion implantation on the sidewall surface SW of the trench TR.

  Next, the above-mentioned “special surface” will be described in detail. As described above, the sidewall surface SW of the trench TR has a special surface.

  As shown in FIG. 13, the side wall surface SW having a special surface includes a surface S1. The plane S1 has a plane orientation {0-33-8}, and preferably has a plane orientation (0-33-8). Preferably, the side wall surface SW includes the surface S1 microscopically. Preferably, side wall surface SW further includes a surface S2 (second surface) microscopically. The plane S2 has a plane orientation {0-11-1}, and preferably has a plane orientation (0-11-1). Here, “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As such a microscopic structure observation method, for example, TEM (Transmission Electron Microscope) can be used.

  Preferably, side wall surface SW has composite surface SR. The composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). Composite surface SR has a plane orientation {0-11-2}, preferably a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used. Preferably, the channel direction CD, which is the direction in which carriers flow on the channel surface, is along the direction in which the above-described periodic repetition is performed. Next, the detailed structure of the composite surface SR will be described.

  In general, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 14, Si atoms (or C atoms) are atoms of the A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.

  As shown in FIG. 15, in the (11-20) plane (cross section taken along line XV-XV in FIG. 14), the atoms in each of the four layers ABCB constituting one cycle described above are (0-11-2). It is not arranged to be completely along the plane. In FIG. 15, the (0-11-2) plane is shown so as to pass through the position of the atoms in the B layer. In this case, the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when the atomic level structure is ignored is limited to (0-11-2), this surface is microscopic. Can take various structures.

  As shown in FIG. 16, in the composite surface SR, a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface on which the surface S1 and the surface S2 are averaged corresponds to the (0-11-2) surface (FIG. 15).

  As shown in FIG. 17, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (part of the surface S1) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 17) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 17). It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.

  Next, the relationship between the crystal plane of the side wall surface SW and the mobility MB of the channel surface will be described with reference to FIG. In the graph of FIG. 18, the horizontal axis indicates the angle D1 formed by the macroscopic surface orientation of the side wall surface SW having the channel surface and the (000-1) plane, and the vertical axis indicates the mobility MB. The plot group CM corresponds to the case where the side wall surface SW is finished as a special surface by thermal etching, and the plot group MC corresponds to the case where such thermal etching is not performed.

  The mobility MB in the plot group MC was maximized when the macroscopic plane orientation of the surface of the channel surface was (0-33-8). This is because when the thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the microscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the visual plane orientation (0-33-8), that is, the plane orientation (0-33-8) when considering even the atomic level is stochastically increased.

  On the other hand, the mobility MB in the plot group CM is maximized when the macroscopic surface orientation of the channel surface is (0-11-2) (arrow EX). The reason for this is that, as shown in FIGS. 16 and 17, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel surface is fine. This is probably because the ratio of the visual plane orientation (0-33-8) is increased.

  The mobility MB has orientation dependency on the composite surface SR. In the graph shown in FIG. 19, the horizontal axis indicates the angle D2 between the channel direction and the <0-11-2> direction, and the vertical axis indicates the mobility MB (arbitrary unit) of the channel surface. A broken line is added to make the graph easier to see. From this graph, in order to increase the channel mobility MB, the angle D2 of the channel direction CD (FIG. 13) is preferably 0 ° or more and 60 ° or less, and more preferably approximately 0 °. all right.

  As shown in FIG. 20, side wall surface SW may further include a surface S3 (third surface) in addition to composite surface SR (shown in FIG. 20 as being simplified by a straight line). In this case, the off angle of the side wall surface SW with respect to the {000-1} plane deviates from 62 °, which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane. More preferably, the off angle of the side wall surface SW with respect to the (000-1) plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.

  More specifically, the sidewall surface SW may include a composite surface SQ configured by periodically repeating the surface S3 and the composite surface SR. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy).

  Although the embodiment of the present invention has been described above, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

  1 base substrate, 2 drift layer, 2A top surface, 3 body region, 4 source region, 5 contact region, 7 n-type channel region, 8 gate insulating film, 9 gate electrode, 10 interlayer insulating film, 12 source electrode, 13 source wiring Layer, 14 drain electrode, 16 mask film, 16w wall surface, 17 mask layer, 100 epitaxial substrate, 200 silicon carbide semiconductor device.

Claims (6)

A first layer having a first conductivity type; a second layer having a second conductivity type provided on the first layer; and a first conductivity type provided on the second layer. A silicon carbide substrate including a third layer having
The silicon carbide substrate is provided with a trench having a sidewall extending through the third layer and the second layer to reach the first layer,
The side wall includes a first surface having a plane orientation {0-33-8}, and the first surface is covered with an insulating film;
A first impurity implantation region having a first conductivity type in contact with the insulating film on the first surface of the sidewall and extending from the third layer to the first layer;
The silicon carbide semiconductor device , wherein an impurity concentration of the first impurity implantation region in a portion facing the second layer is lower on the first layer side than on the third layer side .   2. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of said first impurity implantation region changes in a direction along said first surface. The insulating film and said third layer are in direct contact with silicon carbide semiconductor device according to claim 1 or 2. A first layer having a first conductivity type; a second layer having a second conductivity type provided on the first layer; and a first conductivity type provided on the second layer. Providing a silicon carbide substrate including a third layer having;
Forming a trench having a side wall extending through the third layer and the second layer to the first layer in the silicon carbide substrate,
The side wall includes a first surface having a plane orientation {0-33-8};
In the step of forming the trench, a first impurity implantation region having a first conductivity type from the third layer exposed from the first surface of the side wall to the first layer is formed,
The method for manufacturing a silicon carbide semiconductor device , wherein an impurity concentration of the first impurity implantation region in a portion facing the second layer is lower on the first layer side than on the third layer side . The method for manufacturing a silicon carbide semiconductor device according to claim 4 , wherein an impurity concentration of the first impurity implantation region is changed in a direction along the first surface. 6. The method for manufacturing a silicon carbide semiconductor device according to claim 4 , wherein said first impurity implantation region is formed prior to said trench.

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