JP6146144B2 - Semiconductor device and manufacturing method thereof. - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device having a through electrode penetrating a semiconductor substrate and a manufacturing method thereof.

  In order to stack and mount semiconductor chips, it is known to form through electrodes (for example, TSV: Through Silicon Via) penetrating a semiconductor substrate. It is known to form an insulating film between a through electrode and a through hole (for example, Patent Document 1).

JP 2011-82291 A

  However, the semiconductor substrate may be warped by the insulating film formed on the upper surface of the semiconductor substrate on which the through electrode is formed. The semiconductor device and the manufacturing method thereof are characterized by suppressing warpage of the semiconductor substrate.

Forming a through electrode in a hole formed from the first surface to the second surface of the semiconductor substrate and not reaching the second surface; and an insulating film having an opening on the second surface of the semiconductor substrate. Forming a recess surrounding the through electrode so that an upper surface of the through electrode is exposed by removing the semiconductor substrate using the insulating film as a mask, and forming the through electrode in the recess. seen containing a step of forming an upper surface is embedded so as to expose the insulator, wherein the internal stress of the insulating film using the manufacturing method of a semiconductor device, wherein the internal stress smaller than the insulator.

A semiconductor substrate; a through electrode penetrating the semiconductor substrate; an insulating film formed on the surface of the semiconductor substrate; and the through electrode in a recess formed on the surface of the semiconductor substrate so as to surround the through electrode. There anda insulator embedded to expose the internal stress of the insulating film is used wherein a internal stress smaller than the insulator.

  According to the present semiconductor device and the manufacturing method thereof, warping of the semiconductor substrate can be suppressed.

FIG. 1A to FIG. 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. FIG. 2 is a diagram illustrating a problem in the first comparative example. FIG. 3A to FIG. 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 2. FIG. 4A and FIG. 4B are diagrams for explaining the problem in the second comparative example. FIG. 5A to FIG. 5E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 7A and 7B are cross-sectional views showing the etching of the semiconductor substrate. 8A to 8E are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9A to FIG. 9D are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10A to FIG. 10D are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 11A and FIG. 11B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 12A and 12B are cross-sectional views (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 13A and FIG. 13B are cross-sectional views (part 6) illustrating the method for manufacturing the semiconductor device according to the second embodiment.

  FIG. 1A to FIG. 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. With reference to FIG. 1A, the electrode 14, the metal terminal 16, and the solder 18 are formed on the first surface 72 of the semiconductor substrate 10. The through electrode 12 is formed from the first surface 72 to the second surface 70. The through electrode 12 does not penetrate the semiconductor substrate 10.

  Referring to FIG. 1B, the second surface 70 of the semiconductor substrate 10 is ground or polished to expose the through electrode 12. With reference to FIG. 1C, an insulator 50 is formed on the second surface 70 of the semiconductor substrate 10 so as to cover the through electrode 12. With reference to FIG. 1D, an opening 52 is formed in the insulator 50. The through electrode 12 is exposed through the opening 52. Referring to FIG. 1 (e), a terminal 54 connected to the through electrode 12 through the opening 52 is formed on the insulator 50.

  FIG. 2 is a diagram illustrating a problem in the first comparative example. Referring to FIG. 2, when the internal stress of the insulator 50 is large, when the semiconductor substrate 10 becomes thin, the warp of the semiconductor substrate 10 increases as indicated by an arrow 56. When the insulator 50 is resin, the internal stress is large and the semiconductor substrate 10 is likely to warp.

  FIG. 3A to FIG. 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 2. Referring to FIG. 3A, the through electrode 12 is formed in the semiconductor substrate 10 as in FIG. Referring to FIG. 3B, the second surface 70 of the semiconductor substrate 10 is ground or polished more than in FIG. With reference to FIG. 3C, the insulator 50 is formed on the second surface 70 of the semiconductor substrate 10 so as to cover the through electrode 12. With reference to FIG. 3D, the through electrode 12 is exposed by etching the insulator 50.

  FIG. 4A and FIG. 4B are diagrams for explaining the problem in the second comparative example. Referring to FIG. 4A, in FIG. 3D, the entire surface of the insulator 50 is dry-etched as indicated by an arrow 62. Referring to FIG. 4B, if the etching amount is too large, the insulator 50 becomes thin like the region 64 or the semiconductor substrate 10 is exposed. As a result, the insulator 50 does not function as a protective film for the semiconductor substrate 10.

  FIG. 5A to FIG. 5E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment. Referring to FIG. 5A, as in FIG. 1A, the electrode 14, the metal terminal 16, and the solder 18 are formed on the first surface 72 of the semiconductor substrate 10 such as a silicon substrate. The electrode 14 mainly contains a metal such as Al (aluminum) or Cu (copper). The metal terminal 16 mainly contains a metal such as Cu. The solder mainly contains Sn—Ag, Sn—Bi, Sn—Ag—Cu, and the like. The through electrode 12 is formed from the first surface 72 toward the second surface 70. The through electrode 12 does not penetrate the semiconductor substrate 10. The through electrode 12 mainly contains a metal such as Cu. The insulating film 20 is formed on the second surface 70. The insulating film 20 mainly contains an inorganic insulator such as silicon oxide or silicon nitride.

  Referring to FIG. 5B, an opening 22 is formed in the insulating film 20 using a photolithography method and an etching method. The opening 22 is larger than the through electrode 12 when viewed from above, and is formed so as to include the through electrode 12. When the insulating film 20 mainly contains silicon oxide, for example, hydrofluoric acid-based wet etching is used for etching the insulating film 20. When the insulating film 20 mainly contains silicon nitride, for example, dry etching is used for etching the insulating film 20. With reference to FIG. 5C, the semiconductor substrate 10 is etched using the insulating film 20 as a mask to form the recess 24. The recess 24 is defined by the opening 22. For example, anisotropic etching is used for etching the semiconductor substrate 10. The tip of the through electrode 12 is exposed by the recess 24.

  With reference to FIG. 5D, the insulator layer 25 is formed on the second surface 70 of the semiconductor substrate 10 so as to fill the recess 24. The insulator layer 25 mainly includes a resin such as an epoxy resin or a polyimide resin. The tip of the through electrode 12 is covered with an insulator layer 25.

5 (e) and 6 are referred to, and FIG. 5 (e) shows an AA cross section of FIG. The entire surface of the insulator layer 25 is etched. Etchant and conditions are selected so that the insulator layer 25 is selectively etched with respect to the insulating film 20. For example, dry etching using Ar (argon) or a mixed gas of Ar and O ₂ is used. Thereby, the insulating film 20 on the second surface 70 of the semiconductor substrate 10 is hardly etched, and the insulator layer 25 is etched. An insulator 26 is formed from the insulator layer 25. Therefore, the tip of the through electrode 12 is exposed from the insulator 26 in a state where the second surface 70 of the semiconductor substrate 10 is covered with the insulating film 20. The tip of the through electrode 12 is lower than the insulating film 20, and the through electrode 12 is exposed at the bottom of the recess formed from the insulating film 20 and the insulator 26. As described above, the semiconductor substrate 10 is not exposed to the first surface 72.

  FIGS. 7A and 7B are cross-sectional views showing the etching of the semiconductor substrate. With reference to FIG. 7A, an example of etching in FIG. 5C will be described. Single crystal silicon has the property that the corrosive action proceeds along the crystal direction. For this reason, anisotropic etching can be performed by selecting an etching solution. Thereby, the recessed part 24 can be formed. Further, the silicon substrate includes a (100) or (110) substrate, and the shape and the like of the recess 24 can be controlled by selecting the orientation of the substrate and the etching solution.

  In FIG. 7A, a single crystal silicon substrate having a (100) plane as a main surface is used as the semiconductor substrate 10. An alkaline etching solution such as KOH is used as the etching solution. The upward direction is the <100> direction, and the depth direction is the <110> direction. Etching from the (100) plane makes it difficult to etch the (111) plane. For this reason, the etching is stopped by the (111) plane. The angle θ formed by the (111) plane and the (100) plane is 54.7 °.

  With reference to FIG.7 (b), the example of the dimension in Example 1 is demonstrated. The upper view is a top view of the recess 24, and the lower view is a cross-sectional view. The diameter L1 of the through electrode 12 is 10 μm, and the pitch L2 of the through electrode 12 is 50 μm. When the side surface of the through electrode 12 from the second surface 70 of the semiconductor substrate 10 to the depth D1 is exposed in the recess 24, it is sufficient that the distance L4 between the through electrode 12 and the recess 24 is about 3.5 μm. For this reason, the width L3 of the recess 24 is 17 μm. As described above, by forming the recess 24 by anisotropic etching, the recess 24 can be formed with high accuracy.

  According to the first embodiment, as shown in FIG. 5A, the through electrode is formed in the hole formed from the first surface 72 of the semiconductor substrate 10 toward the second surface 70 and not reaching the second surface 70. . As shown in FIG. 5B, the insulating film 20 having the opening 22 is formed on the second surface 70 of the semiconductor substrate 10. As shown in FIG. 5C, by removing the semiconductor substrate 10 using the insulating film 20 as a mask, a recess 24 surrounding the through electrode 12 is formed so that the upper surface of the through electrode 12 is exposed. As shown in FIGS. 5D and 5E, the insulator 26 embedded in the recess 24 so as to expose the upper surface of the through electrode 12 is formed. Thus, the insulating film 20 is formed on the second surface 70 of the semiconductor substrate 10 as shown in FIGS. In addition, an insulator 26 embedded in the second surface 70 of the semiconductor substrate 10 so as to expose the through electrode 12 is formed in a recess 24 formed so as to surround the through electrode 12.

  In order to obtain etching selectivity, the insulating film 20 and the insulator 26 are different materials. For example, the internal stress of the insulating film 20 is made smaller than the internal stress of the insulator 26. Thereby, the curvature of the semiconductor substrate 10 as shown in FIG. 2 can be suppressed. For example, when the insulating film 20 is an inorganic insulating film and the insulator 26 is a resin insulator, the internal stress of the insulating film 20 can be made smaller than that of the insulator 26. Moreover, since the insulating film 20 and the insulator 26 cover the second surface 70 of the semiconductor substrate 10, the exposure of the semiconductor substrate 10 on the second surface 70 as shown in FIG. 4B can be suppressed.

  When forming the insulator 26, as shown in FIG. 5D, the insulator layer 25 is formed in the recess 24, on the insulating film 20 and on the through electrode 12. As shown in FIG. 5E, the insulator layer 25 is selectively etched with respect to the insulating film 20 and the through electrode 12. Thereby, the insulator 26 can be formed.

  8A to 13B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. With reference to FIG. 8A, the electronic circuit 32 is formed on the first surface 72 of the semiconductor substrate 10. An insulating film 30 is formed on the semiconductor substrate 10. The electronic circuit 32 includes a transistor formed in the semiconductor substrate 10 and a wiring formed in the insulating film 30. The insulating film 30 is a silicon oxide film, for example, and includes an interlayer insulating film of multilayer wiring.

  With reference to FIG. 8B, holes 48 are formed in the insulating film 30 and the semiconductor substrate 10 from the first surface 72. The depth of the hole 48 is slightly shallower than 50 μm, for example. With reference to FIG. 8C, the through electrode 12 is formed in the hole 48. The through electrode 12 mainly contains Cu, for example, and is formed using a plating method. With reference to FIG. 8D, an insulating film 36 is formed on the insulating film 30 and the through electrode 12. A wiring 34 is formed in the insulating films 36 and 30. The insulating film 36 is, for example, a silicon oxide film or a resin film, and is a protective film for the electronic circuit 32. The wiring 34 is a metal mainly containing, for example, Al or Cu. With reference to FIG. 8E, the electrode 14, the metal terminal 16, and the solder 18 are formed on the insulating film 36.

  With reference to FIG. 9A, the first surface 72 side of the semiconductor substrate 10 is attached to the support substrate 38 via the adhesive 37. The support substrate 38 is a silicon substrate, for example. Referring to FIG. 9B, the second surface 70 of the semiconductor substrate 10 is polished or ground. The film thickness of the semiconductor substrate 10 is 50 μm, for example. The through electrode 12 does not penetrate the semiconductor substrate 10. With reference to FIG. 9C, the insulating film 20 is formed on the second surface 70 of the semiconductor substrate 10. With reference to FIG. 9D, an opening 22 is formed in the insulating film 20.

  Referring to FIG. 10A, a recess 24 is formed in the semiconductor substrate 10 using the insulating film 20 as a mask. With reference to FIG. 10B, an insulating layer 25 is formed on the insulating film 20. Referring to FIG. 10C, the insulator layer 25 is selectively etched to expose the tip of the through electrode 12. Referring to FIG. 10 (d), the adhesive 37 is dissolved, and the support substrate 38 is peeled from the semiconductor substrate 10. Thus, the semiconductor chip 80 is completed.

  Referring to FIG. 11A, a wiring board 82 is prepared. The wiring substrate 82 has an electrode 86 formed on the lower surface of the insulating substrate 84 and an electrode 92 formed on the upper surface. A wiring 90 is formed in the insulating substrate 84, and the electrodes 86 and 92 are electrically connected by the wiring 90. Solder 94 is formed on the electrode 92. The insulating substrate 84 is, for example, a resin substrate. The wiring 90 and the electrodes 86 and 92 include a metal such as Cu, for example. The semiconductor chip 80 is supported by the bonder head 40. The first surface 72 of the semiconductor chip 80 a is disposed on the upper surface of the insulating substrate 84. The semiconductor chip 80a is the same as the semiconductor chip 80 in FIG. Referring to FIG. 11B, alignment is performed, and the semiconductor chip 80 and the wiring board 82 are brought into contact with each other. The solder 18 and the solder 94 come into contact with each other. By heating, the solders 18 and 94 are joined.

  Referring to FIG. 12A, using the bonder head 40, the semiconductor chip 80b is brought into contact with the semiconductor chip 80a. The solder 18 of the semiconductor chip 80b comes into contact with the through electrode 12 of the semiconductor chip 80a. A recess is formed in the second surface 70 (upper surface) of the semiconductor chip 80a, and the tip of the through electrode 12 is exposed at the bottom of the recess. For this reason, the solder 18 of the semiconductor chip 80b is guided to the tip of the through electrode 12 of the semiconductor chip 80a, and the alignment between the semiconductor chips 80a and 80b becomes easy. By heating the solder 18, the solder 18 and the through electrode 12 are joined. Referring to FIG. 12B, using the bonder head 40, the semiconductor chip 80c is brought into contact with the semiconductor chip 80b. The semiconductor chip 80c is the same as the semiconductor chip 80 except that the through electrode 12 is not formed. The solder 18 of the semiconductor chip 80c comes into contact with the through electrode 12 of the semiconductor chip 80b. By heating the solder 18, the solder 18 and the through electrode 12 are joined. The solder 18 may be heated at once after the semiconductor chips 18a to 18c are stacked.

  Referring to FIG. 13A, solder balls 98 are formed. The solder ball 98 mainly contains, for example, Sn-Ag. With reference to FIG. 13B, solder balls 98 are provided on the electrodes 86. In the second embodiment, an example in which three semiconductor chips are stacked has been described. However, two or more layers may be stacked. Although the step of forming an underfill between the semiconductor chips 80a and 80c and between the semiconductor chip 80a and the wiring substrate 82 is omitted, the underfill is omitted between the semiconductor chips 80a and 80c and between the semiconductor chip 80a and the wiring substrate 82. A fill may be formed.

  As in the second embodiment, the semiconductor chip 80 can be mounted on the wiring board 82. In addition, the semiconductor chips 80 can be stacked. By stacking the semiconductor chips 80 and electrically connecting the semiconductor chips using the through electrodes 12, the inter-chip connection distance can be shortened and the processing speed can be improved. In addition, high-density mounting is possible. Furthermore, low power consumption is possible.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Appendix 1) A step of forming a through electrode in a hole formed from the first surface of the semiconductor substrate toward the second surface and not reaching the first surface; and an opening on the second surface of the semiconductor substrate A step of forming an insulating film, a step of forming a recess surrounding the through electrode so that an upper surface of the through electrode is exposed by removing the semiconductor substrate using the insulating film as a mask; And a step of forming an insulator embedded so that the upper surface of the through electrode is exposed.
(Supplementary Note 2) The step of forming the insulator includes a step of forming an insulator layer in the recess, on the insulating film and on the through electrode, and the insulator layer on the insulating film and the through electrode. The method for manufacturing a semiconductor device according to appendix 1, wherein a step of selectively etching is included.
(Additional remark 3) The process of forming the said recessed part includes the process of forming the said recessed part by anisotropically etching the said semiconductor substrate, The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.
(Additional remark 4) The internal stress of the said insulating film is smaller than the internal stress of the said insulator, The manufacturing method of the semiconductor device as described in any one of Additional remark 1 to 3 characterized by the above-mentioned.
(Additional remark 5) The said insulating film is an inorganic insulating film, The said insulator is a resin insulator, The manufacturing method of the semiconductor device as described in any one of additional marks 1 to 3 characterized by the above-mentioned.
(Additional remark 6) The said inorganic insulating film is a silicon oxide film or a silicon nitride film, The manufacturing method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.
(Supplementary note 7) Semiconductor substrate, through electrode penetrating the semiconductor substrate, insulating film formed on the surface of the semiconductor substrate, and in a recess formed on the surface of the semiconductor substrate so as to surround the through electrode And an insulator different from the insulating film embedded so as to expose the through electrode.
(Additional remark 8) The said recessed part is demarcated by the opening formed in the said insulating film, The semiconductor device of Additional remark 7 characterized by the above-mentioned.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Through-electrode 14 Electrode 16 Metal terminal 18 Solder 20 Insulating film 22 Opening 24 Recessed part 25 Insulator layer 26 Insulator 30, 36 Insulating film 32 Electronic circuit 34 Wiring 70 2nd surface 72 1st surface

Claims (9)

Forming a through electrode in a hole formed from the first surface to the second surface of the semiconductor substrate and not reaching the second surface;
Forming an insulating film having an opening on the second surface of the semiconductor substrate;
Removing the semiconductor substrate using the insulating film as a mask to form a recess surrounding the through electrode so that an upper surface of the through electrode is exposed;
Forming an insulator embedded in the recess so that an upper surface of the through electrode is exposed;
Only including,
A method for manufacturing a semiconductor device, wherein an internal stress of the insulating film is smaller than an internal stress of the insulator . Forming the insulator includes forming an insulator layer in the recess, on the insulating film and on the through electrode;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of selectively etching the insulator layer with respect to the insulating film and the through electrode.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the recess includes a step of forming the recess by anisotropically etching the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is an inorganic insulating film, and the insulator is a resin insulator. 5. The method according to claim 1, further comprising a step of stacking the another semiconductor substrate on the semiconductor substrate so that solder provided on the other semiconductor substrate is bonded to the through electrode in the recess. A manufacturing method of a semiconductor device given in any 1 paragraph. A semiconductor substrate; a through electrode penetrating the semiconductor substrate; an insulating film formed on the surface of the semiconductor substrate; and the through electrode in a recess formed on the surface of the semiconductor substrate so as to surround the through electrode. And an insulator embedded so as to be exposed ,
The semiconductor device according to claim 1, wherein an internal stress of the insulating film is smaller than an internal stress of the insulator .   The semiconductor device according to claim 6, wherein the recess is defined by an opening formed in the insulating film. 8. The semiconductor device according to claim 6, wherein the insulating film is an inorganic insulating film, and the insulator is a resin insulator. 9. The semiconductor device according to claim 6, further comprising the semiconductor substrate stacked on the semiconductor substrate so that solder provided on the semiconductor substrate is bonded to the through electrode in the recess. The semiconductor device according to any one of claims.

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