JP6130284B2 - Optical waveguide fabrication method - Google Patents

Description

  The present invention relates to a method for producing an optical waveguide having a silicon core built on an SOI substrate in a planar optical circuit such as an optical waveguide filter used in the optoelectronic field and the optical communication field.

  A planar waveguide optical circuit based on an optical waveguide formed on a silicon substrate is easy to manufacture because it can use semiconductor device manufacturing technology in the manufacturing process, and is advantageous for integration and large-scale production. is there. For this reason, the planar waveguide optical circuit is widely used for optical communication key parts such as an optical branch, an optical switch, and a wavelength filter. In the planar waveguide type optical circuit introduced in the current optical communication system, the core and the clad of the optical waveguide are mainly composed of a quartz material.

  The quartz waveguide is an optical waveguide having a relative refractive index difference between the core and the clad of about 0.7 to 1.5%. Therefore, in the communication wavelength band of about 1.5 microns, the bending radius of the optical waveguide is several millimeters. It becomes an order. For this reason, the quartz waveguide has a problem that the size of the optical device increases when the element integration is increased.

  In order to solve this problem, based on silicon optical waveguides, the core of the optical waveguide has been changed from quartz to silicon for the purpose of significantly reducing the size and integration of optical devices in recent years, and the relative refractive index difference is extremely high. Research and development of planar optical circuits is active. Since the silicon optical waveguide is strong in optical confinement, the bending radius can be reduced to several microns, and the optical device can be significantly downsized and highly integrated. Furthermore, since an optical circuit using a silicon optical waveguide matches the material and the manufacturing process, it is easy to integrate with a silicon electronic circuit, and there is an advantage that high functionality of an optical device can be realized at low cost.

  Here, a method for manufacturing a planar waveguide optical circuit based on a silicon optical waveguide will be briefly described with reference to FIGS. 4A to 4C. First, as shown in FIG. 4A, an SOI (Silicon on Insulator) substrate including a silicon substrate 401, a buried insulating layer 402 made of silicon oxide, and a single crystal silicon layer 403 is prepared. For example, an SOI substrate including a buried insulating layer 402 with a layer thickness of 1 to 3 μm and a single crystal silicon layer 403 with a layer thickness of about 200 to 300 nm may be used.

  Next, the single crystal silicon layer 403 is patterned by lithography and etching techniques using ultraviolet light or an electron beam, and a silicon core 431 is formed on the lower clad layer made of the buried insulating layer 402 as shown in FIG. 4B. Form. The silicon core 431 has a rectangular cross section, for example, and is formed so that the dimensions are about 400 nm in width and about 200 nm in height.

  Next, as illustrated in FIG. 4C, a silicon oxide film 404 is formed on the buried insulating layer 402, and the silicon core 431 is buried with the formed silicon oxide film 404. The silicon oxide film 404 thus formed becomes an upper clad layer, and a silicon optical waveguide is completed.

  Here, in the formation of the silicon oxide film 404, the silicon core 431 that has already been formed does not lose its shape due to oxidation, and impurities implanted around the core before film formation diffuse into the silicon core 431. It is important to carry out at a temperature condition that does not. For example, a thermal CVD method such as a flame deposition method that has a proven record in the production of a quartz waveguide cannot be applied to a film forming process on a silicon core because it is a high-temperature process of about 1000 ° C. Therefore, a plasma CVD method is often used for forming the silicon oxide film 404.

  The plasma CVD method can form a high-quality oxide film at a low temperature of about 300 ° C. or lower, and is also applied to the production of electronic circuits such as LSI (Large Scale Integration). However, when an oxide film or an oxynitride film is deposited on the core by plasma CVD, if it is used as it is deposited, the core is used in a process such as chemical cleaning performed in a subsequent device integrated fabrication process. There is a problem that the oxide film deposited over the surface is damaged as if it was eroded along the edge in the shape of the core.

  The damage of the deposited film by the plasma CVD method is shown in FIG. 5 when the silicon oxide film 404 is formed on the pattern having a step such as the silicon core 431 by the CVD method under a low temperature condition in which the film does not flow viscously. This is due to the formation of the weakened portion 501, which is a region having a weak film quality, with the core upper surface edge as a base point due to the step structure. The fragile portion 501 is less resistant to chemicals and gases than other regions, and is easily etched quickly by a cleaning chemical solution or a process gas, and thus is easily damaged.

  In order to improve the film quality of the fragile portion 501 due to the above-described step structure, the silicon oxide film 404 (silicon substrate) is formed at a high temperature condition, for example, 1000 ° C., after the silicon oxide film is formed and the viscous flow of the silicon oxide begins to occur. 401) may be performed (see Patent Document 1). By this treatment, the silicon oxide film 404 is brought into a state in which no film is damaged in a subsequent cleaning process or the like, and the silicon oxide film 404 in this state is used as the upper clad of the silicon optical waveguide. Since this heat treatment is performed in a state where the silicon core 431 is covered with the silicon oxide film 404, there is no problem that the shape of the silicon core 431 is broken.

Japanese Patent No. 4681644

  However, the above-described method for improving the film quality by high-temperature heat treatment at about 1000 ° C. after film formation is not a problem with a structure composed of only an optical waveguide, but various light sources are used for high function and high performance of the device. When an element or an electric element is integrated in one chip, there is a problem that it cannot be used due to the following problems.

  First, high-performance optical devices include not only passive optical waveguide devices such as filters, but also active devices such as light intensity modulation devices composed of optical waveguides with a PIN structure added, and PIN photodiodes for receiving waveguides. Accumulated. In order to integrate the PIN diode structure element, impurities are implanted into and around the silicon core before forming the upper clad of the silicon optical waveguide.

  For this reason, when a silicon oxide film or a silicon oxynitride film is formed on the core by plasma CVD, and then a heat treatment at a high temperature of about 1000 ° C. is performed, the impurities diffuse during the heat treatment, and the PIN diode device This causes a problem that the characteristics of the device deteriorate and stop functioning. In a high-function optical device, an optical waveguide device may be monolithically integrated on a substrate on which an electrical device is made. Even in this case, there is a problem that the electric device is broken by the high temperature treatment in forming the upper clad house.

  The present invention has been made to solve the above-described problems, and in a silicon waveguide monolithically integrated with a PIN structure-added optical device or an electrical device, it is possible to suppress deformation of the silicon core. An object is to prevent the upper clad formed under the low temperature condition from being damaged in the subsequent process.

An optical waveguide manufacturing method according to the present invention includes a first step of forming a core made of silicon on a lower clad layer made of silicon oxide, and silicon oxide or silicon oxynitride covering the core on the lower clad layer. a second step of forming an upper cladding layer of, after the second step, a third step of flattening a step formed on the surface of the upper cladding layer so as to conform to the shape of the core, in the third step And a fourth step of forming an oxide film made of silicon oxide or silicon oxynitride on the planarized upper clad layer. In the second step, the thermal oxidation reaction does not occur in the core, and the core shape collapses or The upper cladding layer is formed in a temperature condition range in which impurity diffusion into the core is suppressed, and in the fourth step, an oxide film is formed in a temperature condition range in which impurity diffusion into the core is suppressed.

In a method for manufacturing the optical waveguide, the upper cladding layer and the oxide film, formed by a plasma CVD method. In particular, the upper cladding layer and the oxide film are preferably formed by ECR plasma CVD. The oxide film functions as a clad on the upper side of the core.

  As described above, according to the present invention, in the silicon waveguide monolithically integrated with the PIN structure additional optical device or the electrical device, the upper cladding formed under a low temperature condition capable of suppressing the shape collapse of the silicon core, An excellent effect is obtained that damage can be prevented from occurring in the subsequent steps.

FIG. 1A is a cross-sectional view illustrating a method for manufacturing an optical waveguide according to Embodiment 1 of the present invention and illustrating a state in each step. FIG. 1B is a cross-sectional view showing a state in each step for explaining a method of manufacturing an optical waveguide in the first embodiment of the present invention. FIG. 1C is a cross-sectional view showing a state in each step for explaining a method of manufacturing an optical waveguide according to Embodiment 1 of the present invention. FIG. 1D is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide according to the first embodiment of the present invention. FIG. 1E is a cross-sectional view illustrating the method for manufacturing the optical waveguide according to Embodiment 1 of the present invention and showing the state in each step. FIG. 2 is a cross-sectional view showing a configuration of an optical waveguide formed by the method of manufacturing an optical waveguide according to Embodiment 1 of the present invention. FIG. 3A is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide according to Embodiment 2 of the present invention. FIG. 3B is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide in Embodiment 2 of the present invention. FIG. 3C is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide according to Embodiment 2 of the present invention. FIG. 3D is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide according to the second embodiment of the present invention. FIG. 3E is a cross-sectional view showing a state in each step for explaining the method of manufacturing the optical waveguide in the second embodiment of the present invention. FIG. 3F is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide according to Embodiment 2 of the present invention. FIG. 3G is a cross-sectional view illustrating the method for manufacturing the optical waveguide according to the second embodiment of the present invention and illustrating the state in each step. FIG. 3H is a cross-sectional view illustrating the method for manufacturing the optical waveguide according to Embodiment 2 of the present invention and illustrating the state in each step. FIG. 3I is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide according to the second embodiment of the present invention. FIG. 3J is a cross-sectional view illustrating a state in each step for explaining a method of manufacturing an optical waveguide in the second embodiment of the present invention. FIG. 4A is a cross-sectional view illustrating a method for manufacturing an optical waveguide and illustrating a state in each process. FIG. 4B is a cross-sectional view showing a state in each step for explaining a method for manufacturing an optical waveguide. FIG. 4C is a cross-sectional view illustrating a method for manufacturing the optical waveguide and illustrating a state in each process. FIG. 5 is a cross-sectional view showing the configuration of the optical waveguide.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIGS. 1A to 1E. 1A to 1E are cross-sectional views illustrating states in respective steps for explaining a method of manufacturing an optical waveguide according to Embodiment 1 of the present invention.

  First, as shown in FIG. 1A, a silicon layer 103 is formed on a silicon substrate 101 with a lower cladding layer 102 interposed therebetween. For example, an SOI (Silicon on Insulator) substrate including a silicon base, a buried insulating layer made of silicon oxide, and a surface silicon layer made of single crystal silicon may be used. For example, an SOI substrate including a buried insulating layer having a thickness of 1 to 3 μm and a surface silicon layer having a thickness of about 200 to 300 nm may be used. The buried insulating layer becomes the lower cladding layer 102.

  Next, by patterning the silicon layer 103 by a known lithography and etching technique, a core 131 made of silicon is formed on the lower cladding layer 102 as shown in FIG. 1B. For example, the core 131 may have a rectangular cross section, a width of about 300 to 600 nm, and a height of about 200 to 400 nm.

  Next, for example, silicon oxide is deposited by a well-known plasma CVD method to form the upper clad layer 104 as shown in FIG. 1C. For example, the upper cladding layer 104 is formed with a layer thickness of about 1 to 1.5 μm, and the core 131 is embedded. At this time, the upper clad layer 104 is formed in a temperature condition range in which the shape of the already formed core 131 is suppressed. Further, in such an optical waveguide using the silicon core 131, a region into which an impurity is introduced may be formed. In such a case, the upper cladding layer 104 is formed within a temperature condition range in which the above-described impurities are suppressed from diffusing into the core 131.

  Next, as shown in FIG. 1D, the surface of the upper cladding layer 104 is planarized by, for example, a well-known chemical mechanical polishing (CMP) method. As described above, the upper surface of the upper clad layer 104 formed by deposition reflects the shape of the core 131 formed on the lower clad layer 102 and has a step. The surface of the upper cladding layer 104 is flattened so as to eliminate this step.

  Next, for example, by depositing silicon oxide by a well-known plasma CVD method, an oxide film 105 is formed on the planarized upper clad layer 104 as shown in FIG. 1E. Since the oxide film 105 is formed on a flat surface, the oxide film 105 is formed in a high quality state, for example, a fragile portion due to a step is not generated.

  Here, in such an optical waveguide using the core 131 made of silicon, a region into which an impurity is introduced may be formed. Therefore, a temperature at which such an impurity is suppressed from diffusing into the core 131. An oxide film 105 is formed within a range of conditions. Further, if the temperature condition is such that the impurities are prevented from diffusing into the core 131, the damage of the electric device monolithically integrated with the silicon optical waveguide can be suppressed. The optical waveguide by the core 131 is obtained by the above. The optical waveguide is monolithically formed on a substrate on which an electrical device or the like is made.

  By forming the oxide film 105 as described above, the fragile portion 201 formed in the upper cladding layer 104 is covered with the high-quality oxide film 105 as shown in FIG. The fragile portion 201 is a region where the film quality generated due to the influence of a step in the lower layer is fragile. As a result, since the weak part 201 does not touch chemicals and gases used in various processes in the subsequent process, damage does not occur.

  By flattening the upper surface of the upper clad layer 104 and then forming the oxide film 105, even if the film is formed at a low temperature without performing a high-temperature treatment that causes viscous flow, it is possible to prevent chemicals and gases. The lower layer can be protected by the highly resistant oxide film 105. As described above, according to the first embodiment, in the silicon waveguide monolithically integrated with the PIN structure added optical device or the electric device, the upper clad layer 104 formed under the low temperature condition that can suppress the shape collapse of the core 131 is formed. In the subsequent process, damage can be prevented from occurring. Note that the oxide film 105 can function as a part of the cladding on the upper side of the core 131.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIGS. 3A to 3J. 3A to 3J are cross-sectional views illustrating a state in each step for explaining a method of manufacturing an optical waveguide according to Embodiment 2 of the present invention.

  First, as shown in FIG. 3A, a silicon layer 303 is formed on a silicon substrate 301 with a lower cladding layer 302 interposed therebetween. For example, an SOI substrate including a silicon base, a buried insulating layer made of silicon oxide, and a surface silicon layer made of single crystal silicon may be used. For example, any SOI substrate including a buried insulating layer having a layer thickness of 1 to 3 μm and a surface silicon layer having a layer thickness of about 200 to 300 nm may be used. The buried insulating layer becomes the lower cladding layer 302. In this case, the silicon layer 303 is made of single crystal silicon.

Next, as illustrated in FIG. 3B, a silicon oxide layer 304 is formed over the silicon layer 303, and a resist layer 305 is formed over the silicon oxide layer 304. The silicon oxide layer 304 can be formed by, for example, a well-known plasma CVD method using SiH ₄ and O ₂ as source gases. The resist layer 305 may be formed by applying an ultraviolet photosensitive resist or an electron beam photosensitive resist by a spin coating method or the like.

  Next, the resist layer 305 is patterned by a well-known photolithography technique or electron beam lithography technique to form a resist pattern 351 on the silicon oxide layer 304 as shown in FIG. 3C. The resist pattern 351 is formed in a strip shape extending in a predetermined direction.

  For example, when the resist layer 305 is an ultraviolet photosensitive resist, a pattern having a desired shape is exposed using an ultraviolet exposure device to form this latent image. Next, the resist pattern 351 can be formed by developing with a predetermined developer so that a latent image appears. Further, when the resist layer 305 is an electron beam photosensitive resist, a pattern having a desired shape is exposed using an electron beam exposure apparatus to form this latent image. Next, the resist pattern 351 can be formed by developing with a predetermined developer so that a latent image appears. The resist pattern 351 formed by development is subjected to a heat treatment (post-bake) at about 300 ° C., for example.

  Next, the silicon oxide layer 304 is selectively removed and patterned by etching using the resist pattern 351 as a mask to form a mask pattern 341 as shown in FIG. 3D. For example, by reactive ion etching using a fluorocarbon-based etching gas, the silicon oxide layer 304 is etched with high anisotropy, and the shape of the resist pattern 351 is transferred to the silicon oxide layer 304. A mask pattern 341 may be formed.

  Next, after removing the resist pattern 351, the silicon layer 303 is selectively removed and patterned using the mask pattern 341 as a mask, thereby forming a core 331 made of single crystal silicon as shown in FIG. 3E. For example, by reactive ion etching using a chlorine-based or fluorine-based etching gas, the silicon layer 303 is etched with high anisotropy, and the shape of the mask pattern 341 is transferred to the silicon oxide layer 304. The core 331 may be formed.

  In this etching, the silicon layer 303 to be processed is etched halfway so as to remain about 1/4 to 1/2 of the original thickness, so that the slab layer 332 remains. As a result, as shown in FIG. 3E, a state in which a rib-type core 331 is formed on the lower cladding layer 302 is obtained. The width of the cross-sectional shape of the core 331 may be, for example, about 300 to 600 nm.

  Next, impurity P ions are implanted into the slab layer 332 on one side of the core 331 by a resist pattern formation technique by photolithography and an ion implantation technique using the resist pattern as a mask, as shown in FIG. 3F. Impurity region 361 is formed, and impurity B ions are implanted into slab layer 332 on the other side of core 331 to form impurity region 362. Note that after removing the resist, heat treatment is performed to activate impurities and recover silicon defects. FIG. 3F shows a state after the resist is removed and heat treatment is performed. As a result, a PIN diode structure is obtained with the core 131 interposed therebetween.

  Next, by depositing silicon oxide on the core 131 and the slab layer 332, as shown in FIG. 3G, an upper clad layer 307 having a layer thickness of about 1.5 μm is formed, and the core 331 is embedded. To do. At this time, the upper clad layer 307 is formed in a temperature condition range in which the shape deformation of the core 331 already formed is suppressed. Further, as described above, since the impurity region 361 and the impurity region 362 are formed, the impurity diffuses into the core 331, and the upper cladding is within a range of temperature conditions in which the initial concentration is suppressed from changing. Layer 307 is formed. For example, when silicon oxide is deposited by the CVD method, it is desirable to set the temperature condition to about 400 ° C. or lower where thermal oxidation reaction does not occur in the core 331 and impurity diffusion can be ignored.

Here, the deposition of silicon oxide under a low temperature condition may be formed by an ECR plasma CVD method using SiH ₄ and O ₂ gases. For example, using a well-known ECR plasma CVD apparatus, SiH ₄ gas and O ₂ gas are introduced at a ratio of about 2: 1 under the condition that the total pressure is about 1 Pa, and ECR plasma is generated at a microwave power of 400 W. Then, silicon oxide may be deposited to form the upper clad layer 307. According to this method, silicon oxide can be deposited at a low film temperature of about 200 ° C. and at a film formation rate of 0.15 μm / min. The formed upper cladding layer 307 has a refractive index of about 1.46. Note that the present invention is not limited to ECR plasma, and as described above, if the temperature conditions are within a range where thermal oxidation of the core 331 can be suppressed, silicon oxide is deposited by another plasma CVD method to form the upper cladding layer 307. May be.

  Here, when the upper cladding layer 307 is formed as described above, the step structure 371 is formed on the upper surface of the upper cladding layer 307 due to the step structure of the core 331. The step structure 371 is removed, and the surface of the upper cladding layer 307 is planarized as shown in FIG. 3H. For example, the upper cladding layer 307 may be planarized by processing the CMP or bias sputtering method. For example, the upper cladding layer 307 can be flattened by processing a thickness that is three times or more the height of the step structure 371. For example, if the height of the core 331 is 200 to 300 nm, the step is eliminated by processing the upper cladding layer 307 by about 1 μm.

  Next, as shown in FIG. 3I, an oxide film 308 made of silicon oxide is formed on the planarized upper clad layer 307. At this time, the thickness of the oxide film 308 may be set so that the total thickness including the flattened upper clad layer 307 functions as the upper clad of the silicon optical waveguide. For example, the oxide film 308 may be formed with a thickness of about 1 μm.

In forming the oxide film 308, it is necessary to suppress the diffusion of impurities from the impurity region 361 and the impurity region 362 into the core 331 during the film formation, and the low temperature condition is used as in the formation of the upper cladding layer 307. . For example, the ECR plasma CVD method using SiH ₄ and O ₂ gas is suitable for forming the oxide film 308. In the ECR plasma CVD method, ions having appropriate energy are irradiated onto the film formation surface, and a dense high-quality silicon oxide film can be formed at a low temperature of about 200 ° C. or less by the assist effect of the irradiated ions. In particular, when a silicon oxide film is formed on a flat surface without a step structure by an ECR plasma CVD method, ions are evenly irradiated to the film, so that a high-quality silicon oxide film close to a thermal oxide film can be formed.

  Since the oxide film 308 is formed in this manner, the fragile portion of the upper cladding layer 307 generated due to the step is covered with the high-quality oxide film 308. Since it is covered with the oxide film 308, the fragile portion does not come into contact with chemicals or gas, so that no damage occurs. By flattening the upper clad layer 307 and then forming an oxide film 308 by an ECR plasma CVD method or the like, silicon oxide having a high resistance to chemicals and gases even when it is formed at a low temperature without being subjected to a high temperature treatment A state in which the core 331 is covered with the film is obtained.

  Next, as illustrated in FIG. 3J, the contact hole 309 forms a contact hole 309 that reaches the impurity region 361 and the impurity region 362. For example, the contact hole 309 can be formed by etching using a resist mask pattern formed by a known lithography technique and using an etchant such as dilute hydrofluoric acid. Since the fragile portion of the upper clad layer 307 generated from the core 331 is covered with the oxide film 308, the etching solution does not come into contact with the fragile portion even after the processing described above, and damage occurs. There is nothing.

  Thereafter, an optical device with a PIN structure is completed by forming a wiring structure (not shown) including a contact plug by filling the contact hole 309 with an electrode material such as aluminum. The mask pattern 341 used for forming the core shape is left without being removed, but it is made of silicon oxide and functions as a part of the upper cladding.

  As described above, according to the second embodiment, the step structure of the upper clad layer 307 formed by the CVD method under the low temperature condition is removed and flattened, and then the dense structure is formed even at a low temperature by the ECR plasma CVD method. An oxide film 308 made of silicon oxide was formed. As a result, low-temperature formation of a silicon oxide film that does not change the impurity concentration and shape of the core 331, and formation of a high-quality silicon oxide film that is not damaged in a cleaning process or a processing process required in an integration process with another device Therefore, it becomes possible to produce a good high-performance optical integrated device.

The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, in the above-described embodiment, the case where the upper clad layer and the oxide film are made of silicon oxide has been described as an example. However, the present invention is not limited to this. For example, the upper clad layer and the oxide film may be made of silicon oxynitride. Further, the silicon oxide is not limited to SiO ₂ but may be SiO _x having a small oxygen composition ratio. Needless to say, the core is not limited to single crystal silicon, and may be polycrystalline silicon or amorphous silicon. The same effect can be obtained not only by the plasma CVD method but also by depositing a silicon oxide film by a sputtering method.

  DESCRIPTION OF SYMBOLS 101 ... Silicon substrate, 102 ... Lower clad layer, 103 ... Silicon layer, 104 ... Upper clad layer, 105 ... Oxide film, 131 ... Core, 201 ... Fragile part.

Claims (3)

A first step of forming a core made of silicon on a lower clad layer made of silicon oxide;
A second step of forming an upper clad layer made of silicon oxide or silicon oxynitride covering the core on the lower clad layer;
After the second step , a third step of flattening the step formed on the surface of the upper cladding layer reflecting the shape of the core ;
A fourth step of forming an oxide film made of silicon oxide or silicon oxynitride on the planarized upper clad layer after the third step ;
In the second step, the upper cladding layer is formed in a temperature condition range in which a thermal oxidation reaction does not occur in the core and the core shape collapses or impurity diffusion into the core is suppressed,
In the fourth step, the oxide film is formed in a temperature condition range in which impurity diffusion to the core is suppressed ,
The upper clad layer and the oxide film are formed by a plasma CVD method. In the manufacturing method of the optical waveguide of Claim 1 ,
The method of manufacturing an optical waveguide, wherein the upper cladding layer and the oxide film are formed by an ECR plasma CVD method. In the manufacturing method of the optical waveguide of Claim 1 or 2 ,
The method for manufacturing an optical waveguide, wherein the oxide film functions as a clad on the upper side of the core.

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