JP6128833B2 - Processing equipment - Google Patents

Description

  The present invention relates to a processing apparatus, and more particularly to an apparatus that performs processing using a plurality of CPUs.

  Conventionally, in an information processing apparatus such as a digital camera, a mobile phone, and a smartphone, information data such as a moving image, a still image, or sound is processed using a CPU (see, for example, Patent Document 1). In portable devices, power consumption is reduced by controlling the frequency of an operation clock supplied to a CPU.

  For example, when there is no work to be processed by the CPU, the CPU itself is put into a power saving sleep mode and the frequency of the CPU operation clock and CPU bus clock is lowered.

JP 2010-98696 A

  In recent years, since the amount of data to be processed has increased, processing has been performed using a plurality of CPUs. When a plurality of CPUs are connected to one CPU bus, each CPU cannot reduce the frequency of the CPU bus clock for its own convenience.

  Therefore, there has been a problem that power consumption cannot be reduced.

  An object of the present invention is to solve such problems and to reduce power consumption with a small circuit scale even when a plurality of CPUs are connected to a common bus. .

  In the present invention, a bus that transfers data according to a bus clock, and is connected to the bus, operates according to the CPU clock, and requests the first information about the frequency of the CPU clock that each requests A plurality of CPUs for outputting second information related to the frequency of the bus clock; and a register for storing the first information and the second information output from each of the plurality of CPUs. The frequency of each of the CPU clocks supplied to the plurality of CPUs and the frequency of the bus clock based on the first information and the second information output from the CPU and stored in the register A clock that determines and supplies the CPU clock to each of the plurality of CPUs and supplies the bus clock to the bus And the clock management means determines the highest frequency among the bus clock frequencies requested by the plurality of CPUs based on the second information stored in the register. And the CPU clock frequency requested by the CPU is equal to or higher than the determined bus clock frequency based on the determined bus clock frequency and the first information stored in the register. , The frequency requested by the CPU is determined as the frequency of the CPU clock supplied to the CPU, and if the frequency of the CPU clock requested by the CPU is lower than the determined bus clock frequency, the determined bus clock Is determined as the frequency of the CPU clock supplied to the CPU.

  According to the present invention, even when a plurality of CPUs are connected to a common bus, power consumption can be reduced with a small circuit scale.

It is a block diagram which shows the structure of a signal processing circuit. It is a figure which shows the structure of a register | resistor, and the relationship between the requested | required clock frequency and the output clock frequency. It is a flowchart which shows an idle task and interruption processing. It is a flowchart which shows the use determination process of CPU bus | bath. It is a time chart which shows the example of the frequency of the clock requested | required by CPU. It is a time chart which shows the example of the frequency of the clock requested | required by CPU, and the frequency of the output clock. It is a block diagram which shows the structure of the signal processing circuit of 2nd Embodiment. It is a figure which shows the relationship between the requested | required clock frequency and the output clock frequency. It is a block diagram which shows the structure of the camera in embodiment.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention with reference to an accompanying drawing is demonstrated in detail. In the embodiment, a case where the processing apparatus of the present invention is applied to a camera will be described as an example. The embodiment described below is an example for realizing the present invention, and should be appropriately modified or changed according to the configuration of the apparatus to which the present invention is applied and various conditions. The present invention is described below. It is not limited to the form. FIG. 9 is a diagram showing a configuration of a camera 900 according to the embodiment of the present invention.

  In FIG. 9, an imaging unit 901 captures a subject in response to an instruction from the signal processing circuit 903 and outputs moving image data or still image data. The microphone 902 acquires sound around the subject and outputs sound data. The signal processing circuit 903 includes a plurality of CPUs as described later, and processes moving images, still image data, or audio data. The operation unit 904 includes various switches and buttons that can be operated by the user, such as a power switch and a recording start / stop instruction switch. In addition, the operation unit 904 can be configured by a touch panel or the like. A memory 905 is a memory used for processing of the signal processing circuit 903, and stores moving image data, still image data, audio data, or other data. The memory 903 is a volatile memory, and is composed of, for example, a DRAM. The memory 905 is configured as an integrated circuit (IC) different from the signal processing circuit 903. The memory cards 906 and 907 each have a built-in flash memory. Each of the memory cards 906 and 907 can be easily attached to and removed from the camera 900 by an attachment / discharge mechanism such as a card slot (not shown). One of the memory cards 906 and 907 may be a memory card having a wireless LAN function. The display 908 displays various types of information such as captured moving images and still images, reproduced images, and operation menus. The display 908 includes a liquid crystal panel and an organic EL panel. The speaker 909 outputs the reproduced sound.

  Next, the signal processing circuit 903 will be described. FIG. 1 is a diagram illustrating a configuration of the signal processing circuit 903. Each processing block of the signal processing circuit 903 shown in FIG. 1 is configured as one integrated circuit.

In FIG. 1, a first CPU (Central Processing Unit) 101 and a second CPU 102 each control the overall operation of the camera 900. Each of the CPU 101 and the CPU 102 includes a microprocessor, a register, and the like, and operates according to software (firmware) stored in a non-illustrated nonvolatile memory. In addition, the CPU 101 and the CPU 102 execute processing in a shared manner. For example, the CPU 101 controls the card controller 105 to write and read various data with respect to the memory card 906. Further, the CPU 102 controls the card controller 106 to write and read various data with respect to the memory card 907. As described above, the CPU 101 and the CPU 102 share different processes or perform the processes at the same time, thereby improving the processing performance of the camera 900. Each of the CPU 101 and the CPU 102 operates according to an operation clock (hereinafter referred to as a CPU clock) supplied from the clock management unit 103.

  The clock management unit 103 supplies a CPU clock to the CPU 101 and the CPU 102, and further supplies a CPU bus clock (hereinafter referred to as a CPU bus clock). Details of the clock management unit 103 will be described later.

  The memory 104 is used as a buffer memory for data communication between the first CPU 101 and the second CPU 102 and for writing and reading data to and from the card controllers 106 and 107.

Each of the card controllers 105 and 106 reads / writes data from / to the memory card. The card controllers 105 and 106 are controlled by the CPUs 101 and 102, and record data input via the CPU bus 113 in the memory cards 906 and 907. The card controllers 105 and 106 store the data read from the memory cards 906 and 907 in the memory 104 via the CPU bus 113. Further, each of the card controllers 105 and 106 outputs an interrupt signal for notifying the completion to each CPU when the writing or reading of data by the writing to the memory card or the reading command is completed.

  The image signal processing unit 107 performs predetermined signal processing such as white balance and gamma correction on the moving image data and still image data output from the imaging unit 901 and stores them in the memory 905 via the memory bus 115. At the time of recording, the audio signal processing unit 108 performs predetermined signal processing such as noise removal on the audio data input from the microphone 902 and stores it in the memory 905 via the memory bus 115. Further, at the time of reproduction, the audio data stored in the memory 905 is read and output from the speaker 909.

  At the time of recording, the codec 109 reads out moving image data and still image data stored in the memory 905 by the image signal processing unit 107, and performs MPEG or H.264 recording. H.264 or JPEG is encoded according to a predetermined encoding method and stored in the memory 905. Further, the codec 109 reads out the audio data stored in the memory 905 by the audio signal processing unit 108, encodes it according to an encoding method such as AAC, and stores the encoded data in the memory 905. Further, the codec 109 decodes the reproduced moving image data, still image data, or audio data and stores them in the memory 905 during reproduction.

  The display unit 110 performs processing for displaying the moving image and audio data stored in the memory 905 and outputs the processing to the display 908. The display unit 110 also outputs various information such as a menu screen to the display 908. Further, when the display 908 has a touch panel function, it has a function of detecting a touch operation by a user and transmitting the user operation to each CPU. In the present embodiment, it is assumed that the first CPU 101 receives a user operation and controls the second CPU 102 as necessary.

  Each of the communication unit 111 and the communication unit 112 has a function of communicating with an external configuration of the signal processing circuit 103. Specifically, it communicates with the lens driving unit in the imaging unit 901, performs lens focus control and zoom control according to instructions from each CPU, or reads data from the autofocus sensor as needed, and reads the read data to the focus It is used to judge the state.

  The CPU buses 113 and 114 are used as transmission paths for transmitting and receiving commands and data for each CPU to control each block. The CPU buses 113 and 114 are used as transmission paths for data transfer between the card controllers 105 and 106 and the memory 104 or data transfer to the memory 905 via the memory bus 115. The CPU buses 113 and 114 operate according to the CPU bus clock supplied from the clock management unit 103, and transfer data between the circuit blocks. In this embodiment, by dividing the CPU bus into two, an increase in circuit scale when a plurality of circuit blocks are connected to a common CPU bus is suppressed.

  The memory bus 115 is a transmission path for transmitting and receiving data and commands between each block and the memory 905. The memory bus 115 and the CPU 101, CPU 102, card controller 105, and card controller 106 are connected via the CPU bus 113, and the memory 905 can be accessed from these circuit blocks.

  In this way, the processing circuits of the CPUs 101 and 102, the memory 104, the card controllers 105 and 106, the image signal processing unit 107, the audio signal processing unit 108, the codec 109, and the display unit 110 are connected to the CPU bus 113. The communication units 111 and 112 are connected to the CPU bus 114.

  Next, the clock management unit 103 will be described. The clock control unit 103 includes an oscillator, and generates a CPU clock and a CPU bus clock having different frequencies by dividing the frequency of the clock generated by the oscillator. In addition, the clock management unit 103 includes a register for storing information regarding the frequencies of the CPU clock and the CPU bus clock output from each CPU.

  FIG. 2A shows a register for storing information on these clock frequencies. The first CPU clock register 201 is a register that stores information on the frequency of the CPU clock requested from the CPU 101. Similarly, the second CPU clock register 202 is a register for storing information on the frequency of the CPU clock requested from the CPU 102. The first CPU bus clock register 203 is a register that stores information on the frequency of the CPU bus clock of the CPU buses 113 and 114 requested from the CPU 101. Similarly, the second CPU bus clock register 204 is a register for storing information on the CPU bus clock frequency of the CPU buses 113 and 114 requested from the CPU 102.

The clock management unit 103 determines the frequency of the CPU clock to be output to the CPU 101 and the CPU 102 based on the frequency information stored in each register. The clock management unit 103 determines the frequency of the CPU bus clock to be output to the CPU buses 113 and 114 based on the frequency information stored in each register. There is a possibility that the frequency of the CPU bus clock requested from the CPU 101 is different from the frequency of the CPU bus clock requested from the CPU 102. In this case, it is necessary to determine how to set the CPU bus clock. . In general, the frequency of the CPU clock and the frequency of the CPU bus clock cannot be controlled completely independently, and a predetermined dependency must be maintained. In the present embodiment, the frequencies of the CPU clock and the CPU bus clock are determined according to the following restrictions and dependency relationships.
(1) When the frequency of the CPU bus clock requested from the CPU 101 is different from the frequency of the CPU bus clock requested from the CPU 102, the higher value is used. This is due to the idea of giving priority to processing performance.
(2) CPU clock frequency ≧ CPU bus clock frequency.
(3) The clock frequency is selected from three types of 200 megahertz (MHz), 100 MHz, and 50 MHz.

  In the present embodiment, when the frequency of the CPU bus clock set by each CPU is 50 Hz, which is the lower frequency, the clock management unit 103 determines the CPU bus clock frequency as 50 MHz. If the CPU bus clock frequency set by at least one CPU is 100 MHz, which is the higher frequency, the clock management unit 103 determines the CPU bus clock frequency as 100 MHz. In other words, the clock management unit 103 determines the highest frequency among the CPU bus clock frequencies set by a plurality of CPUs as the CPU bus clock frequency.

  Furthermore, when the CPU clock frequency set by each CPU is equal to or higher than the CPU bus clock frequency determined in this way, the clock management unit 103 determines the CPU clock frequency supplied to each CPU as the requested frequency. . On the other hand, in the case where the CPU clock frequency set by the CPU is lower than the determined CPU bus clock frequency, the CPU bus clock frequency is set so that the CPU clock frequency is not lower than the CPU bus clock frequency. Set to the same frequency as the frequency.

  Table 205 in FIG. 2B shows values stored in the respective registers and the CPU clock and CPU bus clock frequencies output at that time.

  For example, when the frequency value requested from each CPU and stored in the register is in the state indicated by 206, either of the setting values of the CPU bus clock register is 200 MHz. The frequency is 200 MHz. In addition, due to (2) and (3), the CPU clock frequency of both the CPU 102 and the CPU 102 is 200 MHz. This indicates that the CPU clock frequency of the CPU 102 is set to 200 MHz by the clock management unit 103 even if the set value of the second CPU clock register 202 is 100 MHz.

  Further, even when the CPU 102 requests 50 Hz as the CPU clock frequency as in 207, the clock management unit 103 sets 100 Hz as the CPU bus clock frequency, so that the CPU 102 is supplied with a 100 MHz CPU clock.

  In this way, the frequency of the operation clock supplied to each CPU and the frequency of the bus clock are controlled in accordance with the clock frequency requested from each CPU. Further, since the frequency of each clock can be determined according to the rules as described above, the clock management unit 103 can have a relatively simple circuit configuration.

  Next, software that runs on each CPU will be described. Each CPU operates a real-time OS, and software that operates on the CPU includes interrupt processing and a plurality of task processing (details of the real-time OS are omitted). In each CPU, processing is started in response to an interrupt request from each circuit block, and after processing that requires real-time performance is performed, the processing ends. In the interrupt process, a process for waking up a task may be performed. When such a process is performed, the process for waking up is started after the interrupt process is completed.

  Tasks have priorities, and when there are multiple wake-up tasks, the task with the highest priority operates. The operated task performs necessary processing, wakes up another task, and transitions to a sleep state when the processing is completed. The task with the lowest priority is called an idle task, and when the idle task becomes operable, that is, when there is nothing to be processed by the CPU, the CPU is shifted to an interrupt waiting state. At this time, only the circuit for accepting the interrupt request is functioning in the CPU, and the supply of the clock is cut off to the other internal blocks. Therefore, power consumption of the CPU can be suppressed.

  Further, each CPU sets the frequency of the CPU clock and the CPU bus clock in accordance with the transition to the interrupt waiting state from another processing circuit connected to the CPU bus, and information indicating the set frequency is set in the clock management unit 103. Output to. Each CPU sets the frequency of the requested CPU clock or CPU bus clock in accordance with the transition from the interrupt wait state to the task execution state, and outputs information indicating the set frequency to the clock management unit 103. The clock management unit 103 stores the CPU clock and CPU bus clock frequency values output from each CPU in the register of FIG. That is, the frequency of the CPU clock and the CPU bus clock is set by the clock management unit 103 at the start of interrupt processing and during idle task operation. These processes are shown in FIG.

  Each CPU sets one of a plurality of predetermined frequencies as the CPU clock frequency. Each CPU then outputs information about the set CPU clock frequency (first information) and information about the CPU bus clock frequency (second information) to the clock management unit 103. That is, each CPU sets the CPU clock to one of CPUCLK_MAX and CPUCLK_MIN. Here, CPUCLK_MAX is a CPU clock frequency for the CPU to execute processing at high speed, and CPUCLK_MIN is a CPU clock frequency in a low power consumption state. CPUCLK_MIN is lower than the frequency of CPUCLK_MAX.

  Each CPU requests one of a plurality of predetermined frequencies as the frequency of the CPU bus clock. That is, each CPU sets the CPU bus clock to any frequency of CPUBCLK_MAX, CPUBCLK_MIN, and CPUBCLK_DMA. Here, CPUBCLK_MAX is the CPU bus clock frequency during the CPU bus operation. CPUBCLK_MIN is the frequency of the CPU bus clock when the CPU bus is not operating. CPUBCLK_DMA is a frequency of the CPU bus clock necessary for the card controllers 105 and 106 to perform data transfer at a sufficiently high speed. CPUBCLK_MIN is lower than the frequency of CPUBCLK_MAX.

  FIG. 3A is a flowchart showing idle task processing executed by each CPU. When all the other task processes are eliminated and the process shifts to the idle task process, the CPU sets the CPU clock frequency to the predetermined CPUCLK_MIN (S301).

  Next, the CPU determines whether or not the CPU buses 113 and 114 are in use (S302). This discrimination process will be described with reference to FIG. For this discrimination process, a CPU bus busy flag is used. When a block other than the CPU operates as a bus master of the CPU bus, a predetermined value is set as the CPU bus busy flag. Each of the CPUs 101 and 102 holds the set value of the CPU bus busy flag in an internal register. When the card controllers 105 and 106 perform data transfer (DMA: Direct Memory Access) to the memory 104 or the memory 905, the CPUs 101 and 102 set a predetermined value for the CPU bus busy flag.

  FIG. 4A is a flowchart of the DMA start process which is a part of the control process of the card controllers 105 and 106 by the CPUs 101 and 102. When the processing is started, the CPU transmits a DMA setting command such as a data transfer size and an address to the card controllers 105 and 106, and further instructs the start of data transfer (S401). Next, the CPU adds 1 to the set value of the CPU bus busy flag (S402). In the present embodiment, since there are the card controllers 105 and 106, a state in which the two card controllers 105 and 106 both perform DMA transfer and a state in which only one of them performs DMA transfer can be considered. Therefore, when a DMA transfer is instructed to the card controller, 1 is added to the CPU bus busy flag so that it is possible to determine the state in which the two card controllers are both performing the DMA transfer. It can be said that the CPU bus busy flag is information indicating the number of processing circuits performing data transfer using the CPU buses 113 and 114. Next, the CPU shifts to a DMA transfer completion interrupt wait state, and the processing task enters a sleep state (S403).

  FIG. 4B is a flowchart showing processing of the CPUs 101 and 102 when receiving a DMA transfer completion interrupt notification from the card controllers 105 and 106. This process is one of the specific examples of the process of S303 in FIG.

  When the interrupt process is started, the CPU subtracts 1 from the set value of the CPU bus busy flag (S404). Next, the CPU issues a wake-up instruction to the task in the sleep state, and ends the interrupt process (S405).

  FIG. 4C is a flowchart showing a determination process for determining whether or not the CPU bus in S302 is in use. First, the CPU checks the value set in the CPU bus busy flag (S406), and determines whether or not a value of 1 or more is set (S407). When the CPU bus busy flag is set to 1 or more, at least one of the two card controllers 105 and 106 is transferring data using the CPU buses 113 and 114. Therefore, in this case, the CPU determines that the CPU bus is being used (S408). When the CPU bus busy flag is set to 0, the CPU determines that the CPU buses 113 and 114 are not being used (S409).

  Here, it returns to the flowchart of Fig.3 (a). If it is determined in S302 that the CPU buses 113 and 114 are not in use, the CPU sets the CPU bus clock frequency to the predetermined CPUBCLK_MIN. If it is determined that the CPU bus is in use, the CPU sets the CPU bus clock frequency to the previously determined CPUBCLK_DMA (S305).

  Next, the CPU shifts to an interrupt waiting state and enters a low power consumption state (S304). The CPU maintains this low power consumption state until receiving an interrupt request. The frequency of the CPU bus clock is set to a frequency of CPUBCLK_MIN or CPUBCLK_DMA.

  FIG. 3B is a flowchart of interrupt processing in each CPU. When receiving an interrupt request from each processing block in an interrupt wait state or a normal operation state, the CPU sets the CPU clock frequency to CPUCLK_MAX determined in advance (S306). Next, the CPU sets the CPU bus clock frequency to the previously determined CPUBCLK_MAX (S307). With these processes, the CPU shifts from the low power consumption state to the high speed processing state. Next, the CPU ends the interrupt process after performing the interrupt process according to the received interrupt factor (S308). In the process of S308, if there is a process that wakes up the task, then the process of the wake up task is executed. A specific example of the process of S308 is the process of FIG.

  FIG. 5 is a time chart showing an example of the processing of each software in the CPU 101 or the CPU 102, the CPU bus busy flag, and the frequency set in the register of the clock management unit 103. In FIG. 5, CPUCLK_MAX = CPUBCLK_MAX = 200 MHz, CPUCLK_MIN = CPUBCLK_MIN = 50 MHz, and CPUBCLK_DMA = 100 MHz.

  In FIG. 5, at the start, the processing of task 1 is executed (reference numeral 501), and 200 MHz is set for both the CPU clock register and the CPU basque clock register. Thereafter, the process is switched to the interrupt process 2 (reference numeral 502) and the task 2 process caused thereby (reference numeral 503), but the register setting is not changed. Thereafter, the process returns to task 1 (reference numeral 504). If the card controller DMA start process is executed in this process, 1 is added to the CPU bus busy flag (reference numeral 505), and task 1 sleeps. . Since there is no more processing to be executed due to the sleep of task 1, the idle task operates (reference numeral 506).

  The CPU clock register is set to CPUCLK_MIN = 50 MHz by the idle task. Further, since the CPU bus busy flag is 1, CPUBCLK_DMA = 100 MHz is set and an interrupt is waited for.

  Interrupt processing 1 is executed by the DMA completion interrupt (reference numeral 507), the frequency of the CPU clock and CPU bus clock is set to CPUCLK_MAX = CPUBCLK_MAX = 200 MHz, and 1 is subtracted from the CPU bus busy flag to 0. When the interrupt process 1 ends, the task 1 woken up by the interrupt process 1 operates (reference numeral 508), and when the task 1 sleeps, the idle task operates again (reference numeral 509). At this time, since the CPU bus busy flag is 0, both the CPU clock frequency and the CPU bus clock frequency are set to 50 MHz.

  FIG. 6 is a time chart showing an example of the CPU bus busy flag in the CPU 101 and the CPU 102, the CPU clock requested from each CPU, and the frequency of the CPU bus clock. In the CPU 101, as in FIG. 5, CPUCLK_MAX = CPUBCLK_MAX = 200 MHz, CPUCLK_MIN = CPUBCLK_MIN = 50 MHz, and CPUBCLK_DMA = 100 MHz. In the CPU 102, CPUCLK_MAX = CPUBCLK_MAX = CPUBCLK_DMA = 100 MHz and CPUCLK_MIN = CPUBCLK_MIN = 50 MHz. The clock frequency set by each CPU may be a frequency other than this.

  Reference numerals 601 and 602 indicate the CPU bus busy flag, CPU clock frequency, and CPU bus clock frequency setting state in the CPU 101 and CPU 102, respectively. In such a case, the clock management unit 103 sets the CPU clock frequency to each CPU and the frequency of the CPU bus clock as indicated by reference numeral 603.

  As described above, in this embodiment, it is possible to supply a clock having a frequency corresponding to the operation state of each CPU and the use state of the CPU bus with a simple circuit configuration. Therefore, in a configuration connected to a bus common to a plurality of CPUs, power consumption can be suppressed without increasing the circuit scale.

  In the present embodiment, a case has been described in which it is determined whether or not the CPU bus is in use mainly based on a DMA transfer completion interrupt notification from the card controller. In addition to this, for other circuit blocks connected to the CPU bus, it is possible to determine whether or not the CPU bus is being used by another circuit block by setting the CPU bus busy flag in the same manner. It becomes possible.

  In the present embodiment, two CPUs are connected to one CPU bus. However, even in a configuration in which three or more CPUs are connected to a common CPU bus, the CPU clock is similarly applied. And the CPU bus clock can be controlled.

  In the present embodiment, moving image data, still image data, and the like are recorded on the memory card. However, a random access recording medium other than the memory card can be used. In this case, not a card controller but a recording / reproducing unit that records and reproduces various information on a recording medium is provided.

  Next, a second embodiment will be described. FIG. 7 is a block diagram showing the configuration of the signal processing circuit 903 in the second embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In FIG. 7, the third CPU 701 is connected to the CPU bus 114. The CPU 701 controls the communication unit 111 and the communication unit 112. The CPU 701 uses the memory 702 to control the entire camera 900 while communicating with the CPUs 101 and 102.

  The CPU 701 sets the frequency of the CPU clock and the frequency of the CPU bus clock in the clock management unit 103 by a method different from that of the CPUs 101 and 102. The CPU 701 outputs a sleep signal 701 s to the clock management unit 103. The sleep signal 701s is a signal that is asserted when the CPU 701 shifts to an interrupt waiting state (sleep state).

  When receiving the sleep signal 701 s from the CPU 701, the clock management unit 103 determines that the frequency of the operation clock supplied to the CPU 701 may be lowered. That is, it is handled in the same manner as when CPUCLK_MIN and CPUBCLK_MIN are set in the first embodiment. Conversely, when an interrupt is accepted in the sleep state and interrupt processing is started, the CPU 701 deasserts the sleep signal 701s. When the sleep signal 701s is deasserted, the clock management unit 103 determines that it is necessary to increase the frequency of the operation clock supplied to the CPU 701. That is, it is handled in the same manner as when CPUCLK_MAX and CPUBCLK_MAX are set in the first embodiment.

  The clock management unit 103 sets a clock with a determined frequency as the CPU clock frequency of the CPU 701 when the sleep signal 701 s is in the asserted state and when it is in the deasserted state.

  Then, the clock management unit 103 sets the CPU clock frequency and CPU bus clock to each CPU based on the CPU clock and CPU bus clock frequencies requested by the CPU 101 and CPU 102 and the sleep signal 701s from the CPU 701.

  In the present embodiment, the clock management unit 103 includes a register in which a clock frequency is set according to the asserted state and the deasserted state of the sleep signal 701s from the third CPU 701. That is, when the sleep signal 701s is in the asserted state and the deasserted state, the clock management unit 103 sets values required for the CPU clock frequency of the CPU 701 in the third CPU active / sleep clock register. In addition, when the sleep signal 701s is in the asserted state and the deasserted state, the clock management unit 103 sets a value required as the CPU bus clock frequency of the CPU 701 in the third CPU bus active / sleep clock register.

  For example, when the sleep signal 701s indicates the asserted state, that is, the CPU 701 is in the sleep state, 50 MHz is set in each of the third CPU active / sleep clock register and the third CPU bus active / sleep clock register. . When the sleep signal 701s is in a deasserted state, that is, when the CPU 701 is in an active state, 200 MHz is set in the third CPU active / sleep clock register, and 100 MHz is set in the third CPU bus active / sleep clock register.

  The clock management unit 103 stores in advance clock frequencies to be set when the CPU 701 is in an active state or a sleep state. Therefore, the CPU 701 can set the requested clock frequency by changing the state of the sleep signal 701 s without outputting the clock frequency value to the clock management unit 103.

  In this embodiment, the values stored in each register and the CPU clock and CPU bus clock frequencies output at that time are shown in FIG. Thus, since the frequency of each clock can be determined, the clock management unit 103 can have a relatively simple circuit configuration.

  In the second embodiment, the third CPU 701 is connected to the CPU bus 114, but the third CPU 701 may be connected to the CPU bus 113.

  In the first and second embodiments, the case where the present invention is applied to a camera has been described. However, the present invention can be similarly applied to other devices including a plurality of CPUs. is there.

Claims (3)

A bus that transfers data according to the bus clock; and
Are connected to the bus, as well as operate in accordance with the CPU clock, each requires a plurality of CPU outputs and a second information about the frequency of the first information about the frequency of the CPU clock the bus clock ,
A register for storing the first information and the second information output from each of the plurality of CPUs; and the first information output from the plurality of CPUs and stored in the registers; based on the second information, and the CPU clock respective frequency supplied to the plurality of CPU, together with the to determine the frequency of the bus clock, to supply each of the plurality of CPU said CPU clock, said bus a clock management means for supplying the bus clock,
The clock management means determines, as the bus clock frequency, the highest frequency among the bus clock frequencies requested by the plurality of CPUs based on the second information stored in the register, If the CPU clock frequency requested by the CPU is equal to or higher than the determined bus clock frequency based on the bus clock frequency and the first information stored in the register, the CPU requested If the frequency of the CPU clock requested by the CPU is lower than the determined frequency of the bus clock, the determined frequency of the bus clock is sent to the CPU. process instrumentation, characterized by determining the frequency of the supply the CPU clock . Each of the plurality of CPUs sends to the clock management means information related to the requested CPU clock frequency and bus clock frequency in response to a transition to an interrupt wait state from another processing circuit connected to the bus. 2. The processing according to claim 1 , wherein the first information and the second information are output to the clock management unit in response to transition from the interrupt waiting state to the task execution state. apparatus.   A bus that is connected to the bus and that records data input via the bus on a recording medium, and the CPU requests a frequency of the bus clock depending on whether the data is being transferred by the recording unit; The processing apparatus according to claim 1, wherein:

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