JP6101565B2 - Nitride semiconductor epitaxial wafer - Google Patents

Description

  The present invention relates to a nitride semiconductor epitaxial wafer in which a nitride semiconductor layer is epitaxially grown on a substrate, and more specifically, a nitride semiconductor capable of suppressing cracking of the wafer that occurs in an electronic device manufacturing process after epitaxial growth. It relates to an epitaxial wafer.

  Generally, sapphire, SiC, Si, etc. are used as a substrate material for an electronic device using a nitride semiconductor. Of these, in order to compete with Si devices, which are electronic devices of Si semiconductors, it is essential to reduce the cost of the devices, and therefore nitride semiconductors are actively grown on Si substrates.

  A major problem in growing a nitride semiconductor on an Si substrate is the difference in thermal expansion coefficient between Si and the nitride semiconductor. That is, since the thermal expansion coefficient of Si is smaller than the thermal expansion coefficient of nitride semiconductor, generally, when a nitride semiconductor is grown on the Si substrate, the epitaxial wafer warps in a convex shape downward. It will end up.

  As methods for suppressing the warpage of the epitaxial wafer, methods for hardening the Si substrate itself are disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2010-153817) and Patent Document 2 (Japanese Patent Laid-Open No. 2011-103380).

In the above-mentioned Patent Document 1, the Si substrate itself is obtained by setting the amount of boron, which is a p-type dopant, to 1 × 10 ¹⁹ cm ⁻³ or more and the specific resistance of the Si single crystal to 0.01 Ω · cm or less. An epitaxial substrate for electronic devices in which is hardened is disclosed.

In Patent Document 2, the Si substrate is provided with an oxygen concentration of 0.2 × 10 ¹⁸ atoms / cm ³ or more and 1.4 × 10 ¹⁸ atoms / cm ³ or less to improve the strength of the Si substrate. Thus, a compound semiconductor substrate in which the Si substrate is hardened is disclosed.

  However, the conventional epitaxial substrate for electronic devices disclosed in Patent Document 1 and the conventional compound semiconductor substrate disclosed in Patent Document 2 have the following problems.

  That is, the conventional epitaxial substrate for electronic devices disclosed in Patent Document 1 and the conventional compound semiconductor substrate disclosed in Patent Document 2 are both epitaxial devices in which electronic devices are epitaxially formed on a Si substrate. In order to suppress the warpage of the wafer, the Si substrate is hardened. For this reason, a new problem arises that the epitaxial wafer is liable to break during the process of manufacturing an electronic device using a nitride semiconductor.

  The inventor of the present application has intensively studied to suppress cracking of a nitride semiconductor epitaxial wafer obtained by epitaxially growing a nitride semiconductor layer on a Si substrate. And the structure proposed in the said patent document 1 and the said patent document 2 discovered that it was inadequate.

  That is, increasing the boron impurity concentration or doping with oxygen in order to suppress the warpage of the nitride semiconductor epitaxial wafer may increase the hardness of the Si substrate. It has become clear from a series of studies that it is increasing.

  In particular, in the growth of the nitride semiconductor, ammonia is used as a nitrogen source. Therefore, when the back surface of the Si substrate is exposed to ammonia at a high temperature for a long time, oxygen precipitation on the back surface of the Si substrate is remarkably promoted, and this greatly affects the brittleness of the Si substrate. Became clear.

JP 2010-153817 A JP 2011-103380 A

  Accordingly, an object of the present invention is to provide a nitride semiconductor epitaxial wafer that can suppress the destruction of the epitaxial wafer due to the brittleness of the Si substrate during the process of manufacturing an electronic device using a nitride semiconductor.

In order to solve the above problems, the nitride semiconductor epitaxial wafer of the present invention is
A Si single crystal substrate;
An initial growth layer made of a nitride semiconductor formed on the surface of the Si single crystal substrate;
A plurality of nitride semiconductor layers formed on the initial growth layer,
The oxygen concentration in the Si single crystal substrate is 2.0 × 10 ¹⁷ cm ⁻³ or more and 1.3 × 10 ¹⁸ cm ⁻³ or less,
The Si single crystal substrate is characterized in that the carbon concentration on the back side is 1.0 × 10 ¹⁶ cm ⁻³ or more and 3.7 × 10 ¹⁷ cm ⁻³ or less.

As apparent from the above, in the nitride semiconductor epitaxial wafer of the present invention, the oxygen concentration in the Si single crystal substrate is 2.0 × 10 ¹⁷ cm ⁻³ or more and 1.3 × 10 ¹⁸ cm ⁻³ or less, The carbon concentration on the back side of the Si single crystal substrate is 1.0 × 10 ¹⁶ cm ⁻³ or more and 3.7 × 10 ¹⁷ cm ⁻³ or less.

In general, in order to suppress the warpage of the epitaxial wafer, the hardness is increased by doping the Si substrate with oxygen. However, oxygen concentrations exceeding 1.3 × 10 ¹⁸ cm ⁻³ increase the brittleness of the Si substrate. In the present invention, the oxygen concentration in the Si single crystal substrate is 2.0 × 10 ¹⁷ cm ⁻³ or more and 1.3 × 10 ¹⁸ cm ⁻³ or less. Therefore, the hardness of the Si single crystal substrate can be set to a desired hardness for suppressing the warpage of the epitaxial wafer.

Further, in the growth of the nitride semiconductor layer, ammonia is used as a nitrogen source. In this case, when the back surface of the Si substrate is exposed to ammonia at a high temperature for a long time, oxygen precipitation on the back surface of the Si substrate is remarkably promoted. This greatly affects the fragility of the Si substrate. In the present invention, the back side of the Si single crystal substrate is doped with carbon having a concentration of 1.0 × 10 ¹⁶ cm ⁻³ or more and 3.7 × 10 ¹⁷ cm ⁻³ or less. Therefore, precipitation of oxygen due to ammonia on the back surface side can be suppressed, and the Si single crystal substrate can be prevented from becoming brittle due to an increase in oxygen concentration.

  That is, according to the present invention, it is possible to provide a nitride semiconductor epitaxial wafer capable of suppressing breakage in the device manufacturing process due to the brittleness of the Si single crystal substrate.

It is sectional drawing in the nitride semiconductor epitaxial wafer of this invention.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a cross-sectional view of a nitride semiconductor epitaxial wafer in which a nitride semiconductor layer is epitaxially formed on a substrate in the present embodiment.

In FIG. 1, an Si single crystal substrate (hereinafter simply referred to as an Si substrate) 1 grown by a CZ method (Czochralski method) is used as a substrate. The Si substrate 1 is doped with boron, which is a p-type dopant, at a concentration of 1 × 10 ¹⁹ cm ⁻³ , has a resistivity of 0.01 Ωcm, and has an oxygen concentration of 1 × 10 ¹⁸ cm ⁻³ .

An initial growth layer made of an AlN layer 2 is grown on the Si substrate 1 as described above to a thickness of 100 nm. Continue. Al _0.2 Ga _0.8 N3 is grown to a thickness of 40 nm. Here, the film thickness of the AlN layer 2 or the AlGaN layer 3 can be changed within the range of 20 nm to 200 nm.

Thereafter, a superlattice buffer layer 4 (carbon concentration 1 × 10 ¹⁹ cm ⁻³ ) formed by alternately laminating AlN layers and AlGaN layers is grown 100 cycles, and further a channel GaN layer 5 having a thickness of 1 μm, An AlN intermediate layer 6 having a thickness of 1 nm and an Al _0.2 Ga _0.8 N barrier layer 7 having a thickness of 30 nm are grown.

  The Al composition of the AlGaN layer in the superlattice buffer layer 4 is preferably about 0.05 to 0.3. The thickness of each superlattice buffer layer 4 is preferably about 5 nm to 25 nm. Further, the number of periods of the superlattice buffer layer 4 can be changed according to the required film thickness.

  The growth of each layer is an example, but is performed by the following growth method. The following growth of each layer is performed on a Si wafer that will be the Si substrate 1 by dicing later. Therefore, in the following, the Si wafer (Si substrate) 1 will be referred to.

  First, prior to growth, the surface oxide film of the Si wafer (Si substrate) 1 is removed with a hydrofluoric acid-based etchant, and then the Si wafer (Si substrate) 1 is set in a metal organic chemical vapor deposition (MOCVD) apparatus. Then, the wafer temperature is set to 1100 ° C., the chamber pressure is set to 13.3 kPa, and the surface of the Si wafer (Si substrate) 1 is cleaned.

Here, the Si wafer (Si substrate) 1 has an oxygen concentration of 1 × 10 ¹⁸ cm ⁻³ , and carbon is doped on the back surface side with a concentration of 1 × 10 ¹⁷ cm ⁻³ . In this case, there is no particular limitation on the carbon doping method only on the back side of the Si wafer (Si substrate) 1. For example, an ion implantation method is used. Done later.

  Further, as ion implantation conditions, low energy (about 10 keV to about 100 keV) is desirable because it is desirable to dope the surface layer on the back surface of the Si wafer (Si substrate) 1. Alternatively, by forming an oxide film on the back surface of the Si wafer (Si substrate) 1 and performing ion implantation from the vicinity of the back surface through the oxide film, and removing the oxide film after the ion implantation, It becomes possible to dope the outermost layer. In this case, the thickness of the oxide film can be changed by the implantation energy.

  In this way, the above-described surface oxide film removal and surface cleaning are performed on the Si wafer (Si substrate) 1 whose surface layer on the back surface is doped with carbon.

Next, the surface of the Si wafer (Si substrate) 1 is nitrided by flowing ammonia NH ₃ (12.5 slm) at a constant wafer temperature and chamber pressure. Subsequently, an AlN layer 2 is formed (TMA (trimethylaluminum) flow rate = 117 μmol / min, NH ₃ flow rate = 12.5 slm). Next, Al _0.2 Ga _0.8 N3 is formed at a wafer temperature of 1150 ° C. (TMG (trimethylgallium) flow rate = 100 μmol / min, TMA flow rate = 30 μmol / min, NH ₃ flow rate = 12.5 slm).

Next, AlN (TMA flow rate = 117 μmol / min, NH ₃ flow rate = 12.5 slm) and Al _0.15 Ga _0.85 N (TMG flow rate = 137 μmol / min, TMA flow rate = 18 μmol / min, NH ₃ flow rate = 12.5 slm) Are alternately stacked to form the superlattice buffer layer 4. Further, a channel GaN layer 5 having a thickness of 1.0 μm is formed, an AlN intermediate layer 6 is formed (TMA flow rate = 10 μmol / min, NH ₃ flow rate = 12.5 slm), and an Al _0.2 Ga _0.8 N barrier layer 7 is formed ( TMG flow rate = 33 μmol / min, TMA flow rate = 10 μmol / min, NH ₃ flow rate = 12.5 slm).

Thus, the initial growth layer composed of the AlN layer 2 on the Si wafer (Si substrate) 1 having an oxygen concentration of 1 × 10 ¹⁸ cm ⁻³ and doped with carbon on the back surface at a concentration of 1 × 10 ¹⁷ cm ^−3. through, AlGaN layer 3, AlN layer and the AlGaN layer in made superlattice buffer layer 4, a plurality of nitride semiconductor layer formed in the channel GaN layer 5, AlN intermediate layer 6 and the Al _0.2 Ga _0.8 N barrier layer 7 is formed Is done.

Table 1 shows that 50 Si wafers (Si substrates) 1 doped with carbon at a concentration of 1 × 10 ¹⁷ cm ⁻³ and 50 Si wafers (Si substrates) not doped with carbon are prepared on the back surface. Then, on a total of 100 Si wafers (Si substrates), the AlGaN layer 3, the superlattice buffer layer 4, the channel GaN layer 5, the AlN intermediate layer 6 and the AlN initial growth layer 2 are provided as in FIG. An Al _0.2 Ga _0.8 N barrier layer 7 is grown to form a nitride semiconductor epitaxial wafer. Furthermore, the frequency of the crack in the said electronic device preparation process at the time of performing an electronic device preparation process with respect to this nitride semiconductor epitaxial wafer is shown.

  Here, the electronic device manufacturing process is not particularly limited. In the case of the present embodiment, for example, a source electrode and a drain electrode that form ohmic contact with the two-dimensional electron gas layer formed at the interface between the AlN intermediate layer 6 and the channel GaN layer 5 are formed. For example, a manufacturing process of a field effect transistor (HEMT) in which a gate electrode is formed between a source electrode and the drain electrode.

  As can be seen from Table 1, when the back surface of the Si wafer (Si substrate) 1 is doped with carbon, the crack rate of the wafer is 4%, and when the back surface is not doped with carbon, the crack rate of the wafer. This is an improvement over 20%.

When the back surface of the Si wafer (Si substrate) 1 is not doped with carbon, the AlN layer 2, AlGaN 3, superlattice buffer layer 4, channel GaN layer 5, AlN intermediate layer 6, and AlGaN barrier layer 7 are formed. The back surface of the Si wafer (Si substrate) 1 is exposed to NH ₃ as a nitrogen raw material supplied to the substrate at a high temperature for a long time. As a result, oxygen precipitation on the back surface of the Si wafer (Si substrate) 1 is remarkably promoted, and brittleness of the Si wafer (Si substrate) 1 is induced by an increase in oxygen concentration.

  However, as in the present embodiment, by doping the back surface of the Si wafer (Si substrate) 1 with carbon, a coexistence state of carbon and nitrogen is formed, and precipitation of oxygen is suppressed. Therefore, the brittleness of the Si wafer (Si substrate) 1 is not induced, and cracking of the Si wafer (Si substrate) 1 during the device manufacturing process is suppressed.

As described above, according to the present embodiment, a nitride semiconductor layer is grown by doping carbon on the back surface of the Si wafer (Si substrate) 1 at a concentration of 1 × 10 ¹⁷ cm ⁻³ . It is possible to suppress cracks generated in the device manufacturing process for the nitride semiconductor epitaxial wafer. Therefore, the yield can be improved and the cost can be reduced.

Table 2 shows the concentration of carbon doped on the back surface of the Si wafer (Si substrate) 1 and the crack frequency when an electronic device manufacturing process is performed on an epitaxial wafer formed in the same manner as in Table 1. Shows the relationship.

The oxygen concentration contained in the Si wafer (Si substrate) 1 is 2.0 × 10 ¹⁷ cm in order to make the Si wafer (Si substrate) 1 have a desired hardness for suppressing the warpage of the epitaxial wafer. ^-3 or higher is desirable. Moreover, since excessive oxygen concentration increases brittleness, it is desirable that the oxygen concentration be 1.3 × 10 ¹⁸ cm ⁻³ or less.

On the other hand, referring to FIG. 2, it is desirable that the concentration of carbon doped on the back surface of the Si wafer (Si substrate) 1 is 1 × 10 ¹⁶ cm ⁻³ or more and 3.7 × 10 ¹⁷ cm ⁻³ or less. I understand.

As described above, the nitride semiconductor epitaxial wafer of the present invention is
Si single crystal substrate 1;
An initial growth layer 2 made of a nitride semiconductor formed on the surface of the Si single crystal substrate 1;
A plurality of nitride semiconductor layers 3 to 7 formed on the initial growth layer 2;
The oxygen concentration in the Si single crystal substrate 1 is 2.0 × 10 ¹⁷ cm ⁻³ or more and 1.3 × 10 ¹⁸ cm ⁻³ or less,
The Si single crystal substrate 1 is characterized in that the carbon concentration on the back surface side is 1.0 × 10 ¹⁶ cm ⁻³ or more and 3.7 × 10 ¹⁷ cm ⁻³ or less.

According to the above configuration, the oxygen concentration in the Si single crystal substrate 1 is 2.0 × 10 ¹⁷ cm ⁻³ or more and 1.3 × 10 ¹⁸ cm ⁻³ or less. Therefore, the hardness of the Si single crystal substrate 1 can be set to a desired hardness that suppresses the warpage of the epitaxial wafer.

Further, the carbon concentration on the back surface side of the Si single crystal substrate is not less than 1.0 × 10 ¹⁶ cm ^{−3 and not} more than 3.7 × 10 ¹⁷ cm ⁻³ . Therefore, even when the back surface of the Si single crystal substrate 1 is exposed to the nitrogen source ammonia at a high temperature for a long time during the growth of the nitride semiconductor layers 3 to 7, oxygen precipitation due to the ammonia on the back surface side is suppressed. The brittleness of the Si single crystal substrate 1 can be improved.

  That is, according to the present invention, the hardness of the Si single crystal substrate 1 can be set to a desired hardness that can suppress the warpage of the epitaxial wafer, and the breakdown in the device manufacturing process can be suppressed. In addition, the brittleness of the Si single crystal substrate can be improved.

1 ... Si substrate,
2 ... AlN layer (initial growth layer),
3… Al _0.2 Ga _0.8 N,
4 ... Superlattice buffer layer,
5 ... Channel GaN layer,
6 ... AlN intermediate layer,
7: Al _0.2 Ga _0.8 N barrier layer.

Claims (1)

A Si single crystal substrate;
An initial growth layer made of a nitride semiconductor formed on the surface of the Si single crystal substrate;
A plurality of nitride semiconductor layers formed on the initial growth layer,
The oxygen concentration in the Si single crystal substrate is 2.0 × 10 ¹⁷ cm ⁻³ or more and 1.3 × 10 ¹⁸ cm ⁻³ or less,
A nitride semiconductor epitaxial wafer, wherein a carbon concentration on a back surface side of the Si single crystal substrate is 1.0 × 10 ¹⁶ cm ⁻³ or more and 3.7 × 10 ¹⁷ cm ⁻³ or less.

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