JP6098437B2 - Solid-state imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

  A solid-state imaging device capable of adding signals from a plurality of vertical signal lines on a horizontal signal line is disclosed in FIG.

JP 2009-225301 A

  However, in the conventional solid-state imaging device, signals can be added inside the device, but the weight cannot be changed.

  The present invention has been made in view of such circumstances, and provides a solid-state imaging device capable of weighting and adding signals inside the device and changing the weight, and an imaging device using the same. For the purpose.

The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect includes a pixel unit having a plurality of pixels arranged two-dimensionally,
A plurality of vertical signal lines that are provided for each column of the plurality of pixels and receive signals from pixels in the corresponding column; q amplifying units (q is an integer of 2 or more) having an input unit; One set is provided for each of the amplifying units, and each set is p sets of capacitors (p is an integer of 2 or more), and one electrode is connected to the input unit of the corresponding amplifying unit, The ratio of the capacitance values of at least one set of p capacitors is different from the ratio of the capacitance values of at least one other set of p capacitances, and one to one for the q sets of capacitances. Q sets of switches each consisting of p sets, each corresponding to the other set of p capacitors of the corresponding sets and the q sets of switches of the plurality of vertical signal lines. And q sets of switches for turning on / off each of the p vertical signal lines in common.

  A solid-state imaging device according to a second aspect includes switching means provided corresponding to each of the q sets of capacities in the first aspect, wherein each of the switching means corresponds to a control signal. The other electrodes of the p capacitors in the set are switched between a state where they are electrically connected to each other and a state where they are electrically separated from each other.

  In the first or second aspect, the solid-state imaging device according to the third aspect corresponds to at least one of the q amplification units, and the p capacitors and the p number of the amplification units. A plurality of sets of switches are provided, and the ratio of the capacitance values of the p capacitors is different between the plurality of sets.

  In the solid-state imaging device according to the fourth aspect, in any one of the first to third aspects, a total capacitance value for each set of the p capacitors in each set is the same.

  A solid-state imaging device according to a fifth aspect includes a pixel unit having a plurality of pixels arranged two-dimensionally, and a plurality of vertical signals that are provided for each column of the plurality of pixels and receive signals from pixels in a corresponding column A line, q amplifying units (q is an integer of 2 or more) having an input unit, and q input capacitance forming units respectively provided corresponding to the q amplifying units, Capacitance forming units are connected in common to the q amplification units among the plurality of vertical signal lines and the input unit of the corresponding amplification unit according to a control signal (p is an integer of 2 or more) P input capacitor units connected to each of the vertical signal lines are formed, and the input capacitor forming unit corresponding to at least one of the q amplifier units is formed. The ratio of the capacitance values of the p input capacitance units is other than the q amplification units. Different from the p number of the ratio of the capacitance value of the input capacitance section where the input capacitance forming unit corresponding to at least one amplifier section is formed, in which and a q-number of input capacitance formation section.

  The solid-state imaging device according to a sixth aspect is the solid-state imaging device according to the fifth aspect, wherein the input capacitance forming unit corresponding to at least one of the q amplifying units includes the input capacitance according to a control signal. In this configuration, the ratio of the capacitance values of the p input capacitance units formed by the formation unit is switched between two or more types.

  In the solid-state imaging device according to a seventh aspect, in the fifth or sixth aspect, the sum of the capacitance values of the p input capacitance portions formed by the input capacitance formation portions is the same as each other. .

  In the solid-state imaging device according to the eighth aspect, in any one of the fifth to seventh aspects, each of the q input capacitance forming units corresponds to the input unit of the amplifying unit according to a control signal. Forming the p input capacitance sections connected to the p vertical signal lines common to the q amplification sections among the plurality of vertical signal lines, respectively. One in the state of being connected between the input capacitance forming state and only one vertical signal line that is different for each amplification unit among the corresponding input unit of the amplification unit and the p vertical signal lines To the second input capacitance forming state forming the input capacitance section.

  A solid-state imaging device according to a ninth aspect selects the output signal of one amplification unit selected by a control signal from the q amplification units in the first input capacitance formation state in the eighth aspect. The control part which controls to read out automatically is provided.

  The solid-state imaging device according to a tenth aspect is the solid-state imaging device according to the eighth or ninth aspect, wherein the pixel unit is one of a row direction with respect to a region where the plurality of pixels are arranged in addition to the plurality of pixels. A plurality of optical black pixels that are two-dimensionally arranged in the side or both sides and generate a black level signal, and are provided for each column of the plurality of optical black pixels, and signals from the corresponding optical black pixels A plurality of optical black pixel vertical signal lines, and a plurality of optical black pixel amplifying units for outputting output signals corresponding to the signals of the plurality of optical black pixel vertical signal lines, respectively. In either of the second input capacitance formation state and the second input capacitance formation state, the plurality of optical black pixel amplifying units are different from each other. In which signals from ticarcillin black pixels is obtained.

  In a solid-state imaging device according to an eleventh aspect, in any one of the first to tenth aspects, each of the q amplification units is applied with a predetermined potential with a first input terminal serving as the input unit. An operational amplifier having a second input terminal, a column amplifier reset switch for turning on and off between the first input terminal and the output terminal of the operational amplifier, and between the first input terminal and the output terminal And a feedback capacitor connected to the.

  A solid-state imaging device according to a twelfth aspect includes, in any one of the first to eleventh aspects, a plurality of color filters provided corresponding to each of the plurality of pixels and having a predetermined color arrangement, The p vertical signal lines receive signals from pixels provided with color filters of the same color.

  An imaging device according to a thirteenth aspect includes a solid-state imaging element according to any one of the first to twelfth aspects.

  In each of the above aspects, q may be p or less.

  According to the present invention, it is possible to provide a solid-state imaging device capable of weighting and adding signals inside the device and changing the weight, and an imaging apparatus using the same.

1 is a schematic block diagram schematically showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. FIG. 3 is a circuit diagram showing a pixel in FIG. 2. FIG. 3 is a circuit diagram showing a part of an upper signal output circuit in FIG. 2. FIG. 3 is a circuit diagram showing another part of the upper signal output circuit in FIG. 2. FIG. 5 is a circuit diagram showing still another part of the upper signal output circuit in FIG. 2. FIG. 5 is a circuit diagram showing a specific example of an operational amplifier that constitutes the amplification unit in FIG. 4. FIG. 5 is a circuit diagram illustrating a state when the amplifier and the input capacitance forming unit in FIG. 4 are not added. FIG. 5 is a circuit diagram illustrating a state at the time of addition of an amplification unit and an input capacitance formation unit in FIG. 4. FIG. 3 is an operation explanatory diagram schematically showing a characteristic operation of the horizontal pixel non-addition readout mode of the solid-state imaging device shown in FIG. 2. 3 is a timing chart showing a state of a control signal in a horizontal pixel non-addition readout mode of the solid-state imaging device shown in FIG. FIG. 3 is an operation explanatory diagram schematically showing a characteristic operation of the horizontal pixel addition reading mode of the solid-state imaging device shown in FIG. 2. 3 is a timing chart showing a state of a control signal in a horizontal pixel addition readout mode with weighting 1: 1: 1 of the solid-state imaging device shown in FIG. FIG. 3 is a timing chart showing a state of a control signal in a horizontal pixel addition reading mode by weighting 1: 2: 1 of the solid-state imaging device shown in FIG. 2. FIG. 3 is a timing chart showing a state of a control signal in a horizontal pixel addition readout mode with 1: 3: 1 weighting of the solid-state imaging device shown in FIG. 2. It is a circuit diagram which shows a part of upper signal output circuit of the solid-state image sensor used with the electronic camera by the 2nd Embodiment of this invention. It is a circuit diagram which shows a part of upper signal output circuit of the solid-state image sensor used with the electronic camera by the 3rd Embodiment of this invention. It is a timing chart which shows the state of the control signal in the horizontal pixel addition reading mode by weighting of 1: 4: 1 of the solid-state image sensor used with the electronic camera by the 3rd Embodiment of this invention.

  Hereinafter, a solid-state imaging device and an imaging apparatus according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram schematically showing an electronic camera 1 as an imaging apparatus according to the first embodiment of the present invention.

  The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera. However, the imaging apparatus according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. The present invention can be applied to various imaging devices such as an electronic camera.

  A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 2a for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 3 is arranged.

  The solid-state imaging device 3 is driven by a command from the imaging control unit 4 and outputs an image signal. In the electronic viewfinder mode, moving image shooting, and the like, the imaging control unit 4 controls the solid-state imaging device 3 so as to perform a predetermined reading operation while performing a so-called rolling electronic shutter, for example. Further, at the time of normal main shooting (still image shooting) or the like, the imaging control unit 4 performs a predetermined readout operation after exposure with a mechanical shutter (not shown) after so-called global reset that resets all pixels simultaneously, for example. In this way, the solid-state imaging device 3 is controlled. Each image signal is subjected to signal processing such as black level clamping processing by the signal processing unit 5, is A / D converted by the A / D conversion unit 6, and is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected to a lens control unit 2a, an imaging control unit 4, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. An operation unit 9 a such as a release button is connected to the CPU 9. The ISO sensitivity can be set by the operation unit 9a. A recording medium 11a is detachably attached to the recording unit 11. At this time, as will be described later, the imaging control unit 4 performs solid-state imaging so as to perform a read operation that performs horizontal pixel addition described later or a read operation that does not perform horizontal pixel addition, for example, according to predetermined conditions and settings. The element 3 is controlled. Each image signal is subjected to signal processing such as black level clamping processing by the signal processing unit 5, is A / D converted by the A / D conversion unit 6, and is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected to a lens control unit 2a, an imaging control unit 4, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. An operation unit 9 a such as a release button is connected to the CPU 9. A recording medium 11a is detachably attached to the recording unit 11.

  The CPU 9 in the electronic camera 1 drives the imaging control unit 4 in accordance with the instruction of the electronic viewfinder mode, moving image shooting, or the like by the operation of the operation unit 9a. The imaging control unit 4 controls the solid-state imaging device 3 so as to perform a predetermined reading operation while performing, for example, a rolling electronic shutter. At this time, the focus and the aperture are appropriately adjusted by the lens control unit 2a. An image signal obtained from the solid-state imaging device 3 is stored in the memory 7. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a during moving image shooting. In the case of normal main shooting (during still image shooting) or the like, the CPU 9 stores the image signal in the memory 7 and then, based on a command from the operation unit 9a, the image processing unit 13 or the image compression unit as necessary. 12, the desired processing is performed, and the processed signal is output to the recording unit 11 and recorded on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 3 in FIG. In the present embodiment, the solid-state imaging device 3 is configured as a CMOS type solid-state imaging device, but may be configured as another XY address type solid-state imaging device.

  As shown in FIG. 2, the solid-state imaging device 3 includes a pixel unit 21, a plurality of horizontal control signal lines 22, a vertical scanning circuit 23, a plurality of vertical signal lines V <b> 1 to Vm, and a column direction of the pixel unit 21 ( The upper signal output circuit 24 and the lower signal output circuit 25 are arranged on both sides in the vertical direction (vertical direction in FIG. 2).

  The pixel unit 21 is arranged in a two-dimensional matrix in n rows and k columns, and an effective pixel unit 21A including effective pixels PX that outputs pixel signals according to incident light, and a two-dimensional matrix in n rows (m−k) columns. And an OB pixel unit 21B composed of optical black pixels (OB pixels) OB that generate black level signals. In the present embodiment, the OB pixel portion 21B is arranged on the right side in FIG. 2 in the row direction (horizontal direction, left-right direction in FIG. 2) of the region of the effective pixel portion 21A. However, the OB pixel unit 21B may be arranged on the left side in FIG. 2 of the effective pixel unit 21A, or may be arranged on both the left and right sides in FIG. 2 of the effective pixel unit 21A.

  A horizontal control signal line 22 connected to the vertical scanning circuit 23 is arranged in each row of the pixel unit 21. Each horizontal control signal line 22 supplies control signals (control signals φSEL, φRES, φTX, which will be described later) output from the vertical scanning circuit 23 to the respective rows of the pixels PX, OB.

  The plurality of vertical signal lines V1 to Vk are provided for each column of the effective pixels PX, and receive signals from the effective pixels PX in the corresponding column. The plurality of vertical signal lines Vk + 1 to Vm are provided for each column of the OB pixels OB, and receive signals from the OB pixels OB in the corresponding column. The vertical signal lines Vk + 1 to Vm are OB pixel vertical signal lines. The upper ends of the vertical signal lines V1 to Vm (strictly speaking, in this embodiment, the upper ends of the vertical signal lines in the even-numbered columns of the vertical signal lines) are connected to the upper signal output circuit 24. Yes. The lower ends of the vertical signal lines V1 to Vm (strictly speaking, in this embodiment, the lower side of the vertical signal lines in the odd-numbered columns of the vertical signal lines) are connected to the lower signal output circuit 25. Has been. Here, the vertical signal line in the first column is denoted by reference numeral V1, the vertical signal line in the mth column is denoted by reference numeral Vm, and the same applies to the other vertical signal lines. A constant current source 26 is connected to each of the vertical signal lines V1 to Vm (see FIGS. 4 and 5 described later). The constant current source 26 may be connected to the upper end side and the lower end side of each of the vertical signal lines V1 to Vm, and two constant current sources 26 may be connected to each of the vertical signal lines V1 to Vm. . In this case, the current value per constant current source is set to ½ times the current value required per vertical signal line.

  In order to prevent so-called lateral smear and black sun as necessary, the vertical signal lines V1 to Vm are disclosed, for example, in FIGS. 4 and 5 of Japanese Patent Application Laid-Open No. 2010-263443. A clip circuit may be provided.

  In the present embodiment, on the light incident side of each pixel PX, a plurality of types of color filters that transmit light of different color components are arranged in a color array having a repetition cycle of 2 rows and 2 columns. . The pixel PX outputs an electrical signal corresponding to each color by color separation with a color filter. In this embodiment, as shown in FIG. 2, a Bayer arrangement is adopted as the color arrangement, and red (R), green (Gr, Gb), and blue (B) color filters are applied to each pixel PX according to the Bayer arrangement. Has been placed. That is, R and Gr color filters are alternately arranged in odd rows of the effective pixel portion 21A, and Gb and B filters are alternately arranged in even rows of the effective pixel portion 21A. And in the effective pixel part 21A whole, the green filter is arrange | positioned so that a checkered pattern may be made. Thereby, the effective pixel unit 21A can acquire a color image at the time of imaging. In the present embodiment, a color filter is arranged in the OB pixel portion 21B as well as the effective pixel portion 21A. However, since the OB pixel OB outputs a black level, it is not always necessary to dispose a color filter in the OB pixel portion 21B. In FIG. 2, the color of the color filter is also shown in each pixel PX and OB.

  FIG. 3 is a circuit diagram showing the pixels PX and OB in FIG. In the present embodiment, each pixel PX includes a photodiode PD as a photoelectric conversion unit and a charge-voltage conversion unit that receives the charge and converts the charge into a voltage, like a pixel of a general CMOS solid-state imaging device. As a floating diffusion FD, a reset transistor RES that resets the potential of the floating diffusion FD, a selection transistor SEL that supplies a signal corresponding to the potential of the floating diffusion FD to the vertical signal lines V1 to Vm, and a floating diffusion from the photodiode PD A transfer transistor TX as a charge transfer unit that transfers charges to the FD and an amplification transistor AMP as an amplification unit that outputs the signal corresponding to the potential of the floating diffusion FD are connected as shown in FIG. To have. In FIG. 3, VDD is a power supply potential. In the present embodiment, the transistors AMP, TX, RES, and SEL of the pixels PX and OB are all nMOS transistors.

  In the present embodiment, the OB pixel OB has the same structure as the effective pixel PX except that the photodiode PD is shielded from light. However, the OB pixel OB may have a structure in which the photodiode PD is removed from the effective pixel PX, for example.

  The gates of the transfer transistors TX are commonly connected to each row, and a control signal φTX is supplied from the vertical scanning circuit 23 thereto. The gates of the reset transistors RES are commonly connected to each row, and a control signal φRES is supplied from the vertical scanning circuit 23 to the reset transistors RES. The gates of the selection transistors SEL are commonly connected to each row, and a control signal φSEL is supplied from the vertical scanning circuit 23 thereto. When each control signal φTX is distinguished for each row, the control signal φTX in the j-th row is indicated by a symbol φTX (j). This also applies to the control signals φRES and φSEL.

  The photodiode PD of each pixel PX generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX is turned on during the high level period of the control signal φTX, and transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RES is turned on during the high level period (period of the power supply potential VDD) of the control signal φRES, and resets the floating diffusion FD.

  The amplification transistor AMP has its drain connected to the power supply potential VDD, its gate connected to the floating diffusion FD, its source connected to the drain of the selection transistor SEL, and a constant current source 26 (not shown in FIG. 3). 4 and FIG. 5) is configured as a source follower circuit. The amplification transistor AMP outputs a read signal to the vertical signal lines V1 to Vm via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the control signal φSEL, and connects the source of the amplification transistor AMP to the vertical signal lines V1 to Vm.

  The vertical scanning circuit 23 in FIG. 2 receives the control signal from the imaging control unit 4 in FIG. 1 and outputs control signals φSEL, φRES, and φTX for each row of the pixels PX and OB, and the rolling electronic shutter. And a still image read operation by global reset using a mechanical shutter. Since these specific operations are known, the description thereof is omitted here.

  The configuration of the pixels PX and OB is not limited to the configuration shown in FIG. For example, for each of a plurality of pixels PX and OB adjacent in the column direction, the plurality of pixels PX may share a set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL.

  4 shows a part of the upper signal output circuit 24 in FIG. 2 (corresponding to the vertical signal lines V2, V4, V6 of the second column, fourth column, and sixth column of the effective pixel portion 21A, respectively). 3 is a circuit diagram showing three input capacitance forming units IC1 to IC3 and three amplifying units CA1 to CA3).

  FIG. 5 is provided corresponding to the other portions of the upper signal output circuit 24 in FIG. 2 (vertical signal lines Vk + 2, Vk + 4, Vk + 6 of the k + 2 column, k + 4 column, and k + 6 column of the OB pixel unit 21B). In addition, three input capacitance forming units IC (k / 2) +1, IC (k / 2) +2, IC (k / 2) +3 and three amplifying units CA (k / 2) +1, CA (k / 2) It is a circuit diagram showing +2, CA (k / 2) +3). In FIG. 5, elements that are the same as or correspond to those in FIG.

  FIG. 6 is a diagram showing a further portion of the upper signal output circuit 24 in FIG. 2 (k / each provided corresponding to the vertical signal lines in the even-numbered columns from the second column to the k-th column of the effective pixel portion 21A. The output signals of the two amplification units CA1 to CA (k / 2) and the vertical signal lines of the even-numbered columns from the (k + 2) th column to the m-th column of the OB pixel unit 21B are provided (m -K) / 2 sampling units CDS1 to CDS (m / 2), horizontal scanning circuit 31 and the like that sample and hold the output signals of the two amplification units CA (k / 2) +1 to CA (m / 2), respectively. FIG.

  In the present embodiment, as shown in part in FIG. 4, the upper signal output circuit 24 is provided corresponding to each of the vertical signal lines V2, V4,. Further, k / 2 input capacitance forming units IC1 to IC (k / 2) and k / 2 amplifying units CA1 to CA (k / 2) are included.

  Each of the amplification units CA1 to CA (k / 2) has the same configuration, and has an input unit (in this embodiment, an inverting input terminal as a first input terminal of the operational amplifier OP).

  In the present embodiment, each of the amplification units CA1 to CA (k / 2) includes an operational amplifier OP, a feedback capacitor Cf, and a column amplifier reset switch CARST that resets the column amplifier in response to a column amplifier reset signal φCARST. Have. A feedback capacitor Cf and a column amplifier reset switch CARST are connected in parallel between the inverting input terminal (first input terminal as an input unit) of the operational amplifier OP and the output terminal of the operational amplifier OP. A predetermined potential Vref is applied to a non-inverting input terminal (second input terminal) of the operational amplifier OP. The column amplifier reset switch CARST is composed of a MOS transistor, and is turned on when the column amplifier reset signal φCARST is at a high level, and turned off when the column amplifier reset signal φCARST is at a low level. The gates of the column amplifier reset switches CARST of the amplification units CA1 to CA (k / 2) are connected in common, and a column amplifier reset signal φCARST is supplied from the imaging control unit 4 thereto.

  In the present embodiment, as the operational amplifier OP, an operational amplifier (hereinafter referred to as an “operational amplifier with a standby function”) that can be in an operating state and an operation stopped state with lower power consumption than the operating state in accordance with the operation control signal φSTBY. Is used). Depending on the operation state and operation stop state of the operational amplifier OP, the entire amplification unit having the operational amplifier OP is also in the operation state and the operation stop state. However, a normal operational amplifier that does not have a standby function and is always in an operating state may be used as the operational amplifier OP.

  FIG. 7 is a circuit diagram showing a specific example of an operational amplifier OP which is an operational amplifier with a standby function. In this example, the operational amplifier OP is composed of pMOS transistors T1 to T4 and nMOS transistors T5 to T8. In this example, a standby function is realized by adding transistors T3, T4, and T7 to transistors T1, T2, T5, T6, and T8 that form a general configuration of an operational amplifier. In FIG. 7, VIN_P, VIN_N, and VOUT indicate a non-inverting input terminal, an inverting input terminal, and an output terminal of the operational amplifier OP, respectively. VBIAS is a bias voltage input terminal to which a current source bias voltage from a bias circuit (not shown) is applied.

  In FIG. 7, STBY is a terminal (operation control signal input terminal) to which an operation control signal φSTBY is input, and STBY_N is a terminal to which an inverted signal of the operation control signal φSTBY is input. When the operation control signal φSTBY becomes high level, the transistors T3, T4, T7 are turned off, the current flowing through the operational amplifier OP is cut off, the operational amplifier OP is deactivated, and the output terminal VOUT becomes floating. In FIG. 4 and the like, only the operation control signals φSTBY1 to φSTBY3 corresponding to the operation control signal φSTBY are described as being supplied to the operational amplifier OP, and the inverted operation control signal corresponding to the operation control signal φSTBY_N is supplied to the operational amplifier OP. The control lines are not shown. In the following description, only the operation control signal φSTBY will be referred to, and the reference to the reverse operation control signal will be omitted. When a normal operational amplifier that does not have a standby function is used as the operational amplifier OP, the operation control signal φSTBY is not input to the operational amplifier OP.

  Amplifying sections CA1 to CA (k / 2) are grouped into r groups (three in the present embodiment) having r cycles (three in the present embodiment) in the row direction (horizontal direction). When divided, that is, into a first group of amplifiers CA1, CA4, CA7,..., A second group of amplifiers CA2, CA5, CA8,... And a third group of amplifiers CA3, CA6, CA9,. When divided, the operation control signal φSTBY is input for each group. That is, the operation stop signal input terminals of the first group amplifiers CA1, CA4, CA7,... Are connected in common, and the operation control signal φSTBY1 is supplied from the imaging control unit 4 thereto. The operation stop signal input terminals of the amplifying units CA2, CA5, CA8,... Of the second group are connected in common, and an operation control signal φSTBY2 is supplied from the imaging control unit 4 thereto. The operation stop signal input terminals of the third group amplifiers CA3, CA6, CA9,... Are connected in common, and an operation control signal φSTBY3 is supplied from the image pickup control unit 4 thereto.

  In the present embodiment, each of the k / 2 input capacitance forming units IC1 to IC (k / 2) is supplied with a control signal (φ1, φ2, φSW, or φ3, φ4, φSW, or φ5, φ6). , ΦSW) according to the input unit (in this embodiment, the inverting input terminal of the operational amplifier OP) of the corresponding amplifier, and q (3 in the present embodiment) including the corresponding amplifier. ) P (three in this embodiment) input capacitors connected between p (three in this embodiment) vertical signal lines that are common to the amplifying units) Portions Ca, Cb, and Cc (see FIG. 9 described later) are formed. At this time, p number of input capacitance forming units corresponding to at least one amplifying unit among q amplifying units (three in the present embodiment) common to p vertical signal lines are formed. The ratio of the capacitance values of the input capacitance units Ca, Cb, Cc is such that the p input capacitance units Ca, Cb formed by the input capacitance formation unit corresponding to at least one other amplification unit among the q amplification units. , Cc are different from the ratio of the capacitance values. The capacitance values of the p input capacitance units Ca, Cb, Cc formed by the input capacitance formation unit corresponding to the at least one amplification unit among the q amplification units common to the p vertical signal lines. The ratio may be 1: 1: 1. The input capacitance units Ca, Cb, and Cc may be a combined capacitance constituted by a plurality of capacitances, or may be constituted by a single capacitance.

  In the present embodiment, the vertical signal lines V2, V4,..., Vk of the even-numbered columns, k / 2 input capacitance forming units IC1 to IC (k / 2), and k / 2 amplifying units CA1 to CA ( k / 2) corresponds to every other three vertical signal lines, three input capacitance forming portions provided corresponding to the three vertical signal lines, and the three vertical signal lines, respectively. Each block is composed of three amplifying units. For example, a block composed of three vertical signal lines V2, V4, V6, three input capacitance forming units IC1, IC2, IC3 and three amplifying units CA1, CA2, CA3 (this block is shown in FIG. A block composed of three vertical signal lines V8, V10, V12, three input capacitance forming units IC4, IC5, IC6 and three amplifier units CA4, CA5, CA6, and three vertical signal lines V14 , V16, V18, three input capacitance forming units IC7, IC8, IC9 and three amplifying units CA6, CA7, CA8.

  For each of these blocks, each of the three input capacitance forming units in the block corresponds to the control signal (φ1, φ2, φSW, or φ3, φ4, φSW, or φ5, φ6, φSW). The inverting input terminal of the corresponding amplification unit in the block and the three vertical signal lines (three vertical signal lines in the block) common to the three amplification units in the block Three input capacitance units Ca, Cb, and Cc (see FIG. 9 described later) are formed in a state of being connected therebetween. At this time, in each block, the three input capacitance units Ca and Cb formed by the input capacitance forming unit corresponding to at least one amplification unit among the three amplification units common to the three vertical signal lines. , Cc is a ratio of the capacitance values of the three input capacitance units Ca, Cb, Cc formed by the input capacitance formation unit corresponding to at least one other amplification unit among the three amplification units. It is different from the ratio.

  For example, in the block shown in FIG. 4, the input capacitance forming unit IC1 in the block receives the inverting input terminal of the corresponding amplifying unit CA1 in the block and the in-block in accordance with the control signals φ1, φ2, and φSW. Between the three vertical signal lines V2, V4, and V6 (three vertical signal lines V2, V4, and V6 in the block) common to the three amplifiers CA1, CA2, and CA3, three Input capacitance portions Ca, Cb, Cc (see FIG. 9 described later). Further, in the block shown in FIG. 4, the input capacitance forming unit IC2 in the block, in response to the control signals φ3, φ4, and φSW, the inverting input terminal of the corresponding amplifying unit CA2 in the block, Between the three vertical signal lines V2, V4, and V6 (three vertical signal lines V2, V4, and V6 in the block) common to the three amplifiers CA1, CA2, and CA3, three Input capacitance portions Ca, Cb, Cc (see FIG. 9 described later). Further, in the block shown in FIG. 4, the input capacitance forming unit IC3 in the block, in response to the control signals φ5, φ6, and φSW, the inverting input terminal of the corresponding amplifying unit CA3 in the block, Between the three vertical signal lines V2, V4, and V6 (three vertical signal lines V2, V4, and V6 in the block) common to the three amplifiers CA1, CA2, and CA3, three Input capacitance portions Ca, Cb, Cc (see FIG. 9 described later). At this time, in the block shown in FIG. 4, the input capacitance is formed corresponding to at least one of the three amplifiers CA1, CA2, CA3 common to the three vertical signal lines V2, V4, V6. The ratio of the capacitance values of the three input capacitance units Ca, Cb, Cc formed by the unit corresponds to at least one other amplification unit among the three amplification units CA1, CA2, CA3. Is different from the ratio of the capacitance values of the three input capacitance portions Ca, Cb, and Cc formed by. In this example, IC1, IC2 and IC3 correspond to the IC in FIG. 9, V2 corresponds to Va in FIG. 9, V4 corresponds to Vb in FIG. 9, and V6 corresponds to Vc in FIG. To do.

  In the present embodiment, each of the k / 2 input capacitance forming units IC1 to IC (k / 2) is supplied with a control signal (φ1, φ2, φSW, or φ3, φ4, φSW, or φ5). , Φ6, φSW) according to the input unit of the corresponding amplification unit (in this embodiment, the inverting input terminal of the operational amplifier OP) and q (in this embodiment, including the corresponding amplification unit, Between the three (three in this embodiment) vertical signal lines common to the three (amplification) amplifiers, p (three in this embodiment) input capacitance units Ca, A first input capacitance forming state for forming Cb and Cc (see FIG. 9 to be described later), and one corresponding to each of the amplifying units among the corresponding input unit and p vertical signal lines of the amplifying unit. 2nd input which forms one input capacity | capacitance part Ci (refer FIG. 8 mentioned later) between only the vertical signal lines To the amount formed state switches. In the second input capacitance formation state, for example, in the block shown in FIG. 4 when divided into blocks as described above, the input capacitance formation unit IC1 performs the corresponding amplification according to the control signals φ1, φ2, and φSW. One input capacitance portion Ci (see FIG. 8 to be described later) connected between the inverting input terminal of the portion CA1 and only one vertical signal line V2 is formed, and the input capacitance formation portion IC2 In response to the control signals φ3, φ4, and φSW, one input capacitance unit Ci (described later) is connected between the inverting input terminal of the corresponding amplification unit CA2 and only one vertical signal line V4. The input capacitance forming unit IC3 is connected between the inverting input terminal of the corresponding amplification unit CA3 and only one vertical signal line V6 according to the control signals φ5, φ6, and φSW. One input capacitance unit Ci (described later) That reference to FIG. 8) to form a. In this example, when IC1 corresponds to the IC in FIG. 8, V2 corresponds to Vi in FIG. 8, and when IC2 corresponds to the IC in FIG. 8, V4 corresponds to Vi in FIG. When IC3 corresponds to the IC in FIG. 8, V6 corresponds to Vi in FIG.

  Specifically, in the present embodiment, every two input capacitance forming units IC1, IC4, IC7,... Of the k / 2 input capacitance forming units IC1 to IC (k / 2). Each of the capacitors C1, C2, C3 of one set (one in the present embodiment) having one electrode connected to the inverting input terminal of the corresponding amplifier, and the other of the capacitors C1, C2, C3 One set (p (three in this embodiment)) that turns on and off between the electrode and p (three in this embodiment) vertical signal lines belonging to the same block as the input capacitance forming portion Switches SW1, SW2 as switching means for switching between the input switches CS1, CS2, CS3 and the other electrodes of the capacitors C1, C2, C3 being electrically connected to each other and electrically separated from each other. (In this embodiment, the switch SW1 And off between the other electrode of the capacitor C1, C2, the switch SW2 has, to off.) Between the other electrode of the capacitor C2, C3. For example, in the block shown in FIG. 4, the input capacitance forming unit IC1 includes a set (three) of capacitors C1, C2, C3 in which one electrode is connected to the inverting input terminal of the operational amplifier OP of the corresponding amplifier CA1. A pair (three) of input switches CS1, CS2, CS3 for turning on and off between the other electrodes of the capacitors C1, C2, C3 and the three vertical signal lines V2, V4, V6, and capacitors C1, C2 , C3, and switches SW1 and SW2 as switching means for switching between a state where the other electrodes of C3 are electrically connected to each other and a state where they are electrically separated from each other.

  Specifically, in the present embodiment, every two input capacitance forming portions IC2, IC5, IC8,... Of the k / 2 input capacitance forming portions IC1 to IC (k / 2). Each of the capacitors C4, C5, C6 having one set of electrodes connected to the inverting input terminal of the operational amplifier OP of the corresponding amplifying unit (p (three in this embodiment)), and capacitors One set (p (in this embodiment) that turns on / off each of the other electrodes of C4, C5, and C6 and p (in this embodiment, three) vertical signal lines that belong to the same block as the input capacitance forming section. In the embodiment, three switches)) are switched between the input switches CS4, CS5, CS6 and the other electrodes of the capacitors C4, C5, C6 being electrically connected to each other and electrically separated from each other. Switches SW3 and SW4 (means of this embodiment) In the switch SW3 is turned on and off between the other electrode of the capacitor C4, C5, switch SW4 has an on and off.) Between the other electrode of the capacitor C5, C6. For example, in the block shown in FIG. 4, the input capacitance forming unit IC2 includes one set (three) of capacitors C4, C5, C6 in which one electrode is connected to the inverting input terminal of the operational amplifier OP of the corresponding amplifier CA2. A pair (three) of input switches CS4, CS5 and CS6 for turning on and off between the other electrodes of the capacitors C4, C5 and C6 and the three vertical signal lines V2, V4 and V6, and capacitors C4 and C5 , C6, and switches SW3 and SW4 as switching means for switching between a state in which the other electrodes of C6 are electrically connected to each other and a state in which they are electrically separated from each other.

  More specifically, in the present embodiment, every two input capacitance forming units IC3, IC6, IC9,... Of the k / 2 input capacitance forming units IC1 to IC (k / 2). Each includes one set of capacitors C7, C8, C9 having one electrode connected to the inverting input terminal of the operational amplifier OP of the corresponding amplifier (p (three in this embodiment)), and capacitors One set (p (in this embodiment) that turns on and off between the other electrodes of C7, C8, and C9 and p (in this embodiment, three) vertical signal lines that belong to the same block as the input capacitance forming section. In the embodiment, three switches are switched between the input switches CS7, CS8, CS9 and the other electrodes of the capacitors C7, C8, C9 being electrically connected to each other and electrically separated from each other. Switches SW5 and SW6 as means (this embodiment The state, the switch SW5 is turned on and off between the other electrode of the capacitor C7, C8, switch SW6 has, to off.) Between the other electrode of the capacitor C8, C9. For example, in the block shown in FIG. 4, the input capacitance forming unit IC3 includes one set (three) of capacitors C7, C8, C9 in which one electrode is connected to the inverting input terminal of the operational amplifier OP of the corresponding amplifier CA3. And a set (three) of input switches CS7, CS8, CS9 and capacitors C7, C8 for turning on and off between the other electrodes of the capacitors C7, C8, C9 and the three vertical signal lines V2, V4, V6, respectively. , C9, and switches SW5 and SW6 as switching means for switching between a state in which the other electrodes of C9 are electrically connected to each other and a state in which they are electrically separated from each other.

  In the present embodiment, the switches CS1 to CS9 and SW1 to S6 are composed of, for example, nMOS transistors. The gates of the input switches CS1 of the respective blocks are connected in common, and a control signal φ1 is supplied thereto from the imaging control unit 4. The gates of the input switches CS2 and CS3 of each block are connected in common, and a control signal φ2 is supplied from the imaging control unit 4 thereto. The gates of the input switches CS4 and CS6 of the respective blocks are connected in common, and a control signal φ3 is supplied from the imaging control unit 4 thereto. The gates of the input switches CS5 of the respective blocks are connected in common, and a control signal φ4 is supplied thereto from the imaging control unit 4. The gates of the input switches CS7 and CS8 of the respective blocks are connected in common, and a control signal φ5 is supplied from the imaging control unit 4 thereto. The gates of the input switches CS9 of the respective blocks are connected in common, and a control signal φ6 is supplied thereto from the imaging control unit 4. The gates of the switches SW1 to SW6 of the respective blocks are connected in common, and a control signal φSW is supplied from the imaging control unit 4 thereto. The switches CS1 to CS9 and SW1 to SW6 are turned on when the control signals φ1 to φ6 and φSW supplied to their gates are at a high level (H), while the control signals φ1 to φ6 and φSW supplied to the gates thereof. OFF when is at low level (L).

  FIG. 8 illustrates a case where any one of the amplification units CA1 to CA (k / 2) and the input capacitance formation units IC1 to IC (k / 2) is not added. FIG. 6 is a circuit diagram showing a state (second input capacitance formation state). FIG. 9 shows a case where an arbitrary set of the amplification unit CA and the input capacitance formation unit IC among the amplification units CA1 to CA (k / 2) and the input capacitance formation units IC1 to IC (k / 2) are added. It is a circuit diagram which shows a state (the said 1st input capacitance formation state). In FIG. 8 and FIG. 9, the line for supplying the operation control signal φSTBY is omitted. In FIG. 8, Vi represents one vertical signal line that is selectively and effectively connected to the input capacitance forming unit IC, and Ci represents the input signal forming unit IC of the vertical signal line Vi and the amplification unit CA. One input capacitance section formed between the inverting input terminal of the operational amplifier OP is shown. In FIG. 9, Va, Vb, and Vc represent every other three vertical signal lines that are effectively connected to the input capacitance forming unit IC, and Ca, Cb, and Cc represent the input capacitance forming unit IC. 3 shows three input capacitors formed between the vertical signal lines Va, Vb, Vc and the inverting input terminal of the operational amplifier OP of the amplifier CA.

  In the following description, the voltages of the vertical signal lines Vi, Va, Vb, and Vc are also denoted by the same symbols Vi, Va, Vb, and Vc, respectively, and the capacitance values of the input capacitors Ca, Cb, and Cc are also denoted by the same symbols Ca, Cb, respectively. , Cc. The capacitance values of the feedback capacitor Cf of the amplifier CA and the capacitors C1 to C9 constituting the input capacitor forming unit IC are also denoted by the same symbols Cf and C1 to C9, respectively.

  In the second input capacitance formation state, the control signal φSW is set to the high level, the control signals φCS1, φCS5, φCS9 are set to the high level, and the control signals φCS2 to φCS4, φCS6 to φCS8 are set to the low level. Thus, for each of the input capacitance forming units IC1 to IC (k / 2), the three input capacitance forming units IC are provided between the inverting input terminal of the operational amplifier OP of the amplifying unit CA and the vertical signal line Vi. The capacitors (capacitors C1, C2, C3, or capacitors C4, C5, C6, or capacitors C7, C8, C9) are connected in parallel, and the state shown in FIG. The input capacitor portions Ci are formed. Therefore, in the second input capacitance formation state, Ci = C1 + C2 + C3 in the input capacitance formation units IC1, IC4, IC7,..., And Ci = C4 + C5 + C6 in the input capacitance formation units IC2, IC5, IC8,. Ci = C7 + C8 + C9 in the input capacitance forming units IC3, IC6, IC9,. In the present embodiment, C1 + C2 + C3 = C4 + C5 + C6 = C7 + C8 + C9 = C0 is set, and Ci = C0 in any input capacitance forming unit IC. However, it is not always necessary to set C1 + C2 + C3 = C4 + C5 + C6 = C7 + C8 + C9.

  In this case, when the signal φCARST becomes high level, the column amplifier reset switch CARST is turned on, the inverting input terminal and the output terminal of the operational amplifier OP are short-circuited, and the output terminal of the operational amplifier OP is reset to the predetermined potential Vref. The Thereafter, when the input voltage Vi (voltage of the vertical signal line Vi) changes by ΔVi in a state where the signal φCARST is set to the low level and the column amplifier reset switch CARST is turned off, the signal (output voltage) of the output terminal of the operational amplifier OP Vout is [Vref− (Ci / Cf) × ΔVi]. Thus, when the column amplifier reset switch CARST is turned off, Vout = [Vref− (Ci / Cf) × ΔVi] = [Vref− {C0 / Cf} × ΔVi] is obtained.

  Therefore, in the state shown in FIG. 8, the amplified output by the change ΔVi of the signal Vi of the vertical signal line selectively selectively connected to the input capacitance forming unit IC, that is, non-addition of one vertical signal line A state signal is obtained as the output signal Vout.

  It is known as a so-called column amplifier that the amplifier CA in this embodiment is fixedly connected to a predetermined vertical signal line via a single capacitor. Since the timing of the signal φCARST in this embodiment may be performed at the same timing as that of the known column amplifier, the description thereof is omitted. This is the same in the case of the state of FIG.

  When the first input capacitance is formed and weighted addition is performed with a first weight (1: 1: 1 in the present embodiment), the control signal φSW is set to a low level, and the control signals φCS1 to φCS3 are The control signals φCS4 to φCS9 are set to a low level. As a result, the other electrodes of the three capacitors C1, C2, and C3 are electrically connected to each other with respect to IC1, IC4, IC7,... Among the input capacitance forming units IC1 to IC (k / 2). In the separated state, the other electrodes of the three capacitors C1, C2, and C3 are respectively connected to three vertical signal lines belonging to the same block as the input capacitor forming portion, and the state shown in FIG. C1 forms the input capacitance portion Ca, the capacitance C2 forms the input capacitance portion Cb, and the capacitance C3 forms the input capacitance portion Cc. In the present embodiment, C1, C2, and C3 are set so that C1 + C2 + C3 = C0 and C1: C2: C3 = 1: 1: 1 as described above. That is, C1 = C2 = C3 = C0 / 3 is set. Therefore, regarding the IC1, IC4, IC7,... Among the input capacitance forming units IC1 to IC (k / 2), the state shown in FIG. 9 is obtained, and Ca = Cb = Cc = C0 / 3. On the other hand, for the remaining input capacitance forming units IC2, IC3, IC5, IC6, IC8, IC9,..., The three vertical signals in which the other electrodes of the capacitors C4 to C9 belong to the same block as the input capacitance forming unit. It is electrically disconnected from the line and does not enter the state shown in FIG. The switches SW3 to SW6 may be controlled to be turned on / off independently of the switches SW1 and SW2, but at that time, when the first input capacitance is formed and weighted addition is performed with the first weight. The on / off states of the switches SW3 to SW6 may be arbitrary.

  When the first input capacitance is formed and weighted addition is performed with a second weight (in this embodiment, 1: 2: 1), the control signal φSW is set to a low level, and the control signals φCS4 to φCS6 are The control signals φCS1 to φCS3 and φCS7 to φCS9 are set to a low level. As a result, the other electrodes of the three capacitors C4, C5, C6 are electrically connected to each other with respect to IC2, IC5, IC8,... Among the input capacitance forming units IC1 to IC (k / 2). In the separated state, the other electrodes of the three capacitors C4, C5, and C6 are respectively connected to three vertical signal lines belonging to the same block as the input capacitor forming portion, and the state shown in FIG. C4 forms the input capacitance portion Ca, the capacitance C5 forms the input capacitance portion Cb, and the capacitance C6 forms the input capacitance portion Cc. In the present embodiment, C4, C5, and C6 are set so that C4 + C5 + C6 = C0 and C4: C5: C6 = 1: 2: 1 as described above. That is, C4 = C0 / 4, C5 = C0 / 2, and C6 = C0 / 4 are set. Therefore, with respect to IC2, IC5, IC8,... Among the input capacitance forming units IC1 to IC (k / 2), the state shown in FIG. 9 is obtained, and Ca = C0 / 4, Cb = C0 / 2, Cc = C0 / 4. On the other hand, for the remaining input capacitance forming portions IC1, IC3, IC4, IC6, IC7, IC9,..., The other electrodes of the capacitors C1 to C3 and C7 to C9 belong to the same block as the input capacitance forming portion. It is electrically disconnected from the vertical signal line of the book and does not enter the state shown in FIG. The switches SW1, SW2, SW5, and SW6 may be controlled to be turned on and off independently of the switches SW3 and SW4. In this case, the first input capacitance is formed and weighted with the second weight. In the case of addition, the on / off states of the switches SW1, SW2, SW5, SW6 may be arbitrary.

  When the first input capacitance is formed and weighted addition is performed with a third weight (1: 3: 1 in the present embodiment), the control signal φSW is set to the low level, and the control signals φCS7 to φCS9 are The control signals φCS1 to φCS6 are set to a low level. As a result, the other electrodes of the three capacitors C7, C8, C9 are electrically connected to each other with respect to IC3, IC6, IC9,... Among the input capacitance forming units IC1 to IC (k / 2). In the separated state, the other electrodes of the three capacitors C7, C8, C9 are respectively connected to three vertical signal lines belonging to the same block as the input capacitor forming portion, and the state shown in FIG. C7 forms the input capacitance portion Ca, the capacitance C8 forms the input capacitance portion Cb, and the capacitance C9 forms the input capacitance portion Cc. In the present embodiment, C7, C8, and C9 are set so that C7 + C8 + C9 = C0 and C7: C8: C9 = 1: 3: 1 as described above. That is, C7 = C0 / 5, C8 = 3C0 / 5, and C9 = C0 / 5. Therefore, regarding the IC3, IC6, IC9,... Among the input capacitance forming units IC1 to IC (k / 2), the state shown in FIG. 9 is obtained, and Ca = C0 / 5, Cb = 3C0 / 5, Cc = C0 / 5. On the other hand, with respect to the remaining input capacitance forming portions IC1, IC2, IC4, IC5, IC7, IC8,..., Three vertical signals in which the other electrodes of the capacitors C1 to C6 belong to the same block as the input capacitance forming portion. It is electrically disconnected from the line and does not enter the state shown in FIG. The switches SW1 to SW4 may be controlled to be turned on / off independently of the switches SW5 and SW6. In this case, when the first input capacitance is formed and weighted addition is performed with the third weight. The on / off states of the switches SW1 to SW4 may be arbitrary.

  In the state shown in FIG. 9, when the signal φCARST becomes high level, the column amplifier reset switch CARST is turned on to short-circuit between the inverting input terminal and the output terminal of the operational amplifier OP, and the output terminal of the operational amplifier OP. Is reset to the predetermined potential Vref. Thereafter, when the signal φCARST is set to a low level and the column amplifier reset switch CARST is turned off, the input voltages Va, Vb, and Vc (the voltages of the vertical signal lines Va, Vb, and Vc) change by ΔVa, ΔVb, and ΔVc, respectively. The signal (output voltage) Vout at the output terminal of the operational amplifier OP is [Vref − [{(Ca / Cf) × ΔVa} + {(Cb / Cf) × ΔVb} + {(Cc / Cf) × ΔVc}]]. ]. Thus, when the column amplifier reset switch CARST is turned off, Vout = [Vref − [{(Ca / Cf) × ΔVa} + {(Cb / Cf) × ΔVb} + {(Cc / Cf) × ΔVc}]] Is obtained. Therefore, in the state shown in FIG. 9, a signal obtained by weighting and adding ΔVa, ΔVb, and ΔVc with a weight of Ca: Cb: Cc is obtained as the output signal Vout.

  Therefore, when weighted addition is performed with the first weight (1: 1: 1 in the present embodiment) in the first input capacitance formation state, Ca = Cb = Cc = C0 / 3. Vout = [Vref − [{(C0 / 3Cf) × ΔVa} + {(C0 / 3Cf) × ΔVb} + {(C0 / 3Cf) × ΔVc}]]. Therefore, as each output signal Vout of the amplifiers CA1, CA4, CA7,..., ΔVa, ΔVb, and ΔVc relating to signals of three vertical signal lines belonging to the same block as the amplifier are 1: 1: 1. A signal weighted and added by the weight is obtained.

  In addition, when weighted addition is performed with the second weight (1: 2: 1 in the present embodiment) in the first input capacitance formation state, Ca = C0 / 4, Cb = C0 / 2, Cc = C0 / 4, Vout = [Vref − [{(C0 / 4Cf) × ΔVa} + {(C0 / 2Cf) × ΔVb} + {(C0 / 4Cf) × ΔVc}]]. Therefore, ΔVa, ΔVb, and ΔVc relating to signals of three vertical signal lines belonging to the same block as the amplification unit are 1: 2: 1 as the output signals Vout of the amplification units CA2, CA5, CA8,. A signal weighted and added by the weight is obtained.

  Further, when the first input capacitance is formed and weighted addition is performed with a third weight (1: 3: 1 in the present embodiment), Ca = C0 / 5, Cb = 3C0 / 5, Cc = C0 / 5, Vout = [Vref − [{(C0 / 5Cf) × ΔVa} + {(3C0 / 5Cf) × ΔVb} + {(C0 / 5Cf) × ΔVc}]]. Therefore, as each output signal Vout of the amplifiers CA3, CA6, CA9,..., ΔVa, ΔVb, and ΔVc relating to signals of three vertical signal lines belonging to the same block as the amplifier are 1: 3: 1. A signal weighted and added by the weight is obtained.

  The first to third weights are not necessarily limited to 1: 1: 1, 1: 2: 1, and 1: 3: 1. By appropriately setting the values C1 to C9, the first to third weights can be appropriately set. At this time, so that Ca = Cc and Cb ≧ Ca (that is, the capacitance value of the central input capacitance portion Cb while ensuring the symmetry of the capacitance values Ca, Cb, Cc of the input capacitance portions Ca, Cb, Cc) It is preferable to set the values of C1 to C9 so that Cb is equal to or larger than the capacitance values Ca and Cc of the peripheral input capacitance units Ca and Cc.

  As can be seen from the above description, in the present embodiment, Ci in the second capacitance formation state and Ca + Cb + Cc in the first capacitance formation state with any weight are C0. Therefore, as can be understood from the above-described equation, the present embodiment is preferable because the levels of the output signals Vout are uniform in each case, and it is not necessary to perform level adjustment of these output signals Vout. However, the present invention is not necessarily limited to this. In that case, the level of the output signal Vout in each state may be adjusted as necessary using a variable gain amplifier or the like.

  Reference is now made to FIG. In the present embodiment, as partly shown in FIG. 5, the upper signal output circuit 24 is provided corresponding to the vertical signal lines Vk + 2, Vk + 4,..., Vm in the even-numbered columns of the OB pixel portion 21B. {(M / 2)-(k / 2)} input capacitance forming units IC (k / 2) +1 to IC (m / 2) and {(m / 2)-(k / 2)} Amplifiers CA (k / 2) +1 to CA (m / 2). These are for OB pixels, and k / 2 pieces are provided corresponding to the vertical signal lines V2, V4,..., Vk of the even-numbered columns of the effective pixel portion 21A described with reference to FIG. The input capacitance forming units IC1 to IC (k / 2) and the k / 2 amplification units CA1 to CA (k / 2) are configured in the same manner.

  However, in the present embodiment, the effective pixel PX is switched between horizontal pixel addition and horizontal pixel non-addition, while the OB pixel is always treated as non-horizontal pixel addition and signals in all columns of the OB pixel are individually received. It is configured to read.

  That is, in the OB pixel input capacitance forming part IC (k / 2) +1 to IC (m / 2), a high level is fixedly applied to the gates of the switches SW1 to SW6, CS1, CS5, and CS9, so that the switch SW1 is always switched. ˜SW6, CS1, CS5, CS9 are turned on, and a low level is applied to the gates of the switches CS2 to CS4, CS6 to CS8 in a fixed manner, so that the switches CS2 to CS4 and CS6 to CS8 are always turned off. Accordingly, the OB pixel input capacitance forming units IC (k / 2) +1 to IC (m / 2) are fixed in the non-addition state shown in FIG. In order to realize the same electrical connection state as this, the switches SW1 to SW6 and CS1 to CS9 of the OB pixel input capacitance forming portion IC (k / 2) +1 to IC (m / 2) are removed, and the on state is established. The locations connected by the switches SW1 to SW6, CS1, CS5, and CS9 may be connected by wiring. However, in this case, the uniformity of the circuit is lowered, and an offset or the like is likely to occur in the signal. Therefore, as in the present embodiment, the OB pixel input capacitance forming portions IC (k / 2) +1 to IC (m / It is preferable to provide the switches SW1 to SW6, CS1, CS5, and CS9 of 2).

  Further, the operational control signal φSTBY-OB independent of the operation control signals φSTBY1 to φSTBY3 is supplied to the operational amplifier OP of the OB pixel amplification units CA (k / 2) +1 to CA (m / 2). The OB pixel amplifying sections CA (k / 2) +1 to CA (m / 2) can be always operated independently of the amplifying sections CA1 to CA (k / 2) described above.

  As shown in FIG. 6, the upper signal output circuit 24 includes sampling units CDS1 to CDS (m / 2) provided corresponding to the amplifying units CA1 to CA (m / 2), respectively, and a horizontal scanning circuit 31. And horizontal signal lines 32N and 32S, horizontal line reset transistors RTHS and RTHN, and output amplifiers APS and APN.

  The horizontal scanning circuit 31 outputs a horizontal scanning signal φH for each of the sampling units CDS1 to CDS (m / 2) or for each selected one under the control of the imaging control unit 4, and performs horizontal scanning. Take control. (m / 2) attached to φH indicates a signal in the m-th column.

  The output terminals of the operational amplifiers OP of the corresponding amplifiers CA1 to CA (m / 2) are connected to the sampling units CDS1 to CDS (m / 2). Each sampling unit CDS1 to CDS (m / 2) has a first capacitor CS and a second capacitor CN. In the present embodiment, the first capacitor CS is a capacitor that accumulates optical signals and the like. The second capacitor CN is a capacitor for accumulating a differential signal including a noise component to be subtracted from the optical signal or the like. Each sampling unit CDS1 to CDS (m / 2) includes first and second input switches TVS and TVN, and first and second output switches THS and THN. Each sampling unit CDS1 to CDS (m / 2) samples and holds the output signal Vout of the corresponding amplification unit CA1 to CA (m / 2) in accordance with the control signals φTVN and φTVS, and horizontally holds the held signal. In accordance with the horizontal scanning signal φH from the scanning circuit 31, it is supplied to the horizontal signal lines 32N and 32S. The optical signal and the like and the difference signal output to the horizontal signal lines 32N and 32S are amplified through the output amplifiers APS and APN, respectively, and output to the signal processing unit 5 in FIG. The signal processing unit 5 obtains the difference between the outputs of the output amplifiers APS and APN using a differential amplifier or the like. Thereby, correlated double sampling is realized. Note that such a differential amplifier or the like may be mounted on the solid-state imaging device 3. The sampling units CDS1 to CDS (m / 2) are provided to remove the offset of the amplification units CA1 to CA (m / 2). The horizontal line reset transistors RTHS and RTHN reset the horizontal signal lines 32S and 32N to a predetermined potential Vref0 at a predetermined timing in accordance with the horizontal line reset control signal φRTH.

  Since the sampling units CDS1 to CDS (m / 2) themselves are known, a detailed description thereof will be omitted.

  Although not shown in the drawing, the lower signal output circuit 25 in FIG. 2 is the same as the circuit obtained by inverting the upper signal output circuit 24 upside down. However, in the lower signal output circuit 25, the three vertical signal lines to which signals are added during horizontal pixel addition are three lines V5, V7, V9, three lines V11, V13, V15,... The above-described blocks are determined so that At this time, in the lower signal output circuit 25, the input capacitance forming units IC1 and IC2 are commonly connected to the vertical signal lines V1 and V3, and the input capacitance forming units IC1 and IC2, the amplifying units CA1 and CA2, and the vertical signal line V1. , V2 constitute an incomplete block. For these points, refer to FIG. 12 described later. Specifically, in the lower signal output circuit 25, the input capacitance forming units IC1, IC4, IC7,... Are composed of capacitors C4 to C6 and switches CS4 to CS6, SW3, SW4, and the input capacitance forming units IC2, IC2,. IC5, IC8,... Are composed of capacitors C7 to C9 and switches CS7 to CS9, SW5, SW6, and input capacitance forming units IC3, IC6, IC9,... Are capacitors C1 to C3 and switches CS1 to CS3, SW1. , SW2, the vertical signal line V1 is connected to the switches CS5 and CS8 of the input capacitance forming units IC1 and IC2, and the vertical signal line V3 is connected to the switches CS6 and CS9 of the input capacitance forming units IC1 and IC2 The line V5 is connected to the switches CS1, CS4 and CS7 of the input capacitance forming units IC3, IC4 and IC5, and the vertical signal line V7 is the input capacitance forming unit. Connected to switches CS2, CS5, CS8 of C3, IC4, IC5, vertical signal line V9 is connected to switches CS3, CS6, CS9 of IC3, IC4, IC5, and vertical signal line V11 is formed of an input capacitance. Connected to switches CS1, CS4, and CS7 of IC6, IC7, and IC9, vertical signal line V13 is connected to switches CS2, CS5, and CS8 of input capacitance forming units IC6, IC7, and IC8, and vertical signal line V14 is connected to an input capacitance forming unit. The same applies to the vertical signal lines V15, V17, V19,... Connected to the switches CS3, CS6, CS9 of IC6, IC7, IC8.

  In this embodiment, since the signal output circuit is divided into the upper signal output circuit 24 and the lower signal output circuit 25 as described above, the space can be used effectively and the processes of both are performed in parallel. By doing so, the processing speed can be increased. However, in the present invention, the signal output circuit may be arranged only on either the upper side or the lower side.

  Next, an operation example of the solid-state imaging device 3 shown in FIG. 2 will be described.

  In the present embodiment, an operation mode (hereinafter referred to as “horizontal pixel non-addition readout mode”) in which signals of all pixels PX are read out without horizontal pixel addition during normal main shooting (still image shooting) or the like. Done.

  FIG. 10 is an operation explanatory diagram schematically showing a characteristic operation of the horizontal pixel non-addition readout mode of the solid-state imaging device 3 shown in FIG. FIG. 11 is a timing chart showing the state of the control signal in the horizontal pixel non-addition readout mode of the solid-state imaging device 3 shown in FIG.

  In the horizontal pixel non-addition readout mode, as shown in FIG. 11, the upper and lower control signals φSW, φCS1, φCS5, and φCS9 (of the upper signal output circuit 24 and the lower signal output circuit 25) are maintained at a high level. On the other hand, the upper and lower control signals φCS2 to φCS4 and φCS6 to φCS8 are maintained at a low level. Therefore, both the upper and lower effective pixel input capacitance forming units IC1 to IC (k / 2) are maintained in the non-addition state shown in FIG. The upper and lower OB pixel input capacitance forming portions IC (k / 2) +1 to IC (m / 2) are originally fixed in the non-addition state shown in FIG.

  In the horizontal pixel non-addition readout mode, as can be understood from FIG. 10, the vertical signal lines V2, V4,..., Vm in the even-numbered columns are in the second input capacitance formation state shown in FIG. State) input capacitance forming portions IC1 to IC (m / 2) through input capacitance portions Ci to the input portions of the upper amplification portions CA1 to CA (m / 2) (inverted input terminals of the operational amplifier OP), respectively. Connected. In the horizontal pixel non-addition readout mode, as can be understood from FIG. 10, the odd-numbered vertical signal lines V1, V3,. The input units (inversion of the operational amplifier OP) of the lower amplification units CA1 to CA (m / 2) via the input capacitance units Ci of the input capacitance forming units IC1 to IC (m / 2) in the non-addition state) Input terminal).

  In the horizontal pixel non-addition readout mode, as shown in FIG. 11, the upper and lower operation control signals φSTBY1 to φSTBY3 and φSTBY-OB are maintained at a low level, and all the upper and lower amplifiers CA1 to CA1 are operated. CA (m / 2) is maintained in the operating state.

  In the horizontal pixel non-addition readout mode, the vertical scanning circuit 23 sequentially selects one row at a time from the first row to the n-th row under the control of the imaging control unit 4, and each pixel PX in the row to be read , OB signals are output to the vertical signal lines V1 to Vm of the corresponding column.

  As shown in FIG. 10, when odd-numbered rows are to be read, vertical signal lines V2, V4,..., Vm in even-numbered columns are provided with Gr pixels (Gr color filters provided in corresponding columns). The signals of the effective pixels PX and OB pixels OB) are output, and the signals of the R pixels in the corresponding column are output to the vertical signal lines V1, V3,. The Gr pixel signals output to the vertical signal lines V2, V4,..., Vm in the even columns are upper via the upper input capacitance forming units IC1 to IC (m / 2) in the non-addition state shown in FIG. After being amplified by the amplifying units CA1 to CA (m / 2) and then sampled by the upper sampling units CDS1 to CDS (m / 2), the signals of all the sampled Gr pixels are scanned in the upper horizontal direction. The circuit 31 sequentially outputs the output from the output amplifiers APS and APN. The R pixel signals output to the odd-numbered vertical signal lines V1, V3,..., Vm−1 are supplied to the lower input capacitance forming units IC1 to IC (m / 2) in the non-addition state shown in FIG. After being amplified by the lower amplification units CA1 to CA (m / 2) and then sampled by the lower sampling units CDS1 to CDS (m / 2), the signals of all the sampled R pixels Are sequentially output from the output amplifiers APS and APN by the horizontal scanning circuit 31 on the lower side.

  As shown in FIG. 10, when the even-numbered row is to be read, the signals of the B pixels in the corresponding column are output to the vertical signal lines V2, V4,. The signals of the Gb pixels in the corresponding column are output to the odd-numbered vertical signal lines V1, V3,. The B pixel signals output to the vertical signal lines V2, V4,..., Vm in the even columns are upper via the upper input capacitance forming units IC1 to IC (m / 2) in the non-addition state shown in FIG. After being amplified by the amplifying units CA1 to CA (m / 2) and then sampled by the upper sampling units CDS1 to CDS (m / 2), the signals of all the sampled B pixels are scanned in the upper horizontal direction. The circuit 31 sequentially outputs the output from the output amplifiers APS and APN. The Gb pixel signals output to the odd-numbered vertical signal lines V1, V3,..., Vm-1 are input to the lower input capacitance forming units IC1 to IC (m / 2) in the non-addition state shown in FIG. After being amplified by the lower amplification units CA1 to CA (m / 2) and then sampled by the lower sampling units CDS1 to CDS (m / 2), the signals of all the sampled Gb pixels Are sequentially output from the output amplifiers APS and APN by the horizontal scanning circuit 31 on the lower side.

  In this manner, in the horizontal pixel non-addition readout mode, signals of all the pixels PX and OB can be read out without performing horizontal addition.

  In the present embodiment, an operation mode (hereinafter referred to as “horizontal pixel addition mode”) in which the signal of the effective pixel PX is read by adding the horizontal pixel is performed in the electronic viewfinder mode or in moving image shooting. At this time, the first weight (1: 1: 1), the second weight (1: 2: 1), and the third weight (1) according to the setting by the operation unit 9a or predetermined conditions. : 3: 1).

  FIG. 12 is an operation explanatory diagram schematically showing a characteristic operation of the horizontal pixel addition readout mode of the solid-state imaging device 3 shown in FIG. FIG. 13 is a timing chart showing the state of the control signal in the horizontal pixel addition readout mode by weighting 1: 1: 1 of the solid-state imaging device shown in FIG.

  In the horizontal pixel addition readout mode with the weighting ratio of 1: 1: 1, as shown in FIG. 13, the upper and lower control signals φSW and φCS4 to φCS9 are maintained at the low level, while the upper and lower control signals are φCS1 to φCS3 are maintained at a high level. Therefore, the upper effective pixel amplifiers CA1, CA4, CA7,... And the lower effective pixel amplifiers CA3, CA6, CA9,. : Cb: Cc = C1: C2: C3 = 1: 1: 1). Therefore, the weighted addition of the signals of the three vertical signal lines belonging to the same block as the amplifying unit from each of the upper effective pixel amplifying units CA1, CA4, CA7,. Are output, and the signals of the three vertical signal lines belonging to the same block as the amplifying unit are respectively 1: 1: 1 from the lower effective pixel amplifying units CA3, CA6, CA9,. A signal weighted and added by the weight is output. For example, a signal obtained by weighting and adding signals of three vertical signal lines V2, V4, and V6 belonging to the same block as the amplification unit CA1 with a weight of 1: 1: 1 is output from the upper effective pixel amplification unit CA1. The lower effective pixel amplification unit CA3 outputs a signal obtained by weighting and adding signals of three vertical signal lines V5, V7, and V9 belonging to the same block as the amplification unit CA3 with a weight of 1: 1: 1. The On the other hand, the upper and lower OB pixel amplifiers CA (k / 2) +1 to CA (m / 2) are originally fixed in the non-addition state shown in FIG.

  In the horizontal pixel addition readout mode with weighting of 1: 1: 1, as shown in FIG. 13, the upper control signals φSTBY1, φSTBY-OB are maintained at a low level, and the upper φSTBY2, φSTBY3 are maintained at a high level. . Therefore, in the upper signal output circuit 24, only the effective pixel amplifiers CA1, CA4, CA7,... Are maintained in the active state with respect to the effective pixel unit 21A, and the remaining effective pixel amplifiers CA2, CA3, CA5, CA6. , CA8, CA9,... Are kept in a stopped state. The upper OB pixel amplification units CA (k / 2) +1 to CA (m / 2) are maintained in the operating state.

  In the horizontal pixel addition readout mode with a weighting ratio of 1: 1: 1, as shown in FIG. 13, the lower control signals φSTBY3 and φSTBY-OB are maintained at a low level, and the upper φSTBY1 and φSTBY2 are maintained at a high level. The Therefore, in the lower signal output circuit 25, only the effective pixel amplifiers CA3, CA6, CA9,... CA5, CA7, CA8,... Are maintained in an operation stop state. The lower OB pixel amplifying units CA (k / 2) +1 to CA (m / 2) are maintained in the operating state.

  In the horizontal pixel addition readout mode based on the weighting ratio of 1: 1: 1, the vertical scanning circuit 23 selects the readout target one by one from the first row to the n-th row under the control of the imaging control unit 4 and performs readout. The signals of the pixels PX and OB in the target row are output to the corresponding vertical signal lines V1 to Vm.

  As shown in FIG. 12, when the odd-numbered rows are to be read, the vertical signal lines V2, V4,..., Vm in the even-numbered columns are provided with Gr pixels (Gr color filters provided in the corresponding columns). The signals of the effective pixels PX and OB pixels OB) are output, and the signals of the R pixels in the corresponding column are output to the vertical signal lines V1, V3,.

  The Gr pixel signals output to the vertical signal lines V2, V4,..., Vk in the even-numbered columns are in the addition state shown in FIG. By CA7, ..., the signals of three Gr pixels that do not overlap each other are added with a weight of 1: 1: 1. The Gr pixel signals output to the vertical signal lines Vk + 2,..., Vm in the even-numbered columns are in the non-addition state shown in FIG. ) +1 to CA (m / 2). The output signals of the upper amplification units CA1 to CA (m / 2) including these significant signals are sampled by the upper sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the horizontal scanning circuit 31. At this time, the upper horizontal scanning circuit 31 may output all the sampled signals (read all columns), or output from the upper effective pixel amplifiers CA1, CA4, CA7,... Only the signal (addition signal of Gr pixel) and the output signal (non-addition signal of Gr pixel) of the upper OB pixel amplifier CA (k / 2) +1 to CA (m / 2) are selectively output (column selection). Read out). In the former case, unnecessary signals need not be used in the subsequent circuit.

  The R pixel signals output to the odd-numbered vertical signal lines V5, V7,..., Vk−1 are in the addition state shown in FIG. , CA6, CA9,..., Add three R pixel signals that do not overlap each other with a weight of 1: 1: 1. The R pixel signals output to the odd-numbered vertical signal lines Vk + 1,..., Vm−1 are in the non-added state and in the operating state shown in FIG. k / 2) +1 to CA (m / 2). The output signals of the lower amplification units CA1 to CA (m / 2) including these significant signals are sampled by the lower sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the lower horizontal scanning circuit 31. At this time, the lower horizontal scanning circuit 31 may output all the sampled signals (read all columns), or lower effective pixel amplification units CA3, CA6, CA9,... Output signal (addition signal of R pixel) and output signal (a non-addition signal of R pixel) of the lower OB pixel amplifier CA (k / 2) +1 to CA (m / 2) are selectively output. (Column selection read) may be performed. In the former case, unnecessary signals need not be used in the subsequent circuit.

  As shown in FIG. 12, when the even-numbered row is to be read, signals of the B pixels in the corresponding column are output to the vertical signal lines V2, V4,. The signals of the Gb pixels in the corresponding column are output to the odd-numbered vertical signal lines V1, V3,.

  The B pixel signals outputted to the vertical signal lines V2, V4,..., Vk in the even columns are in the addition state shown in FIG. CA7,... Adds three B pixel signals that do not overlap each other with a weight of 1: 1: 1. The B pixel signals output to the vertical signal lines Vk + 2,..., Vm in the even-numbered columns are in the non-addition state shown in FIG. ) +1 to CA (m / 2). The output signals of the upper amplification units CA1 to CA (m / 2) including these significant signals are sampled by the upper sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the horizontal scanning circuit 31. At this time, the upper horizontal scanning circuit 31 may output all the sampled signals (read all columns), or output from the upper effective pixel amplifiers CA1, CA4, CA7,... Only the signal (addition signal of Gr pixel) and the output signal (non-addition signal of B pixel) of the upper OB pixel amplification unit CA (k / 2) +1 to CA (m / 2) are selectively output (column selection) Read out). In the former case, unnecessary signals need not be used in the subsequent circuit.

  The Gb pixel signals output to the odd-numbered vertical signal lines V5, V7,..., Vk−1 are in the addition state shown in FIG. , CA6, CA9,..., Three Gb pixel signals that do not overlap each other are added. The Gb pixel signals output to the odd-numbered vertical signal lines Vk + 1,..., Vm−1 are in the non-addition state and the operating state of the lower OB pixel amplification unit CA ( k / 2) +1 to CA (m / 2). The output signals of the lower amplification units CA1 to CA (m / 2) including these significant signals are sampled by the lower sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the lower horizontal scanning circuit 31. At this time, the lower horizontal scanning circuit 31 may output all the sampled signals (read all columns), or lower effective pixel amplification units CA3, CA6, CA9,... Output signal (Gb pixel addition signal) and the lower OB pixel amplifier CA (k / 2) +1 to CA (m / 2) output signals (Gb pixel addition signal) are selectively output. (Column selection reading) may be performed. In the former case, unnecessary signals need not be used in the subsequent circuit.

  In this way, in the horizontal pixel addition reading mode with the weighting of 1: 1: 1, the signals of the effective pixels PX can be read out by horizontally adding with the weighting of 1: 1: 1, while all the OB pixels OB are read. Can be read out without adding horizontal pixels.

  In order to obtain a final moving image or the like from the signal read out in this manner, for example, the signal processing unit 5 or the image processing unit 13 in FIG. Alternatively, in the above-described example, the vertical scanning circuit 23 reads out one row at a time. However, reading may be performed every three rows and thinned out in the vertical direction. Alternatively, the solid-state imaging device 3 may be configured so that pixels in the vertical direction can be added, and pixel addition reading can be performed in the vertical direction as well. These points are the same in the horizontal pixel addition readout mode by weighting of 1: 2: 1 or 1: 3: 1 described later.

  FIG. 14 is a timing chart showing the state of the control signal in the horizontal pixel addition readout mode with 1: 2: 1 weighting of the solid-state imaging device shown in FIG.

  In the horizontal pixel addition readout mode with 1: 2: 1 weighting, as shown in FIG. 14, the upper and lower control signals φSW, φCS1 to φCS3, φCS7 to φCS9 are maintained at the low level, while the upper and lower control signals are maintained. Side control signals φCS4 to φCS6 are maintained at a high level. Therefore, the upper effective pixel amplifiers CA2, CA5, CA8,... And the lower effective pixel amplifiers CA4, CA7, CA10,. : Cb: Cc = C4: C5: C6 = 1: 2: 1). Therefore, the weighted addition of the signals of the three vertical signal lines belonging to the same block as the amplifying unit from each of the upper effective pixel amplifying units CA2, CA5, CA8,. .., And the signals of the three vertical signal lines belonging to the same block as the amplifying unit are respectively supplied from the lower effective pixel amplifying units CA4, CA7, CA10,. A signal weighted and added by the weight is output. For example, a signal obtained by weighting and adding signals of three vertical signal lines V2, V4, and V6 belonging to the same block as the amplification unit CA2 with a weight of 1: 2: 1 is output from the upper effective pixel amplification unit CA2. The lower effective pixel amplifier CA4 outputs a signal obtained by weighting and adding signals of three vertical signal lines V5, V7, and V9 belonging to the same block as the amplifier CA4 with a weight of 1: 2: 1. The On the other hand, the upper and lower OB pixel amplifiers CA (k / 2) +1 to CA (m / 2) are originally fixed in the non-addition state shown in FIG.

  In the horizontal pixel addition readout mode with 1: 2: 1 weighting, as shown in FIG. 14, the upper control signals φSTBY2, φSTBY-OB are maintained at a low level, and the upper φSTBY1, φSTBY3 are maintained at a high level. . Therefore, in the upper signal output circuit 24, only the effective pixel amplification units CA2, CA5, CA8,... Are maintained in the active state with respect to the effective pixel unit 21A, and the remaining effective pixel amplification units CA1, CA3, CA4, and CA6. , CA7, CA9,... Are kept in a stopped state. The upper OB pixel amplification units CA (k / 2) +1 to CA (m / 2) are maintained in the operating state.

  In the horizontal pixel addition readout mode with 1: 2: 1 weighting, as shown in FIG. 14, the lower control signals φSTBY1 and φSTBY-OB are maintained at a low level, and the upper φSTBY2 and φSTBY3 are maintained at a high level. The Therefore, in the lower signal output circuit 25, only the effective pixel amplifiers CA1, CA4, CA7, CA10,... Are maintained in the active state with respect to the effective pixel unit 21A, and the remaining effective pixel amplifiers CA2, CA3,. CA5, CA6, CA8, CA9,... Are maintained in the operation stop state. The lower OB pixel amplifying units CA (k / 2) +1 to CA (m / 2) are maintained in the operating state.

  In the horizontal pixel addition readout mode with weighting of 1: 2: 1, the vertical scanning circuit 23 sequentially selects one row at a time from the first row to the n-th row under the control of the imaging control unit 4 and performs reading. The signals of the pixels PX and OB in the target row are output to the corresponding vertical signal lines V1 to Vm.

  As shown in FIG. 12, when the odd-numbered rows are to be read, the vertical signal lines V2, V4,..., Vm in the even-numbered columns are provided with Gr pixels (Gr color filters provided in the corresponding columns). The signals of the effective pixels PX and OB pixels OB) are output, and the signals of the R pixels in the corresponding column are output to the vertical signal lines V1, V3,.

  The Gr pixel signals output to the vertical signal lines V2, V4,..., Vk in the even columns are in the addition state shown in FIG. By CA8,..., Signals of three Gr pixels that do not overlap each other are added with a weight of 1: 2: 1. The Gr pixel signals output to the vertical signal lines Vk + 2,..., Vm in the even-numbered columns are in the non-addition state shown in FIG. ) +1 to CA (m / 2). The output signals of the upper amplification units CA1 to CA (m / 2) including these significant signals are sampled by the upper sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the horizontal scanning circuit 31. At this time, the upper horizontal scanning circuit 31 may output all the sampled signals (read all columns), or output from the upper effective pixel amplifiers CA2, CA5, CA8,. Only the signal (addition signal of Gr pixel) and the output signal (non-addition signal of Gr pixel) of the upper OB pixel amplifier CA (k / 2) +1 to CA (m / 2) are selectively output (column selection). Read out). In the former case, unnecessary signals need not be used in the subsequent circuit.

  The R pixel signals output to the odd-numbered vertical signal lines V5, V7,..., Vk−1 are in the addition state shown in FIG. , CA7, CA10,..., The signals of three R pixels that do not overlap each other are added with a weight of 1: 2: 1. The R pixel signals output to the odd-numbered vertical signal lines Vk + 1,..., Vm−1 are in the non-added state and in the operating state shown in FIG. k / 2) +1 to CA (m / 2). The output signals of the lower amplification units CA1 to CA (m / 2) including these significant signals are sampled by the lower sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the lower horizontal scanning circuit 31. At this time, the lower horizontal scanning circuit 31 may output all the sampled signals (read all columns), or lower effective pixel amplification units CA4, CA7, CA10,... Output signal (addition signal of R pixel) and output signal (a non-addition signal of R pixel) of the lower OB pixel amplifier CA (k / 2) +1 to CA (m / 2) are selectively output. (Column selection read) may be performed. In the former case, unnecessary signals need not be used in the subsequent circuit.

  As shown in FIG. 12, when the even-numbered row is to be read, signals of the B pixels in the corresponding column are output to the vertical signal lines V2, V4,. The signals of the Gb pixels in the corresponding column are output to the odd-numbered vertical signal lines V1, V3,.

  The B pixel signals output to the vertical signal lines V2, V4,..., Vk in the even columns are in the addition state shown in FIG. By CA8,..., Three B pixel signals that do not overlap each other are added with a weight of 1: 2: 1. The B pixel signals output to the vertical signal lines Vk + 2,..., Vm in the even-numbered columns are in the non-addition state shown in FIG. ) +1 to CA (m / 2). The output signals of the upper amplification units CA1 to CA (m / 2) including these significant signals are sampled by the upper sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the horizontal scanning circuit 31. At this time, the upper horizontal scanning circuit 31 may output all the sampled signals (read all columns), or output from the upper effective pixel amplifiers CA2, CA5, CA8,. Only the signal (addition signal of Gr pixel) and the output signal (non-addition signal of B pixel) of the upper OB pixel amplification unit CA (k / 2) +1 to CA (m / 2) are selectively output (column selection) Read out). In the former case, unnecessary signals need not be used in the subsequent circuit.

  The Gb pixel signals output to the odd-numbered vertical signal lines V5, V7,..., Vk−1 are in the addition state shown in FIG. , CA7, CA10,..., Three Gb pixel signals that do not overlap each other are added. The Gb pixel signals output to the odd-numbered vertical signal lines Vk + 1,..., Vm−1 are in the non-addition state and the operating state of the lower OB pixel amplification unit CA ( k / 2) +1 to CA (m / 2). The output signals of the lower amplification units CA1 to CA (m / 2) including these significant signals are sampled by the lower sampling units CDS1 to CDS (m / 2), and then the sampled signals are The signals are sequentially output from the output amplifiers APS and APN by the lower horizontal scanning circuit 31. At this time, the lower horizontal scanning circuit 31 may output all the sampled signals (read all columns), or lower effective pixel amplification units CA4, CA7, CA10,... Output signal (Gb pixel addition signal) and the lower OB pixel amplifier CA (k / 2) +1 to CA (m / 2) output signals (Gb pixel addition signal) are selectively output. (Column selection reading) may be performed. In the former case, unnecessary signals need not be used in the subsequent circuit.

  In this manner, in the horizontal pixel addition reading mode with the weighting of 1: 2: 1, the signal of the effective pixel PX can be read out by horizontally adding with the weighting of 1: 2: 1, while all the OB pixels OB are read. Can be read out without adding horizontal pixels.

  FIG. 15 is a timing chart showing the state of the control signal in the horizontal pixel addition readout mode with 1: 3: 1 weighting of the solid-state imaging device shown in FIG.

  In the horizontal pixel addition readout mode with 1: 3: 1 weighting, as shown in FIG. 15, the upper and lower control signals φSW and φCS1 to φCS6 are maintained at a low level, while the upper and lower control signals are φCS7 to φCS9 are maintained at a high level. Therefore, the upper effective pixel amplifiers CA3, CA4, CA9,... And the lower effective pixel amplifiers CA5, CA8, CA11,. : Cb: Cc = C7: C8: C9 = 1: 3: 1). Therefore, the weighted addition of the signals of the three vertical signal lines belonging to the same block as the amplifying unit from each of the upper effective pixel amplifying units CA2, CA5, CA8,. .. Are output, and the signals of the three vertical signal lines belonging to the same block as the amplifying unit from each of the lower effective pixel amplifying units CA5, CA8, CA11,. A signal weighted and added by the weight is output. For example, a signal obtained by weighting and adding signals of three vertical signal lines V2, V4, and V6 belonging to the same block as the amplification unit CA3 with a weight of 1: 3: 1 is output from the upper effective pixel amplification unit CA3. The lower effective pixel amplifier CA5 outputs a signal obtained by weighting and adding the signals of the three vertical signal lines V5, V7, and V9 belonging to the same block as the amplifier CA5 with a weight of 1: 3: 1. The On the other hand, the upper and lower OB pixel amplifiers CA (k / 2) +1 to CA (m / 2) are originally fixed in the non-addition state shown in FIG.

  In the horizontal pixel addition readout mode with 1: 3: 1 weighting, as shown in FIG. 15, the upper control signals φSTBY3 and φSTBY-OB are maintained at a low level, and the upper φSTBY1 and φSTBY2 are maintained at a high level. . Therefore, in the upper signal output circuit 24, only the effective pixel amplifiers CA3, CA6, CA9,... Are maintained in the active state with respect to the effective pixel unit 21A, and the remaining effective pixel amplifiers CA1, CA2, CA4, CA5. , CA7, CA8,... Are kept in a stopped state. The upper OB pixel amplification units CA (k / 2) +1 to CA (m / 2) are maintained in the operating state.

  In the horizontal pixel addition readout mode with 1: 3: 1 weighting, as shown in FIG. 15, the lower control signals φSTBY3 and φSTBY-OB are maintained at a low level, and the upper φSTBY1 and φSTBY2 are maintained at a high level. The Therefore, in the lower signal output circuit 25, only the effective pixel amplifiers CA2, CA5, CA8, CA11,... Are maintained in the activated state with respect to the effective pixel unit 21A, and the remaining effective pixel amplifiers CA1, CA3,. CA4, CA6, CA7, CA9,... Are maintained in the operation stop state. The lower OB pixel amplifying units CA (k / 2) +1 to CA (m / 2) are maintained in the operating state.

  In the horizontal pixel addition readout mode with weighting of 1: 3: 1, the signal of the effective pixel PX is 1: 2 by an operation according to the operation of the horizontal pixel addition readout mode with weighting of 1: 1: 1 or 1: 2: 1. While it is possible to perform horizontal addition with a weighting of 3: 1 and read out, signals of all OB pixels OB can be read out without performing horizontal pixel addition.

  According to the present embodiment, as described above, the signals in the horizontal direction can be weighted and added inside the solid-state imaging device 3, and the weights are 1: 1: 1, 1: 2: 1, 1: It can be changed to three types of 3: 1. Further, according to this embodiment, as described above, the horizontal pixel addition readout mode can also be performed.

  In this embodiment, the ratio of the input capacitance units Ca, Cb, and Cc of one input capacitance forming unit IC is switched to three types of 1: 1: 1, 1: 2: 1, and 1: 3: 1. Rather than being configured as described above, another input capacitance forming unit IC is set so that the ratio of the input capacitance units Ca, Cb, Cc of one input capacitance forming unit IC is 1: 1: 1. The ratio of the input capacitance units Ca, Cb, and Cc of the other input capacitance forming unit IC is 1: 3 so that the ratio of the input capacitance units Ca, Cb, and Cc is 1: 2: 1. : 1 and one input capacitance forming unit IC is responsible for only one capacitance ratio. Therefore, according to the present embodiment, the ratio of the input capacitance units Ca, Cb, and Cc of each input capacitance forming unit IC is switched to three types of 1: 1: 1, 1: 2: 1, and 1: 3: 1. Compared to the case of being configured, the number of capacities and the occupied area of each input capacitance forming unit IC can be reduced.

  In addition, according to the present embodiment, in the horizontal pixel addition readout mode, the amplifying unit that is not involved in processing of necessary signals is maintained in the operation stop state with low power consumption, so that the power consumption can be reduced. it can.

[Second Embodiment]
FIG. 16 is a circuit diagram showing a part of the upper signal output circuit 24 of the solid-state imaging device used in the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. 16, elements that are the same as or correspond to the elements in FIG. 4 are given the same reference numerals, and redundant descriptions thereof are omitted. This embodiment is different from the first embodiment in the points described below.

  In this embodiment, in the first embodiment, the upper effective pixel amplifiers CA3, CA6, CA9,... And the lower upper effective pixel amplifiers CA2, CA5, CA8,. .., Except that the switches SW5, SW6, CS7, and CS9 are removed, and the points connected by the switches SW5 and SW6 in the on state are connected by wiring. The capacitors C7 to C9 may be one capacitor corresponding to their combined capacity. In this case, the horizontal pixel addition readout mode with 1: 3: 1 weighting cannot be performed, but the horizontal pixel non-addition readout mode, the horizontal pixel addition readout mode with 1: 1: 1 weighting, and 1: The horizontal pixel addition readout mode with 2: 1 weighting can be performed.

  The first embodiment is an example in which q = p = 3 in the solid-state imaging device according to the first aspect described above, whereas this embodiment is a solid-state imaging element according to the first aspect described above. In this example, q = 2 and p = 3. In the present embodiment, the q (= 2) amplification units in the first aspect described above correspond to, for example, the two amplification units CA1 and CA3 in FIG.

[Second Embodiment]
FIG. 17 is a circuit diagram showing a part of the upper signal output circuit 24 of the solid-state imaging device used in the electronic camera according to the third embodiment of the present invention, and corresponds to FIG. 17, elements that are the same as or correspond to those in FIG. 4 are given the same reference numerals, and redundant descriptions thereof are omitted. This embodiment is different from the first embodiment in the points described below.

  In the present embodiment, in each of the input capacitance forming units IC3, IC6, IC9,... Of the upper signal output circuit 24, one electrode is connected to the inverting input terminal of the operational amplifier OP of the corresponding amplifier CA3. p capacitors (three in this embodiment) C10, C11, C12, and p capacitors (three in this embodiment) belonging to the same block as the other electrode of the capacitors C10, C11, C12 and the input capacitor forming portion. ) Input switches CS10, CS11, and CS12 (three in this embodiment) that are turned on and off between the vertical signal lines are added. For example, in the block shown in FIG. 4, in the input capacitance forming unit IC3, three capacitors C10, C11, C12 having one electrode connected to the inverting input terminal of the operational amplifier OP of the corresponding amplifier unit CA3, and the capacitor C12 , C13, C14, and three input switches CS10, CS11, CS12 for turning on and off between the other electrode and the three vertical signal lines V2, V4, V6, respectively. In the present embodiment, the input switches CS10, CS11, CS12 are set so as to satisfy C10 + C11 + C12 = C0 and C10: C11: C12 = 1: 4: 1. The input switches CS10, CS11, CS12 are composed of, for example, nMOS transistors, and the gates of the input switches CS10, CS11, CS12 are connected in common, and a control signal φ7 is supplied from the imaging control unit 4 thereto. The input switches CS10 to CS12 are turned on when the control signal φ7 supplied to the gate is at a high level (H), and turned off when the control signal φ7 supplied to the gate is at a low level (L).

  In the present embodiment, similarly, in each of the input capacitance forming units IC2, IC5, IC8,... Of the lower signal output circuit 25, capacitors C10, C11, C12 and input switches CS10, CS11, CS12 are provided. Have been added.

  According to the present embodiment, horizontal pixel non-addition readout mode, horizontal pixel addition readout mode with weighting of 1: 1: 1, horizontal pixel addition readout mode with weighting of 1: 2: 1, and 1: 3: 1. In addition to the horizontal pixel addition readout mode by weighting, horizontal pixel addition readout mode by weighting 1: 4: 1 can be performed. Among these modes, in modes other than the horizontal pixel addition readout mode with weighting of 1: 4: 1, the upper and lower control signals φ7 are maintained at a low level except for the first embodiment. The same operation as in each mode is performed.

  FIG. 18 is a timing chart showing the state of the control signal in the horizontal pixel addition readout mode with weighting of 1: 4: 1 in the present embodiment. FIG. 18 differs from FIG. 15 which shows the horizontal pixel addition readout mode with 1: 3: 1 weighting in the first embodiment, in that the upper and lower control signals φ5 and φ6 are maintained at a low level. The upper and lower control signals φ7 are only maintained at a high level.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained.

  For example, in the present embodiment, the input capacitance forming units IC3, IC6, IC9,... Of the upper signal output circuit 24 and the input capacitance forming units IC2, IC5, IC8,. In each of these, three capacitors corresponding to the capacitors C10 to C12 (the capacity ratio thereof may be determined as appropriate) and three input switches corresponding to CS10 to CS12 may be further added. For example, in the present embodiment, the input capacitance forming units IC2, IC5, IC8,... Of the upper signal output circuit 24 and the input capacitance forming units IC1, IC4, IC7,. In each of these, three capacitors corresponding to the capacitors C10 to C12 (the capacity ratio thereof may be determined as appropriate) and three input switches corresponding to CS10 to CS12 may be added. In this case, weighted addition can be realized with other types of weights.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, p may be an arbitrary number of 2 or more. For example, p is not limited to horizontal 3-pixel addition, and may be horizontal 2-pixel addition, horizontal 4-pixel addition, horizontal 5-pixel addition,. However, it is preferable that p is an odd number.

  Further, for example, the solid-state imaging device of each of the above embodiments is an example in which the color arrangement of the color filter is a Bayer arrangement. However, in the present invention, the color arrangement of the color filter is not limited to the Bayer arrangement. The present invention includes a solid-state imaging device having a color filter of another color arrangement having a repetition period of 2 rows and 2 columns (for example, a complementary color filter using magenta, green, cyan, and yellow), and a color filter. It can also be applied to a so-called black and white solid-state image sensor.

  In each of the above embodiments, the configuration in which the solid-state imaging device outputs APS and APN as analog signals in a horizontal scanning circuit has been described. However, the image pickup device of the present invention may be a digital output as a column ADC system in which an AD converter is disposed in each of the amplification units CA.

  Furthermore, the solid-state imaging device according to the present invention may be constituted by a single semiconductor chip or a plurality of semiconductor chips. In the latter case, for example, the pixel unit 21, the upper signal output circuit 24, and the lower signal output circuit 25 may be mounted on different semiconductor chips.

DESCRIPTION OF SYMBOLS 1 Electronic camera 21 Pixel part 21A Effective pixel part 21B OB pixel part PX Effective pixel OB OB pixel IC Input capacitance formation part IC
Ca, Cb, Cc, Ci Input Capacitor CA1-CA (m / 2) Amplifier V1-Vm Vertical Signal Line C1-C9 Capacitor CS1-CS9 Input Switch SW1-SW6 Switch

Claims (13)

A pixel portion having a plurality of pixels arranged two-dimensionally;
A plurality of vertical signal lines provided for each column of the plurality of pixels and receiving signals from the pixels of the corresponding column;
Q amplifying units (q is an integer of 2 or more) having input units;
One set is provided for each of the q amplifying units, and each set includes p sets (p is an integer of 2 or more), and one electrode is connected to the input unit of the corresponding amplifying unit. Q sets of capacitances, and a ratio of capacitance values of at least one set of p capacitors is different from a ratio of capacitance values of at least one other set of p capacitances;
Q sets of switches provided in a one-to-one relationship with the q sets of capacitors, each of which consists of p sets, and the other electrode of the corresponding set of p capacitors and the plurality of vertical signal lines Q sets of switches for turning on / off each of the p vertical signal lines common to each of the q sets of switches;
A solid-state imaging device comprising:   Switching means provided corresponding to each of the q sets of capacitors is provided, and each of the switching means is electrically connected between the other electrodes of the corresponding number of p capacitors according to a control signal. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is switched between a connected state and a state in which they are electrically separated from each other.   Corresponding to at least one amplifying unit among the q amplifying units, a plurality of sets of the p capacitors and the p switches are provided, and the p capacitors between the plurality of sets. The solid-state imaging device according to claim 1, wherein the ratios of the capacitance values are different from each other.   4. The solid-state imaging device according to claim 1, wherein a total capacitance value for each set of the p capacitors in each set is the same. 5. A pixel portion having a plurality of pixels arranged two-dimensionally;
A plurality of vertical signal lines provided for each column of the plurality of pixels and receiving signals from the pixels of the corresponding column;
Q amplifying units (q is an integer of 2 or more) having input units;
Q input capacitance forming units provided corresponding to the q amplifying units, respectively, wherein each of the input capacitance forming units corresponds to the input unit of the corresponding amplifying unit and the input unit according to a control signal. P input capacitance units connected to p vertical signal lines (p is an integer of 2 or more) common to the q amplification units among a plurality of vertical signal lines. And the ratio of the capacitance values of the p input capacitance units formed by the input capacitance formation unit corresponding to at least one of the q amplification units is the q amplification units. Q input capacitance forming units different from a ratio of capacitance values of the p input capacitance units formed by the input capacitance forming unit corresponding to at least one other amplification unit;
A solid-state imaging device comprising:   The input capacitance forming unit corresponding to at least one of the q amplifying units is a ratio of capacitance values of the p input capacitance units formed by the input capacitance forming unit according to a control signal. The solid-state imaging device according to claim 5, wherein the solid-state imaging device is configured to switch between two or more types.   7. The solid-state imaging device according to claim 5, wherein the total of the capacitance values of the p input capacitance units formed by the input capacitance formation units is the same as each other.   Each of the q input capacitance forming units is connected to the input unit of the corresponding amplifying unit and the q amplifying units among the plurality of vertical signal lines according to a control signal. A first input capacitance forming state for forming the p input capacitance portions, each being connected between the vertical signal lines, and the corresponding input portion and the p vertical signal lines of the amplifying portion. Switching to a second input capacitance formation state in which one input capacitance portion is formed in a state of being connected to only one vertical signal line that is different for each amplification portion. The solid-state imaging device according to claim 5.   In the first input capacitance formation state, a control unit that controls to selectively read out an output signal of one amplification unit selected by a control signal among the q amplification units is provided. The solid-state imaging device according to claim 8. In addition to the plurality of pixels, the pixel unit is two-dimensionally arranged in one or both sides in a row direction with respect to a region where the plurality of pixels are arranged, and generates a black level signal. Optical black pixels,
A plurality of optical black pixel vertical signal lines that are provided for each column of the plurality of optical black pixels and receive signals from the corresponding optical black pixels, and signals of the plurality of optical black pixel vertical signal lines, respectively. A plurality of optical black pixel amplifying units that output the output signal,
In any of the first and second input capacitance formation states, signals from optical black pixels in different columns can be obtained from the plurality of optical black pixel amplifying units.
The solid-state imaging device according to claim 8 or 9,   Each of the q amplifiers includes an operational amplifier having a first input terminal serving as the input unit and a second input terminal to which a predetermined potential is applied, and the first input terminal and the operational amplifier. 11. A column amplifier reset switch for turning on / off between the output terminal and a feedback capacitor connected between the first input terminal and the output terminal. The solid-state image sensor described in 1. A plurality of color filters provided corresponding to each of the plurality of pixels and having a predetermined color arrangement;
The p vertical signal lines receive a signal from a pixel provided with a color filter of the same color.
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided.   An image pickup apparatus comprising the solid-state image pickup device according to claim 1.

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