JP6097808B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In recent years, thin film transistors (TFTs) using oxide semiconductor layers
Is known (see Patent Document 1 below). Specifically, the thin film transistor disclosed in Patent Document 1 includes a gate electrode layer, a gate insulating layer disposed over the gate electrode, an oxide semiconductor layer disposed over the gate insulating layer, and the oxide semiconductor. A source and drain electrode layer is provided on the layer. In order to improve the mobility of the thin film transistor and suppress increase in off-state current, the thin film transistor includes a plurality of conductive oxide clusters over the gate insulating layer.

JP 2010-171406 A

Here, in general, in a thin film transistor using an oxide semiconductor as described above, water vapor annealing is performed after the formation of the thin film transistor. Thus, oxygen atoms or the like (for example, O or OH) diffuse into the oxide semiconductor, and characteristics such as mobility of the thin film transistor can be improved.

However, in the above thin film transistor, it is difficult to diffuse oxygen atoms and the like sufficiently and uniformly in the oxide semiconductor. Further, in order to sufficiently diffuse oxygen atoms or the like in the oxide semiconductor, it is necessary to perform the water vapor annealing at a high temperature for a long time.

In view of the above problems, the present invention provides a semiconductor device having a thin film transistor using an oxide semiconductor in a semiconductor layer, in which oxygen atoms and the like are diffused more sufficiently and uniformly in the oxide semiconductor, and the characteristics of the thin film transistor are further improved. An object of the present invention is to realize a semiconductor device that can be manufactured or a method for manufacturing the semiconductor device.

(1) A semiconductor device of the present invention includes a gate electrode, a gate insulating film disposed so as to cover one surface of the gate electrode, an oxide semiconductor disposed over the gate insulating film, and the oxidation A source electrode and a drain electrode arranged to overlap with a physical semiconductor; and an oxygen atom-containing film arranged so as to be in contact with the oxide semiconductor between the source electrode and the drain electrode and the gate insulating film layer; Have

(2) In the semiconductor device according to (1), the oxide semiconductor includes a first oxide semiconductor layer and a second oxide semiconductor layer, and the oxygen atom-containing film includes the first oxide semiconductor layer. The oxide semiconductor layer is disposed between the oxide semiconductor layer and the second oxide semiconductor layer.

(3) In the semiconductor device according to (1) or (2), the oxygen atom-containing film includes:
It is a moisture-containing film containing moisture.

(4) In the semiconductor device according to (3), a moisture concentration of the moisture-containing film is higher than a moisture concentration contained in the oxide semiconductor.

(5) In the semiconductor device according to (3) or (4), the moisture concentration of the moisture-containing film is 1 atm% to 30 atm%.

(6) In the semiconductor device according to any one of (1) to (5), the oxygen atom-containing film is provided between 20% and 80% of the thickness of the oxide semiconductor. To do.

(7) In the semiconductor device according to any one of (1) to (6), the oxygen atom-containing film is a discontinuous film.

(8) In the semiconductor device according to any one of (1) to (7), the oxide semiconductor has a thickness of 5 nm to 200 nm.

(9) In the semiconductor device according to any one of (1) to (8), a material of the first oxide semiconductor layer is different from a material of the second oxide semiconductor layer. .

(10) In the method for manufacturing a semiconductor device of the present invention, at least a first electrode layer is formed on a substrate, and an oxide semiconductor layer and an oxygen atom-containing film are formed on the substrate on which the at least first electrode layer is formed. A channel layer is formed, and at least a second electrode layer is formed on the substrate on which the channel layer is formed, and oxygen atoms contained in the oxygen atom-containing film are diffused into the oxide semiconductor layer. And

(11) In the semiconductor device according to (10), the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, and the substrate on which the first electrode layer is formed. Forming at least the first oxide semiconductor layer, forming the oxygen atom-containing film on the first oxide semiconductor layer, and forming the second oxide semiconductor on the oxygen atom-containing film. Forming a layer,
Thus, the channel layer is formed.

It is the schematic which shows the display apparatus in the 1st Embodiment of this invention. It is a conceptual diagram of the pixel circuit formed on the TFT substrate shown in FIG. FIG. 3 is a diagram for explaining a configuration of a TFT shown in FIG. 2. FIG. 3 is a diagram for explaining a configuration of a cross section of the TFT shown in FIG. 2. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 1st Embodiment. It is a figure for demonstrating the flow of the manufacturing method in 1st Embodiment. It is a figure for demonstrating the structure of the cross section of TFT in the 2nd Embodiment of this invention. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure which shows the cross-section in each step of the flow of the manufacturing method in 2nd Embodiment. It is a figure for demonstrating the flow of the manufacturing method in 2nd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings. In addition, about drawing, the same code | symbol is attached | subjected to the same or equivalent element, and the overlapping description is abbreviate | omitted.

FIG. 1 is a schematic view showing a display device according to an embodiment of the present invention. As shown in FIG.
For example, the display device 100 includes a TFT substrate 102 on which a TFT or the like (not shown) is formed, and a filter substrate 1 on which the color filter (not shown) is provided so as to face the TFT substrate 102.
01. The display device 100 includes a liquid crystal material (not shown) sealed in a region sandwiched between the TFT substrate 102 and the filter substrate 101, and the filter substrate 10 of the TFT substrate 102.
The backlight 103 is located in contact with the side opposite to the first side.

FIG. 2 is a conceptual diagram of a pixel circuit formed on the TFT substrate shown in FIG. As shown in FIG. 2, the TFT substrate 102 includes a plurality of gate signal lines 1 arranged at substantially equal intervals in the horizontal direction of FIG.
05 and a plurality of video signal lines 107 arranged at substantially equal intervals in the vertical direction of FIG. The gate signal line 105 is connected to the shift register circuit 104, and the video signal line 107 is connected to the driver 106.

The shift register circuit 104 includes a plurality of basic circuits (not shown) corresponding to the plurality of gate signal lines 105, respectively. Note that each basic circuit includes a plurality of TFTs, capacitors, and the like, and in accordance with a control signal 115 from the driver 106, the basic circuit is high during a corresponding gate scanning period (signal high period) in one frame period. A gate signal that becomes a voltage and becomes a low voltage during the other period (signal low period) is output to the corresponding gate signal line 105.

Each pixel region 130 partitioned in a matrix by the gate signal line 105 and the video signal line 107 includes a TFT 109, a pixel electrode 110, and a common electrode 111, respectively. Here, the gate of the TFT 109 is connected to the gate signal line 105, one of the source and the drain is connected to the video signal line 107, and the other is connected to the pixel electrode 110. The common electrode 111 is connected to the common signal line 108. Note that the pixel electrode 110 and the common electrode 111 face each other.

Next, the operation of the pixel circuit configured as described above will be described. The driver 106
A reference voltage is applied to the common electrode 111 via the common signal line 108. The shift register circuit 104 controlled by the driver 106 is connected via the gate signal line 105.
A gate signal is output to the gate electrode of the TFT 109. Further, the driver 106 supplies the voltage of the video signal to the TFT 109 to which the gate signal is output via the video signal line 107, and the voltage of the video signal is further applied to the pixel electrode 110 via the TFT 109. To do. At this time, a potential difference is generated between the pixel electrode 110 and the common electrode 111.

The driver 106 controls the potential difference generated between the pixel electrode 110 and the common electrode 111, thereby controlling the light distribution of the liquid crystal molecules of the liquid crystal material inserted between the pixel electrode 110 and the common electrode 111. Here, since the light from the backlight 103 is guided to the liquid crystal material, the amount of light from the backlight 103 can be adjusted by controlling the light distribution of the liquid crystal molecules as described above. As a result, an image can be displayed.

FIG. 3 is a diagram for explaining the configuration of the TFT shown in FIG. Specifically, FIG. 3 shows a part of the upper surface around the TFT 109 of the TFT substrate 102 shown in FIG. Note that the structure shown in the TFT shown in FIG. 3 is an example, and the present invention is not limited to this. For example, FIG. 3 shows an example of the structure of a so-called bottom gate type TFT, but it may have a structure of a so-called top gate type TFT as will be described later.

As shown in FIG. 3, when viewed from above, the TFT substrate 102 is provided with a gate electrode 402 extending from the gate signal line 105. Further, the source electrode 405 and the drain electrode 4 are extended from the video signal line 107 and overlap with a part of the gate electrode 402.
06 is provided. Further, a drain electrode 406 and a source electrode 405 are provided so as to overlap a part of the pixel electrode 110 provided adjacent to the gate signal line 105 and the video signal line 107 and a part of the gate electrode 402. Needless to say, each TFT 109 includes the gate electrode 402, the source electrode 405, and the drain electrode 406.

FIG. 4 is a diagram for explaining a cross-sectional configuration of the TFT in this embodiment.
As shown in FIG. 4, the TFT 109 includes a glass substrate 401, a gate electrode 402, a gate insulating film 403, a stacked channel 404, a source electrode 405, and a drain electrode 406 in order from the bottom in the figure.

The stacked channel 404 includes oxide semiconductors 407 and 409 and a moisture-containing film 408. Here, the oxide semiconductors 407 and 409 are, for example, lower oxide semiconductors 40 as shown in FIG.
7 and an upper oxide semiconductor 409, and a moisture-containing film 408 is disposed between the lower oxide semiconductor 407 and the upper oxide semiconductor 409 so as to be in contact with the oxide semiconductors 407 and 409. Note that the case where the moisture-containing film 408 is disposed between the lower oxide semiconductor 407 and the upper oxide semiconductor 409 has been described above; however, the moisture-containing film 408 is disposed so as to be in contact with the single layer oxide semiconductor. Also good. Specifically, for example, the moisture-containing film 408 is formed between the single-layer oxide semiconductor and the gate insulating film 403 or between the source electrode 405 and the drain electrode 406 and the single-layer oxide semiconductor. You may arrange | position between.

The moisture-containing film 408 is preferably disposed between 20% and 80% of the thickness of the oxide semiconductor (the sum of the lower oxide semiconductor 407 and the upper oxide semiconductor 409). Further, at least the moisture-containing film 408 before annealing described later may be a film containing moisture, or O
It may be an O atom-containing film or an OH atom-containing film containing atoms or OH atoms. As the material of the moisture-containing film 408, for example, a silicon oxide (SiO) film, silicon nitride (
An SiN) film, a silicon oxynitride (SiON) film, or the like is used. In addition, the moisture-containing film 408
For example, an insulating film, a semi-metal film, a metal film, or the like may be used.

In addition, the concentration of moisture, O atoms, or the like in the moisture-containing film 408 depends on the oxide semiconductors 407 and 409.
Higher than the moisture and O atom concentrations. Specifically, for example, the concentration of the moisture-containing film 408 may be 1 atm% to 30 atm%. Furthermore, as will be described later, the film thickness of the moisture-containing film 408 is preferably 2 nm or less, for example. Further, the moisture-containing film 408 does not need to be provided as a continuous continuous film as illustrated in FIG. 4 and may be provided discontinuously on the lower oxide semiconductor 407 or the like.

The thickness of the oxide semiconductor (the sum of the lower oxide semiconductor 407 and the upper oxide semiconductor 409) is preferably 5 nm to 200 nm, for example. Note that in the case where the oxide semiconductor is formed as a single layer as described above, the thickness of the oxide semiconductor may be, for example, 5 nm to 200 nm. Note that the upper oxide semiconductor 409 and the lower oxide semiconductor 407 may be formed using the same material or different materials. As a material of the oxide semiconductors 407 and 409, for example, an amorphous or crystalline oxide semiconductor containing In—Ga—Zn—O or at least one element of In, Ga, Zn, and Sn as described later is used. Is used.

As the gate electrode 402, for example, Mo, W, Al, Cu, Cu—Al alloy,
For example, a silicon oxide film (SiO) or a silicon nitride film (SiN) may be used as the single layer of a low resistance metal such as an Al—Si alloy or Mo—W alloy, or a laminated structure thereof, or the gate insulating film 403.
), A single layer of an insulating film such as a silicon oxynitride film (SiON), or a laminated structure thereof. Also, source / drain electrodes 405 and 406 (source or drain electrodes 405 and 40
6 includes, for example, a single layer of a low-resistance metal such as Mo, W, Al, Cu, Cu—Al alloy, Al—Si alloy, or Mo—W alloy, or a laminate thereof. Construction)
Is used.

Next, a manufacturing method of the TFT in this embodiment will be described with reference to FIGS. Here, FIG. 5A thru | or G are figures which show the cross-section of TFT in each step of the flow of the said manufacturing method. FIG. 6 is a diagram for explaining the flow of the manufacturing method in the present embodiment.

As shown in FIG. 5A, first, a gate electrode layer for forming a gate electrode 402, for example, Al, about 300 nm, and Mo, about 50 nm are formed on a glass substrate 401 by using a sputtering apparatus. In addition, the gate electrode 402 is formed by processing the gate electrode layer into an island shape by known photolithography and wet etching or dry etching (see FIG.
S101). In addition to the above, the gate electrode layer includes Mo, W, Al, Cu, and Cu-Al.
A single layer of a low-resistance metal such as an alloy, an Al—Si alloy, or a Mo—W alloy may be used, or a laminated structure of these may be used.

Next, as shown in FIG. 5B, for example, a silicon oxide film (S
iO) is deposited by a plasma enhanced chemical vapor deposition (PECVD) apparatus at a film forming temperature of 350 ° C., using SiH 4 and N 2 O as the film forming gas (S102). Note that the gate insulating film 403 may be a single layer of an insulating film such as a silicon oxide film (SiO), a silicon nitride film (SiN), or a silicon oxynitride film (SiON), or a stacked structure thereof.

Next, as shown in FIGS. 5C and 5D, the lower oxide semiconductor 407, the moisture-containing film 408,
A stacked channel 404 including the upper oxide semiconductor 409 is formed. For the lower and upper oxide semiconductors 407 and 409, for example, an oxide of In—Ga—Zn—O is used.

Specifically, first, for example, as shown in FIG.
Using n2Ga2ZnO7, oxygen is added to Ar gas, and the oxide of In—Ga—Zn—O is formed to a thickness of 25 nm, thereby forming the lower oxide semiconductor 407 (S103).
Then, using a PECVD apparatus, a moisture-containing film 408 is formed to a thickness of about 1 nm using TEOS and O2 as the deposition gas at a temperature of 400 ° C. (S104). Next, as shown in FIG. 5D, in a DC sputtering apparatus, In 2 Ga 2 ZnO 7 is used as a target material, oxygen is added to Ar gas, and In
An upper oxide semiconductor 409 is formed by depositing an oxide of -Ga-Zn-O (IGZO) to a thickness of 25 nm (S105).

Note that the material of the oxide semiconductors 407 and 409 is an amorphous or crystalline oxide semiconductor containing at least one element of In, Ga, Zn, and Sn in addition to the In—Ga—Zn—O. Also good. Specifically, for example, In—Ga—Zn oxide, In—G
a oxide, In—Zn oxide, In—Sn oxide, Zn—Ga oxide, Zn oxide, or the like may be used. The lower layer and upper layer oxide semiconductors 407 and 409 may use the same material, or may use different materials such as IGZO as the lower layer oxide semiconductor 407 and ITO as the upper layer oxide semiconductor 409.

Here, the TEOS film of the moisture-containing film 408 is originally an insulating film, but if the film thickness is about 2 nm or less, the current flowing through the moisture-containing film flows as a tunnel current and does not affect the on-current. . On the other hand, if it is about 2 nm or more, it functions as an insulating film, and the on-current is drastically reduced. For this reason, the TEOS film of the moisture-containing film 408 is formed to be about 2 nm or less.

When a TEOS film of about 2 nm or less is formed, it may be difficult to form a uniform film. Therefore, the TEOS film may be formed in an island shape, and the other portions may not be formed. . In this case, SiO, Si, O 2, OH which is a residue of the film forming gas also in the portion where the film is not formed
Etc. remain. O2 and OH of the residue are diffused into the IGZO film by an annealing process to be described later, and the IGZO film is terminated with oxygen, which can contribute to improvement of on-current. Therefore, the moisture-containing film 408
May be in the form of islands.

Next, as shown in FIG. 5E, a laminated channel 404 is formed by processing into an island shape by well-known photolithography, wet etching, or dry etching (S106).
).

Next, as shown in FIG. 5F, a laminated structure (source / drain electrode layer) of Ti 50 nm / Al 400 nm / Ti 50 nm for forming the source / drain electrodes 405 and 406 (including wiring) is formed by a sputtering apparatus (S107). The source / drain electrode layers are Mo, W,
A single layer of a low resistance metal such as Al, Cu, Cu—Al alloy, Al—Si alloy, or Mo—W alloy, or a laminated structure thereof may be used.

Next, as shown in FIG. 5G, the source / drain electrode layer is processed into a predetermined shape to form a source electrode 405, a drain electrode 406, and wiring portions thereof (S108). In addition,
The shape shown in FIG. 5G is an example, and the present invention is not limited to this.

Next, for example, a silicon oxide film to be a passivation film (not shown) is formed by PECVD.
Depending on the apparatus, the film forming temperature is about 250 ° C., and SiH 4 and N 2 O are used as the film forming gas.
m. Note that the passivation film may be an insulating film such as a silicon nitride (SiN) film, a silicon nitride oxide (SiON) film, and other metal oxide films. Further, as the film forming method, other sputtering, vapor deposition, or the like may be used.

Finally, annealing is performed for about 1 hour in a nitrogen atmosphere at about 300 ° C. (S110). Accordingly, moisture in the moisture-containing film 408 can be diffused into the IGZO film, and the In—Ga—Zn—O oxide can be terminated with oxygen. As a result, the on-current of the TFT 109 can be improved. Note that although the case where the annealing process is performed last is described above, the annealing may be performed at a different stage as long as it is performed after the formation of the upper oxide semiconductor 409 (S105).

According to this embodiment, since the moisture-containing film 408 functions as a storage layer for oxygen, moisture, or the like, the oxide semiconductor 40 is subjected to annealing treatment during the formation of the moisture-containing film 408 or after the TFT 109 is formed.
7 and 409 can diffuse oxygen and moisture more uniformly and sufficiently. As a result, the mobility of the oxide semiconductors 407 and 409 can be increased, and the on-state current of the TFT 109 can be increased. In addition, the drain current rises sharply with respect to the gate voltage,
It is also possible to improve the switch characteristics (decrease S value). In addition, the time required for the annealing process can be further shortened. As a result, the frame area in the display device 100 can be narrowed and the definition can be increased.

In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, it can be replaced with a configuration that is substantially the same as the configuration described in the above embodiment, a configuration that exhibits the same operational effects, or a configuration that can achieve the same purpose.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. While the first embodiment has a so-called bottom gate thin film transistor structure, the present embodiment is mainly different in that it has a so-called top gate thin film transistor structure. In the following, the first
The description of the same points as in the embodiment will be omitted.

FIG. 7 is a diagram for explaining a cross-sectional configuration of the TFT 109 in this embodiment. As shown in FIG. 7, the TFT 109 includes a glass substrate 701, a contamination barrier film 702, source / drain electrodes 703 and 704, a stacked channel 705, a gate insulating film 706, and a gate electrode 707 in order from the bottom in the figure. Here, examples of the contamination barrier film 702 include a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxynitride film (SiON).
) Or the like, or a laminated structure of these. The laminated channel 705 is
Similar to the first embodiment, the lower oxide semiconductor 708, the moisture-containing film 709, and the upper oxide semiconductor 710 are stacked.

Next, a manufacturing method of the TFT 109 in this embodiment will be described with reference to FIGS. 8A to 8G and FIG. 8A to 8G are diagrams showing a cross-sectional structure at each stage of the flow of the manufacturing method. FIG. 9 is a diagram for explaining the flow of the manufacturing method according to the present embodiment.

First, as shown in FIG. 8A, a silicon nitride film that is a contamination barrier film 702 (insulating film) is formed on a glass substrate 701 using, for example, a PECVD apparatus (S201).

As shown in FIG. 8B, source / drain electrodes 703 and 704 and wiring portions thereof are formed.
For example, a laminated structure (source / drain electrode layer) of Ti 50 nm / Al 400 nm / Ti 50 nm is formed using a sputtering apparatus (S202). The source / drain electrode layers include Mo, W, Al, Cu, Cu—Al alloy, Al—Si alloy, and Mo—W.
A single layer of a low-resistance metal such as an alloy, or a laminated structure thereof may be used.

As shown in FIG. 8C, the source / drain electrode layer is processed to form source / drain electrodes 703, 704, etc. (S203). The shape shown in FIG. 8C is an example, and the shape of the source / drain electrodes 703, 704, etc. is not limited to this.

Next, as illustrated in FIG. 8D, a stacked channel layer that forms the stacked channel 705 including the lower oxide semiconductor 708, the moisture-containing film 709, and the upper oxide semiconductor 710 is formed. In addition,
For the oxide semiconductors 708 and 710, an oxide of In—Ga—Zn—O may be used, for example.

Specifically, for example, first, using a sputtering apparatus, In 2 Ga 2 ZnO 7 is used as a target material, oxygen is added to Ar gas, and the oxide of In—Ga—Zn—O is formed to a thickness of about 25 nm. Thus, a lower oxide semiconductor layer for forming the lower oxide semiconductor 708 is formed (
S204).

Next, a moisture-containing film 709 is formed with a PECVD apparatus at a temperature of 400 ° C. using TEOS and O 2 as a film forming gas (S205).

Next, an oxide of In—Ga—Zn—O (IGZO) is formed with a DC sputtering apparatus using In 2 Ga 2 ZnO 7 as a target material and oxygen is added to Ar gas to form a film with a thickness of about 25 nm. Thus, an upper oxide semiconductor layer for forming the upper oxide semiconductor 710 is formed (S206).
).

Note that, as in the first embodiment, the material of the oxide semiconductors 708 and 710 is the same as that of the In.
In addition to —Ga—Zn—O, an amorphous or crystalline oxide semiconductor containing at least one element of In, Ga, Zn, and Sn may be used. Specifically, for example, In-
Ga-Zn oxide, In-Ga oxide, In-Zn oxide, In-Sn oxide, Zn-G
a oxide, Zn oxide, etc. may be used. The lower and upper oxide semiconductors 708 and 710 are
The same material may be used, or different materials such as IGZO as the lower oxide semiconductor 708 and ITO as the upper oxide semiconductor 710 may be used.

Here, as in the first embodiment, the TEOS film of the moisture-containing film 709 is originally an insulating film. If the film thickness is about 2 nm or less, the current flowing through the moisture-containing film 709 is a tunnel current. And does not affect the on-current. On the other hand, if it is about 2 nm or more, it functions as an insulating film, and the on-current is drastically reduced. For this reason, the TEOS film of the moisture-containing film 709 is formed to be 2 nm or less.

Similarly to the first embodiment, when a TEOS film having a thickness of about 2 nm or less is formed, it may be difficult to form a uniform film. Therefore, a TEOS film is formed in an island shape. Other portions may not be formed. In this case, SiO, Si, O 2, OH, etc., which are residues of the film forming gas, remain in the portions where the film is not formed. O2 and OH of the residue are diffused into the IGZO film by an annealing process to be described later, and the IGZO film is terminated with oxygen, which can contribute to improvement of on-current.
Therefore, the moisture-containing film 709 may be formed in an island shape. The moisture-containing film 70
9 materials are silicon oxide (SiO) film, silicon nitride (SiN) film, silicon nitride oxide (
An insulating film such as a SiON) film or AlO or TiO may be used.

Next, as shown in FIG. 8E, the laminated channel layer is processed into an island shape by photolithography, wet etching, or dry etching to form a laminated channel 705 (S207).

Next, as shown in FIG. 8F, for example, a silicon oxide film to be the gate insulating film 706 is formed by a plasma enhanced chemical vapor deposition (PECVD) apparatus at a film forming temperature of 350 ° C. and a film forming gas of SiH 4 and N
A film of about 200 nm is formed using 2O (S208). Note that the gate insulating film 706 may be a single layer of an insulating film such as a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a stacked structure thereof. Then, a stacked layer (gate electrode layer) of Mo 50 nm, Al 300 nm, and Mo 50 nm for forming the gate electrode 707 is formed by a sputtering apparatus (S209). The material for forming the gate electrode 707 is, for example, Mo.
, W, Al, Cu, Cu—Al alloy, Al—Si alloy, Mo—W alloy or other low resistance metal single layer, or a laminated structure thereof.

Next, as shown in FIG. 8G, the gate electrode layer is processed into an island shape by photolithography, wet etching, or dry etching to form a gate electrode 707 (
S210).

Next, for example, a silicon oxide film to be a passivation film (not shown) is formed by PECVD.
Using the apparatus, a film forming temperature of 250 ° C. and a film forming gas of SiH 4 and N 2 O are used to form a film of about 400 nm (S211). Note that the passivation film may be an insulating film such as a silicon nitride (SiN) film, a silicon nitride oxide (SiON) film, and other metal oxide films. As a film forming method,
In addition, sputtering, vapor deposition, etc. may be used.

Finally, annealing is performed for about 1 hour in a nitrogen atmosphere at 300 ° C. (S212). Accordingly, similarly to the first embodiment, moisture or the like of the moisture-containing film 709 can be diffused into the IGZO film, and the In—Ga—Zn—O oxide can be terminated with oxygen. As a result, TFT
109 on-current can be improved. In the above description, the annealing process is performed last. However, the annealing process may be performed at different stages as long as it is performed after the formation of the upper oxide semiconductor 710 (S206).

Similar to the first embodiment, according to the present embodiment, since the moisture-containing film 709 functions as a storage layer for oxygen, moisture, etc., annealing treatment during the formation of the moisture-containing film 709 or after the formation of the TFT 109 is performed. Accordingly, oxygen, moisture, and the like can be more uniformly and sufficiently thermally diffused in the oxide semiconductors 708 and 710. As a result, the mobility of the oxide semiconductors 708 and 710 can be further increased, and the on-state current of the TFT 109 can be further increased. Furthermore, the rise of the drain current with respect to the gate voltage is made steep, and the switch characteristic is improved (the S value is decreased).
You can also. In addition, the time required for the annealing process can be further shortened.

The present invention is not limited to the first or second embodiment, and various modifications can be made. For example, it can be replaced with a configuration that is substantially the same as the configuration described in the first or second embodiment, a configuration that exhibits the same operational effects, or a configuration that can achieve the same purpose.

For example, in the above description, the liquid crystal display device has been mainly described. However, the present invention is not limited to this, and for example, a display device using various light emitting elements such as an organic EL element, an inorganic EL element, and an FED (Field-Emission Device). You may apply. In the above, the pixel region 130
However, the present invention is not limited to this, and the shift register circuit 104 is described.
Further, the present invention may be applied to TFTs constituting the driver 106 and the like.

The image display apparatus according to the present embodiment described above includes a personal computer display, a TV
It can be employed as a display device for displaying various information such as a broadcast receiving display and a notice display. Further, it can be used as a display unit of various electronic devices such as a digital still camera, a video camera, a car navigation system, a car audio, a game device, and a portable information terminal. Note that the first electrode layer in the claims includes, for example, an electrode layer that forms the gate electrode 402, or an electrode layer that forms the source electrode 703 and the drain electrode 704, and the second electrode layer includes , Source electrode 405 and drain electrode 406
Or an electrode layer for forming the gate electrode 707.

100 display device, 101 filter substrate, 102 TFT substrate, 103 backlight, 104 shift register circuit, 105 gate signal line, 106 driver, 109
TFT, 110 pixel electrode, 111 common electrode, 130 pixel region, 401, 701
Glass substrate, 402, 707 Gate electrode, 403, 706 Gate insulating film, 404, 7
05 Stacked channel, 405, 703 Source electrode, 406, 704 Drain electrode, 4
07 Lower oxide semiconductor, 408 Water-containing film, 409 Upper oxide semiconductor, 702 Contamination barrier film.

Claims (9)

Having a first substrate;
A gate electrode on the first substrate;
A gate insulating film disposed to cover one surface of the gate electrode;
An oxide semiconductor disposed over the gate insulating film;
A source electrode and a drain electrode disposed on the oxide semiconductor,
An oxygen atom-containing film disposed between the source and drain electrodes and the gate insulating film so as to be in contact with the oxide semiconductor;
Have
A display device, wherein the oxide of the oxide semiconductor is terminated with oxygen. The display device according to claim 1, wherein the oxygen atom-containing film is one of a metalloid film, a metal film, and an insulating film having a thickness of 2 nm or less. The oxide semiconductor includes a first oxide semiconductor layer and a second oxide semiconductor layer,
Said oxygen atom-containing film, a display device according to claim 2, wherein the first oxide semiconductor layer, the arrangement is the fact between the second oxide semiconductor layer. The display device according to claim 2, wherein the oxygen atom-containing film is provided between 20% and 80% of the thickness of the oxide semiconductor. It said oxygen atom-containing film, a display device according to any one of claims 1 to 4, characterized in that a discontinuous film. The thickness of the oxide semiconductor display device according to any one of claims 1 to 5, characterized in that it is 5nm to 200 nm. The display device according to claim 3 , wherein a material of the first oxide semiconductor layer is different from a material of the second oxide semiconductor layer. Forming at least a first electrode layer on a first substrate;
Forming a channel layer including an oxide semiconductor layer and an oxygen atom-containing film on the first substrate on which the at least first electrode layer is formed;
Forming at least a second electrode layer on the substrate on which the channel layer is formed;
A method for manufacturing a display device, characterized in that an oxide atom of the oxide semiconductor is terminated with oxygen by diffusing oxygen atoms contained in the oxygen atom-containing film into the oxide semiconductor layer in a nitrogen atmosphere. The oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer,
Forming at least the first oxide semiconductor layer on the substrate on which the first electrode layer is formed;
Forming the oxygen atom-containing film on the first oxide semiconductor layer;
The oxygen atom-containing film is formed of either a metalloid film, a metal film, or an insulating film having a thickness of 2 nm or less,
Forming the second oxide semiconductor layer on the oxygen atom-containing film;
The method for manufacturing a display device according to claim 8, wherein the channel layer is formed.

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