JP6093601B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device suitable for use in, for example, an electrostatic induction thyristor (hereinafter referred to as an SI thyristor), a GTO thyristor, or the like.

  In general, in an SI thyristor, a GTO thyristor, and the like, an anode electrode is formed on the back surface of a silicon substrate, and a large number of cathode segments are arranged on the surface of the silicon substrate. A gate region is formed around each cathode segment, and a gate electrode is wired on the gate region (see Patent Documents 1 to 3).

  For example, as a device using an SI thyristor, a pulse generation circuit that applies a pulse to a load (see, for example, Patent Documents 4 and 5) can be given.

JP 2001-1119014 A Japanese Patent Laid-Open No. 9-8280 JP 2000-58814 A JP 2004-72994 A JP 2007-259308 A

  By the way, the conventional thyristor does not have a current saturation characteristic like a transistor. That is, if no gate voltage is applied, the current flowing between the anode and cathode is negligibly small, but when the gate voltage exceeds the trigger voltage and the thyristor is turned on, the current between the anode and cathode (on current) Flows. This on-current continues to flow even if the gate current is subsequently reduced to zero.

  For this reason, there is a possibility that the element including the thyristor etc. may be destroyed when an unintended large current flows due to a sudden change in the load (for example, an arc discharge occurs in the load and a short circuit occurs). In order to prevent this, a protection circuit for instantaneously detecting a load abnormality and protecting the element is necessary.

  Further, in the pulse generation circuits disclosed in Patent Documents 4 and 5, it is conceivable to connect a plurality of thyristors in parallel in order to increase the current flowing through the coil, that is, to increase the current capacity. However, since the current concentrates on the thyristor where the current flows easily due to the variation in the on-current with respect to the on-voltage of each thyristor, it is difficult to increase the current capacity by paralleling a plurality of thyristors. As a method for solving this, it is conceivable to strictly select a plurality of thyristors having substantially the same characteristics and connect them in parallel, but it is still limited to connect two thyristors in parallel.

  In the case of the planar gate type, the p-type base layer and the n-type emitter layer must be adjacent to each other. Therefore, it is difficult to stably obtain a gate breakdown voltage, and it is difficult to provide a wide n-type emitter layer. Have difficulty. Further, when producing a normally-off type, it is necessary to make a bean base of a true gate, and there is a problem that it is difficult to improve on-characteristics.

  The present invention has been made in consideration of such a problem. A conventional thyristor has a thyristor operation in a low on-current region and a similar operation to a transistor in a high on-current region. An object of the present invention is to provide a semiconductor device that can solve the above-described problems.

[1] A semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, an epitaxial layer formed on one surface of the semiconductor substrate, and a second conductivity type formed on the other surface of the semiconductor substrate. anode region and the cathode region of the first conductivity type formed in the upper layer of the epitaxial layer, the upper layer and the plurality of buried because inclusive gate region of a second conductivity type formed over the lower layer of the epitaxial layer of the semiconductor substrate The thickness of the epitaxial layer is not less than 0.5 μm and not more than 3.0 μm, the thickness of the cathode region is not less than 0.2 μm and not more than 2.0 μm, and the maximum width (true gate width) is at 0.5μm or 3.0μm or less, the cathode region impurity concentration of the highest region impurity concentration at 1 × ^{10 18 [atm / cm 3]} ~4 × 0 ^{18 [atm} / cm ^3] der is, performs the thyristor operation in the region of low on-currents, in the region of high on-state current and performing the same operation as the transistor.

  Thus, by setting the thickness of the epitaxial layer including at least the cathode region as described above, in the on-voltage-on-current characteristics, a thyristor operation is performed in a low on-current region, and a transistor in a high on-current region. A similar operation is performed. That is, this semiconductor device has a current saturation characteristic.

  Therefore, in this semiconductor device, once it is turned on, it is turned off when the supply of the gate current is stopped. Therefore, even if an unintended large current is likely to flow due to a sudden load change (for example, an arc discharge occurs in the load and a short circuit occurs), the semiconductor device alone limits the current flow. Thus, the semiconductor device can be operated safely.

  Alternatively, even if an unintended large current is likely to flow, the current flow can be limited by the semiconductor device alone, so that the thermal likelihood (thermal margin) until the semiconductor device breaks down and the time The likelihood (time margin) becomes longer. Therefore, even when a protection circuit is installed, a special detection circuit or the like that instantaneously detects a load abnormality is not necessary, and a commercially available inexpensive detection circuit may be provided, leading to a reduction in the cost of the protection circuit.

  In addition, when a semiconductor device is applied as a switch of a pulse generation circuit that applies a high voltage pulse to a load, if a plurality of semiconductor devices are connected in parallel to increase the current capacity, the characteristics of each semiconductor device may vary. As a result, when a large amount of on-current flows through a certain semiconductor device, the on-voltage of the one semiconductor device increases, thereby limiting an increase in on-current of the one semiconductor device, On-state current also flows to the semiconductor device. That is, the flow of on-current to a plurality of semiconductor devices connected in parallel is automatically balanced, and a saturation current flows in each semiconductor device. Therefore, it is not necessary to strictly select a plurality of semiconductor devices having substantially the same characteristics, and three or more semiconductor devices can be connected in parallel.

[2] In the present invention, by reducing the thickness of the epitaxial layer, an increase in on-current can be further limited, and even if an unintended large current is likely to flow, current flow alone in the semiconductor device The semiconductor device can be operated safely. In this case, the thickness of the epitaxial layer is preferably 0.5 μm or more and 2.0 μm or less.

[3] In the present invention, the thickness of the epitaxial layer may be not less than 1.0 μm and not more than 2.0 μm.

[4] In the present invention, the epitaxial layer may have a thickness of 1.5 μm to 2.0 μm.

[ 5 ] In the present invention, the epitaxial layer may have a thickness of 2.0 μm to 3.0 μm.

[ 6 ] In the present invention, the thickness of the cathode region is preferably 1/10 or more of the thickness of the epitaxial layer.

[ 7 ] In the present invention, by reducing the thickness of the cathode region, it is possible to further limit the increase in on-current, and even if an unintended large current is likely to flow, the semiconductor device alone can reduce the current flow. Therefore, the semiconductor device can be operated safely. In this case, the thickness of the cathode region is preferably 1/10 or more and 5/10 or less of the thickness of the epitaxial layer.

[ 8 ] In the present invention, by increasing the thickness of the cathode region, it is possible to relax the degree of restriction of the on-current and to reduce the on-resistance. This is advantageous when a plurality of semiconductor devices are connected in parallel to form one switch to increase the current capacity. In this case, the thickness of the cathode region is preferably 5/10 or more (10/10 or less) of the thickness of the epitaxial layer.

[ 9 ] In the present invention, by reducing the true gate width, an increase in on-current can be more limited, and even if an unintended large current is likely to flow, the semiconductor device alone can reduce the current flow. Therefore, the semiconductor device can be operated safely. In this case, the true gate width is preferably 0.5 μm or more and 1.0 μm or less.

[ 10 ] In the present invention, by increasing the true gate width, the degree of restriction of the on-current can be relaxed, and the on-resistance can be reduced. This is advantageous when a plurality of semiconductor devices are connected in parallel to form one switch to increase the current capacity. In this case, the true gate width is preferably 1.0 μm or more and 3.0 μm or less.

[ 11 ] Of course, the maximum width of the adjacent buried gate region may be 1.0 μm or more and 2.0 μm or less.

  According to the semiconductor device of the present invention, a thyristor operation is performed in a region with a low on-current, and an operation similar to that of a transistor is performed in a region with a high on-current, thereby solving the problems of the conventional thyristor. Can do.

It is sectional drawing which abbreviate | omits and shows some principal parts of the semiconductor device which concerns on this Embodiment. It is a graph which shows the on-voltage-on-current characteristic (current saturation characteristic) of the semiconductor device which concerns on this Embodiment. It is a circuit diagram which abbreviate | omits and shows an example of a pulse generation circuit. 3 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment. It is sectional drawing which abbreviate | omits and shows some principal parts of the semiconductor device which concerns on a comparative example. It is a graph which shows the on-voltage-on-current characteristic of Example 1, 3, 5, 6 and a comparative example typically among 1st Examples. It is a graph which shows the on-voltage-on-current characteristic of Example 15 and 20 typically among 2nd Examples. It is a graph which shows the on-voltage-on-current characteristic of Example 23, 24, and 25 typically among 3rd Examples. It is a graph which shows the on-voltage-on-current characteristic of 4th Example (Examples 31, 32, and 33).

  Hereinafter, an embodiment in which a semiconductor device according to the present invention is applied to, for example, a normally-off type buried gate type electrostatic induction thyristor will be described with reference to FIGS.

  As shown in FIG. 1, the semiconductor device 10 according to the present embodiment includes a first conductivity type (for example, n-type) semiconductor substrate 12, an epitaxial layer 14 formed on the semiconductor substrate 12, and an epitaxial layer 14. One or more cathode electrodes 16 made of, for example, a metal layer formed on the front surface 14 a, one or more anode electrodes 18 made of, for example, a metal layer formed on the back surface 12 a of the semiconductor substrate 12, and a cathode electrode on the surface 14 a of the epitaxial layer 14 16 and one or more gate electrodes 20 made of, for example, a metal layer that controls conduction of current flowing between the cathode electrode 16 and the anode electrode 18.

  Further, in the semiconductor device 10, a first conductivity type (for example, n-type) cathode region 22 is formed at least in a portion corresponding to the cathode electrode 16 on the surface 14 a of the epitaxial layer 14, and Among them, a second conductivity type (for example, p-type) anode region 24 is formed in a portion corresponding to the anode electrode 18.

  Further, in the semiconductor substrate 12, a region of the second conductivity type that is sandwiched between the cathode region 22 and the anode region 24 and is electrically connected to the gate electrode 20 at a position near the cathode region 22. A plurality of buried gate regions 26 are formed. The plurality of buried gate regions 26 are formed at substantially the same arrangement pitch. A region of the first conductivity type between adjacent buried gate regions 26 constitutes a channel region. The electrical connection between the gate electrode 20 and the buried gate region 26 is performed in the second conductivity type extraction region 28 formed between the buried gate region 26 and the gate electrode 20. A first insulating layer 30 is interposed between the gate electrode 20 and the cathode region 22, and a second insulating layer 32 is interposed between the gate electrode 20 and the cathode electrode 16. Note that the first conductivity type region is interposed between the buried gate region 26 and the extraction region 28, but the distance between the buried gate region 26 and the extraction region 28 is the same as that of the buried gate region 26 and the extraction region 28. It is set to such an extent that conduction can be achieved. A cathode wiring layer 34 that electrically connects the cathode electrodes 16 is formed on the plurality of cathode electrodes 16.

  Further, between the buried gate region 26 and the cathode region 22, more specifically, between the boundary between the semiconductor substrate 12 and the epitaxial layer 14 and the end of the cathode region 22 on the anode region 24 side in the adjacent buried gate region 26. A high-resistance intrinsic semiconductor region 36 is formed therebetween.

  In the semiconductor device 10, the upper portion 26a of the buried gate region 26, the cathode region 22, the extraction region 28, and the intrinsic semiconductor region 36 are formed in the epitaxial layer 14 by the epitaxial growth method. In other words, the semiconductor device 10 has the epitaxial layer 14 on the semiconductor substrate 12, and the epitaxial layer 14 is a part of the buried gate region 26 (upper portion 26 a), the extraction region 28, the cathode region 22, and the intrinsic semiconductor. In particular, the intrinsic semiconductor region 36 includes a boundary between the semiconductor substrate 12 and the epitaxial layer 14 and an end portion of the cathode region 22 on the anode region 24 side in the region between the adjacent buried gate regions 26. It is formed in the area between.

  Further, since the upper portion 26 a of the buried gate region 26 is formed by the epitaxial layer 14, the portion having the highest impurity density in the buried gate region 26 is the boundary between the semiconductor substrate 12 and the epitaxial layer 14. In addition, the central portion of the buried gate region 26 corresponds.

  In the semiconductor device 10, the thickness Da of the epitaxial layer 14 is not less than 0.5 μm and not more than 5.0 μm.

  In the semiconductor device 10, by setting the thickness Da of the epitaxial layer 14 including at least the cathode region 22 as described above, as shown in FIG. A thyristor operation is performed, and an operation similar to that of a transistor is performed in the high on-current region Z2. That is, the semiconductor device 10 has a current saturation characteristic.

  Therefore, the semiconductor device 10 is turned off when the supply of the gate current is stopped after being turned on once. Therefore, even if an unintended large current is likely to flow due to a sudden change in the load (for example, an arc discharge occurs in the load and a short circuit occurs), the current flow is limited by the semiconductor device 10 alone. Therefore, the semiconductor device 10 can be operated safely.

  Alternatively, even if an unintended large current is likely to flow, the current flow can be limited by the semiconductor device 10 alone. Therefore, the thermal likelihood (thermal margin) until the semiconductor device 10 is destroyed, The time likelihood (time margin) becomes longer. Therefore, even when a protection circuit is installed, a special detection circuit or the like that instantaneously detects a load abnormality is not necessary, and a commercially available inexpensive detection circuit may be provided, leading to a reduction in the cost of the protection circuit.

  Further, as schematically shown in FIG. 3, when the semiconductor device 10 is applied as the switch 44 of the pulse generation circuit 42 that applies a high voltage pulse to the load 40, a plurality of semiconductor devices 10 are used in order to increase the current capacity. 2 are connected in parallel, if a large amount of on-current flows through a certain semiconductor device 10 due to variations in the characteristics of the semiconductor devices 10, as can be seen from the on-voltage-on-current characteristics of FIG. As a result, the on-voltage of the one semiconductor device 10 is increased, thereby restricting the rise of the on-current of the one semiconductor device 10, and the on-current flows to the other semiconductor devices 10. That is, the flow of on-current to the plurality of semiconductor devices 10 connected in parallel is automatically balanced, and a saturation current flows in each semiconductor device 10. Accordingly, it is not necessary to strictly select a plurality of semiconductor devices 10 having substantially the same characteristics, and three or more semiconductor devices 10 can be connected in parallel.

  By the way, in a normal SI thyristor, lifetime control by electron beam irradiation or the like is performed for speeding up. However, as the temperature characteristics deteriorate and the environmental temperature increases, the leakage current increases, and the environmental temperature is, for example, 150. When it reaches ° C, it may stop working. However, since the semiconductor device 10 can limit an increase in on-current, the semiconductor device 10 can be increased in speed without performing lifetime control, and the temperature characteristics are also improved.

  In the semiconductor device 10 according to the present embodiment, the thickness Da of the epitaxial layer 14 is reduced, so that an increase in on-current can be further limited. Even if an unintended large current is likely to flow, The device 10 alone can limit the flow of current, and the semiconductor device 10 can be operated safely. In this case, the thickness Da of the epitaxial layer 14 is preferably 0.5 μm or more and 2.0 μm or less. Of course, it may be 1.0 μm or more and 2.0 μm or less, or may be 1.5 μm or more and 2.0 μm or less.

  On the other hand, by increasing the thickness Da of the epitaxial layer 14, the degree of restriction of the on-current can be relaxed, and the on-resistance can be reduced. This is advantageous when a plurality of semiconductor devices 10 are connected in parallel to form one switch 44 to increase the current capacity. In this case, the thickness Da of the epitaxial layer 14 is preferably 2.0 μm or more and 5.0 μm or less. Of course, it may be 2.0 μm or more and 4.0 μm or less, or may be 2.0 μm or more and 3.0 μm or less.

  Further, the thickness Db (see FIG. 1) of the cathode region 22 is preferably 1/10 or more (10/10 or less) of the thickness Da of the epitaxial layer 14. By reducing the thickness Db of the cathode region 22, an increase in on-current can be further restricted, and even if an unintended large current is likely to flow, the semiconductor device 10 alone can restrict the current flow. The semiconductor device 10 can be operated safely. In this case, the thickness Db of the cathode region 22 is preferably 1/10 or more and 5/10 or less of the thickness Da of the epitaxial layer 14.

  On the other hand, by increasing the thickness Db of the cathode region 22, the degree of restriction of the on-current can be relaxed, and the on-resistance can be reduced. This is advantageous when a plurality of semiconductor devices 10 are connected in parallel to form one switch to increase the current capacity. In this case, the thickness Db of the cathode region 22 is preferably 5/10 or more (10/10 or less) of the thickness Da of the epitaxial layer 14. However, if the thickness Db of the cathode region 22 is excessively increased, a large amount of on-current flows, so that a protection circuit may need to be connected. However, as described above, a commercially available inexpensive detection circuit is provided. A protective circuit is sufficient.

  Further, it is preferable that the maximum width (true gate width Wa: see FIG. 1) of the adjacent buried gate region 26 is 0.5 μm or more and 3.0 μm or less. By reducing the true gate width Wa, an increase in on-current can be further restricted, and even if an unintended large current is likely to flow, the semiconductor device 10 alone can restrict the current flow. The semiconductor device 10 can be operated safely. In this case, the true gate width Wa is preferably 0.5 μm or more and 1.0 μm or less.

  On the other hand, by increasing the true gate width Wa, the degree of restriction of the on-current can be relaxed, and the on-resistance can be reduced. This is advantageous when a plurality of semiconductor devices 10 are connected in parallel to form one switch 44 to increase the current capacity. In this case, the true gate width Wa is preferably 1.0 μm or more and 3.0 μm or less. Of course, it may be 1.0 μm or more and 2.0 μm or less. However, if the true gate width Wa is made too thick, a large amount of on-current flows, so it may be necessary to connect a protection circuit. However, as described above, a commercially available inexpensive detection circuit is provided. A protection circuit is sufficient.

Further, the impurity concentration at the highest impurity concentration in the cathode region 22 (simply referred to as the impurity concentration in the cathode region 22) is in the order of 10 ¹⁸ [atm / cm ³ ] to 10 ²⁰ [atm / cm ³ ]. Is preferred. By reducing the impurity concentration in the cathode region 22, the increase in on-current can be further restricted, and even if an unintended large current is likely to flow, the semiconductor device 10 alone can restrict the current flow. The semiconductor device 10 can be operated safely.

  On the other hand, increasing the impurity concentration in the cathode region 22 can relax the degree of restriction of the on-current and can reduce the on-resistance. This is advantageous when a plurality of semiconductor devices 10 are connected in parallel to form one switch 44 to increase the current capacity. However, if the impurity concentration in the cathode region 22 is increased too much, a large amount of on-current flows, so that it may be necessary to connect a protection circuit. However, as described above, a commercially available inexpensive detection circuit is provided. A protective circuit is sufficient.

  As described above, by appropriately changing the thickness Da of the epitaxial layer 14, the thickness Db of the cathode region 22, the true gate width Wa, and the impurity concentration of the cathode region 22 (impurity concentration of the highest part), saturation current limitation can be achieved. Since the degree can be set freely, it is possible to improve the degree of freedom in designing the semiconductor device 10 that allows an appropriate saturation current according to the intended use.

  Here, an example of a method for manufacturing the semiconductor device 10 according to the present embodiment will be briefly described with reference to FIG.

  First, in step S <b> 1 of FIG. 4, a photomask having a plurality of openings is formed on the surface of the semiconductor substrate 12. The opening is formed in the surface of the semiconductor substrate 12 at a position that later becomes the central portion of the buried gate region 26. Therefore, the portion that will later become the intrinsic semiconductor region 36 is protected by the photomask, and the occurrence of scratches on the portion can be prevented.

Thereafter, in step S2, a second conductivity type impurity (for example, boron) is attached to at least a portion of the semiconductor substrate 12 exposed from the opening of the photomask, and an impurity layer (for example, the portion of the semiconductor substrate 12 exposed from the opening of the photomask). Metal boron layer). The impurity density of the impurity layer is on the order of 10 ¹⁹ to 10 ²⁰ [atm / cm ³ ].

  Thereafter, in step S3, the impurity (boron) is diffused from the impurity layer (metal boron layer) to the semiconductor substrate 12 to form part of the buried gate region 26 (lower part 26b: see FIG. 1). The temperature of this diffusion treatment is any temperature within the range of 1100 ° C. to 1200 ° C., for example, 1150 ° C.

  Thereafter, in step S4, vapor phase epitaxial growth including at least a first conductivity type impurity (for example, phosphorus) and silicon is performed, and at least a part of the buried gate region 26 (upper portion 26a: see FIG. 1) is formed on the semiconductor substrate 12. Then, the first epitaxial layer 14A (the lower layer portion of the epitaxial layer 14: see FIG. 1) having the intrinsic semiconductor region 36 is formed. The formation of the first epitaxial layer 14A is performed at any temperature in the range of 1000 ° C. to 1100 ° C., for example, 1050 ° C. At this stage, the buried gate region 26 is completed.

  Thereafter, in step S5, the second epitaxial layer 14B (the upper layer portion of the epitaxial layer 14: see FIG. 1) is formed on the first epitaxial layer 14A by epitaxial growth.

  Thereafter, in step S <b> 6, the extraction region 28 is formed at a location corresponding to the buried gate region 26 in the second epitaxial layer 14 </ b> B, and the cathode region 22 is formed at a location corresponding to the intrinsic semiconductor region 36. As a result, the second epitaxial layer 14B including the cathode region 22 and the extraction region 28 is formed on the first epitaxial layer 14A.

  Thereafter, in step S7, the first insulating layer 30, the gate electrode 20, the cathode electrode 16, the second insulating layer 32, and the cathode wiring layer 34 are formed on the epitaxial layer 14, and the semiconductor device 10 is completed.

[First embodiment]
In the first example, the relationship between the on-voltage and the on-current when the thickness Da of the epitaxial layer 14 was changed was confirmed for examples 1 to 6 and the comparative example.

Example 1
The semiconductor device according to the first embodiment is the same as the semiconductor device 10 shown in FIG. 1 except that the epitaxial layer 14 has a thickness Da of 1.0 μm, the cathode region 22 has a thickness Db of 1.0 μm, and the maximum width (true The gate width Wa) was 1.0 μm, and the impurity concentration of the cathode region 22 was 2 × 10 ¹⁸ [atm / cm ³ ].

(Examples 2 to 6)
In the semiconductor devices according to Examples 2, 3, 4, 5, and 6, except that the thickness Da of the epitaxial layer 14 was 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, and 4.0 μm, respectively. It was produced in the same manner as in Example 1.

(Comparative example)
As shown in FIG. 5, the semiconductor device 100 according to this comparative example has a mesa etching groove 38 that reaches the buried gate region 26, and the gate electrode 20 is formed in the mesa etching groove 38 (groove). A cathode electrode 16 is formed on the land (epitaxial layer 14). The thickness Da of the epitaxial layer 14 is 13.0 μm, the thickness Db of the cathode region 22 is 6 μm, the maximum width (true gate width) Wa of the adjacent buried gate region 26 is 1.5 μm, and the impurity concentration of the cathode region 22 is It was set to 2 × 10 ¹⁹ [atm / cm ³ ].

(Evaluation results)
The relationship between the on-voltage and the on-current in Examples 1 to 6 and Comparative Example is shown in Table 1 below, and in particular, the results of Example 3 and Comparative Example are shown in FIG. In FIG. 6, the results of Examples 1, 3, 5, and 6 are indicated by solid lines La, Lb, Lc, and Ld, and the results of the comparative example are indicated by solid lines Le.

  In the comparative example, as can be seen from the solid line Le in FIG. 6, the value of the on-current steeply increases as the on-voltage increases, and becomes almost infinite at the stage of the on-voltage 5V.

  On the other hand, as shown by the solid line Lb in FIG. 6, the example 3 typically has a current saturation characteristic, and in the region between the on-state currents 0A to 600A, it rises more steeply than the comparative example, It can be seen that the operation is almost similar to the thyristor operation. In the region where the on-current is 600 A or more, it can be seen that the increase rate of the on-current gradually decreases as the on-voltage increases, and the characteristics are similar to the current saturation characteristics of the transistors. The value of the on-current with respect to the on-voltage of 40 V was 1024 A.

  In addition, Examples 1, 2, 4 and 5 also had the same current saturation characteristics as Example 3 described above. From the results of Examples 1 to 3 in Table 1, as the thickness Da of the epitaxial layer 14 becomes thinner, the value of the on-current with respect to the on-voltage 40V decreases, and the increase of the on-current is further restricted. Recognize. Similarly, from the results of Examples 4 and 5, it can be seen that as the thickness Da of the epitaxial layer 14 increases, the value of the on-current with respect to the on-voltage 40V increases, and the degree of restriction of the on-current is relaxed. .

  That is, when the thickness Da of the epitaxial layer 14 is increased, the on-voltage is reduced, and the bipolar characteristics are exhibited. As can be seen from the characteristics shown in the sixth embodiment, it is considered that the on-voltage is constant as the pin diode. On the contrary, when the thickness Da of the epitaxial layer 14 is decreased, an effective n-type emitter region on the channel is not formed, and extreme transistor characteristics are exhibited.

[Second Embodiment]
In the second example, the relationship between the on-voltage and the on-current when the thickness Db of the cathode region 22 was changed was confirmed for examples 11 to 20.

(Example 11)
The semiconductor device according to Example 11 is the same as the semiconductor device 10 shown in FIG. 1, except that the thickness Da of the epitaxial layer 14 is 2.0 μm, the thickness Db of the cathode region 22 is 0.2 μm, the true gate width Wa is 1 μm, and the cathode region. The impurity concentration of 22 was 2 × 10 ¹⁸ [atm / cm ³ ].

(Examples 12 to 20)
In the semiconductor devices according to Examples 12, 13, 14, 15, 16, 17, 18, 19, and 20, the thickness Db of the cathode region 22 is 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, and 1 respectively. It was produced in the same manner as in Example 11 except that the thickness was set to 2 μm, 1.4 μm, 1.6 μm, 1.8 μm, and 2.0 μm. In addition, Example 15 and Example 4 mentioned above are the same semiconductor devices.

(Evaluation results)
The relationship between the on-voltage and on-current in Examples 11 to 20 is shown in Table 2 below, and in particular, the results of Examples 15 and 20 are shown in FIG. In FIG. 7, the result of Example 15 is indicated by a solid line Lf, and the result of Example 20 is indicated by a solid line Lg.

  Typically, Examples 15 and 20 both have current saturation characteristics, as shown in FIG. 7, and are more gradual than the comparative example of FIG. 6 (see solid line Le) in the region between ON currents 0A to 600A. However, it can be seen that the operation rises sharply and the operation is almost similar to the thyristor operation. In the region where the on-current is 600 A or more, it can be seen that the increase rate of the on-current gradually decreases as the on-voltage increases, and the characteristics are similar to the current saturation characteristics of the transistors. The values of the on-current with respect to the on-voltage of 40 V were 1024 A and 1088 A.

  In addition, Examples 11 to 14 and 16 to 19 also had current saturation characteristics similar to those of Examples 15 and 20 described above. From the results of Examples 11 to 15 in Table 2, as the thickness Db of the cathode region 22 is reduced, the value of the on-current with respect to the on-voltage 40V is reduced, and the increase of the on-current is further restricted. Recognize. Similarly, from the results of Examples 15 to 20, it can be seen that as the thickness Db of the cathode region 22 increases, the value of the on-current with respect to the on-voltage of 40 V increases, and the degree of restriction of the on-current is relaxed. .

[Third embodiment]
In the third example, the relationship between the on-voltage and the on-current when the true gate width Wa was changed was confirmed for examples 21 to 27.

(Example 21)
The semiconductor device according to Example 21 is the same as the semiconductor device 10 shown in FIG. 1 except that the epitaxial layer 14 has a thickness Da of 2.0 μm, the cathode region 22 has a thickness Db of 1.0 μm, a true gate width Wa of 0.5 μm, The impurity concentration of the cathode region 22 was 2 × 10 ¹⁸ [atm / cm ³ ].

(Examples 22 to 27)
In the semiconductor devices according to Examples 22, 23, 24, 25, 26, and 27, the true gate widths Wa are 0.8 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, and 3.0 μm, respectively. Except for the above, it was fabricated in the same manner as in Example 21. In addition, Example 23 and Example 4 mentioned above are the same semiconductor devices.

(Evaluation results)
The relationship between the ON voltage and the ON current in Examples 21 to 27 is shown in Table 3 below, and in particular, the results of Examples 23, 24, and 25 are shown in FIG. In FIG. 8, the result of Example 23 is indicated by a solid line Lh, the result of Example 24 is indicated by a solid line Li, and the result of Example 25 is indicated by a solid line Lj.

  Typically, Examples 23, 24 and 25 both have current saturation characteristics, as shown in FIG. 8, and are more gradual than the comparative example of FIG. 6 (see solid line Le) in the region between ON currents 0A to 600A. However, it can be seen that the operation rises sharply and the operation is almost similar to the thyristor operation. In the region where the on-current is 600 A or more, it can be seen that the increase rate of the on-current gradually decreases as the on-voltage increases, and the characteristics are similar to the current saturation characteristics of the transistors. The values of the on-current with respect to the on-voltage of 40 V were 1024A, 1224A, and 1425A.

  In addition, Examples 21, 22, 26, and 27 also had current saturation characteristics similar to those of Examples 23, 24, and 25 described above. From the results of Examples 21 to 23 in Table 3, it can be seen that as the true gate width Wa decreases, the value of the on-current with respect to the on-voltage 40V decreases, and the increase in the on-current is more limited. . Similarly, from the results of Examples 23 to 27, it can be seen that as the true gate width Wa increases, the value of the on-current with respect to the on-voltage 40V increases, and the degree of restriction of the on-current is relaxed.

[Fourth embodiment]
In the fourth example, the relationship between the on-voltage and the on-current when the impurity concentration of the cathode region 22 was changed was confirmed for examples 31 to 33.

(Example 31)
The semiconductor device according to Example 31 is the same as the semiconductor device 10 shown in FIG. 1, except that the epitaxial layer 14 has a thickness Da of 2.0 μm, the cathode region 22 has a thickness Db of 1.0 μm, a true gate width Wa of 1.0 μm, The impurity concentration of the cathode region 22 was set to 1 × 10 ¹⁸ [atm / cm ³ ].

(Examples 32 and 33)
The semiconductor device according to Examples 32 and 33 was the same as Example 31 except that the impurity concentration of the cathode region 22 was 2 × 10 ¹⁸ [atm / cm ³ ] and 4 × 10 ¹⁸ [atm / cm ³ ], respectively. It produced similarly. Note that Example 32 and Example 4 described above are the same semiconductor device.

(Evaluation results)
The relationship between the on voltage and the on current in Examples 31 to 33 is shown in Table 4 and FIG. In FIG. 9, the result of Example 31 is indicated by a solid line Lk, the result of Example 32 is indicated by a solid line Ll, and the result of Example 33 is indicated by a solid line Lm.

  As shown in FIG. 9, each of Examples 31, 32, and 33 has a current saturation characteristic, and in the region from ON current 0A to 600A, it is more gradual than the comparative example of FIG. 6 (see solid line Le). It can be seen that the operation rises sharply and the operation is almost similar to the thyristor operation. In the region where the on-current is 600 A or more, it can be seen that the increase rate of the on-current gradually decreases as the on-voltage increases, and the characteristics are similar to the current saturation characteristics of the transistors. The values of the on-current with respect to the on-voltage of 40 V were 904A, 1024A, and 1168A.

  From the results of Examples 31 and 32, it can be seen that as the impurity concentration in the cathode region 22 decreases, the value of the on-current with respect to the on-voltage of 40 V decreases, and the increase in the on-current is more limited. Similarly, from the results of Examples 32 and 33, it can be seen that as the impurity concentration in the cathode region 22 increases, the value of the on-current with respect to the on-voltage of 40 V increases, and the degree of restriction of the on-current is relaxed. .

  Note that the semiconductor device according to the present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 12 ... Semiconductor substrate 14 ... Epitaxial layer 16 ... Cathode electrode 18 ... Anode electrode 20 ... Gate electrode 22 ... Cathode region 24 ... Anode region 26 ... Embedded gate region 28 ... Extraction region 30 ... 1st insulating layer 32 ... 1st 2 insulating layer 34 ... cathode wiring layer 36 ... intrinsic semiconductor region 40 ... load 42 ... pulse generation circuit 44 ... switch Z1 ... low on-current region Z2 ... high on-current region

Claims (11)

A first conductivity type semiconductor substrate;
An epitaxial layer formed on one surface of the semiconductor substrate;
An anode region of a second conductivity type formed on the other surface of the semiconductor substrate;
A cathode region of a first conductivity type formed in an upper layer of the epitaxial layer;
And a said upper layer and the plurality of buried because inclusive gate region of a second conductivity type formed over the lower layer of the epitaxial layer of the semiconductor substrate,
The thickness of the epitaxial layer is 0.5 μm or more and 3.0 μm or less,
The cathode region has a thickness of 0.2 μm or more and 2.0 μm or less;
The maximum width of the adjacent buried gate region is 0.5 μm or more and 3.0 μm or less,
The cathode region 1 is the impurity concentration of the portion having the highest impurity concentration of ^{× 10 18 [atm / cm 3} ] ~4 × 10 18 [atm / cm 3] der is,
A semiconductor device characterized in that a thyristor operation is performed in a low on-current region and an operation similar to that of a transistor is performed in a high on-current region . The semiconductor device according to claim 1,
The thickness of the said epitaxial layer is 0.5 micrometer or more and 2.0 micrometers or less, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
A thickness of said epitaxial layer is 1.0 micrometer or more and 2.0 micrometers or less, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The thickness of the said epitaxial layer is 1.5 micrometers or more and 2.0 micrometers or less, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
A thickness of said epitaxial layer is 2.0 micrometers or more and 3.0 micrometers or less, The semiconductor device characterized by the above-mentioned. The semiconductor device according to any one of claims 1 to 5,
The thickness of the said cathode area | region is 1/10 or more of the thickness of the said epitaxial layer, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 6.
The thickness of the said cathode area | region is 1/10 or more and 5/10 or less of the thickness of the said epitaxial layer, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 6.
The thickness of the said cathode area | region is 5/10 or more of the thickness of the said epitaxial layer, The semiconductor device characterized by the above-mentioned. The semiconductor device according to any one of claims 1 to 8,
2. The semiconductor device according to claim 1, wherein the adjacent buried gate region has a maximum width of 0.5 [mu] m to 1.0 [mu] m. The semiconductor device according to any one of claims 1 to 8,
2. The semiconductor device according to claim 1, wherein the adjacent buried gate region has a maximum width of 1.0 [mu] m to 3.0 [mu] m. The semiconductor device according to any one of claims 1 to 8,
2. The semiconductor device according to claim 1, wherein the adjacent buried gate region has a maximum width of 1.0 [mu] m to 2.0 [mu] m.

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