JP6080563B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The disclosed invention relates to a method for manufacturing a semiconductor device.

  Note that a semiconductor device in this specification refers to all devices that can function by utilizing semiconductor characteristics, for example, semiconductor elements such as transistors, semiconductor circuits including semiconductor elements, electro-optical devices such as display devices, All electronic devices are semiconductor devices.

  Transistors used in many flat panel displays typified by liquid crystal display devices and light-emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon, or polycrystalline silicon formed on a glass substrate. . In addition, a transistor including the silicon semiconductor is used for an integrated circuit (IC) or the like.

  In recent years, a technique using a metal oxide exhibiting semiconductor characteristics for a transistor instead of a silicon semiconductor has attracted attention. Note that in this specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor.

  For example, a technique is disclosed in which a transistor using zinc oxide or an In—Ga—Zn—O-based oxide as an oxide semiconductor is manufactured, and the transistor is used for a switching element of a pixel of a display device (patent) Reference 1 and Patent Document 2).

  In addition, in a transistor including an oxide semiconductor, a technique is disclosed in which a metal film is formed in contact with an oxide semiconductor film and heat treatment is performed in an oxygen atmosphere (see Patent Document 3). Specifically, by the heat treatment, oxygen in the oxide semiconductor film reacts with the metal film, and the oxygen concentration is reduced, so that the resistance of the oxide semiconductor film is reduced locally, and the source In this technique, the region and the drain region are formed, the metal film is oxidized to form a metal oxide film, and the metal oxide film is used as a barrier film against the outside air.

JP 2007-123861 A JP 2007-96055 A JP 2011-228622 A

  As in the technique disclosed in Patent Document 3, in the heat treatment in an oxygen atmosphere, there is a possibility that the step of locally reducing the resistance of the oxide semiconductor film is not sufficiently performed. For example, when heated in an oxygen atmosphere, it can be expected that the oxidation from the surface of the metal film will proceed predominantly, and if the metal film is sufficiently oxidized before the resistance of the oxide semiconductor film is locally reduced, There is a possibility that the step of locally reducing the resistance of the oxide semiconductor film becomes insufficient. Therefore, the number of steps for manufacturing the transistor can be reduced, but the yield may be reduced.

  In addition, when the metal film is not completely oxidized and a conductive region remains in part of the metal film, the source electrode and the drain electrode may be conducted through the region, and the transistor may not function.

  In view of the above, an object of one embodiment of the present invention is to provide a method for manufacturing a transistor in which part of an oxide semiconductor film can have sufficiently low resistance and yield is high.

  Further, when the on-state characteristics (eg, on-state current and field-effect mobility) of a transistor including an oxide semiconductor are improved, high-speed response and high-speed driving can be performed in the semiconductor device, so that a higher-performance semiconductor device can be realized.

  Thus, an object of one embodiment of the present invention is to provide a transistor including an oxide semiconductor that has high on-state characteristics. An object of one embodiment of the present invention is to provide a high-performance semiconductor device including a transistor capable of high-speed response and high-speed driving.

  In order to improve on-state current and field-effect mobility, the parasitic resistance of the transistor is reduced, that is, in the region other than the channel formation region of the semiconductor film (oxide semiconductor film) included in the transistor, It is effective to reduce the resistance and the resistance in the direction perpendicular to the film thickness direction. It is also effective to reduce the contact resistance with the source electrode and the drain electrode. One means for implementing these is to provide a low resistance region having a concentration difference in a region other than the channel formation region of the semiconductor film (oxide semiconductor film) included in the transistor. The concentration difference includes the step of injecting a dopant into a region other than the channel formation region, and the element of the film including the metal element by performing heat treatment in a state where the film including the metal element is provided in the region other than the channel formation region. Can be provided by a step of diffusing into a part of the region. Further, by providing the low resistance region having the concentration difference, an electric field applied to a semiconductor film (oxide semiconductor film) included in the transistor can be stepped.

  Thus, according to one embodiment of the present invention, an oxide semiconductor film in which part of a surface is exposed, a gate insulating film, a gate electrode, and a sidewall insulating film in contact with at least a side surface of the gate electrode are formed, and at least oxidized After forming a film containing a metal element over part of the surface of the semiconductor film and the sidewall insulating film, heat treatment is performed in a nitrogen atmosphere to oxidize a region in contact with the oxide semiconductor film of the film containing the metal element Then, a method for manufacturing a semiconductor device in which a film containing a metal element having an oxidized region is removed to expose part of the surface of the oxide semiconductor film.

  Further, according to one embodiment of the present invention, an oxide semiconductor film is formed over a substrate having an insulating surface, an insulating film containing oxygen is formed over the oxide semiconductor film, and the first insulating film is formed over the insulating film containing oxygen. Forming a metal oxide film having a property, forming a gate electrode overlapping with the oxide semiconductor film on the first metal oxide film having an insulating property, and implanting a dopant into the oxide semiconductor film using the gate electrode as a mask And forming a first insulating metal oxide film and a sidewall insulating film in contact with the gate electrode, and removing a part of the insulating film containing oxygen and a part of the first insulating metal oxide film. Then, a part of the oxide semiconductor film into which the dopant is implanted is exposed and a gate insulating film is formed, and a film containing a metal element covering at least the exposed oxide semiconductor film is formed, and heat treatment is performed in a nitrogen atmosphere. After the metal element Removing the non-film, a method for manufacturing a semiconductor device for forming a metal oxide film having a second insulating covering the oxide semiconductor film which film has been removed, including at least a metal element.

  Further, in the above method for manufacturing a semiconductor device, the source electrode and the drain electrode are formed by forming an interlayer insulating film on the second insulating metal oxide film, and the second insulating metal oxide film and interlayer insulating film. An opening reaching the oxide semiconductor film (source region and drain region) from which the film containing the metal element is removed can be formed in the opening.

  In the above method for manufacturing a semiconductor device, heat treatment is preferably performed before or after forming the insulating film containing oxygen and after forming the insulating film containing oxygen.

  In the above method for manufacturing a semiconductor device, it is preferable that the insulating metal oxide film has a function of not allowing impurities such as hydrogen or moisture in the outside air to permeate. By providing the insulating metal oxide film, the outside air It is possible to prevent impurities such as hydrogen or moisture from being mixed therein. Therefore, deterioration of the electrical characteristics of the transistor due to outside air can be suppressed.

  In the above method for manufacturing a semiconductor device, the heat treatment performed in a state where the film containing the metal element is in contact with the region containing the dopant in the oxide semiconductor film is performed under a nitrogen atmosphere and the metal element in the oxide semiconductor film containing the dopant. The metal element in the film containing the metal element diffuses into a region in contact with the film including the metal element, and the resistance is lower than that in the region overlapping with the sidewall insulating film of the oxide semiconductor film containing the dopant. The heat treatment can be performed not only in a nitrogen atmosphere but also in a rare gas atmosphere or a reduced pressure atmosphere. Note that the sidewall insulating film is preferably formed using a nitride insulating film.

  In the case where heat treatment is performed in a nitrogen atmosphere, a rare gas atmosphere, or a reduced pressure atmosphere, the entire film containing the metal element is not oxidized, and at least a portion of the film containing the metal element is in contact with the oxide semiconductor film. Therefore, it is preferable to newly form an insulating metal oxide film having a function of preventing permeation of impurities such as hydrogen or moisture in the outside air after removing the film containing the metal element partially oxidized. . In this manner, a transistor with favorable electrical characteristics can be manufactured in which deterioration of electrical characteristics of the transistor due to impurities such as hydrogen or moisture is suppressed. Note that the film containing the metal element which is partially oxidized is removed using a difference in etching rate of the film containing the metal element which is only partially oxidized and the oxide semiconductor film with respect to the etching gas or the etchant. Can do.

  In the case where a film containing a metal element which is partially oxidized is removed by dry etching, it is difficult to obtain an etching selectivity with respect to the oxide semiconductor film provided under the film containing the metal element. There is a possibility that a part of the film is removed (film reduction). Therefore, in the above method for manufacturing a semiconductor device, it is preferable that the film containing a metal element oxidized only in part be removed by wet etching.

  In an oxide semiconductor, electric charges are generated due to oxygen vacancies generated in the oxide semiconductor film. Part of oxygen vacancies in the oxide semiconductor serves as a donor, and electrons serving as carriers are generated. Therefore, a transistor including an oxide semiconductor has poor electrical characteristics such as a threshold voltage that is likely to fluctuate in the negative direction due to oxygen vacancies in the oxide semiconductor and a normally-on characteristic.

  Thus, in the above method for manufacturing a semiconductor device, a base insulating film may be formed between the oxide semiconductor film and the substrate. The base insulating film in contact with the oxide semiconductor film is preferably formed using an insulating film containing oxygen, and more preferably formed using an insulating film containing oxygen in excess of the stoichiometric composition. Note that the insulating film containing oxygen in excess of the stoichiometric composition can be used not only for the base insulating film but also for the gate insulating film. For an insulating film containing oxygen in excess of the stoichiometric composition, an oxide insulating film is formed by a sputtering method while supplying oxygen, or an oxide insulating film or an oxynitride film is formed by a plasma CVD (Chemical Vapor Deposition) method. Then, oxygen ions can be implanted into the oxide insulating film or the oxynitride film.

  In this manner, by using the insulating film containing oxygen for the base insulating film and the gate insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film can be repaired by heat treatment in the manufacturing process of the transistor. Thus, a transistor having favorable electrical characteristics can be manufactured.

  According to one embodiment of the present invention, in a transistor including an oxide semiconductor, a step of reducing resistance of part of the oxide semiconductor film and a step of forming a protective film against impurities such as hydrogen or moisture in the outside air are performed. Accordingly, resistance of part of the oxide semiconductor film can be sufficiently reduced, and a transistor in which deterioration of electrical characteristics due to outside air is suppressed can be manufactured with high yield. Further, according to one embodiment of the present invention, by providing a low resistance region having a concentration difference in a region other than the channel formation region, electric field concentration can be suppressed particularly in the vicinity of the drain region, and the transistor is destroyed due to electric field concentration. This can be suppressed. According to one embodiment of the present invention, a transistor including an oxide semiconductor with high on-state characteristics is provided, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed driving is provided. it can.

10A and 10B are a top view and cross-sectional views illustrating an example of a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10A and 10B are a top view and cross-sectional views illustrating an example of a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10A and 10B are a top view and cross-sectional views illustrating an example of a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10A and 10B are a cross-sectional view, a top view, and a circuit diagram illustrating an example of a semiconductor memory device. FIG. 10 is a circuit diagram illustrating an example of a semiconductor memory device. 6A and 6B are a circuit diagram and a conceptual diagram illustrating an example of a semiconductor memory device. 8A and 8B are a cross-sectional view and a top view illustrating an example of a semiconductor memory device. FIG. 10 is a circuit diagram illustrating an example of a semiconductor memory device. The block diagram which shows the specific example of CPU, and the circuit diagram of the one part. FIGS. 3A and 3B are a diagram and a circuit diagram illustrating an active matrix display device. FIGS. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the following embodiments and examples, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatch patterns in different drawings, and description thereof is not repeated. To do.

  Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

  Further, the terms such as first, second, and third used in this specification are given for avoiding confusion between components, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

The functions of “source” and “drain” may be interchanged when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  In this specification, in the case where an etching step is performed after a photolithography step, the mask formed in the photolithography step is removed.

(Embodiment 1)
In this embodiment, a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to drawings. Hereinafter, the semiconductor device is described as a transistor.

<Example of transistor configuration>
1A and 1B are a top view and a cross-sectional view of the transistor 100. FIG. 1A is a top view of the transistor 100, and FIG. 1B is a cross-sectional view taken along one-dot chain line A-B in FIG. 1A. Note that in FIG. 1A, some components of the transistor 100 (eg, the substrate 101, the base insulating film 103, and the gate insulating film 116) are omitted for clarity.

  1A and 1B, the transistor 100 includes a base insulating film 103 over a substrate 101, an oxide semiconductor film 105 over a base insulating film 103, and an oxide semiconductor film. A gate insulating film 116 is provided over the semiconductor film 105, a gate electrode 117 is provided in a region overlapping with the oxide semiconductor film 105 over the gate insulating film 116, and is in contact with the gate insulating film 116 and the gate electrode 117. A sidewall insulating film 119 is provided, and an insulating metal oxide film 121 in contact with the base insulating film 103, part of the oxide semiconductor film 105, the gate insulating film 116, the gate electrode 117, and the sidewall insulating film 119 is formed. An interlayer insulating film 123 is provided on the insulating metal oxide film 121, and the insulating metal oxide film 121 is provided. Opening 125a formed in the fine interlayer insulating film 123, through 125b, the source electrode 127a and drain electrode 127b in contact with the oxide semiconductor film 105 is provided. Note that the base insulating film 103 and the interlayer insulating film 123 are not necessarily provided.

  The transistor 100 is a top-gate transistor because the gate electrode 117 is provided above the oxide semiconductor film 105 and the source electrode 127 a and the drain electrode 127 b are in contact with the upper surface of the oxide semiconductor film 105. .

  The oxide semiconductor film 105 includes a first region 107, a pair of second regions 109a and 109b that face each other with the first region 107 interposed therebetween, and a first region 107 and a pair of second regions 109a and 109b. And a pair of third regions 111a and 111b facing each other.

  In the oxide semiconductor film 105, the first region 107 is a region containing no dopant, and the pair of second regions 109a and 109b and the pair of third regions 111a and 111b are regions containing a dopant. The resistance of the pair of third regions 111a and 111b is lower than the resistance of the pair of second regions 109a and 109b. Therefore, the first region 107 overlapping with the gate electrode 117 functions as a channel formation region, the pair of third regions 111a and 111b functions as a source region or a drain region, and the pair of second regions 109a, 109b functions as an electric field relaxation region for relaxing an electric field generated in the drain region.

  A transistor using an oxide semiconductor is known to have a lower off-state current at room temperature than a transistor using a silicon semiconductor. This is considered to be because there are few carriers generated by thermal excitation, that is, the carrier density is small. Even in a transistor using a material having a low carrier density, variation in threshold voltage may appear due to a reduction in channel length.

  Thus, like the transistor 100, the pair of second regions 109a and 109b and the pair of third regions 111a and 111b are provided at both ends of the first region 107 which is a channel formation region, whereby the oxide semiconductor film Since the electric field applied between the source region and the drain region 105, particularly the electric field concentration in the vicinity of the drain region, can be relaxed, fluctuations in threshold voltage and the like can be suppressed. In addition, since electric field concentration can be reduced, the transistor can be prevented from being destroyed by electric field concentration. In other words, the transistor 100 is a transistor whose breakdown voltage is improved and electrical characteristic deterioration is suppressed.

  In addition, since the resistance of the pair of third regions 111a and 111b is reduced, the contact resistance with the source electrode 127a and the drain electrode 127b is reduced. Therefore, the transistor 100 is a transistor having excellent on-current characteristics.

  Next, details of each component of the transistor 100 will be described.

[substrate]
There is no particular limitation on the substrate 101, but it is preferable that the substrate 101 have an insulating surface, and at least heat resistance enough to withstand heat treatment performed later. For example, various glass substrates used for the electronic industry such as glass substrates such as barium borosilicate glass and alumino borosilicate glass can be used. The substrate has a thermal expansion coefficient of 25 × 10 ⁻⁷ / ° C. or higher and 50 × 10 ⁻⁷ / ° C. or lower (preferably 30 × 10 ⁻⁷ / ° C. or higher and 40 × 10 ⁻⁷ / ° C. or lower). A substrate having a strain point of 650 ° C. or higher and 750 ° C. or lower (preferably 700 ° C. or higher and 740 ° C. or lower) is preferably used.

  5th generation (1000 mm × 1200 mm or 1300 mm × 1500 mm), 6th generation (1500 mm × 1800 mm), 7th generation (1870 mm × 2200 mm), 8th generation (2200 mm × 2500 mm), 9th generation (2400 mm × 2800 mm), 1st When a large glass substrate such as 10th generation (2880 × 3130 mm) is used, fine processing may be difficult due to shrinkage of the substrate caused by heat treatment in a manufacturing process of a semiconductor device. Therefore, when a large glass substrate as described above is used as the substrate, it is preferable to use a substrate with less shrinkage. For example, a large glass substrate having a shrinkage of 20 ppm or less, preferably 10 ppm or less, more preferably 5 ppm or less after heat treatment at 450 ° C., preferably 500 ° C. for 1 hour, is preferably used as the substrate. Good.

  As the substrate 101, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used. You may use what provided the semiconductor element on these board | substrates.

  Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 101. In order to manufacture a flexible semiconductor device, the transistor 100 may be directly formed over a flexible substrate, or the transistor 100 is manufactured over another manufacturing substrate, and then peeled off. May be transposed. Note that a separation layer is preferably provided between the formation substrate and the transistor 100 in order to separate the transistor from the formation substrate and transfer it to the flexible substrate. As the flexible substrate, there is a substrate formed of an organic resin such as polyimide or polyester.

[Base insulating film]
The base insulating film 103 is an insulating film that suppresses diffusion of impurity elements such as hydrogen and moisture from the substrate 101 into the oxide semiconductor film 105. The base insulating film 103 preferably has an effect of supplying part of oxygen to the oxide semiconductor film by heating in the manufacturing process of the transistor 100 and repairing oxygen vacancies in the oxide semiconductor film. . Therefore, the base insulating film 103 is preferably an insulating film containing oxygen, for example, an oxide insulating film such as silicon oxide, gallium oxide, or aluminum oxide, or an oxynitride insulating film such as silicon oxynitride or aluminum oxynitride, or nitride One insulating film selected from a nitrided oxide insulating film such as silicon oxide, or an insulating film in which a plurality of insulating films are stacked. Note that “silicon nitride oxide” refers to a composition having a higher nitrogen content than oxygen, and “silicon oxynitride” refers to a composition having a higher oxygen content than nitrogen. Say.

In order to supply part of oxygen to the oxide semiconductor film by heating, an insulating film from which part of oxygen is released by heating is preferable. Specifically, TDS (Thermal Desorption Spectroscopy: Insulating film in which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ cm ⁻³ or more, preferably 3.0 × 10 ²⁰ cm ⁻³ or more in the temperature programmed desorption gas spectroscopy) analysis It is preferable that

  Hereinafter, a method for quantifying the amount of released oxygen by converting it into oxygen atoms by TDS analysis will be described.

  The amount of gas released when TDS analysis is performed is proportional to the integral value of the spectrum. For this reason, the amount of gas emission can be calculated from the integral value of the spectrum of the insulating film and the ratio of the standard sample to the reference value. The reference value of the standard sample is the ratio of the density of atoms to the integral value of the spectrum of a sample containing a predetermined atom.

For example, the amount of released oxygen molecules (N _O2 ) in the insulating film can be obtained from Equation 1 from the TDS analysis result of a silicon wafer containing hydrogen of a predetermined density as a standard sample and the TDS analysis result of the insulating film. . Here, it is assumed that all the spectra detected by the mass number 32 obtained by the TDS analysis are derived from oxygen molecules. There is CH ₃ OH as the mass number 32, but it is not considered here because it is unlikely to exist. In addition, oxygen molecules including oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 that are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of a spectrum when a standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N _H2 / SH ₂ . S _O2 is an integral value of a spectrum when the insulating film is subjected to TDS analysis. α is a coefficient that affects the spectral intensity in the TDS analysis. For details of Equation 1, Japanese Patent Laid-Open No. Hei 6-275697 can be referred to. In addition, the numerical value of the amount of released oxygen described above was obtained by using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd., and a silicon wafer containing 1 × 10 ¹⁶ cm ⁻² hydrogen atoms as a standard sample. It is a numerical value measured using.

  In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.

Note that N _{2 O 2} is the amount of released oxygen molecules. In the insulating film, the amount of released oxygen when converted to oxygen atoms is twice the amount of released oxygen molecules.

An insulating film which releases part of oxygen by heating includes an insulating film containing oxygen in excess of the stoichiometric composition, for example, silicon oxynitride containing excessive oxygen, or excessive oxygen. There is a silicon oxide (SiO _x (x> 2)) film included. A silicon oxide (SiO _x (x> 2)) film containing excessive oxygen contains oxygen atoms more than twice the number of silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by Rutherford backscattering method.

  Further, hydrogen or moisture contained in the base insulating film 103 diffuses into the oxide semiconductor film (particularly, the first region 107 which is a channel formation region) during the manufacturing process of the transistor 100, so that the resistance of the oxide semiconductor film is reduced. Thus, the electrical characteristics of the transistor 100 may be deteriorated. Therefore, it is preferable that the base insulating film 103 have hydrogen or moisture reduced as much as possible.

  Further, in manufacturing the transistor 100, it is preferable to reduce the content of alkali metals such as Li and Na because they are impurities. In the case where a glass substrate containing an impurity such as an alkali metal is used for the substrate 101, the base insulating film 103 is preferably provided over a nitride insulating film such as silicon nitride or aluminum nitride in order to prevent alkali metal from entering.

[Oxide semiconductor film]
As described above, the oxide semiconductor film 105 includes a first region 107 that does not include a dopant and functions as a channel formation region, and a pair of second regions 109a and 109b that include a dopant and function as an electric field relaxation region. And a pair of third regions 111a and 111b functioning as a source region or a drain region. The resistance of the pair of third regions 111a and 111b is lower than the resistance of the pair of second regions 109a and 109b.

The dopant contained in the pair of second regions 109a and 109b and the pair of third regions 111a and 111b is boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, indium, tin, antimony, helium, neon, argon, krypton. And one or more elements selected from xenon. Note that the dopant concentration contained in the pair of second regions 109a and 109b and the pair of third regions 111a and 111b is preferably 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²² / cm ³ or less.

The first region 107 functioning as a channel formation region is preferably highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the first region 107 is 5 ×. 10 ¹⁹ atoms / cm ³ or less, desirably 5 × 10 ¹⁸ atoms / cm ³ or less, more desirably 5 × 10 ¹⁷ atoms / cm ³ or less. The hydrogen concentration is measured by SIMS. The first region 107 functioning as a channel formation region is preferably in a supersaturated state with more oxygen than the stoichiometric composition.

The first region 107 is preferably highly purified so as to hardly contain impurities such as copper, aluminum, and chlorine. In a manufacturing process of the transistor 100 described later, it is preferable to appropriately select a process in which these impurities are not mixed or attached to the surface of the oxide semiconductor film. It is preferable to remove impurities on the surface of the oxide semiconductor film by exposure to dilute hydrofluoric acid or the like, or plasma treatment (N ₂ O plasma treatment or the like). Specifically, in particular, the copper concentration in the first region 107 is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. In particular, the aluminum concentration of the first region 107 is 1 × 10 ¹⁸ atoms / cm ³ or less. The chlorine concentration in the first region 107 is 2 × 10 ¹⁸ atoms / cm ³ or less. Thus, the transistor 100 can be a transistor having favorable electrical characteristics.

There are very few carriers (close to zero) in the first region 107, and the carrier concentration is less than 1 × 10 ¹⁴ / cm ³ , preferably less than 1 × 10 ¹² / cm ³ , more preferably 1 × 10 ¹¹ / cm 3. Less than ³ .

The transistor 100 using the oxide semiconductor film 105 which is highly purified and contains oxygen that excessively repairs oxygen vacancies manufactured using this embodiment has a current value in an off state (off-state current value) as a channel width. 100 zA / μm per 1 μm at room temperature (1 zA (zeptoampere) is 1 × 10 ⁻²¹ A) or less, preferably 10 zA / μm or less, more preferably 1 zA / μm or less, more preferably 100 yA / μm or less can do.

  The oxide semiconductor film 105 is an oxide semiconductor film having crystallinity such as single crystal or polycrystal (also referred to as polycrystal), or an amorphous oxide semiconductor film.

  The oxide semiconductor film 105 (in particular, the first region 107) may include a non-single crystal, for example. The non-single crystal includes, for example, CAAC (C Axis Aligned Crystal), polycrystal, microcrystal, and amorphous part. The amorphous part has a higher density of defect states than microcrystals and CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (C Axis Crystallized Oxide Semiconductor).

For example, the oxide semiconductor film 105 may include a CAAC-OS. For example, the CAAC-OS is c-axis oriented, and the a-axis and / or the b-axis are not aligned macroscopically.

For example, the oxide semiconductor film 105 may include microcrystal. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. The microcrystalline oxide semiconductor film includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Alternatively, the microcrystalline oxide semiconductor film includes an oxide semiconductor having a crystal-amorphous mixed phase structure with a crystal part of 1 nm to less than 10 nm, for example.

For example, the oxide semiconductor film 105 may include an amorphous part. Note that an oxide semiconductor having an amorphous part is referred to as an amorphous oxide semiconductor. An amorphous oxide semiconductor film has, for example, disordered atomic arrangement and no crystal component. Alternatively, the amorphous oxide semiconductor film is, for example, completely amorphous and has no crystal part.

Note that the oxide semiconductor film 105 may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film includes an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The mixed film may have a stacked structure of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region, for example.

Note that the oxide semiconductor film 105 may include a single crystal, for example.

The oxide semiconductor film 105 preferably includes a plurality of crystal parts, and the c-axis of the crystal parts is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor film is a CAAC-OS film.

  The CAAC-OS film is not completely amorphous. The CAAC-OS film includes an oxide semiconductor with a crystal-amorphous mixed phase structure, for example, including a crystal part and an amorphous part. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film and the boundary between the crystal part and the crystal part are not clear. In addition, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

  The crystal part included in the CAAC-OS film is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is perpendicular to the ab plane The metal atoms are arranged in a triangular shape or a hexagonal shape as viewed from the side, and the metal atoms are arranged in a layered manner or the metal atoms and the oxygen atoms are arranged in a layered manner as seen from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

  Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. In addition, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

  Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, the directions may be different from each other. The crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface.

  In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

  Note that part of oxygen included in the oxide semiconductor film may be replaced with nitrogen.

  In the case where the oxide semiconductor film 105 is a single crystal, a polycrystalline oxide semiconductor film, or a CAAC-OS film, an amorphous oxide semiconductor film is used by increasing planarity of the surface of the oxide semiconductor film. Thus, a transistor with higher field effect mobility than a conventional transistor can be obtained. In order to improve the flatness of the surface of the oxide semiconductor film, it is preferable to form the oxide semiconductor film over a flat surface. Specifically, the average surface roughness (Ra) is preferably 0.15 nm or less, preferably It is good to form on the surface of 0.1 nm or less.

  Ra is an arithmetic mean roughness defined in JIS B0601: 2001 (ISO4287: 1997) expanded to three dimensions so that it can be applied to curved surfaces. It can be expressed as “average value of absolute values” and is defined by the following equation.

Here, the designated surface is a surface to be subjected to roughness measurement, and coordinates (x1, y1, f (x1, y1)), (x1, y2, f (x1, y2)), (x2, y1) , F (x2, y1)), (x2, y2, f (x2, y2)), and a rectangular area obtained by projecting the designated plane onto the xy plane is represented by S ₀ . the height (the average height of the specific surface) and Z _0. Ra can be measured with an atomic force microscope (AFM).

  An oxide semiconductor used for the oxide semiconductor film 105 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain both In and Zn. In addition, it is preferable that gallium (Ga) be included in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide semiconductor. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable to have a zirconium (Zr) as a stabilizer.

  Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), and terbium (Tb). , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

  For example, as an oxide semiconductor material, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn— Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based oxides (also referred to as IGZO) that are ternary metal oxides, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn Oxide, In—La—Zn oxide, In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In—Sm—Zn oxide, In -Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based acid In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu -Zn-based oxides, In-Sn-Ga-Zn-based oxides that are quaternary metal oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In- Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides, and the like can be used.

  Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

  For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1) / 5), or an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 3: 1: 2 (= 1/2: 1/6: 1/3) and oxidation in the vicinity of the composition. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or oxide in the vicinity of the composition Should be used.

  However, the composition is not limited thereto, and a material having an appropriate composition may be used depending on required semiconductor characteristics (mobility, threshold value, variation, etc.). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic distance, the density, and the like are appropriate.

  For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: C, (A + B + C = 1) is the vicinity of r of the oxide composition, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ It refers to meet the r ^2. For example, r may be 0.05. The same applies to other oxides.

  Further, the first region 107, the pair of second regions 109a and 109b, and the pair of third regions 111a and 111b may be in different states in each region. For example, the first region 107 may be a CAAC-OS film, and the pair of second regions 109a and 109b and the pair of third regions 111a and 111b may be single crystal, polycrystalline, or amorphous.

  Further, the oxide semiconductor film 105 may have a stacked structure of a plurality of oxide semiconductor films. For example, the oxide semiconductor film 105 has a two-layer structure of a first oxide semiconductor film and a second oxide semiconductor film, and the first oxide semiconductor film and the second oxide semiconductor film have different compositions. A metal oxide film may be used. For example, a ternary metal oxide may be used for the first oxide semiconductor film, and a binary metal oxide may be used for the second oxide semiconductor film. For example, the first oxide semiconductor film and the second oxide semiconductor film may be ternary metal oxides having different constituent elements.

  Alternatively, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and the compositions of the elements may be different. For example, the atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 3: 1: 2. It is good. The atomic ratio of the first oxide semiconductor film is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor film is In: Ga: Zn = 2: 1: 3. It is good.

  At this time, the content of In and Ga in the oxide semiconductor film (channel side) in contact with the gate electrode 117 out of the first oxide semiconductor film and the second oxide semiconductor film is larger than that of Ga. (In> Ga) is preferable. The content ratio of In and Ga in the oxide semiconductor film in contact with the base insulating film 103 (back channel side) is preferably such that In is less than or equal to Ga (In ≦ Ga).

  In oxide semiconductors, s orbitals of heavy metals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals, so that an oxide semiconductor having a composition of In> Ga. Has higher mobility than an oxide semiconductor having a composition of In ≦ Ga. In addition, since Ga has a larger energy generation energy for oxygen vacancies than In and oxygen vacancies are less likely to occur, an oxide semiconductor having a composition In ≦ Ga is more stable than an oxide semiconductor having a composition In> Ga. With characteristics.

  By applying an oxide semiconductor film having an In> Ga composition to the channel side and applying an oxide semiconductor film having an In ≦ Ga composition to the back channel side, the field-effect mobility and reliability of the transistor can be further increased It becomes possible to raise.

  Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide semiconductor film and the second oxide semiconductor film. In other words, a single crystal oxide semiconductor film, a polycrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or a CAAC-OS film may be combined as appropriate. In addition, when an amorphous oxide semiconductor film is applied to at least one of the first oxide semiconductor film and the second oxide semiconductor film, internal stress and external stress of the oxide semiconductor film 105 are reduced. The variation in the electrical characteristics of the transistor is reduced, and the reliability of the transistor can be further improved.

  On the other hand, an amorphous oxide semiconductor film easily absorbs an impurity serving as a donor such as hydrogen and easily generates oxygen vacancies, so that the resistance is easily reduced. Therefore, the oxide semiconductor film on the channel side is preferably an oxide semiconductor film having crystallinity such as a single crystal oxide semiconductor film, a polycrystalline oxide semiconductor film, or a CAAC-OS film.

  Alternatively, the oxide semiconductor film 105 may have a stacked structure of three or more layers and a structure in which an amorphous oxide semiconductor film is sandwiched between a plurality of crystalline oxide semiconductor films. Alternatively, a structure in which crystalline oxide semiconductor films and amorphous oxide semiconductor films are alternately stacked may be employed.

[Gate insulation film]
The gate insulating film 116 is provided over the insulating film 113 containing oxygen and the insulating film 113 containing oxygen in contact with the first region 107 and the pair of second regions 109a and 109b. Insulating metal oxide film 115 is provided.

  As the insulating film 113 containing oxygen, an insulating film similar to the base insulating film 103 can be used as appropriate. For example, by applying an insulating film from which part of oxygen is released by heating to the insulating film 113 containing oxygen, oxygen released from the oxide semiconductor film is supplied by heat treatment in the manufacturing process of the transistor 100. And oxygen deficiency in the oxide semiconductor film can be repaired. In this manner, the transistor 100 having favorable electrical characteristics can be manufactured.

Further, as the insulating film 113 containing oxygen, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSiO _x N _y (x> 0) , Y> 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)), and high-k materials such as lanthanum oxide can be used. By using such a material, gate leakage current can be reduced.

  In addition, hydrogen or moisture contained in the insulating film 113 containing oxygen diffuses into the oxide semiconductor film (particularly, the first region 107 which is a channel formation region) during the manufacturing process of the transistor 100, so that the oxide semiconductor film is reduced. The resistance of the transistor 100 may be deteriorated, and the electrical characteristics of the transistor 100 may be deteriorated. Thus, it is preferable that hydrogen or moisture be reduced in the insulating film 113 containing oxygen.

The insulating metal oxide film 115 is preferably formed of an inorganic insulating film of a different type from the insulating film 113 containing oxygen, and is particularly preferably formed of a highly dense inorganic insulating film. As the highly dense inorganic insulating film, an aluminum oxide film can be formed by a sputtering method, for example. By setting the aluminum oxide film to a high density (film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), impurities such as moisture in the outside air can be removed from the oxide semiconductor film 105 (in particular, the first The effect of suppressing entry into the region 107) can be obtained. Further, an effect of preventing oxygen contained in the constituent elements of the transistor 100 from being released to the outside of the transistor 100 can be obtained. Therefore, the insulating metal oxide film 115 serves as a barrier film for preventing entry of moisture into the oxide semiconductor film 105 (particularly, the first region 107) during and after the manufacturing process of the transistor 100. Further, since the oxide semiconductor film 105 functions as a barrier film that prevents release of oxygen which is a main component material of the oxide semiconductor film 105, the transistor 100 having favorable electric characteristics can be manufactured. The film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-ray reflectometry (XRR: X-Ray Reflection).

[Gate electrode]
The gate electrode 117 is formed of, for example, a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or chromium, or an alloy material including these materials. Further, the gate electrode 117 may be formed using a conductive metal oxide material. The conductive metal oxide may be abbreviated as indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , ITO). ), Indium zinc oxide (In ₂ O ₃ —ZnO), or a metal oxide material containing silicon or silicon oxide. The gate electrode 117 may be formed using a conductive metal nitride material.

  The gate electrode 117 may be formed with a single layer structure or a stacked layer structure using the above materials. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, and a tantalum nitride film A two-layer structure in which a tungsten film is stacked on top, a two-layer structure in which a tungsten film is stacked on a tungsten nitride film, a titanium film, an aluminum film stacked on the titanium film, and a titanium film formed on the titanium film. There are three-layer structures. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. Note that the gate electrode 117 may function as a gate wiring.

  Further, between the gate electrode 117 and the gate insulating film 116, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Ga—O film containing nitrogen, In—Zn—O film containing nitrogen, Sn—O film containing nitrogen, In—O film containing nitrogen, metal nitride film (indium nitride film, zinc nitride film, tantalum nitride film, tungsten nitride film, etc.) Is preferably provided. These films have a work function of 5 eV, preferably 5.5 eV or more, can have a positive threshold voltage in the electrical characteristics of the transistor 100, and the transistor 100 is a so-called normally-off transistor. Can do. For example, in the case of using an In—Ga—Zn—O film containing nitrogen, an In—Ga—Zn—O film containing at least a nitrogen concentration higher than that of the oxide semiconductor film 105, specifically, 7 atomic% or more of nitrogen atoms is used. Use.

[Sidewall insulation film]
The sidewall insulating film 119 is formed of a nitride insulating film such as silicon nitride or aluminum nitride.

  In addition, since the width of the pair of second regions 109a and 109b corresponds to the width of the sidewall insulating film 119, the sidewalls are set so that the width of the pair of second regions 109a and 109b becomes a desired value. It is preferable to determine the width and thickness of the insulating film 119 and further the thickness of the gate electrode 117. Note that the thickness of the sidewall insulating film 119 here is from the surface in contact with the gate insulating film 116 (particularly the insulating metal oxide film 115) to the topmost portion of the surface in contact with the gate electrode 117. Say.

[Insulating metal oxide film]
The metal oxide film 121 having an insulating property can be formed using the same material as the metal oxide film 115 having an insulating property. In particular, it is preferably formed using a highly dense inorganic insulating film. By using a highly dense inorganic insulating film, a moisture-containing oxide semiconductor film 105 (especially, the first oxide semiconductor film 105 (especially, the first insulating film)) Thus, the transistor 100 having favorable electrical characteristics can be manufactured in order to prevent entry of the oxide into the region 107) and the like, and further, release of oxygen which is a main component material of the oxide semiconductor film 105.

[Interlayer insulation film]
The interlayer insulating film 123 is preferably formed using an inorganic insulating film, and is similar to the base insulating film 103.

[Source electrode and drain electrode]
The source electrode 127a and the drain electrode 127b are similar to the gate electrode 117. In addition, it may be formed of a metal nitride material (titanium nitride, molybdenum nitride, tungsten nitride) containing molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or chromium as a component. In addition, a refractory metal material such as titanium, molybdenum, tungsten, or a metal nitride material of the refractory metal material (titanium nitride, molybdenum nitride, A stacked structure provided with (tungsten nitride) may be used.

<Method for Manufacturing Transistor>
Next, a method for manufacturing the transistor 100 is described with reference to drawings.

  First, the substrate 101 is prepared, the base insulating film 103 is formed over the substrate 101, and the oxide semiconductor film 154 is formed over the base insulating film 103 (see FIG. 2A).

  The substrate 101 is selected from the above listed types, and the base insulating film 103 and the oxide semiconductor film 154 are formed using the above-listed materials. Specifically, the base insulating film 103 and the oxide semiconductor film 154 are formed by a chemical vapor deposition (CVD) method, a sputtering method, a molecular beam epitaxy (MBE) method, or a pulsed laser deposition (PLD) method. : Pulsed Laser Deposition) method. Alternatively, the oxide semiconductor film 154 may be formed using a sputtering apparatus which performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface.

  In this embodiment, a glass substrate is used as the substrate 101. As the base insulating film 103, an insulating film containing oxygen in excess of the stoichiometric composition, specifically, a silicon oxynitride film containing excess oxygen is used. Silicon oxynitride containing excessive oxygen can be formed, for example, by implanting oxygen ions into silicon oxynitride formed by a plasma CVD method using an ion implantation method or an ion doping method. In addition, in order to remove hydrogen and moisture contained in the base insulating film 103, before implanting oxygen ions, a temperature of 300 ° C. or higher and 700 ° C. under reduced pressure, a nitrogen atmosphere, an oxygen atmosphere, or a rare gas atmosphere is used. It is preferable to perform the heat treatment below or below the strain point of the substrate. The thickness of the base insulating film 103 may be 5 nm to 3000 nm, and is 300 nm here.

  Note that the base insulating film 103 is not necessarily provided, and the oxide semiconductor film 154 may be formed directly over the substrate 101. For example, in the case where a flexible substrate is used as the substrate 101, the oxide semiconductor film 154 may be formed over the base insulating film 103 over the flexible substrate, and the oxide semiconductor may be directly formed on the flexible substrate. A film 154 may be formed.

  The oxide semiconductor film 154 is formed with a thickness of 1 nm to 200 nm, preferably 5 nm to 40 nm. In the transistor 100, the first region 107 which is a channel formation region of the oxide semiconductor film 105 is preferably a CAAC-OS; therefore, here, the CAAC-OS film is formed as the oxide semiconductor film 154 by a sputtering method. To 20 nm.

  Note that in the case where the oxide semiconductor film 154 is a single-crystal or polycrystalline oxide semiconductor film or a CAAC-OS film, the planarity of the surface of the base insulating film 103 is improved before the oxide semiconductor film 154 is formed. It is preferable to perform the process for this. In this manner, the oxide semiconductor film 154 with high surface flatness can be formed, and a transistor with higher field-effect mobility can be obtained. Specifically, before the oxide semiconductor film 154 is formed, a polishing process (for example, chemical mechanical polishing: chemical mechanical polishing) is performed so that the average surface roughness (Ra) of the surface of the base insulating film 103 is in the above range. CMP) method), dry etching treatment, and plasma treatment are preferably performed.

  As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Inverse sputtering is a method in which a surface is modified by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also referred to as particles or dust) attached to the surface of the base insulating film 103 can be removed.

  As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case where the steps are performed in combination, the order of steps is not particularly limited, and may be set as appropriate in accordance with the uneven state of the surface of the base insulating film 103.

  There are two methods for obtaining a CAAC-OS film. The first is a method for forming an oxide semiconductor film at a deposition temperature of 200 ° C. to 500 ° C. Second, after forming the first oxide semiconductor film with a thin film thickness, heat treatment is performed at 200 ° C. or more and 700 ° C. or less, and the second oxide semiconductor film is formed thereon, and further 200 ° C. This is a method of heat treatment at 700 ° C. or lower.

  Note that the oxide semiconductor film 154 can be formed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. The oxide semiconductor film 154 is formed under conditions that include a large amount of oxygen at the time of formation (for example, film formation is performed by a sputtering method in an atmosphere containing 100% oxygen) and includes a large amount of oxygen (preferably an oxide film). It is preferable to use a film in which a physical semiconductor includes a region in which the oxygen content is excessive with respect to the stoichiometric composition in the crystalline state.

For example, as a target for forming the oxide semiconductor film 154 using an In—Ga—Zn-based oxide by a sputtering method, for example, the composition is In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: An oxide target of 2 [molar ratio] is used. Without limitation to the material and the composition of the target, for _{example, In 2 O 3: Ga 2} O 3: ZnO = 1: 1: 1 may be used a metal oxide target [mol ratio].

  The filling rate of the metal oxide target is 90% to 100%, preferably 95% to 99.9%. By using a metal oxide target with a high filling rate, the oxide semiconductor film to be formed can be a dense film.

  The metal oxide target that can be used for the oxide semiconductor film 154 is preferably a target having crystallinity such as single crystal or polycrystal. By using a crystalline target, the formed thin film also has crystallinity, and in particular, the formed thin film tends to be a CAAC-OS film.

  The oxide semiconductor film 154 is preferably in a supersaturated state with more oxygen than the stoichiometric composition immediately after the formation. For example, in the case where an oxide semiconductor film is formed by a sputtering method, the film formation is preferably performed under a condition where the proportion of oxygen in the film formation gas is large, and the film formation is performed particularly in an oxygen atmosphere (oxygen gas 100%). It is preferable. When the film is formed in a condition where the proportion of oxygen in the film forming gas is large, particularly in an atmosphere containing 100% oxygen gas, the release of Zn from the film can be suppressed even when the film forming temperature is set to 300 ° C. or higher.

  As a sputtering gas used for forming the oxide semiconductor film 154, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

When the oxide semiconductor film 154 is formed by a sputtering method, the substrate 101 is held in a deposition chamber kept under reduced pressure. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the deposition chamber is removed, and the oxide semiconductor film 154 is formed over the substrate 101 with the use of the above target. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo molecular pump provided with a cold trap. In the film formation chamber evacuated using a cryopump, for example, a compound containing a hydrogen atom (more preferably a compound containing a carbon atom) such as a hydrogen atom or water (H ₂ O) is exhausted. The concentration of impurities contained in the oxide semiconductor film 154 formed in the chamber can be reduced.

  The base insulating film 103 and the oxide semiconductor film 154 are preferably formed continuously without being released to the atmosphere. When the base insulating film 103 and the oxide semiconductor film 154 are successively formed without being exposed to the air, impurities such as hydrogen and moisture can be prevented from being adsorbed on the surface of the base insulating film 103.

  The oxide semiconductor film 154 may be subjected to heat treatment for removing excess hydrogen (including water and a hydroxyl group) (dehydration or dehydrogenation). The temperature of the heat treatment is set to be 300 ° C. or higher and 700 ° C. or lower, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure, a nitrogen atmosphere, an oxygen atmosphere, a rare gas atmosphere, or the like. For example, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and the oxide semiconductor film is subjected to heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere.

  Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Annealing) device such as a GRTA (Gas Rapid Thermal Annealing) device or an LRTA (Lamp Rapid Thermal Annealing) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

  For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650 ° C. to 700 ° C., heated for several minutes, and then the substrate is taken out of the inert gas.

  Note that heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 154, before the formation of the film containing a metal element, and before the step of introducing oxygen into the oxide semiconductor film 154. Any timing may be used in the manufacturing process of the transistor 440.

  When heat treatment for dehydration or dehydrogenation is performed before the oxide semiconductor film 154 is processed into a desired shape, oxygen contained in the base insulating film 103 is prevented from being released by the heat treatment. This is preferable.

  Note that in the heat treatment, it is preferable that water, hydrogen, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

  In addition, after heating the oxide semiconductor film 154 by heat treatment, a dew point of high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) method) is supplied to the same furnace. The amount of water when measured using a meter may be 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less. It is preferable that water, hydrogen, and the like are not contained in the oxygen gas or the dinitrogen monoxide gas. Alternatively, the purity of the oxygen gas or nitrous oxide introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide is 1 ppm or less, preferably 0.1 ppm or less. ) Is preferable. Oxygen is supplied by supplying oxygen, which is a main component material of the oxide semiconductor, which has been reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or dinitrogen monoxide gas. The physical semiconductor film 154 can be highly purified and i-type (intrinsic).

  In addition, by performing heat treatment on the oxide semiconductor film 154 in contact with the base insulating film 103, dehydration or dehydrogenation is performed, and part of oxygen contained in the base insulating film 103 is subjected to the heat treatment. And the interface state density between the oxide semiconductor film 154 and the base insulating film 103 can be reduced, and oxygen vacancies in the oxide semiconductor film 154 can be repaired.

  Then, after the oxide semiconductor film 154 is formed, oxygen ions may be implanted into the oxide semiconductor film 154 by an ion implantation method or an ion doping method. Accordingly, the interface state density between the oxide semiconductor film 154 and the base insulating film 103 can be reduced, and oxygen vacancies in the oxide semiconductor film 154 can be repaired.

  After the oxide semiconductor film 154 is subjected to heat treatment, the oxide semiconductor film 155 is processed by a photolithography process and an etching process (see FIG. 2B). Further, a resist mask for forming the oxide semiconductor film 155 may be formed by an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used. In the photolithography process performed in the subsequent manufacturing process, a resist mask can be formed using a photomask, an inkjet method, or the like.

  Note that the etching of the oxide semiconductor film may be dry etching or wet etching, or both of them may be used. For example, as an etchant used for wet etching of the oxide semiconductor film, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. In addition, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

  Note that the oxide semiconductor film may be processed into a desired shape, or the shape may be left as it is without being processed. Further, an element isolation region including an insulating film that isolates the oxide semiconductor film for each element may be provided.

  Next, an insulating film 156 containing oxygen is formed over the base insulating film 103 and the oxide semiconductor film 155, and an insulating metal oxide film 157 is formed over the insulating film 156 containing oxygen (FIG. 2C )reference).

  The insulating film 156 containing oxygen is formed using a material that can be used for the above-described insulating film 113 containing oxygen. The insulating metal oxide film 157 is formed using a material that is applied to the above-described insulating metal oxide film 115.

  Here, the insulating film 156 containing oxygen is a silicon oxynitride in which oxygen ions are implanted into silicon oxynitride formed by a plasma CVD method using an ion implantation method or an ion doping method. Form. The insulating film 156 containing oxygen is preferably 5 nm to 200 nm, more preferably 5 nm to 50 nm. Here, a silicon oxynitride film is formed to a thickness of 20 nm.

  Note that similarly to the base insulating film 103, heat treatment for dehydrogenation or dehydration of the formed silicon oxynitride film may be performed. The heat treatment may be performed under reduced pressure, a nitrogen atmosphere, an oxygen atmosphere, a rare gas atmosphere, or the like at a temperature greater than or equal to 300 ° C. and less than or equal to 700 ° C. or less than the strain point of the substrate.

  As the metal oxide film 157 having an insulating property, an aluminum oxide film is formed by a sputtering method. The metal oxide film 157 having an insulating property may be 5 nm to 200 nm, more preferably 5 nm to 50 nm. Here, an aluminum oxide film is formed to 20 nm.

  Next, a conductive film 158 is formed using a material that can be used for the above-described gate electrode 117 (see FIG. 2D). The conductive film 158 can be formed by a CVD method, a sputtering method, an MBE method, or a PLD method. Here, a tantalum nitride film is formed to a thickness of 30 nm on the insulating metal oxide film 157 by a sputtering method, and a tungsten film is formed to a thickness of 200 nm on the tantalum nitride film.

  Next, the conductive film 158 is processed into the gate electrode 117 by a photolithography process and an etching process (see FIG. 2E). Since the sidewall insulating film 119 is formed later, the RIE (Reactive) is performed so that the taper angle of the gate electrode 117 is substantially perpendicular to the bottom surface of the gate electrode 117 (the surface of the insulating metal oxide film 157). It is preferable to process by anisotropic etching such as ion etching (reactive ion etching).

  Next, a dopant 159 is implanted into the oxide semiconductor film 155 using the gate electrode 117 as a mask. The first region 107 functioning as a channel formation region and the first region 107 have a lower resistance and include a pair of dopants 159. Regions 108a and 108b are formed (see FIG. 3A). As the dopant 159, one or more selected from boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, indium, tin, antimony, helium, neon, argon, krypton, and xenon may be used. Note that this method may be performed by an ion implantation method or an ion doping method. The dopant may be injected into the oxide semiconductor film 155 by performing plasma treatment or heat treatment in an atmosphere including a dopant that reduces the resistance of the oxide semiconductor film 155. Preferably, an ion implantation method is used.

The implantation of the dopant 159 may be controlled by appropriately setting the implantation conditions such as the acceleration voltage and the dose, and the thickness of the insulating film 113 containing oxygen to be passed and the insulating metal oxide film 157. For example, when phosphorus is implanted by phosphorus ion implantation, an acceleration voltage of 30 kV and a dose of 1 × 10 ¹³ ions / cm ^{2 to} 5 × 10 ¹⁶ ions / cm ² may be used. It may be 1 × 10 ¹⁵ ions / cm ² .

  Note that heat treatment may be performed after the dopant 159 is implanted into the oxide semiconductor film 155 by an ion implantation method. As heating conditions, it is preferable that the temperature is 300 ° C. or higher and 700 ° C. or lower, preferably 300 ° C. or higher and 450 ° C. or lower for 1 hour in an oxygen atmosphere. Further, the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the air (ultra-dry air).

  In the case where the oxide semiconductor film 155 is an oxide semiconductor film having crystallinity, the oxide semiconductor film 155 may be partially amorphized by implantation of the dopant 159. In the case where the region including the dopant 159 in the oxide semiconductor film 155 is amorphous, in the heat treatment in the manufacturing process of the transistor 100 after the implantation of the dopant 159, hydrogen or moisture contained in the first region 107 reduces the dopant 159. It becomes easy to diffuse to the region including it. Accordingly, hydrogen or moisture in the first region 107 is reduced, the first region 107 is highly purified, and the region including the dopant 159 is further reduced in resistance. Note that in this specification, hydrogen or moisture in the first region 107 diffuses into a region including the dopant 159 and hydrogen or moisture in the first region 107 is reduced, which can be referred to as gettering.

  In the case where the region including the dopant 159 in the oxide semiconductor film 155 is amorphous, heat treatment is performed at a temperature at which the amorphous region is crystallized, so that the crystal in the amorphous region can be obtained. Sexuality may be restored.

  Next, an insulating film 161 is formed over the insulating metal oxide film 157 and the gate electrode 117 in order to form the sidewall insulating film 119 (see FIG. 3B).

  The insulating film 161 is processed by anisotropic etching such as RIE, and a sidewall insulating film 119 in contact with the side surface of the gate electrode 117 is formed in a self-aligning manner. Here, the insulating film 161 is preferably formed using a nitride insulating film (eg, a silicon nitride film or an aluminum nitride film) so as not to react with a film containing a metal element to be formed later. The insulating film 161 can be formed by a CVD method, a sputtering method, or the like.

  Next, by using the gate electrode 117 and the sidewall insulating film 119 as a mask, the oxygen-containing insulating film 156 and the insulating metal oxide film 157 are processed by anisotropic etching such as an RIE method, whereby oxygen is removed. A gate insulating film 116 including an insulating film 113 and an insulating metal oxide film 115 is formed (see FIG. 3D). By forming the gate insulating film 116, part of the pair of regions 108a and 108b is exposed.

  Next, a film 162 containing a metal element is formed so as to cover the base insulating film 103, the pair of regions 108a and 108b, the gate insulating film 116, the sidewall insulating film 119, and the gate electrode 117 (see FIG. 4A).

  The film 162 containing a metal element includes aluminum (Al), indium (In), titanium (Ti), tin (Sn), molybdenum (Mo), tungsten (W), zinc (Zn) hafnium (Hf), and tantalum (Ta ), Lanthanum (La), barium (Ba), magnesium (Mg), zirconium (Zr), and nickel (Ni), a metal film containing one or more metal elements can be used. Alternatively, the film 162 containing a metal element may contain an element applicable to the dopant 159 (such as phosphorus (P) or boron (B)). Note that in this embodiment, the film 162 containing a metal element has conductivity.

  The film 162 containing a metal element can be formed by a CVD method, a sputtering method, an MBE method, or a PLD method. The thickness of the film 162 containing a metal element may be 1 nm to 30 nm, preferably 2 nm to 5 nm.

  In this embodiment, an aluminum film with a thickness of 5 nm is formed as the film 162 containing a metal element by a sputtering method.

  Next, heat treatment is performed in a state where the film 162 containing a metal element is in contact with the pair of regions 108a and 108b, and part of the metal element contained in the film 162 containing a metal element is diffused into the pair of regions 108a and 108b. (See FIG. 4B). In the heat treatment, part of the metal element diffuses into a region in contact with the film 162 containing the metal element in the pair of regions 108a and 108b, and the resistance of the region is reduced. Note that in the case where the film 162 containing a metal element contains an element applicable to the dopant 159, part of the element also diffuses into the pair of regions 108a and 108b.

  By the heat treatment, a pair of second regions 109a and 109b having the same resistance as the pair of regions 108a and 108b and a pair of third regions 111a and 111b that are lower resistance regions than the pair of regions 108a and 108b are formed. can do.

  The heat treatment is preferably performed not in an oxygen atmosphere but in a nitrogen atmosphere or a rare gas atmosphere. Note that it can also be performed under a reduced pressure atmosphere. The heating temperature may be 100 ° C. or higher and 700 ° C. or lower, preferably 200 ° C. or higher and 400 ° C. or lower.

  For example, using an electric furnace which is one of heat treatment apparatuses, a film 162 containing a metal element and an oxide semiconductor film (the first region 107 and the pair of regions 108a and 108b) are formed at 300 ° C. in a nitrogen atmosphere. Heat treatment for 1 hour is performed.

  By the heat treatment, the region in contact with the pair of regions 108a and 108b of the film 162 containing a metal element and the region in contact with the base insulating film 103 of the film 162 containing a metal element are paired with the pair of regions 108a and 108b, And oxidized by oxygen contained in the base insulating film 103. In this embodiment mode, aluminum is used for the film 162 containing a metal element; therefore, the region in contact with the pair of regions 108a and 108b and the base insulating film 103 becomes aluminum oxide by the heat treatment. The oxidized region is typically the region 106 shown in FIG. In addition, although it can be said that the oxidation by the heat treatment is also performed by oxygen contained in the first region 107, the first region is formed by a region overlapping with the sidewall insulating films 119 of the pair of regions 108a and 108b. The use of oxygen contained in 107 is suppressed.

  Further, when the heat treatment is performed in an oxygen atmosphere, it can be expected that oxidation from the surface of the film 162 containing a metal element proceeds dominantly. Therefore, the metal element-containing film 162 is sufficiently oxidized before the metal element is sufficiently diffused into the region in contact with the metal element-containing film 162 in the pair of regions 108a and 108b to reduce the resistance. Therefore, it can be expected that the metal element cannot be diffused and it becomes difficult to uniformly and sufficiently reduce the resistance of the region.

  On the other hand, in the case where the heat treatment is performed in a nitrogen atmosphere, a rare gas atmosphere, or a reduced-pressure atmosphere, the film 162 containing a metal element is oxidized from an interface in contact with the pair of regions 108a and 108b; Since the rate of oxidation of the film 162 containing a metal element is slower than in the case of performing the process, and the entire film 162 containing a metal element is not oxidized, the film 162 containing the metal element in the pair of regions 108a and 108b is in contact with the film 162. The metal element can be uniformly and sufficiently diffused in the region, and the pair of third regions 111a and 111b having a uniform and sufficiently low resistance can be formed. Accordingly, a transistor having favorable electrical characteristics can be manufactured with high yield.

  In this manner, since the pair of third regions 111a and 111b with uniform and sufficiently low resistance can be formed, the pair of third regions 111a and 111b functioning as a source region and a drain region, and electric field relaxation The pair of second regions 109a and 109b functioning as regions can be formed more easily and in a shorter time than the method of forming these regions by performing a step of implanting a dopant after forming the sidewall insulating film 119. Therefore, a transistor having favorable electric characteristics can be manufactured with high productivity.

  Note that the step of implanting the dopant 159 performed to form the pair of regions 108a and 108b may be performed at least before and after the film 162 containing a metal element is formed and heat treatment is performed. The dopant 159 here may be any of the elements listed above, but is preferably an element having a large mass such as a rare gas element. For example, when the dopant 159 is argon and argon is injected through the film 162 containing a metal element, the metal element of the film 162 containing a metal element is also pushed into the dopant 159 and injected into the oxide semiconductor film. Further, the region into which the argon in the oxide semiconductor film including the dopant 159 is implanted may be amorphous. When heat treatment is performed in such an amorphous state, hydrogen or moisture contained in the first region 107 easily moves to the amorphous region of the oxide semiconductor film (gettering). . Thus, the first region 107 is highly purified, and the amorphous region is further reduced in resistance.

  Next, the film 162 containing a metal element having an oxidized region is removed by an etching step (see FIG. 4C). In the etching step, the oxidized region has a higher etching rate with respect to an etching gas or an etchant of the film containing the metal element and the oxide semiconductor film having the oxidized region than the other region of the film 162 containing the metal element. Since it is preferable to use the difference, an etching gas or an etchant is selected as appropriate. Note that in dry etching using an etching gas, the film 162 containing a metal element may not be selectively removed depending on the type of the film 162 containing a metal element. For example, in the case where a titanium film is used for the film 162 containing a metal element, the film 162 containing a metal element can be selectively removed by dry etching using a fluorine-based etching gas. As described above, when aluminum is used for the film 162 containing a metal element, it is difficult to selectively remove the film 162 containing a metal element by dry etching. In addition, when an oxidized region is included in the film 162 containing a metal element, it is difficult to selectively remove the film 162 containing a metal element because only the region changes the etching rate. In addition, wet etching tends to change the etching rate depending on the type and composition of the oxide semiconductor film 105 as compared with dry etching. For example, the etching rate of the above-listed types of oxide semiconductor films with respect to the aqueous ammonia solution is slower than the etching rate of the film 162 containing a metal element with respect to the aqueous ammonia solution. Further, the etching rate of the In—Ga-based oxide with respect to the hydrofluoric acid-based etchant is extremely low, and there is a difference in etching rate with the film 162 containing a metal element. Therefore, the etching process is preferably performed by wet etching.

  The heat treatment performed after the formation of the film 162 containing a metal element is performed in a nitrogen atmosphere or a rare gas atmosphere, and the film 162 containing a metal element is oxidized from a region in contact with the pair of regions 108a and 108b. Not all of the film 162 containing the material is oxidized. Therefore, by performing this etching step, all the non-oxidized regions of the film 162 containing a metal element are removed; therefore, in the transistor 100, between the source electrode 127a and the drain electrode 127b through the non-oxidized region. Can be prevented from conducting.

  Next, an insulating metal oxide film 121 is formed to cover the base insulating film 103, the pair of third regions 111a and 111b, the gate insulating film 116, the sidewall insulating film 119, and the gate electrode 117 (FIG. 4 ( D)).

  The metal oxide film 121 having an insulating property is formed in the same manner as the metal oxide film 157 having an insulating property. In particular, the metal oxide film 121 having an insulating property is preferably formed to have a thickness of 5 nm to 200 nm, more preferably 5 nm to 100 nm. In this embodiment mode, sputtering is preferably performed using a highly dense inorganic insulating film. An aluminum oxide film is formed to 70 nm by this method.

  The step of removing the film 162 containing a metal element and forming the insulating metal oxide film 121 as in this embodiment has the following advantages. For example, by heat treatment performed in a state where the film 162 containing a metal element is in contact with the pair of regions 108a and 108b, the entire film 162 containing a metal element is not oxidized, and a part of the film 162 containing a metal element is electrically conductive. In the case where a region having a gate electrode remains, a source electrode 127a and a drain electrode 127b which are to be formed later are brought into conduction through the region and may not function as a transistor. Therefore, the source electrode 127a and the drain electrode 127b can be electrically separated by removing the formed film 162 containing a metal element and forming the insulating metal oxide film 121 again, so that a transistor with high yield can be obtained. 100 can be made.

  Next, an interlayer insulating film 123 is formed over the insulating metal oxide film 121 (see FIG. 5A). The interlayer insulating film 123 may be formed in the same manner as the base insulating film 103. In this embodiment, 400 nm of silicon oxynitride formed by a plasma CVD method is formed.

  Heat treatment is preferably performed after the metal oxide film 121 having insulating properties is formed. The heat treatment can be performed in a manner similar to that performed after the oxide semiconductor film 154 is formed over the base insulating film 103. By the heat treatment, part of oxygen contained in the insulating film 113 containing oxygen contained in the base insulating film 103 and the gate insulating film 116 is converted into the base insulating film 103 and the oxide semiconductor film 105 (particularly, the first region 107). , An interface between the insulating film 113 containing oxygen and the oxide semiconductor film 105 (especially the first region 107), and an interface at each interface supplied to the oxide semiconductor film 105 (especially the first region 107) The level density can be reduced and oxygen vacancies in the oxide semiconductor film 105 (in particular, the first region 107) can be repaired.

  Further, the metal oxide film 121 having an insulating property has an effect of preventing the oxygen contained in the base insulating film 103 and the insulating film 113 containing oxygen from being released to the outside. The density of potential can be reduced and the oxygen deficiency can be repaired. Therefore, the transistor 100 is prevented from trapping carriers at the interface between the base insulating film 103 and the insulating film 113 containing oxygen and the oxide semiconductor film 105 due to operation of the transistor and the like. It becomes a transistor with excellent properties. In addition, the transistor 100 is a transistor having favorable electric characteristics because electrons due to oxygen deficiency are reduced. Further, since the metal oxide film 121 having an insulating property has an effect of preventing impurities such as hydrogen and moisture from the outside from entering from the outside, the transistor 100 is a highly reliable transistor. Note that hydrogen and moisture contained in the interlayer insulating film 123 are removed by the heat treatment.

  Next, openings 125 a and 125 b reaching the pair of third regions 111 a and 111 b are formed in the insulating metal oxide film 121 and the interlayer insulating film 123 (see FIG. 5B). A conductive film is formed in the openings 125a and 125b, and a source electrode 127a and a drain electrode 127b are formed by a photolithography process and an etching process (see FIG. 1B). Note that the source electrode 127a or the drain electrode 127b also functions as a source wiring or a drain wiring, respectively. The conductive film may be formed in the same manner as the conductive film 158 processed into the gate electrode 117.

  Further, a planarization insulating film may be formed over the interlayer insulating film 123 in order to reduce surface unevenness due to the transistor. As the planarization insulating film, an organic material such as polyimide, acrylic, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. Note that the planarization insulating film may be formed by stacking a plurality of insulating films formed using these materials.

  In the method for manufacturing the transistor 100, part of the insulating film 161 is removed so that the gate electrode 117 is exposed when the sidewall insulating film 119 is formed, so that the gate electrode 117 may be thinned. Therefore, an insulating film 170 is formed over the conductive film 158 processed into the gate electrode 117 (see FIG. 6A). After that, a gate electrode 117 and a gate electrode protective film 122 in contact with the upper surface of the gate electrode 117 are formed by a photolithography process and an etching process (see FIG. 6B). Thereafter, steps similar to those for the method for manufacturing the transistor 100 are performed. Note that the insulating film 170 is formed using an insulating film having a different etching rate with respect to an etching gas from the insulating film 161 processed into the sidewall insulating film 119, here, an insulating film having an etching rate slower than that of the insulating film 161. . In this embodiment mode, a nitride insulating film is used as the insulating film 161; therefore, the insulating film 170 is preferably formed using an oxide insulating film, an insulating metal oxide film, or an insulating metal nitride film. When the insulating film 161 is processed to form the sidewall insulating film 119, the gate electrode protective film 122 functions as an etching stopper film, so that the film loss of the gate electrode 117 can be suppressed. A cross-sectional view of a transistor manufactured by this manufacturing method is illustrated in FIG.

  Through the above steps, a transistor in which deterioration of electrical characteristics due to outside air is suppressed can be manufactured with high yield. In addition, according to one embodiment of the present invention, an oxide semiconductor film is provided with two regions having a difference in resistivity from a channel formation region, so that contact resistance with a source electrode and a drain electrode can be reduced, and high oxidation characteristics are obtained. A transistor using a physical semiconductor can be provided. Since the transistor can respond at high speed and can be driven at high speed, a high-performance semiconductor device can be manufactured using the transistor.

  Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, a transistor whose manufacturing method is partly different from the transistor described in Embodiment 1 will be described. The transistor described in this embodiment is different from the transistor described in Embodiment 1 in the shape and formation method of the gate electrode and the sidewall insulating film. In the transistor of one embodiment of the present invention, the gate electrode may have a substantially triangular shape, and the sidewall insulating film may be in contact with at least the side surface of the gate electrode and cover the gate electrode. Therefore, in this embodiment, the drawings and description used in Embodiment 1 can be used as appropriate, and redundant description may be omitted. Note that the transistor described in this embodiment assumes a fine transistor with a gate electrode width of approximately several hundred nm or less.

  The process up to the step of forming the conductive film 158 to be processed into the gate electrode is similar to that in Embodiment Mode 1 (see FIGS. 2A to 2D).

  Next, in order to form a narrow gate electrode, a resist mask 163 wider than a desired gate electrode width is formed (see FIG. 7A). The resist mask 163 can be formed by a photolithography process, an inkjet method, or the like as in Embodiment 1.

  Next, in this embodiment mode, in order to reduce the gate electrode width, the resist mask 163 is reduced by oxygen plasma to form a resist mask 164 having a desired gate electrode width (see FIG. 6B).

  Next, the conductive film 158 is processed by an etching process using the resist mask 164 to form the gate electrode 169 (see FIG. 7C). By the etching process, not only the conductive film 158 but also the resist mask 164 is removed, so that the conductive film 158 overlapping with the resist mask 164 is removed. Therefore, as shown in this embodiment, in a very fine transistor, the gate electrode 169 has a substantially triangular shape as illustrated in FIG.

  Next, using the gate electrode 169 as a mask, a dopant 159 is implanted into the oxide semiconductor film 155 (see FIG. 8A). The description regarding the step of implanting the dopant 159 is the same as that in the first embodiment.

  Next, an insulating film 161 is formed, and a resist mask 171 is formed over the insulating film 161 (see FIG. 8B). After the insulating film 161 is formed in a manner similar to that of Embodiment 1 (see FIG. 3B), the surface of the insulating film 161 is etched by a polishing process such as a CMP method or an etch back process by a dry etching process. It is a planarized insulating film. Since the surface is planarized like the insulating film 161, the resist mask 171 can be accurately formed with respect to the gate electrode 169 having a narrow gate electrode width.

  Next, the insulating film 161 is processed using the resist mask 171 to process the sidewall insulating film 119, the insulating film 156 containing oxygen, and the metal oxide film 157 having an insulating property, and the insulating film 113 containing oxygen and A gate insulating film 116 having an insulating metal oxide film 115 is formed (see FIG. 8C). In this embodiment mode, since the sidewall insulating film is formed using a resist mask, the shape is different from that of the sidewall insulating film in Embodiment Mode 1. Specifically, the sidewall insulating film is in contact with at least the side surface of the gate electrode and covers the gate electrode.

  Next, a film 162 containing a metal element is formed so as to cover the base insulating film 103, the pair of regions 108a and 108b, the gate insulating film 116, and the sidewall insulating film 119, and then the film 162 containing a metal element is formed into the pair of regions 108a. , 108b is heated and part of the metal element contained in the film 162 containing the metal element is diffused into the pair of regions 108a and 108b shown in FIG. 8C (FIG. 9A). reference).

  By the heat treatment, a pair of second regions 109a and 109b having the same resistance as the pair of regions 108a and 108b and a pair of third regions 111a and 111b that are lower resistance regions than the pair of regions 108a and 108b are formed. can do. Note that the description of the heat treatment performed in a state where the film 162 containing a metal element and the film 162 containing a metal element are in contact with the pair of regions 108a and 108b is similar to that in Embodiment 1. Note that the region oxidized by the heat treatment is typically the region 106 illustrated in FIG.

  Next, the film 162 containing a metal element having an oxidized region is removed by a photolithography process and an etching process, and the base insulating film 103, the pair of third regions 111a and 111b, the gate insulating film 116, and the sidewalls are formed again. An insulating metal oxide film 121 is formed so as to cover the insulating film 119 and the gate electrode 117 (see FIG. 9B).

  The description of the step of removing the film 162 containing the metal element having the oxidized region and the step of forming the metal oxide film 121 having an insulating property is the same as in Embodiment Mode 1.

  Thereafter, the same process as in the first embodiment is performed. Specifically, an interlayer insulating film 123 is formed over the insulating metal oxide film 121, and preferably, heat treatment is performed after at least the insulating metal oxide film 121 is formed. Openings 125a and 125b reaching the pair of third regions 111a and 111b are formed in the insulating metal oxide film 121 and the interlayer insulating film 123, and the source electrode 127a and the drain electrode 127b are formed in the openings 125a and 125b. (See FIG. 9C).

  By using the manufacturing method described in this embodiment, a sidewall insulating film for self-aligning an electric field relaxation region, a source region, and a drain region in an oxide semiconductor film can be formed even in a transistor with a narrow gate electrode width. It can be formed with a high yield.

  Through the above steps, a transistor in which deterioration of electrical characteristics due to outside air is suppressed can be manufactured with high yield. In addition, according to one embodiment of the present invention, an oxide semiconductor film is provided with two regions having a difference in resistivity from a channel formation region, so that contact resistance with a source electrode and a drain electrode can be reduced, and high oxidation characteristics are obtained. A transistor using a physical semiconductor can be provided. Since the transistor can respond at high speed and can be driven at high speed, a high-performance semiconductor device can be manufactured using the transistor.

  Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, a transistor whose manufacturing method is partly different from the transistor described in the above embodiment will be described. Therefore, in this embodiment, the drawings and description used in the above embodiment can be used as appropriate, and redundant description may be omitted.

<Example of transistor configuration>
10A and 10B are a top view and a cross-sectional view of the transistor 200. FIG. 10A is a top view of the transistor 200, and FIG. 10B is a cross-sectional view taken along the dashed-dotted line A-B in FIG. 10A. Note that in FIG. 10A, some components of the transistor 200 (eg, the substrate 101, the base insulating film 103, and the gate insulating film 116) are omitted for clarity.

  10A and 10B, in the transistor 200, the base insulating film 103 is provided over the substrate 101, and the source electrode 127a and the drain electrode 127b are provided over the base insulating film 103. An oxide semiconductor film 105 in contact with part of the source electrode 127a and the drain electrode 127b is provided over the base insulating film 103, a gate insulating film 116 is provided over the oxide semiconductor film 105, and the gate insulating film 116 is provided. A gate electrode 117 is provided in a region overlapping with the upper oxide semiconductor film 105, a gate insulating film 116 and a sidewall insulating film 119 in contact with the gate electrode 117 are provided, a base insulating film 103, and an oxide semiconductor Insulating property in contact with part of the film 105, the gate insulating film 116, the gate electrode 117, and the sidewall insulating film 119 The metal oxide film 121 is provided, the interlayer insulating film 123 is provided over the insulating metal oxide film 121, and the opening 125 a formed in the insulating metal oxide film 121 and the interlayer insulating film 123. , 125b, a source wiring 327a and a drain wiring 327b which are in contact with the source electrode 127a and the drain electrode 127b are provided. Note that the base insulating film 103 and the interlayer insulating film 123 are not necessarily provided.

  In the transistor 200, the substrate 101, the base insulating film 103, the oxide semiconductor film 105, the gate insulating film 116, the gate electrode 117, the sidewall insulating film 119, the insulating metal oxide film 121, the interlayer insulating film 123, and the source electrode 127a. The details of the drain electrode 127 b are the same as those of the transistor 100.

  The source wiring 327a and the drain wiring 327b are provided as lead wirings for the source electrode 127a and the drain electrode 127b, and are electrically connected to the source electrode 127a and the drain electrode 127b.

<Method for Manufacturing Transistor>
Next, a method for manufacturing the transistor 200 is described with reference to drawings.

  First, the substrate 101 is prepared, the base insulating film 103 is formed over the substrate 101, and the source electrode 127a and the drain electrode 127b are formed over the base insulating film 103 (see FIG. 11A).

  The substrate 101 can be selected from the types described in Embodiment Mode 1, and the base insulating film 103 can be formed in the same manner as in Embodiment Mode 1.

  The source electrode 127a and the drain electrode 127b are formed as appropriate by using the materials and methods listed in Embodiment 1.

  The subsequent steps are similar to those for the method for manufacturing the transistor 100. An oxide semiconductor film 155 is formed (see FIG. 11B), an insulating film 156 containing oxygen, an insulating metal oxide film 157, and a gate electrode 117 are formed, and then the gate electrode 117 is used as a mask. The dopant 159 is injected into the oxide semiconductor film 155 to form the first region 107 and the pair of regions 108a and 108b (see FIG. 11C), the insulating film 113 containing oxygen, and the insulating metal. A gate insulating film 116 having an oxide film 115 and a sidewall insulating film 119 are formed (see FIG. 11D), and a film 162 containing a metal element is formed to cover at least the pair of regions 108a and 108b, and then heated. The oxide semiconductor film 105 is formed by treatment (see FIG. 12A), the film 162 containing a metal element is removed, and an insulating metal oxide film 121 is formed. (FIG. 12B), an interlayer insulating film 123 is formed, an opening 125a and an opening 125b are formed (see FIG. 12D), and a source wiring 327a and a drain wiring 327b are formed in the opening 125a and the opening 125b. Thus, the transistor 200 can be manufactured (see FIG. 10B).

  Further, heat treatment can be performed as appropriate as in Embodiment 1. For example, heat treatment is preferably performed on the oxide semiconductor film before being processed into the oxide semiconductor film 155, or heat treatment is performed after the metal oxide film 121 having at least an insulating property is formed. By performing the heat treatment, dehydrogenation or dehydration of the oxide semiconductor film occurs and oxygen vacancies in the oxide semiconductor film can be repaired; thus, the transistor 200 having favorable electrical characteristics can be manufactured.

  In the method for manufacturing the transistor 200, when the sidewall insulating film 119 is formed, part of the insulating film 161 is removed so that the gate electrode 117 is exposed, and thus the gate electrode 117 may be reduced in thickness. Therefore, an insulating film 170 is formed over the conductive film 158 processed into the gate electrode 117 (see FIG. 13A). After that, a gate electrode 117 and a gate electrode protective film 122 in contact with the upper surface of the gate electrode 117 are formed by a photolithography process and an etching process (see FIG. 13B). After that, the same process as the manufacturing method of the transistor 200 is performed. Note that the insulating film 170 is formed using an insulating film having a different etching rate with respect to an etching gas from the insulating film 161 processed into the sidewall insulating film 119, here, an insulating film having an etching rate slower than that of the insulating film 161. . In this embodiment mode, a nitride insulating film is used as the insulating film 161; therefore, the insulating film 170 is preferably formed using an oxide insulating film, an insulating metal oxide film, or an insulating metal nitride film. When the insulating film 161 is processed to form the sidewall insulating film 119, the gate electrode protective film 122 functions as an etching stopper film, so that the film loss of the gate electrode 117 can be suppressed. A cross-sectional view of a transistor manufactured by this manufacturing method is illustrated in FIG.

  Through the above steps, a transistor in which deterioration of electrical characteristics due to outside air is suppressed can be manufactured with high yield. In addition, according to one embodiment of the present invention, an oxide semiconductor film is provided with two regions having a difference in resistivity from a channel formation region, so that contact resistance with a source electrode and a drain electrode can be reduced, and high oxidation characteristics are obtained. A transistor using a physical semiconductor can be provided. Since the transistor can respond at high speed and can be driven at high speed, a high-performance semiconductor device can be manufactured using the transistor.

  Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, a transistor whose manufacturing method is partly different from the transistor described in the above embodiment will be described. Therefore, in this embodiment, the drawings and description used in the above embodiment can be used as appropriate, and redundant description may be omitted.

<Example of transistor configuration>
14A and 14B are a top view and a cross-sectional view of the transistor 300. FIG. 14A is a top view of the transistor 300, and FIG. 14B is a cross-sectional view taken along the dashed-dotted line A-B in FIG. Note that in FIG. 14A, some components of the transistor 300 (eg, the substrate 101, the base insulating film 103, and the gate insulating film 116) are omitted for clarity.

  14A and 14B, the transistor 300 includes a base insulating film 103 provided over a substrate 101, an oxide semiconductor film 105 provided over the base insulating film 103, and an oxide semiconductor film. A gate insulating film 116 is provided over the semiconductor film 105, a gate electrode 117 is provided in a region overlapping with the oxide semiconductor film 105 over the gate insulating film 116, and is in contact with the gate insulating film 116 and the gate electrode 117. A sidewall insulating film 119 is provided, and a base insulating film 103, a part of the oxide semiconductor film 105, a gate insulating film 116, a gate electrode 117, and a source electrode 127a and a drain electrode 127b in contact with the sidewall insulating film 119 are provided. An insulating metal oxide film 121 is provided on the source electrode 127a and the drain electrode 127b. An interlayer insulating film 123 and an interlayer insulating film 124 are provided on the insulating metal oxide film 121, and are formed on the insulating metal oxide film 121, the interlayer insulating film 123, and the interlayer insulating film 124. A source wiring 327a and a drain wiring 327b that are in contact with the source electrode 127a and the drain electrode 127b are provided through the openings 125a and 125b. Note that the base insulating film 103 and the interlayer insulating film 124 are not necessarily provided.

  Compared with the transistor 100, the transistor 300 does not have the insulating metal oxide film 121 in direct contact with the pair of third regions 111a and 111b functioning as a source region and a drain region. An insulating metal oxide film 121 is provided over the electrode 127b.

  In the transistor 100, the opening 125a and the opening 125b need to overlap with the pair of third regions 111a and 111b. In the transistor 300, the opening 125a and the opening 125b overlap with the third regions 111a and 111b. It is not necessary to provide it, and the source electrode 127a and the drain electrode 127b may be provided so as to overlap with regions that are not in contact with the third regions 111a and 111b. For example, when transistors are integrated, the transistors can be integrated with high yield even when the processing accuracy for forming the openings 125a and 125b is low.

  In the transistor 300, the substrate 101, the base insulating film 103, the oxide semiconductor film 105, the gate insulating film 116, the gate electrode 117, the sidewall insulating film 119, the insulating metal oxide film 121, the interlayer insulating film 123, and the source electrode 127a. The details of the drain electrode 127 b are the same as those of the transistor 100. Note that the interlayer insulating film 124 is similar to the interlayer insulating film 123.

  The source wiring 327a and the drain wiring 327b are provided as lead wirings for the source electrode 127a and the drain electrode 127b, and are electrically connected to the source electrode 127a and the drain electrode 127b.

<Method for Manufacturing Transistor>
Next, a method for manufacturing the transistor 300 is described with reference to drawings.

  The steps from the step of forming the base insulating film 103 over the substrate 101 to the step of forming the sidewall insulating film 119 are performed in a manner similar to that of Embodiment 1 (see FIGS. 2A to 3D).

  Next, the conductive film 179 processed into the source electrode 127a and the drain electrode 127b over the base insulating film 103, the pair of third regions 111a and 111b, the gate insulating film 116, the gate electrode 117, and the sidewall insulating film 119. (See FIG. 15A). The conductive film 179 is similar to the conductive film 158 processed into the gate electrode 117.

  Next, in a manner similar to that in Embodiment 1, an insulating metal oxide film 121 is formed over the conductive film 179 (see FIG. 15B).

  Next, as in Embodiment 1, an interlayer insulating film 123 is formed over the insulating metal oxide film 121 (see FIG. 15C).

  Next, at least the conductive film 179, the insulating metal oxide film 121, and the interlayer insulating film 123 are exposed by an etch-back process using a polishing process such as a CMP method or a dry etching process (FIG. 16 ( A)). Accordingly, the conductive film 179 can be processed into the source electrode 127a and the drain electrode 127b, and the metal oxide film 121 and the interlayer insulating film 123 having insulating properties are planarized. In addition to the conductive film 179, the insulating metal oxide film 121, and the interlayer insulating film 123, a part of the gate electrode 117 and the sidewall insulating film 119 is formed so that the source electrode 127a and the drain electrode 127b can be electrically separated. It may be removed.

  Next, an interlayer insulating film 124 is formed over the planarized insulating metal oxide film 121, the planarized interlayer insulating film 123, the sidewall insulating film 119, and the gate electrode 117. Note that the interlayer insulating film 124 is similar to the interlayer insulating film 123.

  Openings 125a and 125b reaching the source electrode 127a and the drain electrode 127b are formed in the planarized insulating metal oxide film 121, the planarized interlayer insulating film 123, and the interlayer insulating film 124, and the openings 125a and 125b are formed. The transistor 300 can be manufactured by forming the source wiring 327a and the drain wiring 327b (see FIG. 16C).

  Further, heat treatment can be performed as appropriate as in Embodiment 1. For example, heat treatment is performed on the oxide semiconductor film before being processed into the oxide semiconductor film 155, heat treatment is performed after the oxide semiconductor film 155 is covered with the insulating film 156 containing oxygen, or at least insulating property It is preferable to perform heat treatment after the metal oxide film 121 having n is formed. By performing the heat treatment, dehydrogenation or dehydration of the oxide semiconductor film occurs and oxygen vacancies in the oxide semiconductor film can be repaired; thus, the transistor 300 having favorable electrical characteristics can be manufactured.

  Further, the transistor 300 has a structure in which a gate electrode protective film is provided over the gate electrode 117 in order to prevent the gate electrode 117 from being reduced when the sidewall insulating film 119 is formed as in the transistors 100 and 200. It may be. Note that the gate electrode protective film can be formed in a manner similar to that of the transistor 100 and the transistor 200.

  In the case where the transistor 300 is a transistor having a narrow gate electrode width of approximately several hundred nm or less, the transistor 300 can be manufactured as follows.

  The process from the step of forming the base insulating film 103 over the substrate 101 to the step of forming the sidewall insulating film 119 is performed in a manner similar to that of Embodiment 2 (FIGS. 2A to 2D and FIG. 7). A) to FIG. 8C).

  Thereafter, the same process as the above process is performed. Specifically, the conductive material processed into the source electrode 127a and the drain electrode 127b over the base insulating film 103, the pair of third regions 111a and 111b, the gate insulating film 116, the gate electrode 117, and the sidewall insulating film 119. A film 179 is formed (see FIG. 17A). An insulating metal oxide film 121 is formed over the conductive film 179 (see FIG. 17B). An interlayer insulating film 123 is formed over the insulating metal oxide film 121 (see FIG. 15C). At least the conductive film 179, the insulating metal oxide film 121, and the interlayer insulating film 123 are exposed by an etch-back process using a polishing process such as a CMP method or a dry etching process, and the source electrode 127 a and the drain are exposed. The electrode 127b is formed (see FIG. 18A). An interlayer insulating film 184 is formed over the planarized insulating metal oxide film 121, the planarized interlayer insulating film 123, the sidewall insulating film 119, and the gate electrode 117 (see FIG. 18B). Openings reaching the source electrode 127a and the drain electrode 127b are formed in the planarized insulating metal oxide film 121, the planarized interlayer insulating film 123, and the interlayer insulating film 184, and the source wiring 327a is formed in the openings 125a and 125b. Then, a drain wiring 327b is formed (see FIG. 18C).

  Further, heat treatment can be performed as appropriate as in Embodiment 1. For example, heat treatment is performed on the oxide semiconductor film before being processed into the oxide semiconductor film 155, heat treatment is performed after the oxide semiconductor film 155 is covered with the insulating film 156 containing oxygen, or at least insulating property It is preferable to perform heat treatment after the metal oxide film 121 having n is formed. By performing the heat treatment, dehydrogenation or dehydration of the oxide semiconductor film occurs and oxygen vacancies in the oxide semiconductor film can be repaired; thus, the transistor 300 having favorable electrical characteristics can be manufactured.

  By using the manufacturing method described in this embodiment, a sidewall insulating film for self-aligning an electric field relaxation region, a source region, and a drain region in an oxide semiconductor film can be formed even in a transistor with a narrow gate electrode width. It can be formed with a high yield.

  Through the above steps, a transistor in which deterioration of electrical characteristics due to outside air is suppressed can be manufactured with high yield. In addition, according to one embodiment of the present invention, an oxide semiconductor film is provided with two regions having a difference in resistivity from a channel formation region, so that contact resistance with a source electrode and a drain electrode can be reduced, and high oxidation characteristics are obtained. A transistor using a physical semiconductor can be provided. Since the transistor can respond at high speed and can be driven at high speed, a high-performance semiconductor device can be manufactured using the transistor.

  Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
In this embodiment, a semiconductor device to which the transistor described in any of Embodiments 1 to 4 is applied will be described. Note that in this embodiment, a storage medium (memory element) is illustrated as an example of a semiconductor device, and description is made by using the reference numerals used in the above embodiments as appropriate. Further, in the following embodiment, a transistor to which the transistor described in any of Embodiments 1 to 4 can be applied is denoted as OS in the drawing.

  The semiconductor device includes a first transistor manufactured over a single crystal semiconductor substrate, a second transistor manufactured using a semiconductor film and a capacitor over the first transistor with an insulating film interposed therebetween. Have.

  In addition, the semiconductor materials and structures of the first transistor and the second transistor to be stacked may be the same or different. Here, an example in which transistors each having a material and structure suitable for a circuit of the semiconductor device are used will be described.

  As the second transistor, the transistor described in any of Embodiments 1 to 4 can be used. Note that the stacking relation and connection relation of the first transistor and the capacitor are changed as appropriate depending on the structure of the transistor used as the second transistor. In this embodiment, an example in which the transistor 200 is used as the second transistor is described.

  FIG. 19 illustrates a configuration example of a semiconductor device. FIG. 19A illustrates a cross section of the semiconductor device, and FIG. 19B illustrates a plan view of the semiconductor device. Note that FIG. 19A corresponds to a cross section taken along lines C1-C2 and D1-D2 in FIG. Note that in FIG. 19B, some components of the semiconductor device (for example, the substrate 401, the insulating film 419, the insulating film 423, the insulating film 425, the base insulating film 103, the gate insulating film 116, Side wall insulating films 119 and the like are omitted.

  FIG. 19C illustrates an example of a circuit diagram of the semiconductor device. As a material and a structure suitable for the semiconductor device illustrated in FIGS. 19A and 19B, the transistor 400 using the first semiconductor material is provided in the lower portion, and the second semiconductor material is used in the upper portion. A transistor 200 and a capacitor 450 are included. In this embodiment, the first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is an oxide semiconductor. As a semiconductor material other than an oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. A transistor using such a semiconductor material can operate at a sufficiently high speed. In addition, an organic semiconductor material or the like may be used as a semiconductor material other than an oxide semiconductor. A transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

  A method for manufacturing the semiconductor device in FIGS. 19A to 19C is described with reference to FIGS.

  The transistor 400 includes a channel formation region 407 provided in a substrate 401 containing a semiconductor material (eg, silicon), impurity regions 402a and 402b provided so as to sandwich the channel formation region 407, and impurity regions 402a and 402b. It has intermetallic compound regions 403 a and 403 b that are in contact with each other, a gate insulating film 405 provided over the channel formation region 407, and a gate electrode 417 provided over the gate insulating film 405.

  As the substrate 401 containing a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used. In general, an “SOI substrate” refers to a substrate having a structure in which a silicon semiconductor film is provided on an insulating surface. In this specification and the like, a semiconductor film made of a material other than silicon is provided on an insulating surface. Also includes a substrate of construction. That is, the semiconductor film included in the “SOI substrate” is not limited to the silicon semiconductor film. The SOI substrate includes a substrate in which a semiconductor film is provided over an insulating substrate such as a glass substrate with an insulating film interposed therebetween.

  As a method for manufacturing an SOI substrate, oxygen ions are implanted into a mirror-polished wafer and then heated at a high temperature to form an oxide layer at a certain depth from the surface and to eliminate defects generated in the surface layer. A method, a method of cleaving a semiconductor substrate using growth by heat treatment of microvoids formed by hydrogen ion irradiation, a method of forming a single crystal semiconductor film by crystal growth on an insulating surface, or the like can be used.

  For example, ions are added from one surface of a single crystal semiconductor substrate to form a weakened layer at a certain depth from one surface of the single crystal semiconductor substrate, and one element of the single crystal semiconductor substrate or element An insulating film is formed on one of the substrates. In a state where the single crystal semiconductor substrate and the element substrate are overlapped with an insulating film interposed therebetween, a crack is generated in the weakened layer, and heat treatment is performed to separate the single crystal semiconductor substrate with the weakened layer, and the semiconductor is removed from the single crystal semiconductor substrate. A single crystal semiconductor film is formed over the element substrate as a film. An SOI substrate manufactured by using the above method can also be preferably used.

  An element isolation insulating film 406 is provided over the substrate 401 so as to surround the transistor 400 (see FIG. 19B). Note that in order to achieve high integration, the transistor 400 preferably has a structure in which a sidewall insulating film is not provided. On the other hand, when importance is attached to the electric characteristics of the transistor 400, a sidewall insulating film may be provided on a side surface of the gate electrode 417 and an impurity region including regions having different impurity concentrations may be provided.

  The transistor 400 using a single crystal semiconductor substrate can operate at high speed. Therefore, by using the transistor 400 as a reading transistor, information can be read at high speed. A plurality of insulating films are formed so as to cover the transistor 400. As a treatment before the formation of the transistor 200 and the capacitor 450, CMP treatment is performed on a plurality of insulating films to form planarized insulating films 423 and 425 and further function as a base insulating film of the transistor 200. A base insulating film 103 is formed, and at the same time, the upper surface of the gate electrode 417 is exposed.

  The insulating film 419, the insulating film 423, and the insulating film 425 are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, and a nitrided oxide film. An inorganic insulating film such as an aluminum film can be used. The insulating films 423 and 425 can be formed by a plasma CVD method, a sputtering method, or the like.

  The insulating film 419, the insulating film 423, and the insulating film 425 can be formed using an organic material such as polyimide, an acrylic resin, or a benzocyclobutene resin. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. In the case where an organic material is used for the insulating films 423 and 425, they may be formed by a wet method such as a spin coating method or a printing method.

  Note that a silicon nitride film is preferably used as the insulating film 425 and heat treatment is performed at 450 ° C. to 650 ° C. in a nitrogen atmosphere. Thus, hydrogen contained in the silicon nitride film can be supplied to the transistor 400, and the semiconductor material of the transistor 400 can be hydrogenated. In addition, when a silicon nitride film is used for the insulating film 425, intrusion of hydrogen contained in the transistor 400 and the insulating film 423 during the manufacturing process of the transistor 200 and the capacitor 450 can be suppressed.

  In this embodiment, a 50-nm-thick silicon oxynitride film is formed as the insulating film 419 by a CVD method, a 550-nm-thick silicon oxide film is formed as the insulating film 423 by a sputtering method, and a silicon oxide film is formed as the insulating film 425 by a CVD method. A silicon nitride film having a thickness of 50 nm is formed.

  The transistor 200 and the capacitor 450 are formed over the insulating film 425. The transistor 200 can be manufactured with reference to the description in the above embodiment (see FIGS. 10 to 12).

  Further, since the capacitor 450 is manufactured using the manufacturing process of the transistor 200 in the semiconductor device of this embodiment, the capacitor 450 can be formed over the same plane as the transistor 200. Accordingly, a process for manufacturing the capacitor 450 can be omitted, so that productivity of the semiconductor device can be improved and manufacturing cost can be reduced.

  In the capacitor 450, the source electrode 127a of the transistor 200 is used as one electrode, the gate insulating film 116 of the transistor 200 is used as a dielectric, and the gate electrode 117 of the transistor 200 is used as the other electrode. Note that in the case where the sidewall insulating film 119 of the transistor 200 is formed in a self-aligned manner, an insulating film similar to the sidewall insulating film 119 of the transistor 200 is formed over the other electrode of the capacitor 450.

  The transistor 200 includes a pair of second regions 109a and 109b and a pair of third regions which are lower resistance regions than the first region 107 with the first region 107 functioning as a channel formation region in the channel length direction. With the oxide semiconductor film 105 including 111a and 111b, the transistor 200 has high on-state characteristics (eg, on-state current and field-effect mobility), and thus high-speed operation and high-speed response are possible.

  In addition, the pair of second regions 109a and 109b functions as an electric field relaxation region capable of relaxing an electric field applied to the channel formation region. The pair of third regions 111a and 111b functions as a source region or a drain region. In the oxide semiconductor film 105, the pair of third regions 111a and 111b has the lowest resistance, and the contact resistance with the source electrode 127a and the drain electrode 127b can be reduced. Accordingly, the on-characteristics (eg, on-current and field-effect mobility) of the transistor 200 are high, and high speed operation and high speed response are possible.

  Further, the transistor 200 and the capacitor 450 are provided with an insulating metal oxide film 121, and the insulating metal oxide film 121 has a function of preventing impurities such as hydrogen and moisture contained in the outside air from passing therethrough. Therefore, the reliability of the transistor 200 and the capacitor 450 is favorable. Therefore, the semiconductor device described in this embodiment is a highly reliable semiconductor device.

  The wiring 427 may be formed in a manner similar to that of the source wiring 327a and the drain wiring 327b of the transistor 200. For example, an opening reaching the drain electrode 127b is formed in the insulating metal oxide film 121 and the interlayer insulating film 123, and the wiring 427 is formed in the opening in the same manner as the source wiring 327a and the drain wiring 327b of the transistor 200.

  As described above, a semiconductor device including the transistor 400, the transistor 200, and the capacitor 450 can be manufactured. The transistor 200 is a transistor including the oxide semiconductor film 105 which is highly purified and in which oxygen vacancies are repaired. Therefore, the transistor 200 is a transistor in which variation in electrical characteristics is suppressed.

  Note that the insulating property is sufficiently ensured by the gate insulating film 116 in the capacitor 450. For example, the capacitor 450 may be a capacitor having a structure in which the oxide semiconductor film 105 is provided under the gate insulating film 116. Further, in the semiconductor device described in this embodiment, when a capacitor is unnecessary, a semiconductor device having a structure in which the capacitor 450 is not provided can be used.

  FIG. 19C illustrates an example of a circuit diagram in the case where the above semiconductor device is used as a memory element. In FIG. 19C, one of a source electrode and a drain electrode of the transistor 200 is electrically connected to one of the electrodes of the capacitor 450 and the gate electrode of the transistor 400. The first wiring (1st Line: also referred to as a source line) is electrically connected to the source electrode of the transistor 400, and the second wiring (2nd Line: also referred to as a bit line) is connected to the drain of the transistor 400. It is electrically connected to the electrode. The third wiring (3rd Line: also referred to as a first signal line) is electrically connected to the other of the source electrode and the drain electrode of the transistor 200, and the fourth wiring (4th Line: second signal). (Also referred to as a line) is electrically connected to the gate electrode of the transistor 200. A fifth wiring (5th Line: also referred to as a word line) is electrically connected to the other electrode of the capacitor 450.

  Since the transistor 200 including an oxide semiconductor has a feature of extremely low off-state current, when the transistor 200 is turned off, one of a source electrode and a drain electrode of the transistor 200 and the capacitor 450 The potential of a node (hereinafter, node FG) where one of the electrodes and the gate electrode of the transistor 400 are electrically connected can be held for an extremely long time. By including the capacitor 450, the charge given to the node FG can be easily held, and the held information can be easily read.

  In the case of storing information in the semiconductor device (writing), first, the potential of the fourth wiring is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Here, it is assumed that one of two charges (hereinafter, referred to as a low level charge and a high level charge) giving two different potential levels is given. After that, when the potential of the fourth wiring is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, the node FG is in a floating state, so that a predetermined charge is held in the node FG. It will remain as it is. As described above, information can be stored in the memory cell by accumulating and holding a predetermined amount of charge in the node FG.

  Since the off-state current of the transistor 200 is extremely small, the charge supplied to the node FG is held for a long time. Therefore, the refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, and the power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

When reading stored information (reading), when a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the data is held in the node FG. The transistor 400 takes different states depending on the amount of charge that has been generated. In general, when the transistor 400 is an n-channel transistor, the apparent threshold V _{th_H} of the transistor 400 when the high-level charge is held at the node FG is equal to the transistor when the low-level charge is held at the node FG. This is because it becomes lower than the apparent threshold value V _{th_L} of 400. Here, the apparent threshold value means a potential of the fifth wiring which is necessary for turning on the transistor 400. Therefore, the charge held in the node FG can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 400 is turned “on” when the potential of the fifth wiring is V ₀ (> V _{th_H} ). In the case where the low-level charge is _supplied , the transistor 400 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the stored information can be read by controlling the potential of the fifth wiring and reading the on state or the off state of the transistor 400 (reading the potential of the second wiring).

  In addition, in the case of rewriting stored information, a new potential is supplied to the node FG that holds a predetermined amount of charge by the above writing, whereby the charge related to the new information is held in the node FG. Specifically, the potential of the fourth wiring is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring (the potential related to new information) is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. After that, the potential of the fourth wiring is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge related to new information is held in the node FG. That is, the stored information can be overwritten by performing the same operation (second writing) as the first writing in a state where a predetermined amount of charge is held in the node FG by the first writing. It is.

  In the transistor 200 described in this embodiment, the off-state current of the transistor 200 can be sufficiently reduced by using the oxide semiconductor film 105 which is highly purified and in which oxygen vacancies are repaired. By using such a transistor, a semiconductor device capable of holding stored data for an extremely long time can be obtained even when power is not supplied.

  As described above, the transistor described in any of Embodiments 1 to 4 has low off-state current, high on-state characteristics (eg, on-state current and field-effect mobility), and high-speed operation and high-speed response are possible. In addition, deterioration due to impurities such as hydrogen or moisture contained in the outside air is also suppressed. Therefore, a high-performance and highly reliable semiconductor device can be provided by using the transistor. Further, since the transistor described in any of Embodiments 1 to 4 has favorable electric characteristics, miniaturization of the transistor, and further miniaturization or high integration of the semiconductor device can be achieved.

  Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
In this embodiment, application examples of the semiconductor device including the transistor described in the above embodiment will be described with reference to FIGS.

  20A and 20B illustrate a semiconductor device formed using a plurality of the semiconductor devices illustrated in FIGS. 19A to 19C (hereinafter also referred to as memory cells 550). It is a circuit diagram. FIG. 20A is a circuit diagram of a so-called NAND semiconductor device in which memory cells 460 are connected in series. FIG. 20B is a so-called NOR-type semiconductor device in which memory cells 460 are connected in parallel. It is a circuit diagram of a semiconductor device.

  The semiconductor device illustrated in FIG. 20A includes a source line SL, a bit line BL, a first signal line S1, a plurality of second signal lines S2, a plurality of word lines WL, and a plurality of memory cells 460. In FIG. 20A, the structure includes one source line SL and one bit line BL; however, the present invention is not limited to this, and a structure including a plurality of source lines SL and bit lines BL may be employed.

  In each memory cell 460, the gate electrode of the transistor 400, one of the source electrode or the drain electrode of the transistor 200, and one of the electrodes of the capacitor 450 are electrically connected. The first signal line S1 and the other of the source electrode and the drain electrode of the transistor 200 are electrically connected, and the second signal line S2 and the gate electrode of the transistor 200 are electrically connected. The word line WL and the other electrode of the capacitor 450 are electrically connected.

  Further, the source electrode of the transistor 400 included in the memory cell 460 is electrically connected to the drain electrode of the transistor 400 of the adjacent memory cell 460, and the drain electrode of the transistor 400 included in the memory cell 460 is connected to the drain electrode of the adjacent memory cell 460. It is electrically connected to the source electrode of the transistor 400. Note that the drain electrode of the transistor 400 included in the memory cell 460 provided at one end of the plurality of memory cells connected in series is electrically connected to the bit line. In addition, among the plurality of memory cells connected in series, the source electrode of the transistor 400 included in the memory cell 460 provided at the other end is electrically connected to the source line.

  In the semiconductor device illustrated in FIG. 20A, writing operation and reading operation are performed for each row. The write operation is performed as follows. A potential at which the transistor 200 is turned on is applied to the second signal line S2 in the row where writing is performed, so that the transistor 200 in the row where writing is performed is turned on. Thus, the potential of the first signal line S1 is applied to the gate electrode of the transistor 400 in the designated row, and a predetermined charge is applied to the gate electrode. In this way, data can be written to the memory cell in the designated row.

  The read operation is performed as follows. First, a potential at which the transistor 400 is turned on is applied to the word line WL other than the row where reading is performed regardless of the charge applied to the gate electrode of the transistor 400, and the transistors 400 other than the row where reading is performed are turned on. State. Then, a potential (reading potential) is applied to the word line WL of the row where reading is performed so that the on state or the off state of the transistor 400 is selected by the charge of the gate electrode of the transistor 400. Then, a constant potential is applied to the source line SL, and a reading circuit (not shown) connected to the bit line BL is set in an operating state. Here, since the plurality of transistors 400 between the source line SL and the bit line BL are in an on state except for the row where reading is performed, the conductance between the source line SL and the bit line BL is that of the row where reading is performed. It is determined by the state of the transistor 400 (on state or off state). Since the conductance of the transistor varies depending on the charge of the gate electrode of the transistor 400 in the row to be read, the potential of the bit line BL varies accordingly. By reading the potential of the bit line by the reading circuit, information can be read from the memory cell in the designated row.

  A semiconductor device illustrated in FIG. 20B includes a plurality of source lines SL, bit lines BL, first signal lines S1, second signal lines S2, and word lines WL, and includes a plurality of memory cells 460. The gate electrode of each transistor 400, one of the source electrode or the drain electrode of the transistor 200, and one of the electrodes of the capacitor 450 are electrically connected. Further, the source line SL and the source electrode of the transistor 400 are electrically connected, and the bit line BL and the drain electrode of the transistor 400 are electrically connected. The first signal line S1 and the other of the source electrode and the drain electrode of the transistor 200 are electrically connected, and the second signal line S2 and the gate electrode of the transistor 200 are electrically connected. The word line WL and the other electrode of the capacitor 450 are electrically connected.

  In the semiconductor device illustrated in FIG. 20B, writing operation and reading operation are performed for each row. The writing operation is performed by a method similar to that of the semiconductor device illustrated in FIG. The read operation is performed as follows. First, a potential at which the transistor 400 is turned off is applied to the word line WL other than the row where reading is performed regardless of the charge applied to the gate electrode of the transistor 400, and the transistors 400 other than the row where reading is performed are turned off. State. Then, a potential (reading potential) is applied to the word line WL of the row where reading is performed so that the on state or the off state of the transistor 400 is selected by the charge of the gate electrode of the transistor 400. Then, a constant potential is applied to the source line SL, and a reading circuit (not shown) connected to the bit line BL is set in an operating state. Here, the conductance between the source line SL and the bit line BL is determined by the state (on state or off state) of the transistor 400 in the row where reading is performed. That is, the potential of the bit line BL varies depending on the charge of the gate electrode of the transistor 400 in the row where reading is performed. By reading the potential of the bit line by the reading circuit, information can be read from the memory cell in the designated row.

  In the above description, the amount of information held in each memory cell 460 is 1 bit; however, the structure of the memory device described in this embodiment is not limited thereto. Three or more potentials may be provided to the gate electrode of the transistor 400 to increase the amount of information held in each memory cell 460. For example, in the case where four potentials are applied to the gate electrode of the transistor 400, each memory cell can hold 2-bit information.

  Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 7)
In this embodiment, a semiconductor device to which the transistor described in any of Embodiments 1 to 4 is applied will be described. Note that in this embodiment also, a storage medium (memory element) is shown as an example of a semiconductor device, and a semiconductor device having a structure different from the structure shown in the above embodiment is described.

  FIG. 21A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 21B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 21A will be described, and then the semiconductor device illustrated in FIG. 21B will be described below. In addition, description will be made by appropriately using the reference numerals used in the previous embodiment.

  In the semiconductor device illustrated in FIG. 21A, the bit line BL and the source or drain electrode of the transistor 500 are electrically connected, and the word line WL and the gate electrode of the transistor 500 are electrically connected. The source or drain electrode and one electrode of the capacitor 510 are electrically connected.

  The transistor 500 including an oxide semiconductor has a feature of extremely low off-state current. Therefore, when the transistor 500 is turned off, the potential of one electrode of the capacitor 510 (or the charge accumulated in the capacitor 510) can be held for an extremely long time.

  Next, the case where data is written to and stored in the semiconductor device (memory cell 550) illustrated in FIG.

  First, the potential of the word line WL is set to a potential at which the transistor 500 is turned on, so that the transistor 500 is turned on. Thus, the potential of the bit line BL is applied to one electrode of the capacitor 510 (writing). After that, the potential of the one electrode of the capacitor 510 is held (held) by setting the potential of the word line WL to a potential at which the transistor 500 is turned off and the transistor 500 being turned off.

  Since the off-state current of the transistor 500 is extremely small, the potential of one electrode of the capacitor 510 (or the charge accumulated in the capacitor) can be held for a long time.

  Next, reading of information will be described. When the transistor 500 is turned on, the bit line BL in a floating state and the capacitor 510 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 510. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of one electrode of the capacitor 510 (or the charge accumulated in the capacitor 510).

  For example, the potential of one electrode of the capacitor 510 is V, the capacitance of the capacitor 510 is C, the capacitance component (hereinafter also referred to as bit line capacitance) of the bit line BL is CB, and the bit before the charge is redistributed When the potential of the line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, if the potential of one electrode of the capacitor 510 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell 550, the potential of the bit line BL when the potential V1 is held ( = CB * VB0 + C * V1) / (CB + C)) is higher than the potential of the bit line BL when the potential V0 is held (= CB * VB0 + C * V0) / (CB + C)).

  Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

  As described above, the semiconductor device illustrated in FIG. 21A can hold charge that is accumulated in the capacitor 510 for a long time because the off-state current of the transistor 500 is extremely small. In other words, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

  Next, the semiconductor device illustrated in FIG. 21B is described.

  A semiconductor device illustrated in FIG. 21B includes a memory cell array 551a and a memory cell array 551b each including a plurality of memory cells 550 illustrated in FIG. 21A as a memory circuit in an upper portion, and the memory cell array 551a and the memory cell array in a lower portion. A peripheral circuit 553 necessary for operating 551b is provided. Note that the peripheral circuit 553 is electrically connected to the memory cell array 551a and the memory cell array 551b.

  With the structure shown in FIG. 21B, the peripheral circuit 553 can be provided immediately below the memory cell array 551a and the memory cell array 551b, so that the semiconductor device can be downsized.

  The transistor provided in the peripheral circuit 553 is preferably formed using a semiconductor material different from that of the transistor 500. For example, a first semiconductor material that can be used for the transistor 400 described in Embodiment 5 can be used, and a single crystal semiconductor is preferably used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various circuits (such as a logic circuit and a drive circuit) that require high-speed operation can be suitably realized with the transistor.

  Note that in the semiconductor device illustrated in FIG. 21B, the structure in which the memory cell array 551a, the memory cell array 551b, and the two memory cell arrays are stacked is illustrated; however, the number of stacked memory cell arrays is not limited thereto. Three or more memory cell arrays may be stacked.

  Next, a specific structure of the memory cell 550 illustrated in FIG. 21A will be described with reference to FIGS.

  FIG. 22 shows an example of the configuration of the memory cell 550. FIG. 22A shows a cross-sectional view of the memory cell 550, and FIG. 22B shows a top view of the memory cell 550. Here, FIG. 22A corresponds to a cross section taken along lines E1-E2 and F1-F2 in FIG.

  As the transistor 500 illustrated in FIGS. 22A and 22B, the transistor described in any of Embodiments 1 to 4 can be used. Note that the stacking relationship and connection relationship between the transistor 500 and the capacitor 510 are changed as appropriate depending on the structure of the transistor used in the transistor 500. Here, the transistor 300 described in Embodiment 4 is used as the transistor 500. Therefore, in order to describe the transistor 500, the reference numerals used to describe the transistor 300 are used as appropriate.

  The memory cell 550 includes a transistor 500 and a capacitor 510, and the transistor 500 has a structure similar to that of the transistor 300 described in Embodiment 4 (see FIG. 14B). In addition, the memory cell 550 includes an insulating film 502 provided over the source wiring 327 a and the drain wiring 327 b of the transistor 500 and the interlayer insulating film 124, and an electrode 504 provided over the insulating film 502. An insulating film 506 is provided over the electrode 504. In addition, an opening reaching the drain wiring 327 b is provided in the insulating film 502 and the insulating film 506, and a wiring 508 is provided in the opening. Note that the wiring 508 functions as a wiring for connecting to an adjacent memory cell, and corresponds to the bit line BL in the circuit diagram of FIG.

  The capacitor 510 of the memory cell 550 includes a source wiring 327a that is one electrode, an electrode 504 that is the other electrode, and an insulating film 502 that is a dielectric.

  The insulating film 502 and the insulating film 506 are insulating films used in the transistor 500 (for example, the base insulating film 103, the gate insulating film 116, the sidewall insulating film 119, the insulating metal oxide film 121, and the interlayer insulating film 123). Alternatively, a single layer structure or a stacked layer structure can be formed using a material and a formation method applicable to the interlayer insulating film 124). Note that the insulating film 502 is preferably formed using at least an insulating film applicable to the metal oxide film 121 having an insulating property.

  The electrode 504 and the wiring 508 are formed using a material and a formation method applicable to the electrode or the wiring used in the transistor 500 (the gate electrode 117, the source electrode 127a, the drain electrode 127b, the source wiring 327a, or the drain wiring 327b). Can be formed. For the opening in which the wiring 508 is provided, a method for forming the opening 125 a and the opening 125 b of the transistor 500 can be used. Note that the wiring 508 may be formed so as to be directly connected to the drain electrode 127b.

  The transistor 500 includes a pair of second regions 109a and 109b and a pair of third regions which are lower resistance regions than the first region 107 with the first region 107 functioning as a channel formation region in the channel length direction. With the oxide semiconductor film 105 including 111a and 111b, the transistor 500 has high on-state characteristics (eg, on-state current and field-effect mobility), so that high-speed operation and high-speed response are possible.

  In addition, the pair of second regions 109a and 109b functions as an electric field relaxation region capable of relaxing an electric field applied to the channel formation region. The pair of third regions 111a and 111b functions as a source region or a drain region. In the oxide semiconductor film 105, the pair of third regions 111a and 111b is the region with the lowest resistance, and the contact resistance with the source electrode 127a and the drain electrode 127b can be reduced. Accordingly, the on-characteristics (eg, on-current and field-effect mobility) of the transistor 500 are high, and high-speed operation and high-speed response are possible.

  Further, since the insulating film 502 is provided with an insulating metal oxide film, the transistor 500 has a function of preventing impurities such as hydrogen and moisture contained in the outside air from passing, and thus the reliability of the transistor 500 is improved. Therefore, the semiconductor device described in this embodiment is a highly reliable semiconductor device.

  22A and 22B, the drain electrode 127b of the transistor 500 can also function as a source electrode of a transistor included in an adjacent memory cell. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

  As described above, the plurality of memory cells formed in multiple layers are formed using transistors including an oxide semiconductor. Since a transistor including an oxide semiconductor has a small off-state current, stored data can be held for a long time by using the transistor. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

  As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, sufficiently off) By integrally including a memory circuit using a transistor having a small current, a semiconductor device having characteristics that have never been achieved can be realized. In addition, by providing the peripheral circuit and the memory circuit in a stacked structure, the semiconductor device can be highly integrated.

  As described above, the transistor described in any of Embodiments 1 to 4 has low off-state current, high on-state characteristics (eg, on-state current and field-effect mobility), and high-speed operation and high-speed response are possible. In addition, deterioration due to impurities such as hydrogen or moisture contained in the outside air is also suppressed. Therefore, a high-performance and highly reliable semiconductor device can be provided by using the transistor. Further, since the transistor described in any of Embodiments 1 to 4 has favorable electric characteristics, miniaturization of the transistor, and further miniaturization or high integration of the semiconductor device can be achieved.

  Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 8)
In this embodiment, a semiconductor device to which the transistor described in any of Embodiments 1 to 4 is applied will be described with reference to FIGS.

  FIG. 23A illustrates an example of a semiconductor device having a structure corresponding to a so-called DRAM (Dynamic Random Access Memory). A memory cell array 1120 illustrated in FIG. 23A has a structure in which a plurality of memory cells 1130 are arranged in a matrix. Further, the memory cell array 1120 includes m first wirings and n second wirings. Note that in this embodiment mode, the first wiring is referred to as a bit line BL and the second wiring is referred to as a word line WL.

  The memory cell 1130 includes a transistor 1131 and a capacitor 1132. A gate electrode of the transistor 1131 is connected to the first wiring (word line WL). One of a source electrode and a drain electrode of the transistor 1131 is connected to the second wiring (bit line BL), and the other of the source electrode and the drain electrode of the transistor 1131 is connected to one of the electrodes of the capacitor. ing. In addition, the other electrode of the capacitor is connected to the capacitor line CL and given a constant potential. The transistor described in any of the above embodiments is applied to the transistor 1131.

  The transistor described in any of Embodiments 1 to 4 is formed using a highly purified oxide semiconductor film in which oxygen vacancies are repaired. The off-state current of the transistor is sufficiently low, so that electrical characteristics are reduced. This is a transistor in which fluctuations in are suppressed. By using such a transistor, the semiconductor device shown in FIG. 23A recognized as a so-called DRAM can be used as a substantially nonvolatile memory.

  FIG. 23B illustrates an example of a semiconductor device having a structure corresponding to a so-called SRAM (Static Random Access Memory). A memory cell array 1140 illustrated in FIG. 23B can have a structure in which a plurality of memory cells 1150 are arranged in a matrix. The memory cell array 1140 includes a first wiring (word line WL), a second wiring (bit line BL) and a third wiring (inverted bit line BLB), a power supply potential line VDD, and a ground potential line VSS. .

  The memory cell 1150 includes a first transistor 1151, a second transistor 1152, a third transistor 1153, a fourth transistor 1154, a fifth transistor 1155, and a sixth transistor 1156. The first transistor 1151 and the second transistor 1152 function as selection transistors. One of the third transistor 1153 and the fourth transistor 1154 is an n-channel transistor (here, the fourth transistor 1154), and the other is a p-channel transistor (here, the third transistor 1153). ). That is, the third transistor 1153 and the fourth transistor 1154 form a CMOS circuit. Similarly, the fifth transistor 1155 and the sixth transistor 1156 form a CMOS circuit.

  The first transistor 1151, the second transistor 1152, the fourth transistor 1154, and the sixth transistor 1156 are n-channel transistors, and any of the transistors described in the above embodiments can be used. The third transistor 1153 and the fifth transistor 1155 are p-channel transistors, and a material other than an oxide semiconductor (eg, single crystal silicon) is used for a channel formation region.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 9)
A CPU (Central Processing Unit) can be formed using at least part of a transistor in which an oxide semiconductor is used for a channel formation region.

  FIG. 24A is a block diagram illustrating a specific structure of a CPU. 24A includes an arithmetic circuit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus, and the like. It has an interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM I / F 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 24A is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

  Instructions input to the CPU via the Bus I / F 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

  The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

  In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits.

  In the CPU illustrated in FIG. 24A, the register 1196 is provided with a memory element. As the memory element of the register 1196, the memory element described in any of Embodiments 5 to 8 can be used.

  In the CPU illustrated in FIG. 24A, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, in the memory element included in the register 1196, whether to hold data by a logic element that inverts logic (value) or to hold data by a capacitor element is selected. When holding of data by a logic element that inverts logic (value) is selected, power supply voltage is supplied to the memory element in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor, and supply of power supply voltage to the memory element in the register 1196 can be stopped.

  The power supply is stopped by providing a switching element between the memory element group and the node to which the power supply potential Vdd or the power supply potential Vss is applied as shown in FIG. Can do. The circuits in FIGS. 24B and 24C will be described below.

  FIGS. 24B and 24C illustrate an example of a structure of a memory circuit including a transistor in which an oxide semiconductor is used for a channel formation region as a switching element that controls supply of a power supply potential to the memory element.

  A memory device illustrated in FIG. 24B includes a switching element 1141 and a memory element group 1143 including a plurality of memory elements 1142. Specifically, for each memory element 1142, the memory element described in any of Embodiments 5 to 8 can be used. A high-level power supply potential Vdd is supplied to each memory element 1142 included in the memory element group 1143 through the switching element 1141. Further, each memory element 1142 included in the memory element group 1143 is supplied with the potential of the signal IN and the low-level power supply potential Vss.

  In FIG. 24B, a transistor including an oxide semiconductor in a channel formation region is used as the switching element 1141, and switching of the transistor is controlled by a signal SigA applied to a gate electrode thereof.

  Note that FIG. 24B illustrates a structure in which the switching element 1141 includes only one transistor; however, there is no particular limitation, and a plurality of transistors may be included. In the case where the switching element 1141 includes a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or a combination of series and parallel may be used. May be connected.

  In FIG. 24B, the switching element 1141 controls the supply of the high-level power supply potential Vdd to each memory element 1142 included in the memory element group 1143. The switching element 1141 controls the low-level power supply potential Vdd. The supply of the power supply potential Vss may be controlled.

  FIG. 24C illustrates an example of a memory device in which a low-level power supply potential Vss is supplied to each memory element 1142 included in the memory element group 1143 through the switching element 1141. The switching element 1141 can control supply of the low-level power supply potential Vss to each memory element 1142 included in the memory element group 1143.

  A switching element is provided between the memory element group and a node to which the power supply potential Vdd or the power supply potential Vss is applied to temporarily stop the operation of the CPU and retain data even when the supply of the power supply voltage is stopped. It is possible to reduce power consumption. Specifically, for example, the operation of the CPU can be stopped while the user of the personal computer stops inputting information to an input device such as a keyboard, thereby reducing power consumption. it can.

  Here, the CPU has been described as an example, but the present invention can also be applied to LSIs such as a DSP (Digital Signal Processor), a custom LSI, and an FPGA (Field Programmable Gate Array).

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 10)
In this embodiment, an example in which at least part of a driver circuit and a transistor placed in a pixel portion are formed over the same substrate will be described below.

  The transistor provided in the pixel portion is formed according to the method described in Embodiment Modes 1 to 4. In addition, since the transistor can easily be an n-channel transistor, part of the driver circuit that can be formed using an n-channel TFT in the driver circuit can be formed over the same substrate as the transistor in the pixel portion. . In this manner, a highly reliable display device can be provided by using the transistor described in Embodiments 1 to 4 for the pixel portion and the driver circuit.

  An example of the active matrix display device is illustrated in FIG. A pixel portion 601, a first scan line driver circuit 602, a second scan line driver circuit 603, and a signal line driver circuit 604 are provided over a substrate 600 of the display device. In the pixel portion 601, a plurality of signal lines are extended from the signal line driver circuit 604, and a plurality of scan lines are extended from the first scan line driver circuit 602 and the scan line driver circuit 603. Yes. Note that pixels each including a display element are provided in a matrix in the intersection region between the scan line and the signal line. In addition, the substrate 600 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection unit such as an FPC (Flexible Printed Circuit).

  In FIG. 25A, the first scan line driver circuit 602, the second scan line driver circuit 603, and the signal line driver circuit 604 are formed over the same substrate 600 as the pixel portion 601. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when a drive circuit is provided outside the substrate 600, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 600, the number of connections between the wirings can be reduced, and reliability or yield can be improved.

  An example of a circuit configuration of the pixel portion is shown in FIG. Here, a pixel structure of a VA liquid crystal display panel is shown.

  In this pixel structure, a single pixel has a plurality of pixel electrodes, and a transistor is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, a multi-domain designed pixel has a configuration in which signals applied to individual pixel electrodes are controlled independently.

  The gate wiring 612 of the transistor 616 and the gate wiring 613 of the transistor 617 are separated so that different gate signals can be given. On the other hand, the source or drain electrode 614 functioning as a data line is used in common by the transistor 616 and the transistor 617. As the transistors 616 and 617, any of the transistors described in the above embodiments can be used as appropriate. Thereby, a highly reliable liquid crystal display panel can be provided.

  The first pixel electrode electrically connected to the transistor 616 and the second pixel electrode electrically connected to the transistor 617 have different shapes and are separated by a slit. A second pixel electrode is formed so as to surround the outside of the first pixel electrode extending in a V shape. The timing of the voltage applied to the first pixel electrode and the second pixel electrode is made different between the transistor 616 and the transistor 617, thereby controlling the alignment of the liquid crystal. The transistor 616 is connected to the gate wiring 612, and the transistor 617 is connected to the gate wiring 613. By giving different gate signals to the gate wiring 612 and the gate wiring 613, the operation timings of the transistor 616 and the transistor 617 can be made different.

  In addition, a storage capacitor is formed by the capacitor wiring 610, the gate insulating film functioning as a dielectric, and the capacitor electrode electrically connected to the first pixel electrode or the second pixel electrode.

  The first liquid crystal element 618 is formed by overlapping the first pixel electrode, the liquid crystal layer, and the counter electrode. In addition, a second liquid crystal element 619 is formed by overlapping the second pixel electrode, the liquid crystal layer, and the counter electrode. A multi-domain structure is provided in which a first liquid crystal element 618 and a second liquid crystal element 619 are provided in one pixel.

  Note that the pixel structure illustrated in FIG. 25B is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

  An example of a circuit configuration of the pixel portion is shown in FIG. Here, a pixel structure of a display panel using an organic EL element is shown.

  In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing a light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

  FIG. 25C illustrates an example of a pixel structure to which digital time grayscale driving can be applied as an example of a semiconductor device.

  A structure and operation of a pixel to which digital time gray scale driving can be applied will be described. Here, an example is shown in which two n-channel transistors each using an oxide semiconductor layer for a channel formation region are used for one pixel.

  The pixel 620 includes a switching transistor 621, a driving transistor 622, a light-emitting element 624, and a capacitor 623. In the switching transistor 621, the gate electrode is connected to the scanning line 626, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 625, and the second electrode (the other of the source electrode and the drain electrode) is driven. The transistor 622 is connected to the gate electrode. The driving transistor 622 has a gate electrode connected to the power supply line 627 through the capacitor 623, a first electrode connected to the power supply line 627, and a second electrode connected to the first electrode (pixel electrode) of the light emitting element 624. Has been. The second electrode of the light emitting element 624 corresponds to the common electrode 628. The common electrode 628 is electrically connected to a common potential line formed over the same substrate.

  As the switching transistor 621 and the driving transistor 622, any of the transistors described in the above embodiments can be used as appropriate. Thereby, a display panel using a highly reliable organic EL element can be provided.

  Note that a low power supply potential is set for the second electrode (the common electrode 628) of the light-emitting element 624. Note that the low power supply potential is a potential satisfying the low power supply potential <the high power supply potential with respect to the high power supply potential set in the power supply line 627. For example, GND, 0V, or the like is set as the low power supply potential. Also good. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 624 and a current is passed through the light emitting element 624 to cause the light emitting element 624 to emit light. Each potential is set to be equal to or higher than the forward threshold voltage.

  Note that the capacitor 623 can be omitted by using the gate capacitance of the driving transistor 622 instead. With respect to the gate capacitance of the driving transistor 622, a capacitance may be formed between the channel formation region and the gate electrode.

  Here, in the case of the voltage input voltage driving method, a video signal is input to the gate electrode of the driving transistor 622 so that the driving transistor 622 is in a sufficiently on state or an off state. That is, the driving transistor 622 is operated in a linear region. Since the driving transistor 622 operates in a linear region, a voltage higher than the voltage of the power supply line 627 is applied to the gate electrode of the driving transistor 622. Note that a voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 622) is applied to the signal line 625.

  In addition, when analog grayscale driving is performed instead of digital time grayscale driving, the same pixel structure as that in FIG. 25C can be used by changing signal input.

  When analog gradation driving is performed, a voltage equal to or higher than the forward voltage of the light emitting element 624 and Vth of the driving transistor 622 is applied to the gate electrode of the driving transistor 622. The forward voltage of the light-emitting element 624 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage. Note that when a video signal that causes the driving transistor 622 to operate in the saturation region is input, a current can flow through the light-emitting element 624. In order to operate the driving transistor 622 in the saturation region, the potential of the power supply line 627 is set higher than the gate potential of the driving transistor 622. By making the video signal analog, current corresponding to the video signal can be supplied to the light emitting element 624 to perform analog gradation driving.

  Note that the pixel structure illustrated in FIG. 25C is not limited thereto. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 11)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (a mobile phone or a mobile phone). Large-sized game machines such as portable game machines, portable information terminals, sound reproduction apparatuses, and pachinko machines. Examples of electronic devices each including the semiconductor device described in any of the above embodiments will be described.

  FIG. 26A illustrates a portable information terminal which includes a main body 1001, a housing 1002, display portions 1003a and 1003b, and the like. The display portion 1003b is a touch panel, and screen operations and character input can be performed by touching a keyboard button 1004 displayed on the display portion 1003b. Of course, the display unit 1003a may be configured as a touch panel. By manufacturing a liquid crystal panel or an organic light-emitting panel using the transistor described in the above embodiment as a switching element and applying it to the display portions 1003a and 1003b, the reliability of the display portion of the portable information terminal can be improved. it can.

  FIG. 26A illustrates a function for displaying various types of information (still images, moving images, text images, etc.), a function for displaying a calendar, date, time, or the like on the display unit, and operating or editing information displayed on the display unit. A function, a function of controlling processing by various software (programs), and the like can be provided. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing.

  The portable information terminal illustrated in FIG. 26A may be configured to be able to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

  FIG. 26B shows a portable music player. A main body 1021 is provided with a display portion 1023, a fixing portion 1022 to be attached to the ear, a speaker, operation buttons 1024, an external memory slot 1025, and the like. By manufacturing a liquid crystal panel or an organic light-emitting panel using the transistor described in the above embodiment as a switching element and applying it to the display portion 1023, the reliability of the display portion of the portable music player can be improved.

  Further, if the portable music player shown in FIG. 26B has an antenna, a microphone function, and a wireless function and is linked to a mobile phone, a wireless hands-free conversation is possible while driving a passenger car or the like.

  FIG. 26C illustrates a mobile phone, which includes two housings, a housing 1030 and a housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone 1034, a pointing device 1036, a camera lens 1037, an external connection terminal 1038, and the like. The housing 1030 is provided with a solar battery cell 1040 for charging the portable information terminal, an external memory slot 1041, and the like. The antenna is incorporated in the housing 1031. By applying the transistor described in the above embodiment to the display panel 1032, the reliability of the display portion of the cellular phone can be improved.

  The display panel 1032 includes a touch panel. A plurality of operation keys 1035 displayed as images is illustrated by dashed lines in FIG. Note that a booster circuit for boosting the voltage output from the solar battery cell 1040 to a voltage required for each circuit is also mounted.

  In the display panel 1032, the display direction can be appropriately changed depending on a usage pattern. In addition, since the camera lens 1037 is provided on the same surface as the display panel 1032, a videophone can be used. The speaker 1033 and the microphone 1034 can be used for videophone calls, recording and playing sound, and the like as well as voice calls. Further, the housing 1030 and the housing 1031 can be slid to be in an overlapped state from the developed state as illustrated in FIG. 26C, so that the size of the mobile phone can be reduced.

  The external connection terminal 1038 can be connected to an AC adapter and various types of cables such as a USB cable, and charging and data communication with a personal computer are possible. In addition, a recording medium can be inserted into the external memory slot 1041 so that a larger amount of data can be stored and moved.

  In addition to the above functions, an infrared communication function, a television reception function, or the like may be provided.

  FIG. 26D illustrates an example of a television set. In the television device 1050, a display portion 1053 is incorporated in a housing 1051. An image can be displayed on the display portion 1053. Here, a configuration in which the housing 1051 is supported by a stand 1055 with a built-in CPU is shown. By applying the transistor described in the above embodiment to the display portion 1053, the reliability of the display portion of the television device 1050 can be improved.

  The television device 1050 can be operated with an operation switch provided in the housing 1051 or a separate remote controller. Further, the remote controller may be provided with a display unit that displays information output from the remote controller.

  Note that the television set 1050 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

  In addition, the television device 1050 includes an external connection terminal 1054, a storage medium playback / recording unit 1052, and an external memory slot. The external connection terminal 1054 can be connected to various types of cables such as a USB cable, and data communication with a personal computer or the like is possible. The storage medium playback / recording unit 1052 can insert a disk-shaped recording medium, read data stored in the recording medium, and write data to the recording medium. In addition, an image, a video, or the like stored in the external memory 1056 inserted into the external memory slot can be displayed on the display portion 1053.

  In addition, by applying the memory device described in the above embodiment to the external memory 1056 or the CPU, the highly reliable television device 1050 with sufficiently reduced power consumption can be provided.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Claims (5)

Forming an oxide semiconductor film in which a part of the surface is exposed, a gate insulating film, a gate electrode, and a sidewall insulating film in contact with at least a side surface of the gate electrode;
After forming the film containing a metal element over the exposed oxide semiconductor film, the gate electrode, and the sidewall insulating film, the oxide of the film containing the metal element is subjected to heat treatment in a nitrogen atmosphere. Oxidizes the region in contact with the semiconductor film,
A method for manufacturing a semiconductor device is characterized in that the film containing a metal element having the oxidized region is removed to expose part of the oxide semiconductor film. Forming an oxide semiconductor film in which a part of the surface is exposed, a gate insulating film, a gate electrode, and a sidewall insulating film in contact with at least a side surface of the gate electrode;
After forming the film containing a metal element over the exposed oxide semiconductor film, the gate electrode, and the sidewall insulating film, the oxide of the film containing the metal element is subjected to heat treatment in a nitrogen atmosphere. Oxidizes the region in contact with the semiconductor film,
Said film comprising a metal element having the oxidized region and the by utilizing a difference in etching rate of the etching gas or etchant of the oxide semiconductor film, and removing a film containing a metal element having the oxidized region, said oxide A method for manufacturing a semiconductor device, comprising exposing a part of the surface of a semiconductor film. In claim 1 or claim 2,
The semiconductor is characterized in that the heat treatment is performed at a temperature at which the element of the film containing the metal element diffuses into a region in contact with the film containing the metal element of the oxide semiconductor film and the region has a low resistance. Device fabrication method. Forming an oxide semiconductor film over a substrate having an insulating surface;
Forming an insulating film containing oxygen over the oxide semiconductor film;
Forming an insulating first metal oxide film on the insulating film containing oxygen;
Forming a gate electrode overlying the oxide semiconductor film on the first metal oxide film;
Using the gate electrode as a mask, a dopant is implanted into the oxide semiconductor film,
Forming a sidewall insulating film in contact with the first metal oxide film and the gate electrode;
Removing a part of the insulating film containing oxygen and a part of the first metal oxide film to expose a part of the oxide semiconductor film into which the dopant has been implanted and forming a gate insulating film;
Forming a film containing a metal element covering at least the exposed oxide semiconductor film, removing the film containing the metal element after heat treatment in a nitrogen atmosphere;
A method for manufacturing a semiconductor device, wherein an insulating second metal oxide film is formed to cover an oxide semiconductor film from which a film containing at least the metal element is removed. Oite to claim 4,
In the heat treatment performed by forming the film containing the metal element, the metal element of the film containing the metal element diffuses into a region in contact with the film containing the metal element of the oxide semiconductor film into which the dopant is implanted, The method for manufacturing a semiconductor device is performed at a temperature at which the resistance of the oxide semiconductor film into which the dopant is implanted is lower than that of a region overlapping with the sidewall insulating film.