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JP6075789B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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Publication number
JP6075789B2
JP6075789B2 JP2014016269A JP2014016269A JP6075789B2 JP 6075789 B2 JP6075789 B2 JP 6075789B2 JP 2014016269 A JP2014016269 A JP 2014016269A JP 2014016269 A JP2014016269 A JP 2014016269A JP 6075789 B2 JP6075789 B2 JP 6075789B2
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Prior art keywords
insulating layer
insulating
cavity
resin layer
layer
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JP2015144151A (en
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安田　正治
正治 安田
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

本発明は、絶縁層に設けられたキャビティ内に電子部品が収容されて成る電子部品内蔵型の配線基板の製造方法に関するものである。   The present invention relates to a method of manufacturing a wiring board with a built-in electronic component in which an electronic component is accommodated in a cavity provided in an insulating layer.

まず、図４を基に、従来の製造方法により製造される配線基板Ｂの一例を説明する。
配線基板Ｂは、絶縁板２１と、第１絶縁層２２と、第２絶縁層２３と、配線導体２４と、ソルダーレジスト層２５と、電子部品Ｄとを具備する。 First, an example of a wiring board B manufactured by a conventional manufacturing method will be described with reference to FIG.
The wiring board B includes an insulating plate 21, a first insulating layer 22, a second insulating layer 23, a wiring conductor 24, a solder resist layer 25, and an electronic component D.

絶縁板２１には、電子部品Ｄを収容するキャビティ２６が形成されている。そして、キャビティ２６内に、電子部品Ｄが第１絶縁層２２および第２絶縁層２３により固着された状態で収容されている。
さらに絶縁板２１には、複数のスルーホール２７が形成されている。そして、絶縁板２１の表面およびスルーホール２７内には、配線導体２４が被着されている。絶縁板２１上下の配線導体２４同士は、スルーホール２７を介して電気的に接続される。 The insulating plate 21 is formed with a cavity 26 for accommodating the electronic component D. The electronic component D is accommodated in the cavity 26 in a state of being fixed by the first insulating layer 22 and the second insulating layer 23.
Furthermore, a plurality of through holes 27 are formed in the insulating plate 21. A wiring conductor 24 is deposited on the surface of the insulating plate 21 and in the through hole 27. The wiring conductors 24 above and below the insulating plate 21 are electrically connected through a through hole 27.

第１絶縁層２２は、絶縁板２１の上面に被着されている。第２絶縁層２３は、絶縁板２１の下面に被着されている。第１および第２絶縁層２２，２３には、複数のビアホール２８が形成されている。そして、第１および第２絶縁層２２，２３の表面およびビアホール２８内には、配線導体４が被着されている。第１絶縁層２２上面の配線導体２４の一部は、絶縁板２１上面の配線導体２４にビアホール２８を介して電気的に接続されている。また、第１絶縁層２２表面の配線導体２４の別の一部は、電子部品Ｄの電極Ｔにビアホール２８を介して電気的に接続されている。
さらに第１絶縁層２２の表面に形成された配線導体２４の一部は、ソルダーレジスト層２５に形成された第１開口部２５ａ内に露出して、半導体素子接続パッド２９を形成している。そして、この半導体素子接続パッド２９に、半導体素子Ｓの電極を半田バンプを介して接続することにより、配線基板Ｂの上面に半導体素子Ｓが搭載される。 The first insulating layer 22 is attached to the upper surface of the insulating plate 21. The second insulating layer 23 is attached to the lower surface of the insulating plate 21. A plurality of via holes 28 are formed in the first and second insulating layers 22 and 23. A wiring conductor 4 is deposited on the surfaces of the first and second insulating layers 22 and 23 and the via hole 28. A part of the wiring conductor 24 on the upper surface of the first insulating layer 22 is electrically connected to the wiring conductor 24 on the upper surface of the insulating plate 21 through a via hole 28. In addition, another part of the wiring conductor 24 on the surface of the first insulating layer 22 is electrically connected to the electrode T of the electronic component D through the via hole 28.
Further, a part of the wiring conductor 24 formed on the surface of the first insulating layer 22 is exposed in the first opening 25 a formed in the solder resist layer 25 to form a semiconductor element connection pad 29. The semiconductor element S is mounted on the upper surface of the wiring board B by connecting the electrodes of the semiconductor element S to the semiconductor element connection pads 29 via solder bumps.

第２絶縁層２３下面の配線導体２４の一部は、絶縁板２１下面の配線導体２４にビアホール２８を介して電気的に接続されている。また、第２絶縁層２３下面の配線導体２４の別の一部は、電子部品Ｄの電極Ｔにビアホール２８を介して電気的に接続されている。
第２絶縁層２３の下面に形成された配線導体２４の一部は、ソルダーレジスト層２５に形成された第２開口部２５ｂ内に露出して、外部の電気回路基板と接続するための外部接続パッド３０を形成している。そして、外部接続パッド３０と電気回路基板の電極とを接続することにより、半導体素子Ｓが外部の電気回路基板に電気的に接続され、半導体素子Ｓと外部の電気回路基板との間で配線導体２４および電子部品Ｄを介して信号を伝送することにより半導体素子Ｓが作動する。
電子部品Ｄとしては、例えば半導体素子Ｓへの電力の供給を安定化させるチップコンデンサー等が挙げられる。 A part of the wiring conductor 24 on the lower surface of the second insulating layer 23 is electrically connected to the wiring conductor 24 on the lower surface of the insulating plate 21 through a via hole 28. Further, another part of the wiring conductor 24 on the lower surface of the second insulating layer 23 is electrically connected to the electrode T of the electronic component D through the via hole 28.
A part of the wiring conductor 24 formed on the lower surface of the second insulating layer 23 is exposed in the second opening 25b formed in the solder resist layer 25 and is connected to an external electric circuit board. A pad 30 is formed. Then, by connecting the external connection pad 30 and the electrode of the electric circuit board, the semiconductor element S is electrically connected to the external electric circuit board, and the wiring conductor is connected between the semiconductor element S and the external electric circuit board. The semiconductor element S is activated by transmitting a signal via the electronic component 24 and the electronic component D.
Examples of the electronic component D include a chip capacitor that stabilizes the supply of power to the semiconductor element S.

次に、図５〜図６を基に、従来の配線基板Ｂの製造方法の一例を説明する。なお、図５〜図６においては、製造工程毎の要部を概略断面図で示す。なお、図４と同一の個所については同じ符号を付して詳細な説明は省略する。   Next, an example of a conventional method for manufacturing the wiring board B will be described with reference to FIGS. In addition, in FIGS. 5-6, the principal part for every manufacturing process is shown with a schematic sectional drawing. The same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

まず、図５（ａ）に示すように、スルーホール２７内および上下面に配線導体２４が形成された絶縁板２１を準備する。   First, as shown in FIG. 5A, an insulating plate 21 having a wiring conductor 24 formed in the through hole 27 and on the upper and lower surfaces is prepared.

次に、図５（ｂ）に示すように、絶縁板２１にキャビティ２６を形成する。   Next, as shown in FIG. 5B, the cavity 26 is formed in the insulating plate 21.

次に、図５（ｃ）に示すように、絶縁板２１を粘着シートＮ上に載置する。   Next, as shown in FIG. 5C, the insulating plate 21 is placed on the adhesive sheet N.

次に、図５（ｄ）に示すように、キャビティ２６内に電子部品Ｄを挿入して、キャビティ２６内に露出する粘着シートＮ上に電子部品Ｄを載置する。   Next, as shown in FIG. 5D, the electronic component D is inserted into the cavity 26, and the electronic component D is placed on the adhesive sheet N exposed in the cavity 26.

次に、図５（ｅ）に示すように、絶縁板２１の上側に未硬化の第１樹脂層２２ａを積層するとともに加熱処理して硬化することにより第１絶縁層２２を形成する。これにより電子部品Ｄがキャビティ２６内の所定の位置に固定される。   Next, as shown in FIG.5 (e), the 1st insulating layer 22 is formed by laminating | stacking uncured 1st resin layer 22a on the upper side of the insulating board 21, and heat-processing and hardening | curing it. As a result, the electronic component D is fixed at a predetermined position in the cavity 26.

次に、図６（ｆ）に示すように、粘着シートＮを剥離する。   Next, as shown in FIG. 6F, the adhesive sheet N is peeled off.

次に、図６（ｇ）に示すように、絶縁板２１の下側に未硬化の第２樹脂層２３ａを積層するとともに加熱処理して硬化することにより、第２絶縁層２３を形成する。   Next, as shown in FIG. 6G, the second insulating layer 23 is formed by laminating an uncured second resin layer 23a on the lower side of the insulating plate 21 and curing it by heat treatment.

次に、図６（ｈ）に示すように、第１および第２絶縁層２２、２３に複数のビアホール２８を形成する。一部のビアホール２８は、電子部品Ｄの電極Ｔを底面としている。また、別のビアホール２８は、絶縁板２１上の配線導体２４を底面としている。ビアホール２８を形成した後は、第１および第２絶縁層２２、２３の表面を粗化処理する。   Next, as shown in FIG. 6H, a plurality of via holes 28 are formed in the first and second insulating layers 22 and 23. Some of the via holes 28 have the electrode T of the electronic component D as a bottom surface. Another via hole 28 has the wiring conductor 24 on the insulating plate 21 as a bottom surface. After the via hole 28 is formed, the surfaces of the first and second insulating layers 22 and 23 are roughened.

次に、図６（ｉ）に示すように、第１および第２絶縁層２２、２３の表面およびビアホール２８内に配線導体２４を被着させる。
なお、上述の粗化処理により、配線導体２４と第１および第２絶縁層２２、２３の表面との密着力が向上する。 Next, as shown in FIG. 6I, the wiring conductor 24 is deposited on the surfaces of the first and second insulating layers 22 and 23 and the via hole 28.
Note that the above-described roughening treatment improves the adhesion between the wiring conductor 24 and the surfaces of the first and second insulating layers 22 and 23.

最後に、図６（ｊ）に示すように、第１および第２絶縁層２２、２３の表面に形成された配線導体２４の一部を露出させる第１開口部２５ａおよび第２開口部２５ｂを有するソルダーレジスト層２５を、第１絶縁層２２の上面および第２絶縁層２３の下面に被着することで配線基板Ｂが形成される。   Finally, as shown in FIG. 6 (j), the first opening 25a and the second opening 25b that expose a part of the wiring conductor 24 formed on the surfaces of the first and second insulating layers 22 and 23 are formed. The wiring board B is formed by depositing the solder resist layer 25 having the upper surface of the first insulating layer 22 and the lower surface of the second insulating layer 23.

ところで、このような方法で配線基板Ｂを形成する場合には、第１樹脂層２２ａを硬化する１回目の加熱工程と、第２樹脂層２３ａを硬化する２回目の加熱工程とがある。
このため、第１絶縁層２２は、第２絶縁層２３よりも多くの加熱履歴を受けており、第２絶縁層２３よりも硬化度合が進んでいる。第１および第２絶縁層は、その硬化度合いが進むにしたがって粗化がされにくくなる。
したがって、第１絶縁層２２と、第２絶縁層２３との硬化度合が異なると、図６（ｈ）で説明した粗化処理において、第１絶縁層２２表面の粗化状態と、第２絶縁層２３表面の粗化状態とが異なってしまう。具体的には、第１絶縁層２２表面の粗化が小さいのに対して、第２絶縁層２３表面の粗化が大きくなる。そのため、第１絶縁層２２表面に形成される配線導体２４の密着力と、第２絶縁層２３表面に形成される配線導体２４の密着力とにバラツキが生じてしまい、安定した密着力を有する配線導体２４を形成できないという問題がある。
なお、第１および第２絶縁層の硬化度合の差を小さくするために、第２樹脂層２３ａを積層する時点では先に積層された第１樹脂層２２ａを半硬化状態にとどめておき、第２樹脂層２３ａの硬化時に第１樹脂層２２ａもあわせて完全に硬化することも考えられる。
しかし、電子部品Ｄが第１樹脂層２２ａにより完全に固定されていないため、第２樹脂層２３ａ硬化時に、第１および第２樹脂層２２ａ、２３ａの熱伸縮により電子部品Ｄの位置が変動して所定の位置に内蔵できない場合がある。 By the way, when the wiring board B is formed by such a method, there are a first heating process for curing the first resin layer 22a and a second heating process for curing the second resin layer 23a.
For this reason, the first insulating layer 22 has received a larger heating history than the second insulating layer 23, and the degree of cure is higher than that of the second insulating layer 23. The first and second insulating layers are less likely to be roughened as the degree of curing progresses.
Therefore, if the first insulating layer 22 and the second insulating layer 23 have different degrees of curing, the roughening state of the surface of the first insulating layer 22 and the second insulation in the roughening process described with reference to FIG. The roughened state on the surface of the layer 23 is different. Specifically, the surface of the first insulating layer 22 is less rough, whereas the surface of the second insulating layer 23 is roughened. For this reason, the adhesion force of the wiring conductor 24 formed on the surface of the first insulating layer 22 and the adhesion force of the wiring conductor 24 formed on the surface of the second insulating layer 23 vary, and the adhesion force is stable. There is a problem that the wiring conductor 24 cannot be formed.
In order to reduce the difference in the degree of cure between the first and second insulating layers, the first resin layer 22a previously laminated is kept in a semi-cured state when the second resin layer 23a is laminated. It is also conceivable that the first resin layer 22a is cured completely when the two resin layers 23a are cured.
However, since the electronic component D is not completely fixed by the first resin layer 22a, the position of the electronic component D fluctuates due to thermal expansion and contraction of the first and second resin layers 22a and 23a when the second resin layer 23a is cured. May not be built in place.

特許第４０５４２１６号公報Japanese Patent No. 4054216

本発明は、第１絶縁層表面の硬化度合と第２絶縁層表面の硬化度合との差を抑えて、第１絶縁層表面の粗化状態と第２絶縁層表面の粗化状態との差を小さくすることで、第１絶縁層表面に形成される配線導体の密着力と、第２絶縁層表面に形成される配線導体の密着力とのバラツキが小さい安定した密着力を有する配線導体を備えた配線基板を提供することを課題とする。   The present invention suppresses the difference between the degree of cure of the first insulating layer surface and the degree of cure of the second insulating layer surface, and the difference between the roughened state of the first insulating layer surface and the roughened state of the second insulating layer surface. The wiring conductor having a stable adhesion force in which the variation between the adhesion force of the wiring conductor formed on the surface of the first insulating layer and the adhesion force of the wiring conductor formed on the surface of the second insulating layer is small. It is an object to provide a wiring board provided.

本発明の配線基板の製造方法は、一方の主面側から他方の主面側に貫通するキャビティを有する絶縁板を準備する工程と、キャビティ内に電子部品を挿入するとともに、一方の主面に、該一方の主面およびキャビティを覆う未硬化の第１樹脂層を、電子部品に密着してキャビティ内の隙間の一部を充填するように被着する工程と、第１樹脂層を硬化させ、硬化した第１樹脂層により電子部品をキャビティ内に固定する工程と、他方の主面に、他方の主面およびキャビティを覆う未硬化の第２樹脂層を、キャビティ内の隙間の残部を充填するように被着するとともに、第１樹脂層の外側主面に、外側主面を覆う未硬化の第３樹脂層を被着する工程と、第２および第３樹脂層を硬化させ、一方の主面上に第１および第３樹脂層から成る第１絶縁層と、他方の主面上に第２樹脂層から成る第２絶縁層とを形成する工程と、第１および第２絶縁層の表面を粗化する工程と、粗化された第１および第２絶縁層の表面に配線導体を形成する工程とを含むことを特徴とするものである。   The method for manufacturing a wiring board according to the present invention includes a step of preparing an insulating plate having a cavity penetrating from one main surface side to the other main surface side, inserting an electronic component into the cavity, and Applying the uncured first resin layer covering the one main surface and the cavity so as to be in close contact with the electronic component and filling a part of the gap in the cavity; and curing the first resin layer. The step of fixing the electronic component in the cavity with the cured first resin layer, and the other main surface is filled with an uncured second resin layer covering the other main surface and the cavity, and the remainder of the gap in the cavity is filled A step of applying an uncured third resin layer covering the outer main surface to the outer main surface of the first resin layer, curing the second and third resin layers, A first insulating layer comprising first and third resin layers on the main surface A step of forming a second insulating layer made of the second resin layer on the other main surface, a step of roughening the surfaces of the first and second insulating layers, and a roughened first and second insulation. And a step of forming a wiring conductor on the surface of the layer.

本発明の配線基板の製造方法によれば、絶縁板に形成されたキャビティ内の電子部品を、電子部品に密着して絶縁板の一方の主面に被着された未硬化の第１樹脂層を硬化させることによりキャビティ内に固定する。そして、絶縁板の他方の主面に未硬化の第２樹脂層を被着するとともに、第１樹脂層の外側主面に未硬化の第３樹脂層を被着する。その後に、第２および第３樹脂層を硬化させて一方の主面上に第１および第３樹脂層から成る第１絶縁層と、他方の主面上に第２樹脂層から成る第２絶縁層とを形成する。このようにすることで、第１および第２絶縁層表面における硬化履歴が同じとなる。したがって、第１および第２絶縁層表面の硬化度合は略同一となる。これにより、第１絶縁層表面および第２絶縁層表面を粗化処理する際に、両表面の粗化状態は略同一となる。その結果、第１絶縁層表面に形成される配線導体の密着力と、第２絶縁層表面に形成される配線導体の密着力とのバラツキが小さい安定した密着力を有する配線導体を備えた配線基板を提供することができる。   According to the method for manufacturing a wiring board of the present invention, an uncured first resin layer in which an electronic component in a cavity formed on an insulating plate is attached to one main surface of the insulating plate in close contact with the electronic component. Is fixed in the cavity by curing. Then, an uncured second resin layer is applied to the other main surface of the insulating plate, and an uncured third resin layer is applied to the outer main surface of the first resin layer. Thereafter, the second and third resin layers are cured to form a first insulating layer composed of the first and third resin layers on one main surface and a second insulating layer composed of the second resin layer on the other main surface. Forming a layer. By doing in this way, the hardening history in the 1st and 2nd insulating layer surface becomes the same. Therefore, the degree of cure of the first and second insulating layer surfaces is substantially the same. Thereby, when roughening the surface of the first insulating layer and the surface of the second insulating layer, the roughened state of both surfaces becomes substantially the same. As a result, the wiring provided with a wiring conductor having a stable adhesion force with little variation between the adhesion force of the wiring conductor formed on the surface of the first insulating layer and the adhesion force of the wiring conductor formed on the surface of the second insulating layer A substrate can be provided.

図１は、本発明の製造方法により製造される配線基板の実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board manufactured by the manufacturing method of the present invention. 図２（ａ）〜（ｅ）は、本発明の製造方法における実施形態の一例を説明するための工程毎の要部概略断面図である。FIGS. 2A to 2E are schematic cross-sectional views of main parts for each step for explaining an example of the embodiment in the production method of the present invention. 図３（ｆ）〜（ｊ）は、本発明の製造方法における実施形態の一例を説明するための工程毎の要部概略断面図である。FIGS. 3F to 3J are schematic cross-sectional views of main parts for each process for explaining an example of the embodiment in the manufacturing method of the present invention. 図４は、従来の製造方法により製造される配線基板の実施形態の一例を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing an example of an embodiment of a wiring board manufactured by a conventional manufacturing method. 図５（ａ）〜（ｅ）は、従来の製造方法における実施形態の一例を説明するための工程毎の要部概略断面図である。5 (a) to 5 (e) are schematic cross-sectional views of main parts for each step for explaining an example of an embodiment in a conventional manufacturing method. 図６（ｆ）〜（ｊ）は、従来の製造方法における実施形態の一例を説明するための工程毎の要部概略断面図である。FIGS. 6F to 6J are schematic cross-sectional views of main parts for each process for explaining an example of the embodiment in the conventional manufacturing method.

まず、図１を基に、本発明の製造方法により製造される配線基板Ａの一例を説明する。
配線基板Ａは、絶縁板１と、第１絶縁層２と、第２絶縁層３と、配線導体４と、ソルダーレジスト層５と、電子部品Ｄとを具備する。 First, an example of a wiring board A manufactured by the manufacturing method of the present invention will be described with reference to FIG.
The wiring board A includes an insulating plate 1, a first insulating layer 2, a second insulating layer 3, a wiring conductor 4, a solder resist layer 5, and an electronic component D.

絶縁板１には、電子部品Ｄを収容するキャビティ６が形成されている。そして、キャビティ６内に、電子部品Ｄが第１絶縁層２および第２絶縁層３により固着された状態で収容されている。
また、絶縁板１には、複数のスルーホール７が形成されている。そして、絶縁板１の表面およびスルーホール７内に配線導体４が被着されており、絶縁板１上下の配線導体４同士がスルーホール７を介して電気的に接続される。 The insulating plate 1 is formed with a cavity 6 for accommodating the electronic component D. In the cavity 6, the electronic component D is accommodated in a state of being fixed by the first insulating layer 2 and the second insulating layer 3.
A plurality of through holes 7 are formed in the insulating plate 1. The wiring conductor 4 is attached to the surface of the insulating plate 1 and in the through hole 7, and the wiring conductors 4 above and below the insulating plate 1 are electrically connected to each other through the through hole 7.

第１絶縁層２は、絶縁板１の上面に被着されている。第２絶縁層３は、絶縁板１の下面に被着されている。これらの第１および第２絶縁層２、３には、複数のビアホール８が形成されている。そして、第１および第２の絶縁層２、３の表面およびビアホール８内には、配線導体４が被着されている。なお、この配線基板Ａにおいては、第１絶縁層２は、電子部品Ｄをキャビティ内に固定する第１樹脂層２ａと、この第１樹脂層２ａ上に積層された第３樹脂層２ｂとから成る。第１樹脂層２ａは単独で硬化され、第３樹脂層２ｂは第２絶縁層３と同時に硬化されている。
第１絶縁層２上面の配線導体４の一部は、絶縁板１上面の配線導体４にビアホール８を介して電気的に接続されている。また、第１絶縁層２表面の配線導体４の別の一部は、電子部品Ｄの電極Ｔにビアホール８を介して電気的に接続されている。
さらに第１絶縁層２の表面に形成された配線導体４の一部は、ソルダーレジスト層５に形成された第１開口部５ａ内に露出して、半導体素子接続パッド９を形成している。そして、この半導体素子接続パッド９に、半導体素子Ｓの電極を半田バンプを介して接続することにより、配線基板Ａの上面に半導体素子Ｓが搭載される。 The first insulating layer 2 is attached to the upper surface of the insulating plate 1. The second insulating layer 3 is attached to the lower surface of the insulating plate 1. A plurality of via holes 8 are formed in the first and second insulating layers 2 and 3. A wiring conductor 4 is deposited on the surfaces of the first and second insulating layers 2 and 3 and the via hole 8. In the wiring board A, the first insulating layer 2 includes a first resin layer 2a that fixes the electronic component D in the cavity, and a third resin layer 2b that is laminated on the first resin layer 2a. Become. The first resin layer 2 a is cured alone, and the third resin layer 2 b is cured simultaneously with the second insulating layer 3.
A part of the wiring conductor 4 on the upper surface of the first insulating layer 2 is electrically connected to the wiring conductor 4 on the upper surface of the insulating plate 1 through a via hole 8. Further, another part of the wiring conductor 4 on the surface of the first insulating layer 2 is electrically connected to the electrode T of the electronic component D through the via hole 8.
Further, a part of the wiring conductor 4 formed on the surface of the first insulating layer 2 is exposed in the first opening 5 a formed in the solder resist layer 5 to form a semiconductor element connection pad 9. Then, the semiconductor element S is mounted on the upper surface of the wiring board A by connecting the electrodes of the semiconductor element S to the semiconductor element connection pads 9 via solder bumps.

第２絶縁層３下面の配線導体４の一部は、絶縁板１下面の配線導体４にビアホール８を介して電気的に接続されている。また、第２絶縁層３下面の配線導体４の別の一部は、電子部品Ｄの電極Ｔにビアホール８を介して電気的に接続されている。
また、第２絶縁層３の下面に形成された配線導体４の一部は、ソルダーレジスト層５に形成された第２開口部５ｂ内に露出して、外部の電気回路基板と接続するための外部接続パッド１０を形成している。そして、外部接続パッド１０と電気回路基板の電極とを接続することにより、半導体素子Ｓが外部の電気回路基板に電気的に接続され、半導体素子Ｓと外部の電気回路基板との間で配線導体４および電子部品Ｄを介して信号を伝送することにより半導体素子Ｓが作動する。
電子部品Ｄとしては、例えば半導体素子Ｓへの電力の供給を安定化させるチップコンデンサー等が挙げられる。 A part of the wiring conductor 4 on the lower surface of the second insulating layer 3 is electrically connected to the wiring conductor 4 on the lower surface of the insulating plate 1 through a via hole 8. Further, another part of the wiring conductor 4 on the lower surface of the second insulating layer 3 is electrically connected to the electrode T of the electronic component D through the via hole 8.
In addition, a part of the wiring conductor 4 formed on the lower surface of the second insulating layer 3 is exposed in the second opening 5b formed in the solder resist layer 5, and is connected to an external electric circuit board. External connection pads 10 are formed. Then, by connecting the external connection pad 10 and the electrode of the electric circuit board, the semiconductor element S is electrically connected to the external electric circuit board, and the wiring conductor is connected between the semiconductor element S and the external electric circuit board. The semiconductor element S is activated by transmitting a signal via 4 and the electronic component D.
Examples of the electronic component D include a chip capacitor that stabilizes the supply of power to the semiconductor element S.

次に、図２〜図３を基に、本発明の配線基板の製造方法を説明する。なお、図２〜図３においては、製造工程毎の要部を概略断面図で示し、図１を基に説明した配線基板Ａと同一の箇所には同一の符号を付し、その詳細な説明は省略する。   Next, a method for manufacturing a wiring board according to the present invention will be described with reference to FIGS. 2 to 3, the main part for each manufacturing process is shown in a schematic cross-sectional view, and the same parts as those of the wiring board A described based on FIG. Is omitted.

まず、図２（ａ）に示すように、スルーホール７および上下面に配線導体４が形成された絶縁板１を準備する。
絶縁板１は、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁板１の厚みは、およそ４０〜６００μｍ程度である。
配線導体４は、例えば周知のセミアディティブ法やサブトラクティブ法により、銅等の良導電性金属で形成される。
スルーホール７の直径は、例えば５０〜３００μｍ程度であり、例えばドリル加工やレーザー加工、あるいはブラスト加工により形成される。 First, as shown in FIG. 2A, an insulating plate 1 having through-holes 7 and wiring conductors 4 formed on upper and lower surfaces is prepared.
The insulating plate 1 is made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the insulating plate 1 is about 40 to 600 μm.
The wiring conductor 4 is formed of a highly conductive metal such as copper by a known semi-additive method or subtractive method, for example.
The diameter of the through hole 7 is, for example, about 50 to 300 μm and is formed by, for example, drilling, laser processing, or blasting.

次に、図２（ｂ）に示すように、絶縁板１にキャビティ６を形成する。キャビティ６は、例えばブラスト加工やレーザー加工により形成される。   Next, as shown in FIG. 2B, the cavity 6 is formed in the insulating plate 1. The cavity 6 is formed by, for example, blasting or laser processing.

次に、図２（ｃ）に示すように、絶縁板１を粘着シートＮ上に載置する。   Next, the insulating plate 1 is placed on the adhesive sheet N as shown in FIG.

次に、図２（ｄ）に示すように、キャビティ６内に電子部品Ｄを挿入して、キャビティ６内に露出する粘着シートＮ上に電子部品Ｄを載置する。   Next, as shown in FIG. 2D, the electronic component D is inserted into the cavity 6, and the electronic component D is placed on the adhesive sheet N exposed in the cavity 6.

次に、図２（ｅ）に示すように、絶縁板１の上側に未硬化の第１樹脂層２ａを積層する。そして、未硬化の第１樹脂層２ａを加熱処理して硬化することで、電子部品Ｄをキャビティ６内の所定の位置に固定するとともにキャビティ６内の隙間の一部を充填する。このとき、電子部品Ｄが後工程の処理の際に動かないように未硬化の第１樹脂層２ａを完全に硬化しておくことが重要である。
第１樹脂層２ａは、例えばエポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含有する電気絶縁材料から成り、厚みはおよそ５〜１５μｍ程度である。 Next, as illustrated in FIG. 2E, an uncured first resin layer 2 a is laminated on the upper side of the insulating plate 1. Then, the uncured first resin layer 2 a is cured by heat treatment, thereby fixing the electronic component D at a predetermined position in the cavity 6 and filling a part of the gap in the cavity 6. At this time, it is important to completely cure the uncured first resin layer 2a so that the electronic component D does not move during the subsequent process.
The first resin layer 2a is made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin, and has a thickness of about 5 to 15 μm.

次に、図３（ｆ）に示すように、粘着シートＮを剥離する。   Next, as shown in FIG. 3F, the adhesive sheet N is peeled off.

次に、図３（ｇ）に示すように、絶縁板１の下側に未硬化の第２樹脂層３ａを積層するとともに、硬化された第１樹脂層２ａの上側に未硬化の第３樹脂層２ｂを積層する。そして、未硬化の第２樹脂層３ａおよび未硬化の第３樹脂層２ｂを加熱処理して硬化する。これにより、絶縁板１の上側に第１および第３樹脂層２ａ、２ｂから成る第１絶縁層２と、絶縁板１の下側に第２樹脂層３ａから成る第２絶縁層３とが形成される。また、キャビティ６内の隙間の残部は第２絶縁層３により充填される。
このとき、第１および第２絶縁層２、３表面の硬化履歴は同じであるため、第１絶縁層２表面の硬化度合と、第２絶縁層３表面の硬化度合とは実質的に同じとなる。
第２樹脂層３ａは、例えばエポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含有する電気絶縁材料から成り、厚みはおよそ３０〜４０μｍ程度である。また、第３樹脂層２ｂは、例えばエポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含有する電気絶縁材料から成り、厚みはおよそ１５〜３５μｍ程度である。 Next, as shown in FIG. 3G, an uncured second resin layer 3a is laminated on the lower side of the insulating plate 1, and an uncured third resin is disposed on the upper side of the cured first resin layer 2a. Layer 2b is laminated. Then, the uncured second resin layer 3a and the uncured third resin layer 2b are heated and cured. Thus, the first insulating layer 2 composed of the first and third resin layers 2a and 2b is formed on the upper side of the insulating plate 1, and the second insulating layer 3 composed of the second resin layer 3a is formed on the lower side of the insulating plate 1. Is done. Further, the remainder of the gap in the cavity 6 is filled with the second insulating layer 3.
At this time, since the curing history of the surfaces of the first and second insulating layers 2 and 3 is the same, the curing degree of the surface of the first insulating layer 2 and the curing degree of the surface of the second insulating layer 3 are substantially the same. Become.
The 2nd resin layer 3a consists of an electrically insulating material containing thermosetting resins, such as an epoxy resin and a polyimide resin, for example, and thickness is about 30-40 micrometers. Moreover, the 3rd resin layer 2b consists of an electrically insulating material containing thermosetting resins, such as an epoxy resin and a polyimide resin, for example, and thickness is about 15-35 micrometers.

次に、図３（ｈ）に示すように、第１絶縁層２および第２絶縁層３に複数のビアホール８を形成する。一部のビアホール８は、電子部品Ｄの電極Ｔを底面としている。また、別のビアホール８は、絶縁板１表面の配線導体４を底面としている。ビアホール８を形成した後は、第１絶縁層２および第２絶縁層３表面を、例えば過マンガン酸カリウム溶液により粗化処理する。
このとき、第１絶縁層２表面の硬化度合と、第２絶縁層３表面の硬化度合とは実質的に同じであることから、第１絶縁層２表面の粗化状態と、第２絶縁層３表面の粗化状態とが実質的に同じとなる。
なお、ビアホール８の直径は、２０〜１００μｍ程度であり、例えばレーザー加工により形成される。 Next, as shown in FIG. 3 (h), a plurality of via holes 8 are formed in the first insulating layer 2 and the second insulating layer 3. Some via holes 8 have the electrode T of the electronic component D as a bottom surface. Another via hole 8 has the wiring conductor 4 on the surface of the insulating plate 1 as a bottom surface. After the via hole 8 is formed, the surfaces of the first insulating layer 2 and the second insulating layer 3 are roughened with, for example, a potassium permanganate solution.
At this time, since the degree of cure of the surface of the first insulating layer 2 and the degree of cure of the surface of the second insulating layer 3 are substantially the same, the roughened state of the surface of the first insulating layer 2 and the second insulating layer The roughened state of the three surfaces is substantially the same.
The diameter of the via hole 8 is about 20 to 100 μm and is formed by laser processing, for example.

次に、図３（ｉ）に示すように、第１絶縁層２および第２絶縁層３の表面およびビアホール８内に配線導体４を被着させる。配線導体４は、例えば周知のセミアディティブ法により、銅等の良導電性金属で形成される。
なお、上述のように、第１絶縁層２表面の粗化状態と、第２絶縁層３表面の粗化状態とが実質的に同じであることから、第１絶縁層２表面の配線導体４の密着力と、第２絶縁層３表面の配線導体４の密着力とのバラツキを抑えることができる。 Next, as shown in FIG. 3 (i), the wiring conductor 4 is deposited on the surfaces of the first insulating layer 2 and the second insulating layer 3 and in the via holes 8. The wiring conductor 4 is formed of a highly conductive metal such as copper by, for example, a known semi-additive method.
As described above, since the roughened state of the surface of the first insulating layer 2 and the roughened state of the surface of the second insulating layer 3 are substantially the same, the wiring conductor 4 on the surface of the first insulating layer 2 is used. And the adhesion between the wiring conductor 4 on the surface of the second insulating layer 3 can be suppressed.

最後に、図３（ｊ）に示すように、第１および第２絶縁層２、３表面に形成された配線導体４の一部を露出させる第１開口部５ａおよび第２開口部５ｂを有するソルダーレジスト層５を、第１絶縁層２の上面および第２絶縁層３の下面に被着することで配線基板Ａが形成される。
ソルダーレジスト層５は、例えばエポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含有する電気絶縁材料から成る樹脂ペーストまたはフィルムを、第１および第２絶縁層２、３および配線導体４の上に塗布または貼着して熱硬化させることにより形成される。 Finally, as shown in FIG. 3 (j), the first and second insulating layers 2 and 3 have a first opening 5a and a second opening 5b that expose a part of the wiring conductor 4 formed on the surface. The wiring board A is formed by depositing the solder resist layer 5 on the upper surface of the first insulating layer 2 and the lower surface of the second insulating layer 3.
For the solder resist layer 5, for example, a resin paste or film made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin is applied on the first and second insulating layers 2 and 3 and the wiring conductor 4. Alternatively, it is formed by sticking and thermosetting.

ところで、本発明の配線基板の製造方法によると、絶縁板１に形成されたキャビティ６内の電子部品Ｄを、電子部品Ｄに密着して絶縁板１の一方の主面に被着された未硬化の第１樹脂層２ａを完全に硬化させることによりキャビティ６内に固定する。そして、絶縁板１の他方の主面に未硬化の第２樹脂層３ａを被着するとともに、第１樹脂層２ａの外側主面に未硬化の第３樹脂層２ｂを被着する。その後に、第２および第３樹脂層３ａ、２ｂを硬化させて一方の主面上に第１および第３樹脂層２ａ、２ｂから成る第１絶縁層２と、他方の主面上に第２樹脂層３ａから成る第２絶縁層３とを形成する。このようにすることで、第１および第２絶縁層２、３表面における硬化履歴が同じになる。したがって、第１及び第２絶縁層２、３表面の硬化度合は略同一となる。これにより、第１絶縁層２表面および第２絶縁層３表面を粗化処理する際に、両表面の粗化状態は略同一となる。その結果、第１絶縁層２表面に形成される配線導体４の密着力と、第２絶縁層３表面に形成される配線導体４の密着力とのバラツキが小さい安定した密着力を有する配線導体４を備えた配線基板Ａを提供することができる。
なお、本発明においては、未硬化の第１樹脂層２ａを完全に硬化して電子部品Ｄを固定した後に、第２および第３樹脂層３ａ、２ｂを被着して硬化する。このため、電子部品Ｄが両樹脂３ａ、２ｂの熱伸縮により変動することなく所定の位置に内蔵することもできる。
By the way, according to the method for manufacturing a wiring board of the present invention, the electronic component D in the cavity 6 formed in the insulating plate 1 is not adhered to the electronic component D and adhered to one main surface of the insulating plate 1. The cured first resin layer 2a is completely cured to be fixed in the cavity 6. Then, the uncured second resin layer 3a is applied to the other main surface of the insulating plate 1, and the uncured third resin layer 2b is applied to the outer main surface of the first resin layer 2a. Thereafter, the second and third resin layers 3a and 2b are cured to form a first insulating layer 2 composed of the first and third resin layers 2a and 2b on one main surface, and a second on the other main surface. The second insulating layer 3 made of the resin layer 3a is formed. By doing in this way, the hardening history in the 1st and 2nd insulating layers 2 and 3 surface becomes the same. Therefore, the degree of curing of the surfaces of the first and second insulating layers 2 and 3 is substantially the same. Thereby, when roughening the surface of the 1st insulating layer 2 and the 2nd insulating layer 3, the roughening state of both surfaces becomes substantially the same. As a result, the wiring conductor having a stable adhesion force with little variation between the adhesion force of the wiring conductor 4 formed on the surface of the first insulating layer 2 and the adhesion force of the wiring conductor 4 formed on the surface of the second insulating layer 3. 4 can be provided.
In the present invention, after the uncured first resin layer 2a is completely cured and the electronic component D is fixed, the second and third resin layers 3a and 2b are applied and cured. For this reason, the electronic component D can also be incorporated in a predetermined position without fluctuating due to the thermal expansion and contraction of both resins 3a and 2b.

１ 絶縁板
２ 第１絶縁層
２ａ 第１樹脂層
２ｂ 第３樹脂層
３ 第２絶縁層
３ａ 第２樹脂層
４ 配線導体
６ キャビティ
Ａ 配線基板 DESCRIPTION OF SYMBOLS 1 Insulation board 2 1st insulating layer 2a 1st resin layer 2b 3rd resin layer 3 2nd insulating layer 3a 2nd resin layer 4 Wiring conductor 6 Cavity A Wiring board

Claims (1)

一方の主面側から他方の主面側に貫通するキャビティを有する絶縁板を準備する工程と、
前記キャビティ内に電子部品を挿入するとともに、前記一方の主面に、該一方の主面および前記キャビティを覆う未硬化の第１樹脂層を、前記電子部品に密着して前記キャビティ内の隙間の一部を充填するように被着する工程と、
前記第１樹脂層を硬化させ、該硬化した第１樹脂層により前記電子部品を前記キャビティ内に固定する工程と、
前記他方の主面に、該他方の主面および前記キャビティを覆う未硬化の第２樹脂層を、前記キャビティ内の隙間の残部を充填するように被着するとともに、前記第１樹脂層の外側主面に、該外側主面を覆う未硬化の第３樹脂層を被着する工程と、
前記第２および第３樹脂層を硬化させ、前記一方の主面上に前記第１および第３樹脂層から成る第１絶縁層と、前記他方の主面上に前記第２樹脂層から成る第２絶縁層とを形成する工程と、
前記第１および第２絶縁層の表面を粗化する工程と、
粗化された前記第１および第２絶縁層の表面に配線導体を形成する工程と、
を含むことを特徴とする配線基板の製造方法。 Preparing an insulating plate having a cavity penetrating from one main surface side to the other main surface side;
An electronic component is inserted into the cavity, and an uncured first resin layer that covers the one main surface and the cavity is attached to the one main surface in close contact with the electronic component, and a gap in the cavity is formed. Depositing to fill a portion;
Curing the first resin layer and fixing the electronic component in the cavity with the cured first resin layer;
An uncured second resin layer covering the other main surface and the cavity is deposited on the other main surface so as to fill the remainder of the gap in the cavity, and outside the first resin layer. Adhering to the main surface an uncured third resin layer covering the outer main surface;
The second and third resin layers are cured, and a first insulating layer composed of the first and third resin layers is formed on the one main surface, and a second resin layer is formed on the other main surface. Forming two insulating layers;
Roughening the surfaces of the first and second insulating layers;
Forming a wiring conductor on the roughened surfaces of the first and second insulating layers;
A method for manufacturing a wiring board, comprising:
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