JP6071613B2 - 半導体基板、半導体装置、撮像素子、および撮像装置 - Google Patents
半導体基板、半導体装置、撮像素子、および撮像装置 Download PDFInfo
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- JP6071613B2 JP6071613B2 JP2013027057A JP2013027057A JP6071613B2 JP 6071613 B2 JP6071613 B2 JP 6071613B2 JP 2013027057 A JP2013027057 A JP 2013027057A JP 2013027057 A JP2013027057 A JP 2013027057A JP 6071613 B2 JP6071613 B2 JP 6071613B2
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Description
しかし、近年、半導体デバイスは小型化が求められているため、接合電極のピッチはますます狭ピッチになっている。現在の半田バンプ形成技術では数μmの大きさの半田バンプを形成することは難しいため、半田バンプを用いた接続方法では、接合時に電極同士がショートするおそれがあり、このような小型化に対応できないという問題がある。
金属バンプを用いた加熱圧着による接続方法においても、接合電極の狭ピッチ化に対応して金属バンプを微細化する必要がある。これに伴い、金属バンプの高さも微細化するため、金属バンプの製造誤差による高さのバラツキ、半導体基板を押圧する際の基板の平面度や平行度の誤差等の要因により加圧力にムラが生じやすくなる。この結果、接続不良が発生しやすくなる。しかし、接続不良を抑制するために加圧力を増大させると、半導体デバイスへの加圧によるダメージが生じやすくなる。
このような加圧ムラの改善に関連する技術として、特許文献1には、液晶パネル等のドライバICの出力端子に、略蒲鉾形状(半円状の断面が一方向に延ばされたドーム形状)に成形されたアクリル樹脂等の樹脂からなる弾性部材の表面に金メッキなどによって形成された第2の導電部材を接触させた導電部材を設け、この導電部材を電極パッドに当接させることで電気接続を行う技術が記載されている。
特許文献1に記載の技術は、接合時に樹脂製の弾性部材が弾性変形するため、導電部材の高さのバラツキや半導体基板の平面度、平行度の誤差を、弾性変形の範囲で吸収することができるものの、樹脂製の弾性部材は精度よく微細化することが難しいという問題がある。
すなわち、この技術は、例えば、ドライバICのように出力端子数も少なく接合電極ピッチも広い場合に適用可能な技術であり、例えば、撮像素子の積層型半導体基板の接続など、格段に狭ピッチで配列された膨大な数の微小な接合電極同士の接合には適用することは難しいという問題がある。
万一、特許文献1に記載の構成を微細化できたとしても、弾性変形を利用するため、接合時の変形形状を接合後も保持することは難しいという問題がある。
また、弾性部材として樹脂を用いるため、変形が大きすぎると、第2の導電部材にクラックが入ったり、第2の導電部材が割れたりする。このため、経時の特性劣化や接合不良が発生するおそれがあるという問題がある。
特に微細化を進めると第2の導電部材も薄肉化されるため、このような第2の導電部材の強度不足が顕著になる。
図1は、本発明の実施形態の撮像装置のシステム構成を示すシステム構成図である。図2(a)は、本発明の実施形態の撮像素子の平面図である。図2(b)は、図2(a)におけるA−A断面図である。図2(c)は、図2(b)におけるB部の詳細図である。図3は、本発明の実施形態の撮像素子における接合電極の接合状態を説明する模式的な断面図である。図4(a)は、本発明の実施形態の半導体基板の接合電極の模式的な平面図である。図4(b)は、図4(a)におけるC−C断面図である。
なお、各図面は模式図であるため、形状や寸法は誇張されている(以下の図面も同様)。
図1に示すように、本実施形態のデジタルカメラ10(撮像装置)は、レンズ部1、レンズ制御装置2、固体撮像素子3(撮像素子、半導体装置)、駆動回路4、メモリ5、信号処理回路6、記録装置7、制御装置8、および表示装置9を備える。
固体撮像素子3は、受光面に結像された被写体像を画像信号に変換して出力する。固体撮像素子3の受光面には、複数の画素が行方向および列方向に2次元的に配列されている。固体撮像素子3の詳細構成は後述する。
図2(a)、(b)に示すように、固体撮像素子3は、平面視矩形状の外形を有し、第1基板12(半導体基板)と第2基板11(被接合部材)とが貼り合わせて構成された積層型の半導体装置からなる。
装置外側に向いた第1基板12の表面である第1表面12bの中心部には、光電変換の画素に対応する複数のフォトダイオードからなる受光部Pが互いに間隔をあけて形成されている。本実施形態では、受光部Pは、固体撮像素子3の平面視の外形の長辺(図2(a)における図示横方向に延びる辺)、短辺(図2(a)における図示縦方向に延びる辺)に平行な配列方向を有する2次元格子状に配置されている。
なお、見にくくなるため図示は省略するが、各受光部P上には、被写体の像を取得するための入射光L(図2(b)参照)の色分解を行うオンチップカラーフィルタや、入射光Lを受光部P上に集光するオンチップマイクロレンズが形成されている。また、受光部Pが配置された領域の外側には、必要に応じて、画像ノイズとなる可能性のある不要光を遮光するための遮光膜が設けられている。
第1基板12は、図2(c)に示すように、半導体製造プロセスによってウエハ基板上に拡散層や単層もしくは複層の配線を形成した回路部を有する半導体デバイスが形成された基板本体12d(半導体基板本体)と、第2基板11と接合して電気的な接続を行うための複数の接合電極12aとを備える。接合電極12aは、基板本体12dにおいて第1表面12bと反対側の第2表面12c(半導体基板本体の厚さ方向の一方の面)に設けられている。
第2基板11は、半導体製造プロセスによってウエハ基板上に拡散層や単層もしくは複層の配線を形成した回路部を有する半導体デバイスが形成された基板本体11d(半導体基板本体)と、第1基板12と接合して電気的な接続を行うための複数の接合電極12aとを備える。接合電極11aは、基板本体11dにおいて厚さ方向の一方の面である第1表面11cにおいて第1基板12の接合電極12aと対向する位置に設けられ、接合電極12aと密着して接合されている。
基板本体11dにおいて、第1表面11cの裏面側の第2表面11bは、固体撮像素子3において、装置外側に向いており、第1表面12bと反対側の固体撮像素子3の表面を構成している。また、第2表面12cと第1表面11cとは、接合層部13を介して互いに対向している。
各回路部の図示は省略するが、基板本体12d、11dに適宜振り分けて配置されている。
接合電極12a、11aは、これら基板本体12d、11dに振り分けられた図示略の回路部の配線に接続されており、各回路部を電気的に接続している。
接合層部13は、第2基板11の第1表面11cに設けられた接合電極11aと、第1基板12の第2表面12cに設けられた接合電極12aと、第1表面11cおよび第2表面12cの間の隙間に充填後に固化され、第2基板11および第1基板12を互いに接合する接着剤層13aとを備える。
接合電極11a、12aは、本実施形態では、それぞれ第1表面11c、第2表面12cから突出して設けられ、それぞれの突出方向の先端で互いに当接している。
接合電極12aは、接合時の加圧力によって容易に塑性変形して突出高さが変化するようになっている。図3では、接合電極12aの変形後の形状の一例を模式的に示している。
接合電極11aの材質は、半導体基板の電極に用いられる適宜の金属、例えば、アルミニウム、金、銀、銅、ニッケル、白金、タングステン、チタンなどからなる金属を採用することができる。
なお、本明細書では、特に断らない限り、「金属」を広義の意味で用いており、金属元素からなる純金属、複数の金属元素を含む導電性を有する合金が含まれる。このため、例えば、単に、「アルミニウム」と称する場合、特に断らない限り、純アルミニウムでもよいし、アルミニウム合金でもよいことを意味する。
配線部17は、パターニングされた配線本体17cと、接合電極11aの下層側(図3における図示上側)に位置する配線本体17cと接合電極11aとを電気的に接続する複数の柱状の接続部17aを備える。
このため、接続部17aは、接合電極11aと配線本体17cとの間に積層された絶縁層11eを貫通するように設けられている。
接続部17aの配置位置および個数は、接合電極11aと配線本体17cとを電気的に接続できれば、特に限定されない。
配線本体17a、および接続部17aの材質は、いずれも、半導体基板の配線に用いられる適宜の金属、例えば、アルミニウム、銅、タングステンなどからなる金属を採用することができる。
さらに、配線部17は複数層あってもよい。
接合電極12aは、図4(a)、(b)に示すように、第2表面12cに設けられた導電性を有する突起部であり、本実施形態では、第2表面12c上に底面15aが密着して形成された直方体状の第2金属部15と、第2金属部15の外周側の第2表面12cから突出され、第2金属部15の側面15b、および上面15cを覆うように形成された第1金属部14との複合体で構成される。
このため、第1金属部14は、突出方向の基端部において第2金属部15の側方を囲む範囲で第2表面12cと密着された平面視矩形状の配線接続部14bと、配線接続部14b上で配線接続部14bの平面視外形より小さい四角柱状に突出された突状部14aとを有している。
また、第1金属部14の内壁部14cは、第2金属部15の側面15bおよび上面15cと密着された有底の角穴状の形状を有する。
第1金属部14を構成する第1の金属としては、例えば、アルミニウム(HV25、融点660℃)、金(HV26、融点1063℃)、銀(HV26、融点961℃)、銅(HV46、融点1083℃)、ニッケル(HV96、融点1453℃)、白金(HV41、融点1769℃)、タングステン(HV100〜350、融点3380℃)、およびチタン(HV120、融点1668℃)を好適に用いることができる。
ここで、HVはビッカース硬さを示す。また、融点は純金属の融点である。
また、第2の金属は、第1金属部14に用いられた第1の金属よりも硬度が低ければ、第1の金属として好適でないような低硬度の金属も採用することができる。
また、金属は熱処理によっても硬度が変わるため、第2の金属として第1金属部14に用いる第1の金属と同じ金属を用いることも可能である。この場合、第2金属部15を形成した後に、硬度を低減するための熱処理を行ってから、第1金属部14を形成することによって硬度が異なる複合体を形成することができる。
第2の金属として好ましい低硬度の金属としては、例えば、インジウム(融点157℃)、スズ(融点231℃)、スズ半田合金(融点231℃)を挙げることができる。
これら低硬度の金属のビッカース硬度は、温度によっても異なるが、上記の第1の金属に好適な金属群のいずれとも組み合わせることが可能である。
また、第2の金属として金を採用した場合、第1の金属は、銀、銅、ニッケル、およびタングステンのうちから選択された金属を採用することができる。このうちで、特に好ましいのは、銅である。
また、第2の金属としてインジウムを採用した場合、第1の金属は、金、銅、およびアルミニウムのうちから選択された金属を採用することが特に好ましい。
すなわち、接合電極12aの外形は、従来と同様、各接合電極12aの配列間隔、接合相手である接合電極11aの大きさや、基板本体12d、11dの間の好ましい基板間隔などによって決まる。
そして、接合電極12aの硬さは、第2基板11および第1基板12の半導体デバイス等を損傷させない許容加圧力によって、第2基板11との接合時の製造誤差バラツキによって決まる最大変形量だけ接合電極12aを塑性変形させることができる硬さに設定する。
ここで、接合時の製造誤差バラツキとは、例えば、接合電極12aの突出高さの製造バラツキ、第2基板11および第1基板12の平面度誤差、押圧時の第2基板11および第1基板12の平行度誤差などを挙げることができる。すなわち、このような製造誤差があると、一部の接合電極11a、12aの間に隙間が生じるため、すべての接合電極11a、12aを電気的に接続するためには、この隙間が解消するまで、当接済みの他の接合電極11aを変形させる必要がある。
そこで、許容加圧力の範囲で、接合電極12aが必要な最大変形量だけ変形するように硬さを調整する。
具体的には、例えば、数値計算による変形解析を行うことにより、必要な硬度を実現する細部形状を決定することができる。その際、突状部14aの肉厚は全体的に変更する以外にも、部分的に変更すること可能である。
配線部16は、パターニングされた配線本体16cと、接合電極12aの下層側に位置する配線本体16cと接合電極11aとを電気的に接続する複数の柱状の接続部16a、16bを備える。
接続部16aは、配線本体16cと第1金属部14とを電気的に接続するもので、配線接続部14bと配線本体16cとの間に積層された絶縁層12eを貫通するように設けられている。
接続部16bは、配線本体16cと第2金属部15とを電気的に接続するもので、第2金属部15の底面15aと配線本体16cとの間に積層された絶縁層12eを貫通するように設けられている。
接続部16a、16bの配置位置および個数は、それぞれ第1金属部14、第2金属部15と、配線本体16cとを電気的に接続できれば、特に限定されないが、本実施形態では、一例として、図4(a)に破線で示すように、合計12個の接続部16aが矩形状に配列され、合計4個の接続部16bが矩形状をなして接続部16aが整列された矩形の中心部に配列されている。
配線本体16cおよび接続部16a、16bの材質は、いずれも、例えば、タングステン、アルミニウムなどからなる金属を採用することができる。
さらに、第1金属部14と第2金属部15とは、内壁部14cと、側面15bおよび上面15cとの間で互いに電気的に接続されている。
例えば、第2金属部15を設けるには、第2表面12c上に、例えば、スパッタリング、蒸着、メッキなどによって第2の金属からなる金属層を形成し、フォトリソグラフィによって第2金属部15のパターンを形成すればよい。
第1金属部14を設けるには、第2表面12cおよび第2金属部15上に、例えば、スパッタリングや蒸着によって第1の金属からなる金属層を形成し、フォトリソグラフィによって、第1金属部14のパターンを形成すればよい。
次に、各各接合電極12aが対応する接合電極11aに対向するように、位置合わせして、第2基板11および第1基板12を対向させる。そして、真空雰囲気または大気雰囲気において、接合電極11a、12aを加熱しつつ、第2基板11および第1基板12を対向方向に押圧する。
このとき、接合電極12aの突出高さの製造バラツキや、第2基板11および第1基板12の平面度誤差や、押圧時の第2基板11および第1基板12の平行度誤差などがあると、接合電極11a、12aとの当接状態にバラツキが生じてしまう。
しかし、本実施形態では、接合電極12aが低硬度の第2金属部15と高硬度の第1金属部14との複合体からなるため、接合電極12a全体が第1の金属からなる場合に比べて低い加圧力で、先に当接した接合電極12aが塑性変形し、許容加圧力の範囲で、すべての接合電極12aを対向する接合電極11aに当接させることができる。
互いに密着した接合電極12a、11aの先端部はそれぞれ表面活性化処理されているため、強固に接合される。
また、低硬度の接合電極12aは、容易に塑性変形するため、加圧力を解除しても、変形状態が維持され、第1表面12b、第2表面11bの間の間隙の変化を抑制できる。
これにより、仮に、第1金属部14の一部が断線した状態になっても、第1金属部14と第2金属部15との電気的接続状態は変わらない。このため、接合電極12aとしては、断線状態になることはなく、接続抵抗の変化も抑制される。
これにより、接合の際の加圧時に第2基板11と第1基板12とを対向方向と交差する方向にずらす力が発生しにくくなるため、対向方向と交差する方向への、第2基板11および第1基板12の位置ずれを抑制することができる。この結果、接合電極12a、11aが狭ピッチで配置された場合でも、良好に接合させることができる。
その後、必要に応じて、スクライビングすることにより、固体撮像素子3が製造される。
このような接合電極12aは、半導体製造プロセスによって形成することができるため、微細化することが可能であり、配線間隔が狭い半導体基板にも高精度に設けることができる。このため、第1基板12は、例えば、固体撮像素子3のような多数の接合電極が必要となり、配線密度も高い半導体装置を製造する半導体基板として好適である。
次に、本実施形態の第1変形例の半導体基板について説明する。
図5(a)は、本発明の実施形態の第1変形例の半導体基板の接合電極の模式的な平面図である。図5(b)は、図5(a)におけるD−D断面図である。
第1基板22は、上記実施形態の第1基板12の接合電極12aに代えて、接合電極22aを備える。
以下、上記実施形態と異なる点を中心に説明する。
第1金属部24は、上記実施形態の第1金属部14の突状部14aに代えて、突状部24aを備える。突状部24aは、突状部14aの第2金属部15の上面15cより上側の部分を削除した形状を有する点のみが異なり、第1金属部14と同様の第1の金属で形成されている。
このため、第1金属部24の突出方向の先端部である先端面24dは、第2金属部15の上面15c整列しており、第2表面12cからの高さは上面15cと等しく、かつ第2表面12cと略平行(平行の場合を含む)である。
ただし、第2表面12cから先端面24dまでの高さは、接合時に必要な高さであり、例えば、接合電極12aにおける第2表面12cから先端面14dまでの高さと同一の高さである。
先端面24dの平面視矩形状は、上面15cの外周を周回する角環状である。
先端面24dは、第2基板11と接合される際に、第2金属部15の上面15cとともに、第2基板11の接合電極11aと当接して接合する部位になる。
第1金属部24の角穴状の内壁部24cは、第2金属部15の側面15bと密着されている。
また、上記実施形態と同様にして、第1金属部24を第2基板11と接合することができる。
このような接合電極22aは、半導体製造プロセスによって形成することができるため、微細化することが可能であり、配線間隔が狭い半導体基板にも高精度に設けることができる。このため、第1基板22は、例えば、固体撮像素子3のような多数の接合電極が必要となり、配線密度も高い半導体装置を製造する半導体基板として好適である。
このため、接合電極12aと同程度の硬度を得る場合に、第1金属部24の突状部24aの肉厚を、上記実施形態の突状部14aの肉厚よりも厚くすることが可能である。
これにより、接合の際の加圧時に第2基板11と第1基板22とを対向方向と交差する方向にずらす力が発生しにくくなるため、対向方向と交差する方向への、第2基板11および第1基板22の位置ずれを抑制することができる。この結果、接合電極22a、11aが狭ピッチで配置された場合でも、良好に接合させることができる。
次に、本実施形態の第2変形例の半導体基板について説明する。
図6(a)は、本発明の実施形態の第2変形例の半導体基板の接合電極の模式的な平面図である。図6(b)は、図6(a)におけるE−E断面図である。
第1基板32は、上記実施形態の第1基板12の接合電極12aに代えて、接合電極32aを備える。
以下、上記実施形態と異なる点を中心に説明する。
第1金属部34は、第2表面12cから突出され、第2金属部15の上面15cと、側面15bの1つを覆うように形成されている。
すなわち、第1金属部34は、第2金属部15の基端部において側面15bの1つの側方の第2表面12c上に密着して延ばされた平面視矩形状の配線接続部34bと、配線接続部34b上で側面15bを覆うとともに上面15cを覆う側面視L字状の突状部34aとを有している。
突状部34aの突出方向の先端には、第2表面12cと略平行な(平行の場合を含む)平面視矩形状の先端面34dが形成されている。先端面34dは、第2基板11と接合される際に、第2基板11の接合電極11aと当接して接合する部位になる。
このため、接合電極32aにおける第2金属部15は、突状部34aによって側面15bの1つと上面15cが覆われ、他の三方の側面15bは側方に露出されている。
配線部36は、上記実施形態の配線部16と同様に、配線本体16c、および接続部16a、16bを備える。
配線部36においては、配線本体16cが第2金属部15と第1金属部34の配線接続部34bとに重なる範囲に設けられ、接続部16aが配線本体16cと第1金属部34とを電気的に接続する点が上記第1の実施形態と異なる。
このため、本変形例の接続部16aは、配線接続部34bと配線本体16cとの間に積層された絶縁層12eを貫通するように設けられている。
本変形例の接続部16aは、一例として、図6(b)に破線で示すように、合計4個が矩形状をなして配列されている。
また、上記実施形態と同様にして、第1金属部34を第2基板11と接合することができる。
このような接合電極32aは、半導体製造プロセスによって形成することができるため、微細化することが可能であり、配線間隔が狭い半導体基板にも高精度に設けることができる。このため、第1基板32は、例えば、固体撮像素子3のような多数の接合電極が必要となり、配線密度も高い半導体装置を製造する半導体基板として好適である。
このため、接合電極32aは、接合電極12aに比べてより低硬度の構成とすることが容易となる。
次に、本実施形態の第2変形例の半導体基板について説明する。
図7(a)は、本発明の実施形態の第3変形例の半導体基板の接合電極の模式的な部分断面図である。
第1基板42は、上記実施形態の接合電極12aに代えて、接合電極42aを備える。
以下、上記実施形態と異なる点を中心に説明する。
バリアメタル層40は、第1金属部14における第1の金属と、第2金属部15における第2の金属との間で、拡散が起こることを抑制する金属層である。
バリアメタル層40の材質としては、第1の金属および第2の金属の組合せに応じて、拡散を防止に好適な適宜の金属を採用することができる。例えば、上記実施形態に例示した金属同士の組合せでは、チタン、クロム、タンタルなどを好適に採用することができる。
次に、本実施形態の第4変形例の半導体基板について説明する。
図8は、本発明の実施形態の第4変形例の半導体基板の接合電極の模式的な断面図である。
第1基板52は、上記実施形態の第1基板12の接合電極12aに代えて、接合電極52aを備える。
以下、上記実施形態と異なる点を中心に説明する。
第2金属部55は、第2表面12cに設けられた導電性を有する突起部であり、第2表面12c上に底面55aが密着して形成された半球状とされている。
第2金属部55は、上記実施形態の第2金属部15と同様の第2の金属で形成されている。
第1金属部54は、第2金属部55の基端部の外周側に延ばされ、第2表面12cに密着された平面視円環状の層状部からなる配線接続部54bと、第2金属部55の半球状の表面を覆って密着するとともに、配線接続部54bに接続した半球状の突状部54aとを有している。
突状部54aの突出方向の先端の頂部54dは、第2基板11と接合される際に、第2基板11の接合電極11aと当接して接合する部位になる。
配線部56は、上記実施形態の配線部16と同様に、配線本体16c、および接続部16a、16bを備える。
配線部56においては、配線本体16cが第2金属部55と第1金属部54の配線接続部54bとに重なる範囲に設けられ、接続部16bが配線本体16cと第2金属部55とを、接続部16aが配線本体16cと第1金属部54とを電気的に接続する点が上記実施形態と異なる。
このため、本変形例の接続部16b、16aは、それぞれ、第2金属部55の底面55aと第1金属部54の配線接続部54bとの間に積層された絶縁層12eを貫通するように設けられている。
本変形例の接続部16b、16aの配置位置および個数は特に限定されず、例えば、複数のものが、接合電極52aの中心軸線の同心円の円周上に適宜間をあけて配置されている。
第2金属部55の半球状の形状を形成するには、例えば、第2金属部55を形成する位置に、第2の金属を円状のパターンを形成し、この第2の金属を加熱溶融した後に硬化させる。この場合、溶融時の表面張力によって半球状の形状が形成される。
このように一度溶融させると、熱処理されたのと同様であるため、溶融前よりも硬度を低減することができる。
また、上記実施形態と同様にして、第1基板52を第2基板11と接合することができる。
また、このような接合電極52aは、配線間隔が狭い半導体基板にも高精度に設けることができ、例えば、固体撮像素子3のような多数の接合電極が必要となり、配線密度も高い半導体装置を製造する半導体基板として好適である。
また、製造誤差や加圧時の平行度誤差などによって、接合電極11aに、接合電極52aが傾斜して押圧されても、当接距離が変わらないため、円滑に当接させることが可能となる。
次に、本実施形態の第5変形例の半導体基板について説明する。
図9(a)は、本発明の実施形態の第5変形例の半導体基板の接合電極の模式的な平面図である。図9(b)は、図9(a)におけるF−F断面図である。
第1基板62は、上記実施形態の第1基板12の配線部16に代えて、配線部66(配線)を備える。
以下、上記実施形態と異なる点を中心に説明する。
このため、各接続部16a、16bは、いずれも接続電極66dと電気的に接続されている。
また、接続電極66dは、第1金属部14の下面および第2金属部15の底面15aの全面と密着して接合されている。
接続電極66dの材質は、半導体基板の配線に用いられる適宜の金属、例えば、アルミニウム、銅、金などからなる金属を採用することができる。
また、第2金属部15、第1金属部14は、接続電極66dを形成してから、その上層に形成されることになる。このため、メッキによって製造することも可能になるため、第2金属部15、第1金属部14を接続電極66d上に、選択的に形成できる。
また、第2金属部は、半導体基板本体の表面と接していることは必須ではない。このため、第2金属部は、第1金属部によって全外周が覆われていることが可能である。
よって、第2金属部は、球体、楕円体などの形状も採用することが可能である。
ただし、接合電極をより確実に電気的に接続し、かつ経時的に電気接続を維持しやすくなるため、第2金属部が配線部に直接接続されていることが好ましい。
また、被接合部材の接合電極が接合パッドであることは必須ではなく、被接合部材にも、第1金属部と第2金属部との複合体である接合電極を設けてもよい。すなわち、第1金属部と第2金属部との複合体である接合電極を設けた本発明の半導体基板同士を互いに接合した半導体装置、撮像素子を構成してもよい。
例えば、上記第3変形例のバリアメタル層40は、上記第1、2、4、5変形例における第1金属部と第2金属部との間に設けることが可能である。
また、上記第5変形例の接続電極66dは、上記第1〜4変形例の配線部に設けることが可能である。
10 デジタルカメラ(撮像装置)
11 第2基板(被接合部材)
11a、12a、22a、32a、42a、52a 接合電極
11c 第1表面(半導体基板本体の一方の表面)
11d 基板本体
12、22、32、42、52 第1基板(半導体基板本体)
12d 基板本体
13 接合層部
13a 接着剤層
14、24、34、54 第1金属部
14a、24a、34a、54a 突状部
14b、34b、54b 配線接続部
14d、24d、34d 先端面
15、55 第2金属部
16、36、56、66 配線部(配線)
16a、16b 接続部
16c 配線本体
17 配線部
40 バリアメタル層
54d 頂部
66d 接続電極
P 受光部
Claims (9)
- 配線が形成された半導体基板本体と、
該半導体基板本体の厚さ方向の一方の面に突出して設けられた接合電極と、
を備え、
該接合電極は、
前記半導体基板本体の前記一方の面から突出して設けられ、突出方向の基端部が前記配線と電気的に接続された第1金属部と、
該第1金属部を構成する第1の金属よりも硬度が低い第2の金属からなり、前記第1金属部の突出高さ以下の範囲に前記第1金属部と接合して設けられた第2金属部と、
を有する複合体からなり、
前記第2金属部は、
バリアメタル層を介して前記第1金属部と接合されている、
半導体基板。 - 前記接合電極は、
その突出方向の先端部では、前記第2金属部が前記第1金属部によって覆われていることを特徴とする、請求項1に記載の半導体基板。 - 前記接合電極は、
前記半導体基板本体の前記一方の面から突出した表面の全体が前記第1金属部によって形成されている
ことを特徴とする、請求項1または2に記載の半導体基板。 - 前記第2の金属は、アルミニウムであり、
前記第1の金属は、金または銅である
ことを特徴とする、請求項1〜3のいずれか1項に記載の半導体基板。 - 前記第2の金属は、金であり、
前記第1の金属は、銅である
ことを特徴とする、請求項1〜3のいずれか1項に記載の半導体基板。 - 前記第2の金属は、インジウムであり、
前記第1の金属は、金、銅、およびアルミニウムのうちから選択された金属であることを特徴とする、請求項1〜3のいずれか1項に記載の半導体基板。 - 請求項1〜6のいずれか1項に記載の半導体基板と、
該半導体基板の前記接合電極を介して接合された被接合部材と、
を備える、半導体装置。 - 請求項1〜6のいずれか1項に記載の半導体基板を備える、撮像素子。
- 請求項8に記載の撮像素子を備える、撮像装置。
Priority Applications (5)
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JP2013027057A JP6071613B2 (ja) | 2013-02-14 | 2013-02-14 | 半導体基板、半導体装置、撮像素子、および撮像装置 |
EP14751278.4A EP2958136A4 (en) | 2013-02-14 | 2014-01-16 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR ASSEMBLY, IMAGE RECORDING AND IMAGING DEVICE |
PCT/JP2014/050655 WO2014125861A2 (ja) | 2013-02-14 | 2014-01-16 | 半導体基板、半導体装置、撮像素子、および撮像装置 |
CN201480008493.1A CN105074893A (zh) | 2013-02-14 | 2014-01-16 | 半导体基板、半导体装置、摄像元件及摄像装置 |
US14/823,482 US20150357300A1 (en) | 2013-02-14 | 2015-08-11 | Semiconductor substrate, semiconductor device, imaging element, and imaging device |
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JP2013027057A JP6071613B2 (ja) | 2013-02-14 | 2013-02-14 | 半導体基板、半導体装置、撮像素子、および撮像装置 |
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JP2014157884A JP2014157884A (ja) | 2014-08-28 |
JP2014157884A5 JP2014157884A5 (ja) | 2014-10-09 |
JP6071613B2 true JP6071613B2 (ja) | 2017-02-01 |
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Country Status (5)
Country | Link |
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US (1) | US20150357300A1 (ja) |
EP (1) | EP2958136A4 (ja) |
JP (1) | JP6071613B2 (ja) |
CN (1) | CN105074893A (ja) |
WO (1) | WO2014125861A2 (ja) |
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WO2016174733A1 (ja) * | 2015-04-28 | 2016-11-03 | オリンパス株式会社 | 半導体装置 |
KR20170098462A (ko) * | 2016-02-22 | 2017-08-30 | 삼성전기주식회사 | 패키지 및 그의 제조방법 |
WO2017205644A1 (en) | 2016-05-26 | 2017-11-30 | The Trustees Of The University Of Pennsylvania | Laminated magnetic cores |
WO2018193531A1 (ja) * | 2017-04-19 | 2018-10-25 | オリンパス株式会社 | 内視鏡、撮像モジュール、および撮像モジュールの製造方法 |
JP2022125445A (ja) * | 2021-02-17 | 2022-08-29 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
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JPS62206857A (ja) * | 1986-03-07 | 1987-09-11 | Oki Electric Ind Co Ltd | 突起状電極の形成方法 |
JPH07201864A (ja) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | 突起電極形成方法 |
KR100335167B1 (ko) * | 1994-11-15 | 2002-05-04 | 이고르 와이. 칸드로스 | 반도체 장치를 시험하는 방법 |
JP2000138249A (ja) * | 1998-10-29 | 2000-05-16 | Matsushita Electric Ind Co Ltd | 突起電極形成方法及び実装方法 |
JP2007258518A (ja) | 2006-03-24 | 2007-10-04 | Epson Imaging Devices Corp | 半導体装置、電気光学装置及び電子機器 |
JP5282380B2 (ja) * | 2007-08-06 | 2013-09-04 | 富士通株式会社 | 半導体装置およびその製造方法 |
WO2010061551A1 (ja) * | 2008-11-25 | 2010-06-03 | パナソニック株式会社 | 半導体装置および電子機器 |
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2014
- 2014-01-16 CN CN201480008493.1A patent/CN105074893A/zh active Pending
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- 2014-01-16 EP EP14751278.4A patent/EP2958136A4/en not_active Withdrawn
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2015
- 2015-08-11 US US14/823,482 patent/US20150357300A1/en not_active Abandoned
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CN105074893A (zh) | 2015-11-18 |
WO2014125861A2 (ja) | 2014-08-21 |
EP2958136A2 (en) | 2015-12-23 |
US20150357300A1 (en) | 2015-12-10 |
EP2958136A4 (en) | 2016-09-07 |
JP2014157884A (ja) | 2014-08-28 |
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