JP6064416B2 - Drive control device, drive control method and program, and image forming apparatus - Google Patents

Description

  The present invention relates to a drive control apparatus that performs drive control of a rotating body, a drive control method and program, and an image forming apparatus.

  In an electrophotographic image forming apparatus, an electrostatic latent image is formed on a photoconductor by optical writing and developed to obtain a toner image. The toner image is transferred to a sheet and fixed on the sheet by heat or pressure to form an image on the sheet.

  In a full-color image forming apparatus, a technique is known in which a toner image is transferred to an intermediate transfer member, and the transferred toner image is transferred from the intermediate transfer member to a sheet. That is, the color toner image is once transferred (primary transfer) to an intermediate transfer body such as an intermediate transfer belt or an intermediate transfer drum. After superimposing a plurality of color toner images on the intermediate transfer member, the color toner image is transferred (secondary transfer) from the intermediate transfer member to a sheet. Thereafter, the color toner image on the paper is fixed to obtain a full color image.

  In such an image forming apparatus using an intermediate transfer body, if a speed fluctuation occurs in the intermediate transfer body, a color toner image overlapping position at the time of primary transfer is displaced, resulting in color unevenness and a streak image. The quality will be degraded.

  In order to suppress the speed fluctuation of the intermediate transfer member, conventionally, measures such as increasing the machining accuracy of the shaft and the motor and using high-precision gears have been taken so as to suppress rotational eccentricity. In addition, as a control system, two sensors have been used to suppress the eccentricity of the rotary encoder of the rotation detection system, and the control circuit has been designed to increase the detection sensitivity by increasing the gain of the control circuit. .

  However, a simple increase in the gain of the control circuit may excite mechanical resonance, become less robust against variations in mechanism parameters and noise, and may destabilize the control system.

  In Patent Document 1, a tracking error signal is accumulated for each phase pulse generated during one rotation of the magnetic disk, and this accumulated value is sequentially fed forward in order of accumulation for each phase pulse to suppress the tracking error. In Patent Document 1, a tracking error signal is multiplied by a predetermined value and accumulated, or the tracking error signal is accumulated as a constant value. Since the value obtained by accumulating the tracking error signal is sequentially fed forward, if the multiplication value is made small, the robustness can be improved against fluctuations in mechanism parameters, noise, and sudden disturbances.

  However, the technique of Patent Document 1 has a problem that it takes time until the accumulated value converges by making the multiplication value small. On the other hand, if the multiplication value is increased, the robustness is lowered and the control system may be destabilized.

  Further, since Patent Document 1 is a technology that considers a magnetic disk as a control target, it is necessary to prepare an accumulated value corresponding to a phase pulse for one rotation of the disk. When an encoder with high resolution is used, an arithmetic unit is used. There was a problem of having to take a large storage area.

  The present invention has been made in view of the above, and an object thereof is to more stably perform drive control of a rotating system.

  In order to solve the above-described problems and achieve the object, the present invention provides a pulse-by-pulse detection speed obtained from a pulse output from a position detection unit according to the rotational position of a speed reducer that decelerates the rotation of a motor. And a storage unit for storing the detection speed for each pulse filter-calculated by the filter-calculation unit for the number of pulses corresponding to a predetermined cycle shorter than the cycle of one rotation of the speed reducer A first multiplier that multiplies the detection speed for each pulse stored in the storage unit by a first constant that is predetermined, and a delay that is predetermined for the multiplication output of the first multiplier And a first adder that adds the multiplication output delayed by the phase adjuster to the output of the compensator that compensates for the rotational speed of the motor.

  According to the present invention, there is an effect that drive control of the rotation system can be performed more stably.

FIG. 1 is a diagram schematically showing an example of the structure of an image forming apparatus applicable to each embodiment. FIG. 2 is a diagram illustrating an example of a drive control mechanism applicable to each embodiment. FIG. 3 is a block diagram illustrating a configuration of an example of a drive control unit applicable to each embodiment. FIG. 4A is a block diagram illustrating the configuration of an example of a periodic component extraction unit according to the first embodiment. FIG. 4-2 is a block diagram illustrating a configuration example of a periodic component extraction unit according to a modification of the first embodiment. FIG. 5 is a block diagram illustrating a configuration of an example of a periodic component extraction unit according to the second embodiment. FIG. 6 is a block diagram illustrating a configuration of an example of a periodic component extraction unit according to the third embodiment. FIG. 7 is a diagram for explaining on / off control of integration operation with hysteresis according to the third embodiment. FIG. 8 is a timing chart illustrating an example of acquisition of a periodic variation value and output timing of a correction value according to the third embodiment. FIG. 9 is a functional block diagram illustrating functions of the periodic component extraction unit according to the third embodiment. FIG. 10 is a diagram for explaining the ring buffer according to the third embodiment. FIG. 11 is a diagram for schematically explaining the correction operation according to the third embodiment. FIG. 12 is a Bode diagram for explaining phase compensation according to the third embodiment. FIG. 13 is a diagram schematically illustrating an example of phase compensation when the effect of suppressing the fluctuation period component cannot be sufficiently obtained. FIG. 14 is a functional block diagram illustrating functions of an example of a periodic component extraction unit according to a modification of the third embodiment. FIG. 15 is a block diagram illustrating a configuration of an example of a periodic component extraction unit according to the fourth embodiment. FIG. 16 is a diagram for explaining that it is preferable to input the detection speed to the periodic component extraction unit rather than the speed deviation. FIG. 17 is a block diagram illustrating an exemplary configuration when the periodic component extraction unit according to each embodiment is realized by software.

  Exemplary embodiments of a drive control device, a drive control method and program, and an image forming apparatus will be described below in detail with reference to the accompanying drawings.

  Hereinafter, an example in which the drive control device according to each embodiment is applied to an image forming apparatus, for example, a copier that forms a color image will be described. However, the applicable apparatus is not limited to this. For example, a printing device that receives image data from an external controller such as a PC (personal computer) and forms an image is also included. Also, for example, it can be applied to any image forming apparatus such as a copying machine, a printer, a scanner device, a facsimile device, and a multifunction device having at least two functions among a copy function, a printer function, a scanner function, and a facsimile function. can do. Furthermore, the drive control device according to each embodiment can be applied to other types of devices as long as it has a structure for driving the rotating body by decelerating the rotation of the motor using a reduction mechanism. is there.

(Configuration common to each embodiment)
FIG. 1 schematically shows an example of the structure of an image forming apparatus 10 applicable to each embodiment. In each embodiment, a case where a breakage of a gear for driving an intermediate transfer belt used in a color copying machine is detected will be described as an example. As shown in FIG. 1, the image forming apparatus 10 includes a scanner unit 11, photoconductor units 12a to 12d, a fixing unit 13, an intermediate transfer belt 14, a secondary transfer roller 15, a registration roller 16, and a supply roller. A paper roller 17, a paper transport roller 18, a transfer paper 19, a paper feed unit 20, a repulsive roller 21, a paper discharge unit 22, and an intermediate transfer scale detection sensor 23 are provided.

  The scanner unit 11 reads an image of a document placed on the upper surface of the document table. Each of the photosensitive units 12a to 12d corresponds to four colors of YCMK, and includes a drum-shaped photosensitive drum as a latent image carrier, a photosensitive member cleaning roller, and the like. Hereinafter, when the color is not specified, it may be simply referred to as the photoreceptor unit 12.

  The fixing unit 13 fixes the transferred toner image on the transfer paper 19. The intermediate transfer belt 14 superimposes and transfers the YCMK color toner images formed by the photoconductor units 12 a to 12 d to the transfer paper 19. The intermediate transfer belt 14 is an image forming medium on which an image is formed by the photoreceptor units 12a to 12d. The intermediate transfer belt 14 is driven by a driving roller 30. The driving roller 30 is driven by a motor 52 at a reduced rotational speed via gears 55 and 56 connected with different numbers of teeth.

  The secondary transfer roller 15 transfers the image on the intermediate transfer belt 14 to the transfer paper 19. The registration roller 16 performs skew correction of the transfer paper 19 and transfer paper transfer. The paper feed roller 17 sends the transfer paper 19 from the paper feed unit 20 to the transport unit. The paper transport roller 18 transports the transfer paper 19 sent from the paper feed roller 17 to the registration roller 16.

  The paper feeding unit 20 loads the transfer paper 19. The repulsive roller 21 is disposed at a portion facing the secondary transfer roller 15, and generates and maintains a nip between the intermediate transfer belt 14 and the secondary transfer roller 15. The paper discharge unit 22 discharges the transfer paper on which the image has been transferred and fixed. The intermediate transfer scale detection sensor 23 is an encoder for measuring the conveyance speed of the intermediate transfer belt 14 and detects a scale formed on the intermediate transfer belt 14 to generate a pulse output.

  In the above-described configuration, when the surface speed of the intermediate transfer belt 14 fluctuates, the overlapping positions of the YCMK toner images may be shifted or the toner images may expand and contract. This causes image defects such as color misregistration and color shading called banding.

  As a cause of changing the surface speed of the intermediate transfer belt 14, a friction load, eccentricity or load fluctuation of a rotating body such as the driving roller 30 and gears 55 and 56, thickness fluctuation of the intermediate transfer belt 14, and rotational position of the motor 52 are detected. There may be a mounting eccentricity of a rotary encoder (not shown), a mounting eccentricity of a speed reduction mechanism (gears 55, 56, etc.), load fluctuation, motor rotation unevenness, torque fluctuation due to paper entry or clutch on / off, and the like. Considering these as disturbances, fluctuations due to frictional loads are steady or very low frequency components, and can be suppressed by performing feedback control. Since the fluctuation due to the thickness of the intermediate transfer belt 14 is also a low frequency component compared to the fluctuation due to the eccentricity of other rotating bodies, if the surface speed of the intermediate transfer belt 14 can be directly detected, feedback control using this is possible. Can be suppressed.

  On the other hand, among the fluctuation components of the rotating body, the eccentricity of the speed reduction mechanism and the rotation unevenness of the motor are caused by the mechanical resonance frequency (hereinafter referred to as the rigidity of the rotating body and the intermediate transfer belt 14 and the rigidity of the connecting portion between the drive shaft and the speed reduction mechanism). The frequency is close to the mechanical resonance frequency of the intermediate transfer belt mechanism. For this reason, the control system that simply feeds back the belt surface speed is a control system having a response frequency equal to or lower than the mechanical resonance frequency of the intermediate transfer belt mechanism, and the disturbance cannot be sufficiently suppressed due to insufficient gain, thereby achieving the desired required specifications. Have difficulty.

  Therefore, a double-loop feedback control system is proposed that consists of a minor loop that attaches a rotary encoder to the drive shaft after deceleration and feeds back the value of this rotary encoder, and a major loop that feeds back the value of the encoder pattern on the belt surface. Has been. In JP 2009-222112 A, in this double loop feedback control system, by further providing means for amplifying a gain of a desired frequency in the minor loop, the frequency due to eccentricity of the speed reduction mechanism and motor rotation unevenness is disclosed. Belt drive control devices that suppress components are proposed.

  In each embodiment, a drive control device having a configuration capable of suppressing even a high frequency component instead of means for amplifying a gain of a desired frequency according to Japanese Patent Application Laid-Open No. 2009-222112 will be described.

  FIG. 2 shows an example of a drive control mechanism of the intermediate transfer belt 14 in the image forming apparatus 10 applicable to each embodiment. In FIG. 2, the same reference numerals are given to portions common to those in FIG. 1 described above, and detailed description thereof is omitted.

  The motor and speed reduction mechanism 50 includes a motor 52 having a gear 55 cut on a shaft, and a speed reduction gear 56 that reduces the rotation of the gear 55 and transmits it to the drive roller 30. In the example of FIG. 2, the gear 55 and the reduction gear 56 constitute a reduction mechanism. In the speed reduction mechanism, the input side gear may be attached to the shaft of the motor 52. In the example of FIG. 2, the speed reduction mechanism is shown as having two gears 55 and a speed reduction gear 56, but this is not limited to this example. For example, the motor and the speed reduction mechanism 50 may be configured using three or more gears, or may be a planetary gear mechanism.

  A code wheel 58 of a rotary encoder is attached to the output shaft of the reduction mechanism (in the example of FIG. 2, the shaft of the reduction gear 56), and the slit of the code wheel 58 is connected to the drive shaft encoder sensors 59a and 59b. read. The drive shaft encoder sensors 59a and 59b are arranged at positions that are 180 degrees out of phase with respect to the code wheel 58. By using the average value of the outputs of the drive shaft encoder sensors 59a and 59b, the eccentric component of the code wheel 58 is reduced. It can be corrected.

  The drive shaft encoder sensors 59a and 59b detect the movement of the code wheel 58 and output encoder pulses that are binary signals. The output of the drive shaft encoder sensors 59a and 59b may be a two-phase binary signal having a 90-degree phase difference, a single-phase analog signal, or a two-phase analog signal. In this example, the two drive shaft encoder sensors 59a and 59b are used. However, the eccentric component of the code wheel 58 can be suppressed by feedback of the surface speed of the intermediate transfer belt 14, and in this case, Only one of the drive shaft encoder sensors 59a and 59b may be used.

  The belt mechanism 51 includes an intermediate transfer belt 14, a driving roller 30, and repulsive rollers 21, 25 and 26. In the belt mechanism 51, the driving roller 30 is driven by a rotation shaft of a reduction gear 56 that is an output shaft of the reduction mechanism. The output shaft of the speed reduction mechanism and the shaft of the drive roller 30 may be integrally formed, but may be connected by a joint mechanism or the like in consideration of maintainability. The driving roller 30 drives the intermediate transfer belt 14. The intermediate transfer belt 14 is supported by a plurality of repulsive rollers 21, 25 and 26. For example, the driven roller 26 has a tension adjusting mechanism for the intermediate transfer belt 14, and the repulsive roller 21 also has a function of a transfer shaft that transfers a toner image formed on the intermediate transfer belt 14 to a sheet.

  An encoder pattern 24 is engraved on the surface of the intermediate transfer belt 14, and the surface speed (belt surface speed) of the intermediate transfer belt 14 is detected by reading the encoder pattern 24 with the intermediate transfer scale detection sensor 23. The intermediate transfer scale detection sensor 23 outputs an encoder pulse which is a binarized output according to the read encoder pattern 24.

  The encoder pattern 24 may be carved on the back surface of the intermediate transfer belt 14. In the example of FIG. 2, the intermediate transfer scale detection sensor 23 is provided between the driven rollers 25 and 26, but this is an example, and in order to correctly measure the belt surface speed, the intermediate transfer belt 14. If is a flat part, the intermediate transfer scale detection sensor 23 may be provided in another part. For example, it may be between the driving roller 30 and the driven roller 25 or between the driving roller 30 and the repulsive roller 21.

  Further, when the intermediate transfer scale detection sensor 23 is provided on the rotation shaft of each roller or the like, the influence of the curvature of the rotation shaft appears on the output of the intermediate transfer scale detection sensor 23. In this case, the distance between the encoder patterns 24 may change due to the thickness variation in manufacturing of the intermediate transfer belt 14 or the variation due to environmental changes, and the belt surface speed may not be correct. Therefore, it is necessary to avoid providing the intermediate transfer scale detection sensor 23 on the rotation shaft of each roller or the like.

  The encoder pattern 24 may be manufactured by any method. For example, the sheet-like encoder pattern 24 may be attached to the intermediate transfer belt 14 or may be directly patterned on the intermediate transfer belt 14. The encoder pattern 24 may be processed integrally with the intermediate transfer belt 14 in the manufacturing process of the intermediate transfer belt 14.

  Further, the intermediate transfer scale detection sensor 23 is assumed to be a reflection type optical sensor having slits at equal intervals. However, any sensor that can accurately detect the surface position of the intermediate transfer belt 14 from the encoder pattern 24 may be used. For example, the surface position may be detected by imaging the encoder pattern 24 using a camera using a CCD (Charge Coupled Device) as an imaging device and performing image processing on the captured image. Furthermore, the encoder pattern 24 can be omitted if the sensor system can detect the surface position by image processing from the Doppler method or the unevenness of the belt surface.

  The outputs of the drive shaft encoder sensors 59 a and 59 b and the output of the intermediate transfer scale detection sensor 23 are input to the drive control unit 100. The drive control unit 100 uses the output signals of the drive shaft encoder sensors 59a and 59b and the intermediate transfer scale detection sensor 23 to calculate the rotation speed of the drive roller 30 and the belt surface speed, and determines a predetermined value based on the calculation result. A control value is calculated to obtain a command value for driving the motor 52 at a predetermined rotational speed. The command value is passed from the drive control unit 100 to a motor driver (not shown), and the motor driver drives the motor 52 according to the command value.

  The motor 52 may be a brush motor or a brushless motor. The drive circuit of the motor driver varies depending on the type of the motor 52. The motor driver may be a voltage control method or a current control method. If it is a driver of a current control system, it will be robust against changes over time and environmental changes. The signal format of the command value to the motor driver is not particularly limited, and analog values, digital values, PWM (Pulse Width Modulation), etc. can be used, and the motor driver can obtain an output proportional to the command value. Anything is acceptable. The motor driver may be PWM driving or linear driving.

  The control calculation performed by the drive control unit 100 may be performed using either an analog value or a digital value. For example, a control operation is generally performed using a digital arithmetic unit such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). In this case, the control operation is described by software. However, the present invention is not limited to this, and simple control calculation and operation logic may be performed by hardware logic as long as there is no parameter change.

  FIG. 3 shows an exemplary configuration of the drive control unit 100 applicable to each embodiment. The drive controller 100 includes comparators 110 and 112, an adder 114, a belt speed compensator 111, a drive shaft speed compensator 113, a motor driver 115, a drive shaft speed calculator 116, and a belt speed calculator. 117 and a periodic component extraction unit 200. In the drive control unit 100, the motor driver 115 drives the motor 52 in accordance with the command value output from the adder 114, and drives the mechanism unit 101 including the motor and speed reduction mechanism 50 and the belt mechanism 51. In FIG. 3, the drive shaft encoder sensors 59 a and 59 b attached to the drive shaft of the reduction gear 56 are collectively shown as the drive shaft encoder sensor 59.

  The drive control unit 100 performs a major loop that feeds back the belt surface speed based on the output of the intermediate transfer scale detection sensor 23 of the belt mechanism 51 and the output of the drive shaft encoder sensor 59 attached to the drive shaft of the reduction gear 56. The rotational speed of the motor 52 is controlled by a double loop including a minor loop that feeds back the rotational speed of the drive shaft.

  A target speed (belt target speed) of the intermediate transfer belt 14 is input to one input terminal of the comparator 110. The belt speed calculation unit 117 calculates the speed (belt speed) of the intermediate transfer belt 14 based on the output of the intermediate transfer scale detection sensor 23 provided in the belt mechanism 51. The calculated belt speed is input to the other input terminal of the comparator 110. In the comparator 110, values input to one and the other input terminals are compared, and a difference is output. More specifically, the comparator 110 subtracts the belt speed input to the other input terminal from the belt target speed input to one input terminal, and outputs a belt speed deviation. The belt speed deviation is input to the belt speed compensator 111.

  The belt speed compensator 111 outputs a drive shaft target speed based on the belt speed deviation. The drive shaft target speed is a target speed for driving the drive roller 30 so as to control the belt surface speed of the intermediate transfer belt 14 to be constant. The drive shaft target speed is input to one input terminal of the comparator 112.

  The drive shaft speed calculation unit 116 calculates the rotation speed (drive shaft speed) of the drive shaft of the reduction gear 56 based on the output of the drive shaft encoder sensor 59. The calculated drive shaft speed is input to the other input terminal of the comparator 112. In the comparator 112, the values input to one and the other input terminals are compared and a difference is output. More specifically, in the comparator 112, the drive shaft speed input to the subtraction input terminal is subtracted from the drive shaft target speed input to the subtracted input terminal, and the drive shaft speed deviation is output.

  The drive shaft speed compensator 113 calculates a motor command value that specifies the rotation speed of the motor 52 based on the drive shaft speed deviation. In the adder 114, the motor command value and the output of the periodic component extraction unit 200 are added. As will be described in detail later, the periodic component extraction unit 200 extracts a periodic variation of the speed reduction mechanism, and outputs a correction value for correcting the motor command value output from the drive shaft speed compensation unit 113 based on the extracted periodic variation. To do. In the example of FIG. 3, the adder 114 is used as a subtracter because the input end on the periodic component extraction unit 200 side is an inverting input.

  The corrected motor command value output from the adder 114 is supplied to the motor driver 115. The motor driver 115 drives the motor 52 in accordance with the corrected motor command value supplied from the adder 114. The rotation of the motor 52 is transmitted to the drive roller 30 via the gear 55 and the reduction gear 56, and the intermediate transfer belt 14 is driven.

  Since the rotational speed of the drive shaft of the reduction gear 56 is detected by a rotary encoder and the belt surface speed is detected by a linear encoder, the unit system differs between the rotational speed of the drive shaft and the belt surface speed. In general, the detection output of the rotary encoder is output as an angle, the unit system is radians (rad), the detection output of the linear encoder is output as a length, and the unit system is meters (m). Therefore, it is necessary to convert the speed obtained by the drive shaft encoder sensor 59 and the intermediate transfer scale detection sensor 23 into one of the unit systems.

  When unifying the rotational speed of the drive shaft with the belt surface speed, the speed unit is "m / s" (meter per second), and the unit conversion coefficient for converting the drive shaft speed is the drive shaft speed calculation unit. 116. Further, the drive shaft speed compensator 113 also has a coefficient matched to “m / s”. On the other hand, when the belt surface speed is unified with the drive shaft speed, the unit of speed is “rad / s” (radian per second), and the belt speed compensator 111 has a coefficient for conversion to “rad / s”. Become.

  The response frequency of the minor loop that feeds back the value of the rotary encoder (drive shaft encoder sensor 59) is the response frequency of the major loop that feeds back the value of the outer linear encoder (intermediate transfer scale detection sensor 23). On the other hand, it needs to be high enough. Generally, the response frequency band of the minor loop is a frequency band that is 5 to 10 times higher than the response frequency band of the major loop.

(First embodiment)
Next, a first embodiment will be described. FIG. 4A illustrates an exemplary configuration of the periodic component extraction unit 200A according to the first embodiment. In FIG. 4A, the configuration of the drive control unit 100 including the periodic component extraction unit 200 </ b> A is illustrated by extracting portions related to the periodic component extraction unit 200 </ b> A. This also applies to FIGS. 4-2, 5, 6, and 15 described later. The configuration shown in FIG. 4A and FIG. 4B, FIG. 5, FIG. 6, and FIG. 15, which will be described later, corresponds to the minor loop portion of the double loop described above.

  4A, the comparator 202 corresponds to the comparator 112 in FIG. 3, and the adder 204 corresponds to the adder 114 in FIG. 3. Also, the compensator 203, the driver 205, and the speed calculation unit 208 in FIG. 4-1 correspond to the drive shaft speed compensator 113, the motor driver 115, and the drive shaft speed calculation unit 116 in FIG. 3, respectively. Further, the motor 206 and the speed reduction mechanism 207 in FIG. 4A are included in the motor and the speed reduction mechanism 50 of FIG. 3, respectively, and the output of the speed reduction mechanism 207 is the output of the drive shaft encoder sensor 59.

  In the first embodiment, the periodic component extraction unit 200A includes a filter calculation unit 210, a speed storage unit 211, a speed integration unit 212, a multiplication unit 213, and a phase adjustment unit 214.

  The speed calculation unit 208 detects the rotation speed of the drive shaft of the reduction gear, that is, the reduction gear 56 from the output of the drive shaft encoder sensor 59 attached to the reduction side in the reduction mechanism unit 207. For speed detection, a method can be used in which the interval between encoder pulses output from the drive shaft encoder sensor 59 is counted with a basic clock to obtain a cycle. However, the present invention is not limited to this, and speed detection may be performed using a method of calculating from the difference of the pulse counter.

  The speed calculation unit 208 outputs the rotation speed for each encoder pulse of the drive shaft encoder sensor 59. The rotation speed is represented, for example, by a count value when the encoder pulse interval is counted with a basic clock. The rotational speed of the drive shaft output from the speed calculation unit 208 is compared with the target speed 201 (drive shaft target speed) by the comparator 202, and the difference is output as a drive shaft speed deviation. The compensator 203 outputs a PWM value corresponding to the drive voltage for driving the motor 206 based on the drive shaft speed deviation output from the comparator 202.

  In the adder 204, the PWM value corresponding to the correction value output from the periodic component extraction unit 200A is added to the PWM value corresponding to the drive voltage output from the compensator 203, and the drive voltage output from the compensator 203 is output. A corrected PWM value obtained by correcting the corresponding PWM value is output. In the example of FIG. 4A, since the input end of the adder 204 on the periodic component extraction unit 200A side is an inverting input, the correction PWM value is changed from the PWM value corresponding to the drive voltage to the PWM value corresponding to the correction value. The value obtained by subtracting. The corrected PWM value is input to the driver 205 as a motor command value for driving the motor 206. The driver 205 drives the motor 206 in voltage according to the supplied motor command value. The rotation of the motor 206 is decelerated by the decelerating mechanism of the decelerating mechanism unit 207 to drive the belt mechanism 51 (not shown).

  Next, the operation of the periodic component extraction unit 200A according to the first embodiment will be described. The rotational speed of the drive shaft on the deceleration side output for each encoder pulse of the drive shaft encoder sensor 59 from the speed calculation unit 208 is supplied to the filter calculation unit 210. The filter calculation unit 210 performs band pass filter calculation for extracting a predetermined frequency component from the rotation speed for each supplied encoder pulse.

  For example, when the speed calculation unit 208 uses a count value obtained by counting the intervals of encoder pulses output from the drive shaft encoder sensor 59 with a basic clock as a value indicating the rotation speed, the speed calculation unit 208 receives a value for each encoder pulse. The count value is output. The filter calculation unit 210 can extract a variation in the count value for each encoder pulse by performing a band pass filter operation on the count value for each encoder pulse.

  The frequency component extracted by the filter calculation unit 210 corresponds to the frequency component of the periodic fluctuation to be suppressed. For example, a frequency equivalent to one rotation of the motor and a meshing frequency of the gears of the reduction mechanism (the gear 55 and the reduction gear 56) can be set in advance for the filter calculation unit 210. The frequency that can be set in the filter calculation unit 210 is not limited to one type, and a plurality of frequencies can be set. In this case, a plurality of filter operation units 210 each having a predetermined frequency are connected in parallel.

  A value (referred to as a period variation value) for each encoder pulse of the frequency component extracted by the filter calculation unit 210 is supplied to the speed storage unit 211. The speed storage unit 211 sequentially holds the supplied period variation value for each phase corresponding to each encoder pulse in the period of the period variation. For example, the speed storage unit 211 has a storage region for each encoder pulse included in the cycle of the cycle variation, and sequentially stores the cycle variation value of each phase in each storage region. The speed integration unit 212 has a storage area corresponding to the speed storage unit 211, and uses the storage area to calculate the cycle variation value held in the speed storage unit 211 for each corresponding phase in the cycle. To do.

  The period variation values accumulated by the speed accumulation unit 212 are sequentially selected for each encoder pulse, and the multiplication unit 213 multiplies a predetermined gain. Each period variation value multiplied by the gain by the multiplication unit 213 is supplied to the phase adjustment unit 214 to adjust the phase and output from the period component extraction unit 200A. Each periodic variation value output from the periodic component extraction unit 200A is added to the output of the compensator 203 by the adder 204 as a correction value for correcting the periodic variation.

  The correction value output from the periodic component extraction unit 200A moves so that the error (period fluctuation) approaches zero. In other words, the correction value is 0 when it completely converges. At this time, since the error is accumulated by the speed integrating unit 212, a predetermined time is required until the error is converged to a steady value. The convergence time of the correction value can be adjusted by the gain setting in the multiplier 213. By setting a larger gain, the convergence time can be made faster, but it is more susceptible to noise and parameter fluctuations, and the correction value becomes unstable. A method of setting the gain of the multiplier 213 for stabilizing the correction value will be described later.

  In the above-described configuration, each storage area of the speed storage unit 211 and the speed integration unit 212 only needs to be able to hold data for the number of encoder pulses corresponding to one rotation of the motor 52. It is not necessary to be able to hold data for the number of encoder pulses.

  The desired frequency can be expressed with at least two pulses per cycle. However, in order to increase the correction accuracy when correcting the period fluctuation, the encoder pulse needs to have a resolution higher than a predetermined value.

  As an example, consider the case of correcting the periodic variation of the motor 52. In this case, for example, assuming that the number of encoder pulses corresponding to one rotation of the motor 52 is 40 pulses and the reduction ratio of the reduction mechanism is 10, the encoder pulses by the drive shaft encoder sensor 59 necessary for correcting the cycle fluctuation of the motor 52 The number may be an integer multiple of 40 pulses × 10 = 400 pulses per rotation of the motor 52. Therefore, here, the resolution of the drive shaft encoder sensor 59 is set to 400 (pulse / rotation).

  As described above, in the first embodiment, the speed storage unit 211 sequentially holds the period fluctuation values for the pulses included in the period fluctuation period for each encoder pulse. Therefore, when the number of encoder pulses corresponding to one rotation of the motor 52 is 40, the storage area of the speed storage unit 211 and the speed integration unit 212 only needs to hold 40 pieces of data.

  As another example, let us consider a case where periodic fluctuation due to gear meshing is suppressed. For example, the number of gear teeth per revolution of the motor 52 is 10. In this case, the number of encoder pulses per one gear cycle is four pulses. Assuming that the number of encoder pulses per rotation of the motor 52 is 40 as described above, the least common multiple of the number of encoder pulses per one cycle of the gear and the number of encoder pulses per one rotation of the motor 52 is 40. The storage area of 211 and the speed integration unit 212 only needs to be able to hold 40 pieces of data.

  Furthermore, in order to improve the effect of suppressing the gear meshing cycle variation, it is necessary to increase the resolution by increasing the number of encoder pulses corresponding to the gear meshing frequency.

  Furthermore, the number of encoder pulses obtained as described above is the number of encoder pulses necessary for suppressing the period fluctuation, and is different from the number of encoder pulses necessary for ensuring the control performance of the feedback control system. . In order to reduce the dead time due to the output signal processing of the drive shaft encoder sensor 59 and improve the response frequency of the feedback control system, a finer resolution may be required for the encoder pulse.

  The phase adjustment unit 214 sets a value in consideration of the phase delay from the input of the corrected PWM value to the driver 205 to the output from the drive shaft encoder sensor 59.

  Incidentally, since the voltage and current that can be applied to the driver 205 are limited, the correction value that is the output of the periodic component extraction unit 200A must also be limited. When the integrated value of the speed integrating unit 212 exceeds the limit value, the corresponding voltage or current cannot actually be applied to the driver 205, so that the time for the correction value to converge to the steady value becomes long. Therefore, a limit is provided on the integrated value of the speed integrating unit 212 so that the integrated value does not exceed the limit value.

The limit value int_dat_lim of the integrated value can be obtained by the following equation (1), for example. In Equation (1), the value Vlim is the voltage limit of the driver 205, and the constant Gi _FF is the gain of the multiplier 213. When the integrated value of the speed integrating unit 212 exceeds the limit value int_dat_lim, the integrated value is fixed to the limit value int_dat_lim. Although the example on the positive side has been described here, the same applies to the negative side.

(Modification of the first embodiment)
Next, a modification of the first embodiment will be described. The speed integration unit 212 may be omitted from the periodic component extraction unit 200A illustrated in FIG. 4A described above, and the period variation value held in the speed storage unit 211 may be directly supplied to the multiplication unit 213 as a correction value. FIG. 4B illustrates an example of the configuration of the periodic component extraction unit 200A ′ in which the speed integration unit 212 is omitted according to a modification of the first embodiment. In FIG. 4B, parts common to those in FIG. 4A are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the periodic component extraction unit 200 </ b> A ′ illustrated in FIG. 4B, the periodic variation value held in the speed storage unit 211 is directly supplied to the multiplication unit 213. In this case, since the suppression effect of the periodic component is small as compared with the configuration using the speed integration unit 212 illustrated in FIG. 4A, the time required for convergence of the correction output is short. Responsiveness is improved. At the same time, the configuration of FIG. 4B does not require a storage area for the speed integration unit 212 as compared to the configuration of FIG.

(Second Embodiment)
Next, a second embodiment will be described. In the second embodiment, the outputs of the speed storage unit 211 and the speed integration unit 212 are respectively multiplied by gains and added to the configuration of the first embodiment, and the addition result is added via the phase adjustment unit 214 to the compensator 203. Is added to the output of.

  FIG. 5 shows an example of the configuration of the periodic component extraction unit 200B according to the second embodiment. In FIG. 5, the same reference numerals are given to portions common to the above-described FIG. 4A, and detailed description thereof is omitted. The periodic component extraction unit 200B according to the second embodiment is provided with multiplication units 213A and 213B instead of the multiplication unit 213 with respect to the periodic component extraction unit 200A according to the first embodiment, and the multiplication units 213A and 213B. An adder 215 for adding the outputs is added.

The output of the speed storage unit 211 is input to the speed integration unit 212 and also input to the multiplication unit 213B and multiplied by the proportional gain Gp _FF . The output of the speed integrating unit 212 is input to the multiplying unit 213A, and the integrated value is multiplied by the proportional gain Gi _FF . The outputs of the multiplication unit 213A and the multiplication unit 213B are added by the adder 215, and the phase is adjusted by the phase adjustment unit 214. The output of the phase adjustment unit 214 is added to the output of the compensator 203 by the adder 204. Thereby, the periodic fluctuation of the output of the compensator 203 is corrected.

According to the periodic component extraction unit 200B of the second embodiment, the time required for correcting the periodic fluctuation is shortened by the output of the speed storage unit 211, and the correction accuracy of the periodic fluctuation is improved by the output of the speed integrating unit 212. Can do. By increasing the proportional gain Gi _FF of the multiplication unit 213A, the correction performance from the initial state can be improved. Further, by increasing the proportional gain Gp _FF of the multiplication unit 213B, the convergence of the correction output can be made faster.

(Multiplier gain setting)
Here, a setting method of the proportional gains Gi _FF and Gp _FF of the multipliers 213A and 213B will be described. The setting of the proportional gain Gp _FF of the multiplication unit 213B to which the output of the speed storage unit 211 is supplied may generally be equal to or less than the inverse model to be controlled in the case of feedforward control. For example, consider that the transfer function from voltage to angular velocity is expressed by the following equation (2). Here, the value ω is the angular velocity (rad / s), the value V is the voltage value (volt), the value K _e is an induced voltage constant (volt / (rad / s) ), the value T _e is the electrical time constant (s), The value T _m is the machine time constant (s) and the value s is the Laplace operator.

Based on the equation (2), the inverse model is expressed by the following equation (3).

Therefore, Gp _FF is obtained by setting the frequency of periodic fluctuation as Laplace operator s → jω.

The proportional gain Gi _FF of the multiplication unit 213A to which the output of the speed integration unit 212 is supplied is obtained as a form of a compensator of Gi _FF / s that does not make the controlled transfer loop function unstable. If the proportional gain Gi _FF is too large, it becomes unstable.

Generally, the convergence time of the correction operation changes depending on the setting of the proportional gain Gi _FF of the multiplication unit 213A. When a proportional gain Gi _FF that is a gain with respect to the output of the speed integrating unit 212 is used, the proportional gain Gp _FF that is a gain with respect to the output of the speed storage unit 211 may be small, and correction can be performed by setting the proportional gain Gp _FF . The rise characteristics can be adjusted.

(Third embodiment)
Next, a third embodiment will be described. In the third embodiment, the configuration of the speed integration unit 212 is different from the configuration of the second embodiment described above. FIG. 6 shows an example of the configuration of a periodic component extraction unit 200C according to the third embodiment. In FIG. 6, parts common to those in FIG. 5 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

In the periodic component extraction unit 200C, the output of the speed storage unit 211 is supplied to the multiplication unit 213B, multiplied by the proportional gain Gp _FF , and supplied to the speed integration unit 216. The output of the speed integration unit 216 is supplied to the multiplication unit 213A and multiplied by the proportional gain Gi _FF . The outputs of the multiplication unit 213A and the multiplication unit 213B are added by the adder 215, and the phase is adjusted by the phase adjustment unit 214. The output of the phase adjustment unit 214 is added to the output of the compensator 203 by the adder 204. Thereby, the periodic fluctuation of the output of the compensator 203 is corrected.

  The speed integration unit 216 integrates the periodic variation value output from the speed storage unit 211, and turns on / off the integration operation by the integration unit 218 in accordance with the periodic variation value output from the filter calculation unit 210. And a switch unit 217 to be controlled. Since the operation of the accumulating unit 218 is common to the operation of the speed accumulating unit 212 described above, description thereof is omitted here.

  The switch unit 217 controls the speed integration unit 216 so that the integration operation in the integration unit 218 is not performed (turned off) when the periodic variation value output from the filter calculation unit 210 is within a predetermined range near 0. Control. On the other hand, when the cycle variation value output from the filter calculation unit 210 is outside the predetermined range, the switch unit 217 performs the integration operation of the output of the speed storage unit 211 (turns on) in the integration unit 218. In addition, the speed integrating unit 216 is controlled.

  In the example of FIG. 6, the output of the speed storage unit 211 is input to one input terminal of the switch unit 217, and the value “0” is input to the other input terminal. The switch unit 217 selects the other input end and inputs 0 to the integrating unit 218 when the period variation value from the filter calculating unit 210 is within the predetermined range. On the other hand, when the period variation value from the filter calculation unit 210 is outside the predetermined range, the switch unit 217 selects one input end and inputs the output of the speed storage unit 211 to the integration unit 218.

  In a state where the periodic fluctuation value output from the filter operation unit 210 approaches 0, in other words, in a state where the error due to the periodic component approaches 0, noise components and discretization errors included in the output of the filter operation unit 210, The effect of numerical rounding error is relatively large. In the third embodiment, when the output value of the filter calculation unit 210 approaches zero, the speed accumulation unit 216 does not perform the accumulation operation. As a result, the influence of noise, discretization error, numerical rounding error, etc. included in the output of the filter calculation unit 210 can be eliminated, the correction output of the periodic component extraction unit 200C can be stabilized, and the periodic fluctuation suppression effect can be achieved. Can be stabilized.

  In the above description, the integration operation of the speed integration unit 216 is described as simply performing threshold determination on the output value of the filter calculation unit 210 to control on / off, but this is not limited to this example. That is, by providing hysteresis to the ON / OFF control of the integration operation as illustrated in FIG. 7, it is possible to prevent malfunction due to noise and improve transient characteristics by switching ON / OFF of the integration operation. preferable.

  That is, as the period fluctuation component decreases, the value extracted by the filter calculation unit 210 also decreases, error components such as noise and digit loss due to digital calculation increase, and S / N deteriorates. If a value with a poor S / N is accumulated, the periodic fluctuation correction value becomes an abnormal value, and the control system may oscillate by feed-forwarding this correction value. The operation which prevents is performed. For example, when the output of the filter calculation unit 210 is within the threshold range, the integration operation is turned off, and when the output is outside the threshold range, the integration operation is turned on.

  The on / off control of the integration operation with hysteresis will be described more specifically with reference to FIG. 7A shows an example of ON / OFF determination with respect to the periodic variation value output from the filter calculation unit 210, and FIG. 7B shows the periodic variation value. The example of operation | movement of the corresponding switch part 217 is shown. In FIG. 7B, the switch unit 217 turns on the integration operation in the high (H) state and turns off the integration operation in the low (L) state. In FIG. 7A, the on / off determination is shown on the positive side of the period variation value, but the same on / off determination is performed on the negative side.

  As illustrated in FIG. 7A, the first threshold value for performing the OFF determination of the integration operation is set to a value lower than the second threshold value for performing the ON determination with respect to the period variation value near 0. At time A when the error in the correction value decreases and the periodic fluctuation value output from the filter calculation unit 210 approaches 0 and becomes equal to or less than the first threshold value for the OFF determination, the switch unit 217 turns off the integration operation. Thereafter, the error increases, and at time B when the period variation value exceeds the first threshold and becomes equal to or greater than the second threshold of the ON determination, the switch unit 217 turns on the integration operation. After that, when the error decreases and the period variation value becomes smaller than the second threshold value and further becomes equal to or lower than the first threshold value (time point C), the switch unit 217 turns off the integration operation again.

  By bringing the first threshold value for performing the OFF determination closer to 0, the effect of suppressing the periodic fluctuation component is increased, but it is easily affected by an error due to noise or the like. Further, the smaller the difference between the first threshold value and the second threshold value for performing the ON determination, the smaller the fluctuation after suppression of the periodic fluctuation component, but the more easily affected by noise and the like. Therefore, it is preferable to leave a certain distance between the first threshold value and the second threshold value. At this time, if the interval between the first threshold value and the second threshold value is increased, the integrated value (learned) is obtained after the output of the filter calculation unit 210 becomes equal to or less than the first threshold value for performing the OFF determination. Value) will continue to be used. If the periodic fluctuation component becomes large for some reason such as temperature rise or change over time, the integration operation is performed again.

  FIG. 8 shows an example of the acquisition of the period variation value and the output timing of the correction value in the period component extraction unit 200C. In FIG. 8, FIG. 8 (a) shows an example of an encoder pulse (ENC_pulse). Here, it is assumed that 40 pulses of encoder pulses are output from the drive shaft encoder sensor 59 by one rotation of the motor 206, and the fluctuation of the rotation cycle of the motor 206 is suppressed. In FIG. 8A, 40 encoder pulses per rotation of the motor 206 are indicated by numbers # 0 to # 39, respectively.

  8B shows an example of data (fluctuation period values) stored in the storage areas mem_p0, mem_p1, mem_p2,..., Mem_p39 corresponding to each phase of the speed storage unit 211, and FIG. Shows an example of the correction value of each phase output from the adder 215.

  For example, at the n-th rotation of the motor 206, data DATA0_n, DATA1_n, DATA2_n,. Is remembered. That is, the data DATA0_n is stored in the storage area mem_p0 by the encoder pulse # 0. Data DATA1_n is stored in the storage area mem_p1 by the next encoder pulse # 1. Similarly, data is sequentially stored in the storage area for each encoder pulse, and data DATA39_n is stored in the storage area mem_p39 by the last encoder pulse # 39 at the n-th rotation of the motor 206.

  Also in the speed integration unit 216, at the same timing, the integrated values Σ (DATA0) to Σ (DATA39) of the periodic fluctuation values of the respective phases are stored in the storage areas mem_i0, mem_i1, mem_i2, ..., mem_i39 corresponding to the respective phases. Is remembered.

The data DATA0_n is read from the storage area mem_p0 by the encoder pulse # 0 of the (n + 1) th rotation of the motor 206, and is multiplied by the proportional gain Gp _FF by the multiplier 213B. At the same time, with the encoder pulse # 0, the integrated value Σ (DATA0) is read from the storage area mem_i0 and is multiplied by the proportional gain Gi _FF in the multiplier 213A. Data DATA0_n multiplied by the proportional gain Gp _FF and the integrated value Σ (DATA0) multiplied by the proportional gain Gi _FF are added by the adder 215 and output as a correction value before phase adjustment.

  Thereafter, data corresponding to the phase and the integrated value are sequentially read from each storage area for each encoder pulse. Then, the read data and integrated value are respectively multiplied by the corresponding proportional gain, and the data and integrated value multiplied by the proportional gain are added and output as a correction value.

  In parallel with the correction value output process using the data DATA0_n read from the storage area mem_p0 and the integrated value Σ (DATA0) read from the storage area mem_i0, the encoder pulse at the (n + 1) th rotation of the motor 206 Data DATA0_n + 1 by # 0 is acquired and stored in the storage area mem_p0, and data DATA_0n + 1 is added to the integrated value Σ (DATA0), and the integrated value Σ (DATA0) is updated.

  Next, the operation of the periodic component extraction unit 200C will be described in more detail. FIG. 9 is a functional block diagram illustrating functions of the periodic component extraction unit 200C. Note that, in FIG. 9, the same reference numerals are given to portions common to FIG. 6 described above, and detailed description thereof is omitted.

  In the example of FIG. 9, the periodic component extraction unit 200 </ b> C includes a filter calculation unit 210, a speed integration unit 216 having a determination unit 251 and an integration unit 218, selectors / phase adjustment units 252 </ b> A and 252 </ b> B, and multiplication units 213 </ b> A and 213 </ b> B. And an adder 215. Note that the determiner 251 has a function corresponding to the switch unit 217 described above.

  Among these, the selectors / phase adjustment units 252A and 252B respectively correspond to the phase adjustment unit 214 of FIG. That is, the configuration of FIG. 9 is different from the configuration of FIG. 6 in the processing order of the multipliers 213A and 213B, the adder 215, and the phase adjustment unit 214. In the case of performing phase adjustment common to the selectors / phase adjustment units 252A and 252B in the configuration of FIG. 9, each correction value is multiplied by a gain and added to each correction value after phase adjustment. It can be considered that the process of adjusting the phase after multiplying and adding the gains to each is substantially the same.

  In the following, it is assumed that the desired cycle fluctuation to be extracted is a cycle of 40 pulses of encoder pulses output from the drive shaft encoder sensor 59. That is, each of the speed storage unit 211 and the speed integration unit 216 only needs to have a storage area that can hold a period fluctuation value for 40 pulses.

  The rotational speed output for each encoder pulse by the speed calculation unit 208 is supplied to the filter calculation unit 210. The filter calculation unit 210 performs band pass filter calculation for extracting a predetermined frequency component from the supplied rotation speed. As described above, the frequency component extracted by the band-pass filter operation corresponds to the frequency component of the periodic fluctuation to be suppressed. The frequency component data extracted by the filter calculation unit 210, that is, the period variation value is supplied to the determiner 251 as a determination reference signal and also to the distributor 250.

  The distributor 250 is supplied with an encoder pulse (ENC pulse) and sequentially outputs a period variation value at the timing of the encoder pulse. At this time, the distributor 250 distributes the period fluctuation value for each encoder pulse in units of 40 encoder pulses, which are the period of the desired period fluctuation to be extracted. That is, the distributor 250 outputs the supplied frequency fluctuation value for each phase corresponding to each encoder pulse in the desired period fluctuation period to be extracted. In this example, in which the desired period variation period is 40 encoder pulses, the period variation value is distributed and output by the distributor 250 for each phase corresponding to each 40 pulse.

  The phase fluctuation values output from the distributor 250 are input to the determiner 251 and sequentially stored in the 40 storage areas mem_p0, mem_p1, mem_p2,..., Mem_p39 of the speed storage unit 211. .

  The determiner 251 determines whether or not to integrate the supplied periodic variation values of each phase using the periodic variation value output from the filter calculation unit 210 as a determination reference signal in the same manner as the switch unit 217 described above. Determine. More specifically, the determiner 251 determines whether to use the extracted periodic variation value or the value “0” in the subsequent integrating unit 218 based on the magnitude of the periodic variation signal. The details of the operation in the determiner 251 are as described with reference to FIG. 7, and thus description thereof is omitted here.

The output of each phase of the determiner 251 is input to the integrating unit 218. Integrating unit 218, 40 of the adder _{Σ 0, Σ 1, Σ 2} , ..., an adder 260 having a sigma _39, the addition circuit _{Σ 0, Σ 1, Σ 2} , ..., corresponding respectively to the sigma ₃₉ And an integrated value storage unit 261 having 40 storage areas mem_i0, mem_i1, mem_i2, ..., mem_i39. Integrating unit 218, determination unit and output of each phase supplied from the 251, respectively summing circuit _{Σ 0, Σ 1, Σ 2} , ..., integrated with sigma _39, each integrated value storage area mem_i0, mem_i1, mem_i2, ..., mem_i39 is stored. For example, the addition circuit Σ ₀ adds the input value and the value stored in the storage area mem_i0, and overwrites the storage result mem_i0.

  The selector / phase adjustment unit 252A selects values stored in the storage areas mem_i0, mem_i1, mem_i2,..., Mem_i39 of the integrated value storage unit 261 so as to match the phases with the encoder pulse as a reference. The output of the selector / phase adjustment unit 252A is an integrated value of a periodic component whose phase is slightly advanced from one cycle delay in order to match the phases. For example, the selector / phase adjustment 252A reads the integrated value from the storage area mem_i0, mem_i1, mem_i2,..., Mem_i39 with the storage area mem_i2 as the head of the cycle, and thereafter the storage areas mem_i3, mem_i4, mem_i5,. The integrated value is read sequentially, and further the integrated value is read sequentially from the storage areas mem_i0 and mem_i1.

The output of each phase of the selector / phase adjustment unit 252A is supplied to the multiplication unit 213A, and is multiplied by the proportional gain Gi _FF set as described using the equations (2) and (3). 215 is input.

On the other hand, the phase fluctuation value of each phase stored in the speed storage unit 211 is matched with the selector pulse / phase adjustment unit 252B using the encoder pulse as a reference in the same manner as the selector / phase adjustment unit 252A described above. As described above, the data is read from each storage area mem_p0, mem_p1, mem_p2, ..., mem_p39. The phase amount adjusted by the selector / phase adjuster 252B is the same as that of the selector / phase adjuster 252A. The output of each phase of the selector / phase adjustment unit 252B is supplied to the multiplication unit 213B, and multiplied by the proportional gain Gp _FF set as described using the equations (2) and (3). 215 is input.

  The adder 215 adds the output of each phase of the multiplication unit 213A and the output of each phase of the multiplication unit 213B for each corresponding phase and outputs the result. The addition result of the adder 215 is added to the output of the compensator 203 by the adder 204. Here, the correction output of the period variation is updated independently of the output update timing of the compensator 203. That is, the correction output is feedforward.

  Storage areas mem_i0, mem_i1, mem_i2, ..., mem_i39 and storage areas mem_p0, mem_p1, mem_p2, ..., mem_p39, which store data for 40 encoder pulses, have a ring buffer configuration, and are overwritten in order from the old values. do it. If the ring buffer has a storage area for one cycle, the memory address value stored 36 pulses before is read, that is, the phase is delayed, and the memory address value stored after 4 pulses is read, that is, the phase is advanced. Is equivalent.

  FIG. 10 shows an example using a ring buffer having 40 storage areas each storing data for one pulse. For example, when reading data delayed in phase by 36 pulses at the timing of writing the data DAT # 37 to the address ADD # 37, an address that is 36 addresses before or 4 addresses after the address ADD # 37 Data DAT # 01 of ADD # 01 is used.

  The correction operation according to the third embodiment will be schematically described with reference to FIG. Note that the correction operation described here is applied not only to the third embodiment but also to each embodiment. Due to the transfer characteristics of the controlled object, the detected cyclic fluctuation component before correction causes a phase delay with respect to the input. Therefore, in consideration of the phase delay, a correction value with the phase advanced in advance is prepared. The correction value is a value that also takes into account the gain of the frequency corresponding to the periodic component of the transfer characteristic to be controlled. By adding this correction value in the input unit 204 of the control target input, it is possible to cancel the periodic fluctuation component and reduce the periodic fluctuation component detected from the output of the control target.

  In each embodiment, the adding unit 204 inverts the sign of the correction value and adds it to the output of the compensator 203.

  Since the phase cannot be advanced in the actual machine, the phase is advanced with respect to the stored periodic fluctuation component delayed by one cycle. FIG. 11 shows that a correction value 311 having a delayed phase is generated with respect to the detected cyclic fluctuation component 310 before correction, and the result is added by the adding unit 204 to become a corrected cyclic fluctuation component 312. ing. As can be seen from the example of FIG. 11, the phase is advanced with respect to the periodic component delayed by one period, and therefore the amount of delaying the phase is smaller than one period (360 deg).

The correction operation according to the third embodiment will be described in more detail with reference to the configuration of FIG. The phase amount adjusted by the selector / phase adjustment units 252A and 252B is the phase delay from the input voltage corresponding to the extracted periodic component (frequency) to the detection speed when the drive system to be controlled is a voltage drive system. It is a value that takes into account. For example, consider a case where the phase of the desired frequency f ₁ is determined as −40 deg based on the transfer characteristics represented by a Bode diagram or the like. In this case, the periodic fluctuation correction value is advanced by 40 degrees in advance by the selectors / phase adjustment units 252A and 252B, and then added to the output of the compensator 203, whereby the rotational speed periodic fluctuation can be suppressed. Here, in consideration of correcting the cycle fluctuation after one cycle, it can be realized by delaying the phase by 360 deg−40 deg = 320 deg.

Assuming that the extracted period fluctuation is 40 encoder pulses, it can be realized by delaying the encoder pulse by 36 pulses according to the following equation (4).

  This phase compensation will be described in more detail using the Bode diagram of FIG. In FIG. 12, FIG. 12A shows a gain diagram, and FIG. 12B shows a phase diagram corresponding to the gain diagram.

An ideal frequency response from the motor input voltage to be controlled to the detection speed is determined by the induced voltage constant K _e , the mechanical time constant T _m , and the electrical time constant T _e according to the above-described equation (2). If wrote asymptote to the Bode diagram, first break point α is 1 / T _{m, 2} nd break point β becomes 1 / T _e. FIG. 12 shows the response when the induced voltage constant K _e is ignored (K _e = 1) because it is a DC change for simplification.

  For example, when the frequency response from the motor input voltage to be controlled to the detection speed has the characteristics as shown in FIG. 12, if a motor input voltage having a sinusoidal variation of 40 Hz is given, it is exemplified in FIG. As described above, it is detected as a sinusoidal velocity whose phase is delayed by 40 degrees.

  Consider a case in which a fluctuation period component of 40 Hz generated by the eccentricity of a rotating system (motor rotor, shaft, gear, drive shaft, etc.) is applied to a controlled object having such characteristics and detected as a speed. In this case, in order to suppress the 40 Hz fluctuation period component, the motor may be driven so as to cancel out the extracted 40 Hz fluctuation period component.

  Here, if the waveform of 40 Hz detected as the fluctuation period component is simply adjusted with a proportional gain and added to the output of the compensator 203 by the adding unit 204, the fluctuation period component of 40 Hz generated in the rotating system. Therefore, there is a possibility that the effect of suppressing the fluctuation period component cannot be sufficiently obtained. Since the correction waveform is inverted and added to the fluctuation period component, the correction waveform is actually a subtraction process. The sign of the correction waveform when added to the fluctuation period component differs depending on whether the period fluctuation is extracted from the speed or the period fluctuation is extracted from the speed deviation.

FIG. 13 schematically shows an example of phase compensation when the effect of suppressing the fluctuation period component cannot be sufficiently obtained. In FIG. 13, an example of a waveform detected as a fluctuation period component is shown as a sine wave 300. This sine wave 300 is assumed to be y = sin (ωt). A waveform 301 shows a first correction example in which a sine wave shifted by phase θ ₁ = −30 deg = −0.52 rad with respect to the sine wave 300 is inverted and added. A waveform 302 represents a second correction example in which a sine wave shifted by a phase θ ₂ = −180 deg = −3.14 rad with respect to the sine wave 300 is inverted and added. As can be seen from FIG. 13, even if correction is performed with the waveform 301 whose phase is delayed by 30 degrees, the effect is that only the amplitude of the sine wave 300 can be reduced by about 30%. Furthermore, if the phase is corrected with a waveform delayed by 180 degrees, the amplitude is amplified instead, resulting in destabilization of the control system.

(Modification of the third embodiment)
Next, a modification of the third embodiment will be described. The periodic component extraction unit 200 </ b> C according to the third embodiment described with reference to FIG. 9 performs arithmetic processing for each encoder pulse. That is, for example, when the periodic component extraction unit 200C operates according to the control of the CPU (not shown), or when the entire periodic component extraction unit 200C is configured by a program that operates on the CPU, the CPU receives an interrupt due to an encoder pulse. In addition, predetermined arithmetic processing is executed.

  FIG. 14 is a diagram illustrating an example of a function of the periodic component extraction unit 200C ′ according to a modification of the third embodiment. In FIG. 14, the same reference numerals are given to the portions common to FIG. 9 described above, and detailed description thereof is omitted.

  In the modification of the third embodiment, each part of the periodic component extraction unit 200C ′ is divided into a part that performs processing by interrupting an encoder pulse and a part that performs processing by interrupting a timer, according to the contents of the processing. Mainly, data acquisition and output are performed in the part where the interrupt is performed by the encoder pulse, and filter operation is performed on the acquired data in the part where the timer interrupt is performed.

  More specifically, as shown in FIG. 14, the periodic component extraction unit 200C ′ includes ENC interrupt function units 270 and 272 that perform arithmetic processing by an interrupt of an encoder pulse (ENC pulse), and a timer based on a reference clock. The configuration is divided into a timer interrupt function unit 271 that performs arithmetic processing by interruption. As the reference clock, for example, a system clock serving as a reference for the operation of the CPU can be used.

The input-side ENC interrupt function unit 270 includes a distributor 250 ′. Timer interrupt function unit 271 includes 'a determination unit 251' filter operation unit 210 and, 40 of the adder _{Σ 0, Σ 1, Σ 2} , ..., and an adding portion 260 comprises a sigma _39. Further, the ENC interrupt function unit 272 on the output side includes selectors / phase adjustment units 252A and 252B, multipliers 213A and 213B, an adder 215, and an adder 264 including an adder 204.

  40 storage areas mem_i0, mem_i1, mem_i2,..., Mem_i39 of the integrated value storage section 261 for storing the addition result of the addition section 260, and 40 storage areas mem_p0, mem_p1, mem_p2,. mem_p39 is provided across the timer interrupt function unit 271 and the ENC interrupt function unit 272, respectively. In addition, 40 storage areas mem_v0, mem_v1, mem_v2,..., Mem_v39 in the buffer 263 for absorbing the difference in processing speed between the distributor 250 ′ and the filter operation unit 210 ′ are provided with the ENC interrupt function unit 270 and the timer interrupt. It is provided across the function part 271.

  As described above, the periodic component extraction unit 200C ′ according to the modification of the third embodiment is partially different in processing order from the periodic component extraction unit 200C according to the third embodiment described above. That is, in the periodic component extraction unit 200C ', the input rotation speed is distributed to each phase for each encoder pulse by the distributor 250', and then the filter operation is performed by the filter operation unit 210 '.

  In FIG. 14, the rotational speed data indicating the rotational speed of the drive shaft on the deceleration side output for each encoder pulse of the drive shaft encoder sensor 59 from the speed calculation unit 208 is supplied to the ENC interrupt function unit 270 and supplied to the distributor 250 ′. Entered. The distributor 250 'distributes the rotation speed data to each phase corresponding to each of the 40 encoder pulses in accordance with the encoder pulse (ENC pulse). The distributor 250 'stores the rotational speed data distributed to each phase in each storage area mem_v0, mem_v1, mem_v2, ..., mem_v39 of the buffer 263 at the timing of the encoder pulse.

  Respective rotation speed data stored in each storage area mem_v0, mem_v1, mem_v2,..., Mem_v39 are sequentially read out by a timer interrupt based on the system clock and supplied to the filter operation unit 210 'of the timer interrupt function unit 271. In accordance with the timer interrupt, the filter operation unit 210 ′ performs digital filter operation with a bandpass filter on the supplied rotation speed data to extract a predetermined frequency component, and the period variation of each phase based on the extracted frequency component Output the value.

  The period fluctuation values of the respective phases output from the filter calculation unit 210 ′ are input to the determiner 251 ′, and sequentially to the 40 storage areas mem_p0, mem_p1, mem_p2,... Mem_p39 of the speed storage unit 211. Remembered. Further, the filter calculation unit 210 ′ obtains the magnitude of the period variation based on the extracted frequency component, and supplies the obtained value to the determiner 251 ′ as a determination reference value for determination by the determiner 251 ′.

  The determiner 251 ′ determines whether or not to integrate the supplied periodic variation values of the respective phases based on the determination reference value supplied from the filter calculation unit 210 ′ in the same manner as the determiner 251 described above. . More specifically, based on the magnitude of the periodic fluctuation signal, the determiner 251 ′ uses the extracted periodic fluctuation value in the integrating section including the adding section 260 and the integrated value storage section 261, or uses the value “ It is determined whether to use “0”.

The output of each phase of the determiner 251 ′ is input to the integrating unit. Integrating unit determinator the output of each phase supplied from the 251 ', respectively summing circuit _{Σ 0, Σ 1, Σ 2} , ..., integrated with sigma _39, each integrated value storage area mem_i0, mem_i1, mem_i2, ..., mem_i39 is stored. Each accumulated value stored in the storage areas mem_i0, mem_i1, mem_i2,..., Mem_i39 is used to suppress period fluctuations after the next period.

  The rotation speed data stored in each storage area mem_p0, mem_p1, mem_p2,..., Mem_p39 of the speed storage unit 211 is subjected to filter calculation processing by the filter calculation unit 210 ′, and then is overwritten to store the rotation speed data. It can be used in common with each storage area mem_v0, mem_v1, mem_v2, ..., mem_v39.

  In the ENC interrupt function unit 272, the selector / phase adjustment unit 252A stores the values stored in the storage areas mem_i0, mem_i1, mem_i2,. Is selected. The output of the selector / phase adjustment unit 252A is an integrated value of a periodic component whose phase is slightly advanced from one cycle delay in order to match the phases. As an example, the selector / phase adjustment 252A reads the integrated value from the storage area mem_i0, mem_i1, mem_i2,..., Mem_i39 with the storage area mem_i2 as the head of the cycle. And sequentially read the integrated value, and further read the integrated value sequentially from the storage areas mem_i0 and mem_i1. The integrated value is read from each storage area mem_i0, mem_i1, mem_i2,..., Mem_i39 according to the encoder pulse.

The output of each phase of the selector / phase adjustment unit 252A is supplied to the multiplication unit 213A, and is multiplied by the proportional gain Gi _FF set as described using the equations (2) and (3). 215 is input.

On the other hand, in the ENC interrupt function unit 271, the periodic fluctuation value of each phase stored in the speed storage unit 211 is converted into an encoder pulse by the selector / phase adjuster 252B in the same manner as the selector / phase adjuster 252A. Are read from each storage area mem_p0, mem_p1, mem_p2,..., Mem_p39 so as to match the phases. The phase amount adjusted by the selector / phase adjuster 252B is the same as that of the selector / phase adjuster 252A. The output of each phase of the selector / phase adjustment unit 252B is supplied to the multiplication unit 213B, and multiplied by the proportional gain Gp _FF set as described using the equations (2) and (3). 215 is input.

  The adder 215 adds the output of each phase of the multiplication unit 213A and the output of each phase of the multiplication unit 213B for each corresponding phase and outputs the result. The addition result of the adder 215 is added to the output of the compensator 203 by the adder 204. Here, the correction output of the period variation is updated independently of the output update timing of the compensator 203. That is, the correction output is feedforward.

  In this way, the load of the ENC interrupt process can be reduced by dividing the process into the operation for performing the ENC interrupt process and the operation for performing the timer interrupt process in the periodic component extraction unit 200C ′. Thereby, even if it is a structure which uses a some encoder, the delay of data acquisition can be made small.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 15 shows an exemplary configuration of a periodic component extraction unit 200D according to the fourth embodiment. In FIG. 15, parts common to those in FIG. 6 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 15, the periodic component extraction unit 200D according to the fourth embodiment limits the band just before the filter calculation unit 210 with respect to the periodic component extraction unit 200C according to the third embodiment shown in FIG. A calculation unit 219 is added. That is, the rotation speed output from the speed calculation unit 208 is input to the filter calculation unit 210 after being subjected to band limitation processing by the band limitation calculation unit 219.

  In the first to third embodiments described above, the calculation in the periodic component extraction units 200A, 200B, and 200C is performed for each encoder pulse, so that a large calculation load is generated when the resolution of the encoder is high. On the other hand, even when a high-resolution encoder is used, if the frequency of the periodic component to be corrected is low, the high-resolution of the encoder is unnecessary, and therefore it is conceivable that the detection data detected by the encoder is thinned out. Also, when the sampling frequency is the same in the compensator 203 and the periodic component correction feedforward process, if the encoder frequency is higher than the sampling period of the compensator 203, it is necessary to thin out the output data of the feedforward process. .

  Here, if values are simply thinned out, periodic fluctuations called aliasing occur, and for example, a periodic shift occurs in each color toner image formed on the intermediate transfer belt 14 driven by the drive control unit 100. And the toner image on the intermediate transfer belt 14 may cause moire fringes in the image formed on the paper.

  Therefore, in the fourth embodiment, the band limitation calculation unit 219 provided at the input of the periodic component extraction unit 200D performs low-pass filter processing on the rotation speed detected for each encoder pulse to limit the band. The low-pass filter calculation performed by the band limitation calculation unit 219 may be performed using either an IIR (Infinite Impulse Response) filter or an FIR (Finite Impulse Response) filter. Further, the low-pass filter calculation in the band limit calculation unit 219 needs to be executed with the period of the encoder pulse as the sampling period. For example, when the number of pulses is decimated to 1/2, as a simple method, a moving average filter process (a kind of FIR filter process) for averaging using data for two samples may be performed.

  In this case, in the periodic component extraction unit 200D, the calculation after the filter calculation unit 210 is performed on the averaged data with the decimated encoder sampling period in the same manner as the periodic component extraction units 200A, 200B, and 200C described above. To do.

  On the other hand, when the calculation cycle of the periodic component extraction unit 200 </ b> D is longer than the sampling cycle of the compensator 203, the adder 204 adds the periodic component correction feedforward value for each sampling cycle of the compensator 203.

  In addition, the structure which performs a periodic component extraction process after performing the low pass filter process in the zone | band limitation calculating part 219 with respect to the rotational speed data output from the speed calculating part 208 by this 4th Embodiment is mentioned above. It can also be applied to the periodic component extraction units 200A and 200B according to the second embodiment.

(Matters common to each embodiment)
In each of the above-described embodiments, as illustrated in FIG. 3, the detection speed is input to the periodic component extraction unit 200 and the correction value of the periodic variation is calculated, but this is not limited to this example. That is, the correction value of the period variation may be calculated from the speed deviation that is the difference between the target value and the detected speed. Note that in this case, the sign of the adder for correction is different.

  On the other hand, when the periodic component extraction process according to each embodiment is used for a minor loop of a control system having a double feedback loop, the detected speed is set to the periodic component extraction unit rather than the method of inputting the speed deviation to the periodic component extraction unit 200. The method of inputting to 200 is more preferable.

  The reason for this will be described with reference to FIG. Consider the two types of configurations of FIG. 16 (a) and FIG. 16 (b). In FIG. 16A and FIG. 16B, the circuit 401, the circuit 403, and the circuit 404 perform the operation C, the operation P, and the operation G on the input, respectively. The comparator 400 outputs a difference e between the input signal r and signal y. Adders 402 and 405 add the outputs of circuit 401 and circuit 404 and output signal u. Note that the adder 405 inverts the output of the circuit 404 and adds it to the output of the circuit 401.

First, in FIG. 16A, the signal u output from the adder 402 can be expressed as the following equation (5).
u = (ry) * (C + G) = (ry) * C + (ry) * G (5)

On the other hand, in FIG. 16B, the signal u can be expressed as the following equation (6).
u = (r−y) × C−y × G (6)

  Here, a compensator that performs feedback compensation (the drive shaft speed compensator 113 in the example of FIG. 3) is considered as a circuit 401 (calculation C), and the periodic component extraction unit 200 is considered as a circuit 404 (calculation G). In this case, in the example of FIG. 16A, the calculation G includes the signal y (corresponding to the detection speed) and the signal r (corresponding to the target value). On the other hand, in the example of FIG. 16B, only the signal y is included in the calculation of the calculation G, and the signal r is not included.

  In the case of a double loop, the target speed (signal r) changes depending on the outer major loop. For this reason, in the configuration of FIG. 16A, the fluctuation of the target speed is also detected as a period fluctuation. Since the purpose of the control is periodic fluctuation of the motor or the like, the configuration of FIG. 16B that does not include fluctuation of the target value is preferable. Therefore, the configuration in which the detection speed is input to the periodic component extraction unit 200 can perform control with higher accuracy.

  In each of the above-described embodiments, after the timing at which the integrated values of the speed integration units 212 and 216 converge to a predetermined value or after a predetermined time has elapsed, the input of values to the periodic component extraction unit is stopped, and the drive shaft The values stored in the speed storage unit 211 and the speed integration units 212 and 216 may be selected by the encoder pulse output from the encoder sensor 59 to correct the period variation. Thereby, it is possible to reduce a calculation load such as filter calculation for each interruption by encoder pulse, selection, storage, and addition of data.

  In the above description, when a plurality of frequency components are extracted, a plurality of filter arithmetic units 210 are used in parallel. However, this is not limited to this example. For example, there is a case where it is desired to change the periodic fluctuation suppression performance for each extracted frequency. In this case, a plurality of periodic component extraction units are used, and the multiplication unit 213 (in the case of the first embodiment) and the multiplication units 213A and 213B (second to fourth embodiments) so as to obtain the required suppression performance. Adjust the gain in the case of.

  In addition, for example, when it is desired to suppress periodic fluctuations due to two periodic components having different frequencies, the phase correction amounts are greatly different, and therefore it is preferable to prepare separate periodic component extraction units.

(Other embodiments)
The periodic component extraction unit 200 (periodic component extraction units 200 </ b> A to 200 </ b> D) according to each embodiment described above can be realized using hardware such as a logic circuit or an FPGA (Field-Programmable Gate Array). However, the present invention is not limited to this, and the periodic component extraction unit can be realized as software by a program operating on the CPU.

  FIG. 17 shows an exemplary configuration when the periodic component extraction unit 200 is realized by software. Here, a description will be given assuming that the motor to be controlled by the drive control unit 100 including the periodic component extraction unit 200 is a DC brushless motor. In addition, the configuration shown in FIG. 17 shows, for example, a portion that is deeply related to each embodiment in the overall configuration for controlling the image forming apparatus 10 in FIG.

  A CPU 610, a ROM (Read Only Memory) 611, a RAM (Random Access Memory) 612, a period counter 613, a PIO (Programmed I / O) 614, and a PWM generator 615 are connected to the bus 600 so as to communicate with each other. The CPU 610 controls the entire configuration shown in FIG. 17 using the RAM 612 as a work memory according to a program stored in advance in the ROM 611.

  For example, a program for realizing the periodic component extraction unit 200 according to each embodiment is provided by being stored in the ROM 611 in advance. Not limited to this, the program is a file in an installable or executable format and can be read by a computer such as a CD (Compact Disk), FD (Flexible Disk), DVD (Digital Versatile Disk), or flash memory. You may comprise so that it may record and provide on a medium.

  Furthermore, the program for realizing the periodic component extraction unit 200 according to each embodiment may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. The program may be provided or distributed via a network such as the Internet.

  The program for realizing the periodic component extraction unit 200 according to each embodiment includes the above-described units (in the case of the third embodiment, the filter calculation unit 210, the speed storage unit 211, the speed integration unit 216, the multipliers 213A and 213B, The module configuration includes an adder 215 and a phase adjustment unit 214). As actual hardware, the CPU 610 reads the program from the ROM 611 and executes the program, and these units are loaded onto the RAM 612. A filter calculation unit 210, a speed storage unit 211, a speed integration unit 216, multipliers 213A and 213B, an adder 215, and a phase adjustment unit 214 are generated on the RAM 612. In addition, each storage area mem_p0, mem_p1, mem_p2,..., Mem_p39 of the speed storage unit 211 and each storage area mem_i0, mem_i1, mem_i2,. can do.

  In the configuration of FIG. 17, the cycle counter 613 measures the pulse interval of encoder pulses supplied from a rotary encoder 618 provided on the output side of the speed reduction mechanism that decelerates the rotation of the motor 617, using a basic clock (system clock). The encoder pulse cycle is obtained, the reciprocal of the cycle is calculated, and the rotation speed on the output side of the speed reduction mechanism is calculated. Information indicating the calculated rotation speed is supplied to the CPU 610.

  The PIO 614 is an interface between the CPU 610 and the motor driver 616. The CPU 610 instructs the motor driver 616 to turn on / off the motor driver 616, turn on / off the brake for the motor 617, and specify the rotation direction for the motor 617 via the PIO 614. The PWM generator 615 generates a PWM signal having a duty equivalent to the drive voltage for driving the motor 617 in accordance with a command from the CPU 610. The PWM signal generated by the PWM generator 615 is supplied to the motor driver 616.

  A motor 617 corresponds to the motor 52 and the motor 206 described above, and drives the intermediate transfer belt 14 via a speed reduction mechanism. Motor driver 616 drives three-phase currents U, V, and W according to the logic of Hall signals HU, HV, and HW output from the Hall element attached to motor 617 to drive motor 617. The rotation of the motor 617 is transmitted to a speed reduction mechanism (not shown). A rotary encoder 618 attached to the output side of the speed reduction mechanism detects the movement of the speed reduction mechanism and outputs an encoder pulse.

  In such a configuration, the CPU 610 compares the preset target speed with the detected speed calculated by the period counter 613 based on the output of the rotary encoder 618, and compensates for the rotational speed of the motor 617. And the duty of the PWM signal corresponding to the result is set in the PWM generator 615.

  Further, in each embodiment, in addition to the processing described above, the encoder pulse is measured by the period counter 613, and at the same time, an interrupt to the CPU 610 is generated at the edge of the encoder pulse. The CPU 610 performs the operation and calculation of the periodic component extraction unit 200 according to each embodiment described above according to the interrupt according to the program for realizing the periodic component extraction unit 200 described above.

DESCRIPTION OF SYMBOLS 10 Image forming apparatus 14 Intermediate transfer belt 23 Intermediate transfer scale detection sensor 50 Motor and deceleration mechanism 52, 206, 617 Motor 59, 59a, 59b Drive shaft encoder sensor 110, 112, 202 Comparator 111 Belt speed compensator 113 Drive shaft speed Compensator 114, 204, 215 Adder 115, 616 Motor driver 116 Drive shaft speed calculator 117 Belt speed calculator 200, 200A, 200B, 200C, 200C ', 200D Periodic component extractor 203 Compensator 205 Driver 207 Deceleration mechanism 208 Speed calculation unit 210, 210 'Filter calculation unit 211 Speed storage unit 212, 216 Speed integration unit 213, 213A, 213B Multiplication unit 214 Phase adjustment unit 217 Switch unit 218 Integration unit 250, 250' Distributor 251, 251 'Determinator 252 A, 252B selector / phase adjuster 610 CPU
611 ROM
612 RAM
613 Period counter 614 PIO
615 PWM generator 618 rotary encoder

Japanese Examined Patent Publication No. 62-6241

Claims (11)

A filter calculation unit that performs a filter calculation for each pulse with respect to a detection speed obtained from a pulse output by the position detection unit according to a rotation position of a speed reducer that decelerates rotation of the motor;
A storage unit for storing the detection speed for each pulse filtered by the filter calculation unit for a number of pulses corresponding to a predetermined cycle shorter than a cycle of one rotation of the speed reducer;
A first multiplier that multiplies a predetermined first constant by the detection speed for each pulse stored in the storage;
A phase adjustment unit that gives a predetermined delay to the multiplication output of the first multiplication unit;
A drive control apparatus comprising: a first addition unit that adds the multiplication output delayed by the phase adjustment unit to an output of a compensator that compensates for a rotation speed of the motor. An accumulating unit that accumulates the detection speed for each pulse stored in the storage unit for each corresponding phase in the predetermined period ;
The phase adjusting unit is
Giving the delay to the integrated value obtained by integrating the detection speed by the integrating unit;
The first adding unit includes:
The drive control apparatus according to claim 1, wherein the integrated value given the delay by the phase adjustment unit is added to an output of the compensator. A second multiplication unit that multiplies the detection speed accumulated by the accumulation unit by a second constant;
A second addition unit that adds the multiplication output of the first multiplication unit and the multiplication output of the second multiplication unit;
The phase adjusting unit is
Giving the delay to the addition output of the second addition unit;
The first adding unit includes:
The drive control apparatus according to claim 2, wherein an addition output of the second addition unit given the delay by the phase adjustment unit is added to an output of the compensator. The integrating unit is
When the detection speed calculated by the filter calculation unit is outside a predetermined range, the detection speed calculated by the filter is integrated, and when the detection speed calculated by the filter is within the range, 4. The drive control apparatus according to claim 2, wherein the detection speed calculated by the filter is not integrated. The integrating unit is
5. The drive control device according to claim 2, wherein when the integrated value obtained by integrating the detected speeds exceeds a limit value, the integrated value is fixed to the limit value. The filter operation unit performs the filter operation to perform a Pand pass filter process,
6. The drive control device according to claim 1, further comprising a low-pass filter arithmetic unit that performs a low-pass filter process on the detection speed input to the filter arithmetic unit. 6. The operation of the filter operation unit and the writing process in the storage unit are performed using a reference clock,
7. The read process in the storage unit and the operations of the first multiplication unit and the addition unit are performed using the pulse as a clock. 8. Drive control device. The pulse output from the position detection unit is an integral multiple of a reduction ratio by the decelerator and has a resolution that is an integral multiple of the number of pulses corresponding to the predetermined period. The drive control apparatus according to any one of claims 1 to 7. A filter calculation step for performing a filter calculation for each pulse with respect to a detection speed obtained from a pulse output by the position detection unit according to a rotation position of a decelerator that decelerates rotation of the motor;
A storage step of storing the detection speed for each pulse subjected to the filter calculation in the filter calculation step by the number of pulses corresponding to a predetermined cycle shorter than the cycle of one rotation of the speed reducer;
A multiplication step of multiplying a detection rate for each pulse stored in the storage step by a predetermined constant;
A phase adjustment step for giving a predetermined delay to the multiplication output of the multiplication step;
A drive control method comprising: an addition step of adding the multiplication output delayed in the phase adjustment step to an output of a compensator that compensates for the rotation speed of the motor. A filter calculation step for performing a filter calculation for each pulse with respect to a detection speed obtained from a pulse output by the position detection unit according to a rotation position of a decelerator that decelerates rotation of the motor;
A storage step of storing the detection speed for each pulse subjected to the filter calculation in the filter calculation step by the number of pulses corresponding to a predetermined cycle shorter than the cycle of one rotation of the speed reducer;
A multiplication step of multiplying a detection rate for each pulse stored in the storage step by a predetermined constant;
A phase adjustment step for giving a predetermined delay to the multiplication output of the multiplication step;
A program for causing a computer to execute an addition step of adding the multiplication output delayed in the phase adjustment step to the output of a compensator that compensates for the rotation speed of the motor. The drive control device according to any one of claims 1 to 8,
A motor driven according to the control of the drive control device;
An image forming apparatus comprising: an image forming unit that forms an image on an image forming medium driven by the motor.

Images