[go: up one dir, main page]

JP6012533B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

Info

Publication number
JP6012533B2
JP6012533B2 JP2013079786A JP2013079786A JP6012533B2 JP 6012533 B2 JP6012533 B2 JP 6012533B2 JP 2013079786 A JP2013079786 A JP 2013079786A JP 2013079786 A JP2013079786 A JP 2013079786A JP 6012533 B2 JP6012533 B2 JP 6012533B2
Authority
JP
Japan
Prior art keywords
power semiconductor
substrate
inter
semiconductor device
bending
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013079786A
Other languages
Japanese (ja)
Other versions
JP2014204006A (en
Inventor
進吾 須藤
進吾 須藤
晋助 浅田
晋助 浅田
隆男 荒木
隆男 荒木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2013079786A priority Critical patent/JP6012533B2/en
Publication of JP2014204006A publication Critical patent/JP2014204006A/en
Application granted granted Critical
Publication of JP6012533B2 publication Critical patent/JP6012533B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L2224/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、電力用半導体素子を有する電力用半導体装置に関する。   The present invention relates to a power semiconductor device having a power semiconductor element.

一般的に電力用半導体装置は、放熱性に優れた絶縁基板上に電力用半導体素子を実装し、この電力用半導体素子に例えばアルミワイヤなどで配線を行うことで回路を構成する。この回路には、絶縁基板を支持する樹脂筐体に設けた外部端子が電気的に接続されている。
このような構造では、絶縁基板上で配線が行われ、さらに樹脂筐体の外部端子にも配線が行われるため、高価である絶縁基板の面積が大きくなりコストアップすると共に、電力用半導体装置の外形も大きくなるという課題がある。よって、電力用半導体装置の小型化が検討されてきた。 In general, in a power semiconductor device, a circuit is configured by mounting a power semiconductor element on an insulating substrate excellent in heat dissipation and wiring the power semiconductor element with, for example, an aluminum wire. The circuit is electrically connected to external terminals provided on a resin casing that supports the insulating substrate.
In such a structure, wiring is performed on the insulating substrate, and further, wiring is performed also on the external terminal of the resin casing. This increases the area of the expensive insulating substrate and increases the cost. There is a problem that the outer shape becomes larger. Therefore, downsizing of power semiconductor devices has been studied.

装置小型化の手法として、例えば、絶縁基板上の配線パターンに外部端子を実装し、この外部端子の先端面を露出させるように樹脂封止することで、外部端子を絶縁基板面積内から取り出す構造が提案されている（特許文献１）。この特許文献１の図８から図１３では、チップ下部の導電パターンに設けた可撓性配線構造（図１０）、及び、向きを変えた応力緩和構造（図９ｂ）が示されている。
また、アルミワイヤの配線面積を削減する構造として、特許文献２には、半導体素子に固着され、かつプリント基板に固着されたインプラントピンを用い、このインプラントピンと電気的に接続された外部端子を樹脂ケース外部へ取り出す構造が提案されている。 As a method for downsizing the device, for example, a structure in which an external terminal is mounted on a wiring pattern on an insulating substrate, and the external terminal is taken out from the area of the insulating substrate by resin sealing so as to expose the end surface of the external terminal. Has been proposed (Patent Document 1). 8 to 13 of Patent Document 1 show a flexible wiring structure (FIG. 10) provided in a conductive pattern under the chip and a stress relaxation structure (FIG. 9 b) whose direction is changed.
Further, as a structure for reducing the wiring area of an aluminum wire, Patent Document 2 uses an implant pin fixed to a semiconductor element and fixed to a printed circuit board, and external terminals electrically connected to the implant pin are made of resin. A structure for taking it out of the case has been proposed.

特開２００１−２８４５２４号公報JP 2001-284524 A 特開２０１１−１４２１２４号公報JP 2011-142124 A

しかしながら、特に多数の半導体素子が搭載される３相インバータ回路などの複雑な回路構成の装置の場合、上述の各特許文献に開示される構造では、絶縁基板上へはんだ付けしたときに生じた半導体素子の傾きあるいは絶縁基板の反りに起因して、外部端子の高さにバラツキが発生する。このようなバラツキを吸収するために、はんだなどの接合材を通常よりも多めに供給するあるいはピンの高さを調整する等の手当が必要となる。よって、電力用半導体装置の生産性向上に対して問題があった。
また、プリント基板を用いた場合には、半導体素子が実装されてその動作中に高温になる絶縁基板と、比較的温度上昇が起こり難いプリント基板との熱変形差に起因した応力が端子接続部に作用することから、電力用半導体装置の高温環境での使用、及び、長期の動作信頼性の確保に対して問題があった。 However, particularly in the case of a device having a complicated circuit configuration such as a three-phase inverter circuit on which a large number of semiconductor elements are mounted, in the structure disclosed in each of the above-mentioned patent documents, a semiconductor generated when soldered onto an insulating substrate Due to the inclination of the element or the warping of the insulating substrate, the height of the external terminal varies. In order to absorb such a variation, it is necessary to supply a bonding material such as solder more than usual or to adjust the height of the pin. Therefore, there has been a problem in improving the productivity of power semiconductor devices.
Also, when a printed circuit board is used, the stress caused by the thermal deformation difference between the insulating substrate that is mounted with a semiconductor element and becomes hot during operation and the printed circuit board that is relatively difficult to rise in temperature is caused by the terminal connection portion. Therefore, there are problems in using the power semiconductor device in a high temperature environment and ensuring long-term operation reliability.

本発明は、このような問題点を解決するためになされたもので、従来に比べて生産性が高く、長期にわたる動作信頼性を確保可能な電力用半導体装置を提供することを目的とする。   The present invention has been made to solve such a problem, and an object of the present invention is to provide a power semiconductor device that is higher in productivity than conventional ones and can ensure long-term operation reliability.

上記目的を達成するため、本発明は以下のように構成する。
即ち、本発明の一態様における電力用半導体装置は、放熱板に絶縁層を介して形成した回路パターンに複数の電力用半導体素子を実装した第１基板と、表裏両面に配線回路を形成した第２基板と、上記放熱板を一側面に露出させて上記第１基板を保持し、かつ上記電力用半導体素子に対向して配置した上記第２基板を保持する樹脂筐体と、上記第２基板における上記配線回路に接続され上記樹脂筐体の外部へ導出される外部端子と、を備えた電力用半導体装置において、上記第１基板と上記第２基板との間に設けられる基板間接続端子と、上記樹脂筐体内に充填され、上記基板間接続端子を封止する絶縁性樹脂と、をさらに備え、上記基板間接続端子は、２つの上記電力用半導体素子における電極間を電気的に接続する素子間接続部と、この素子間接続部と一体に形成され上記素子間接続部に対して折れ曲がって延在して上記素子間接続部を上記第２基板における配線回路に電気的に接続する素子−回路接続部とを有し、この素子−回路接続部は、一方の電力用半導体素子の上方に位置し可撓性を有する屈伸部を有することを特徴とする。 In order to achieve the above object, the present invention is configured as follows.
That is, a power semiconductor device according to an aspect of the present invention includes a first substrate in which a plurality of power semiconductor elements are mounted on a circuit pattern formed on an insulating layer on a heat sink, and wiring circuits formed on both front and back surfaces. Two substrates, a resin casing for holding the first substrate by exposing the heat sink to one side surface, and holding the second substrate arranged to face the power semiconductor element, and the second substrate In the power semiconductor device comprising: an external terminal connected to the wiring circuit and led out to the outside of the resin casing; an inter-substrate connection terminal provided between the first substrate and the second substrate; And an insulating resin that fills the resin casing and seals the inter-substrate connection terminal, and the inter-substrate connection terminal electrically connects the electrodes of the two power semiconductor elements. Inter-element connection and this And an element-circuit connection portion that is formed integrally with the inter-element connection portion and is bent and extends with respect to the inter-element connection portion to electrically connect the inter-element connection portion to the wiring circuit on the second substrate. And this element-circuit connection part is located above one power semiconductor element, and has the bending part which has flexibility, It is characterized by the above-mentioned.

本発明の一態様における電力用半導体装置によれば、互いに対向する第１基板と第２基板との間に基板間接続端子が設けられ、この基板間接続端子は屈伸部を有する。よって、第１基板の反りあるいは電力用半導体素子の傾きが存在する場合でも、屈伸部がこれらの反り又は傾斜を吸収可能である。したがって、第１基板における回路パターン及び電力用半導体素子の少なくとも一方と、第２基板における配線回路とは、電気的に接続可能となる。その結果、電力用半導体装置の組み立てが容易になり、生産性を向上させることができる。さらに、第１基板と第２基板との間の熱変形差を基板間接続端子の屈伸部で吸収することができ、電力用半導体装置の長期にわたる電気接続の信頼性向上も達成することができる。   According to the power semiconductor device of one aspect of the present invention, the inter-substrate connection terminal is provided between the first substrate and the second substrate facing each other, and the inter-substrate connection terminal has a bending portion. Therefore, even when there is a warp of the first substrate or an inclination of the power semiconductor element, the bending / extending portion can absorb the warp or inclination. Therefore, at least one of the circuit pattern and the power semiconductor element on the first substrate and the wiring circuit on the second substrate can be electrically connected. As a result, assembly of the power semiconductor device is facilitated, and productivity can be improved. Furthermore, the thermal deformation difference between the first substrate and the second substrate can be absorbed by the bent portion of the inter-substrate connection terminal, and the reliability improvement of the electrical connection over a long period of the power semiconductor device can also be achieved. .

また、第１基板に電力用半導体素子が実装され、第１基板の回路パターンと第２基板の配線回路とが基板間接続端子によって電気的に接続され、配線回路から外部端子を樹脂筐体の外部へ導出したことから、第１基板の面積を縮小でき、電力用半導体装置の小型化を図ることができ、第１基板における配置に依存せずに端子取り出し位置の自由度を向上させることができる。また、第１基板における複数の電力用半導体素子を基板間接続端子における素子間接続部で接続したことで部品点数の削減を図ることができ、さらに、第２基板を固定する力を軽減することで組み立て工程を簡略化でき、さらに生産性を向上させることが可能となる。   In addition, the power semiconductor element is mounted on the first substrate, the circuit pattern on the first substrate and the wiring circuit on the second substrate are electrically connected by the inter-substrate connection terminal, and the external terminal is connected to the resin housing from the wiring circuit. Since it is derived to the outside, the area of the first substrate can be reduced, the power semiconductor device can be miniaturized, and the degree of freedom of the terminal extraction position can be improved without depending on the arrangement on the first substrate. it can. In addition, the number of components can be reduced by connecting a plurality of power semiconductor elements on the first substrate at the inter-element connection portions at the inter-substrate connection terminals, and further, the force for fixing the second substrate can be reduced. As a result, the assembly process can be simplified and the productivity can be further improved.

またこれにより、電力用半導体装置の長寿命化及び歩留まりの向上を図ることも可能となる。   This also makes it possible to extend the life of the power semiconductor device and improve the yield.

本発明の実施の形態１における電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power in Embodiment 1 of this invention. 図１に示す絶縁基板に形成した回路パターンを示す平面図である。It is a top view which shows the circuit pattern formed in the insulating substrate shown in FIG. 図１に示すプリント基板に形成した配線回路のパターンを示す平面図である。It is a top view which shows the pattern of the wiring circuit formed in the printed circuit board shown in FIG. 図１に示す基板間接続端子の正面図である。FIG. 2 is a front view of the inter-substrate connection terminal shown in FIG. 1. 図１に示す基板間接続端子の変形例における正面図である。It is a front view in the modification of the connection terminal between board | substrates shown in FIG. 本発明の実施の形態２における電力用半導体装置に備わる基板間接続端子を示し、（ａ）はその正面図であり（ｂ）は側面図である。The board | substrate connection terminal with which the power semiconductor device in Embodiment 2 of this invention is equipped is shown, (a) is the front view, (b) is a side view. 本発明の実施の形態３における電力用半導体装置に備わる基板間接続端子を示し、（ａ）はその正面図であり（ｂ）は側面図である。The board | substrate connection terminal with which the power semiconductor device in Embodiment 3 of this invention is equipped is shown, (a) is the front view, (b) is a side view. 図７に示す基板間接続端子の変形例を示し、（ａ）はその正面図であり（ｂ）は側面図である。The modification of the board | substrate connection terminal shown in FIG. 7 is shown, (a) is the front view, (b) is a side view. 図７に示す基板間接続端子の別の変形例を示し、（ａ）はその正面図であり（ｂ）は側面図である。7 shows another modification of the inter-substrate connection terminal shown in FIG. 7, (a) is a front view thereof, and (b) is a side view thereof. 本発明の実施の形態４における電力用半導体装置に備わる基板間接続端子を示し、（ａ）はその正面図であり（ｂ）は側面図である。The board | substrate connection terminal with which the power semiconductor device in Embodiment 4 of this invention is equipped is shown, (a) is the front view, (b) is a side view. 図１０に示す基板間接続端子の展開図である。FIG. 11 is a development view of the inter-substrate connection terminal shown in FIG. 10.

本発明の実施形態である電力用半導体装置について、図を参照しながら以下に説明する。尚、各図において、同一又は同様の構成部分については同じ符号を付している。また、以下の説明が不必要に冗長になるのを避け当業者の理解を容易にするため、既によく知られた事項の詳細説明及び実質的に同一の構成に対する重複説明を省略する場合がある。また、以下の説明及び添付図面の内容は、特許請求の範囲に記載の主題を限定することを意図するものではない。   A power semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. In addition, in order to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art, a detailed description of already well-known matters and a duplicate description of substantially the same configuration may be omitted. . Further, the contents of the following description and the accompanying drawings are not intended to limit the subject matter described in the claims.

実施の形態１．
図１は、本発明の実施の形態１における電力用半導体装置１０１の断面図であり、また図２は、電力用半導体装置１０１の絶縁基板１に構成された回路の一例を示す平面図であり、図３は、プリント基板７に構成された配線回路７ａのパターンの一例を示す平面図である。尚、絶縁基板１は、第１基板の一例に相当し、プリント基板７は、第２基板の一例に相当する。第１基板及び第２基板は、実施形態のものに限定されるものではなく、要するに熱膨張率に差がある２種類の基板に相当する。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of power semiconductor device 101 according to the first embodiment of the present invention, and FIG. 2 is a plan view showing an example of a circuit configured on insulating substrate 1 of power semiconductor device 101. FIG. 3 is a plan view showing an example of the pattern of the wiring circuit 7 a formed on the printed circuit board 7. The insulating substrate 1 corresponds to an example of a first substrate, and the printed circuit board 7 corresponds to an example of a second substrate. The first substrate and the second substrate are not limited to those in the embodiment, and in short, correspond to two types of substrates having different thermal expansion coefficients.

電力用半導体装置１０１は、基本的構成として、絶縁基板１と、プリント基板７と、樹脂筐体９と、外部端子８と、基板間接続端子６と、絶縁性樹脂の一例としてのシリコーンゲル１１とを備え、ここで基板間接続端子６は、素子間接続部６０と、素子−回路接続部６１Ａとを有し、さらに素子−回路接続部６１Ａは屈伸部６１を有する。これらの各構成部分について以下に説明する。   The power semiconductor device 101 basically includes an insulating substrate 1, a printed circuit board 7, a resin housing 9, an external terminal 8, an inter-substrate connection terminal 6, and a silicone gel 11 as an example of an insulating resin. Here, the inter-substrate connection terminal 6 has an inter-element connection portion 60 and an element-circuit connection portion 61A, and the element-circuit connection portion 61A further has a bending / extension portion 61. Each of these components will be described below.

電力用半導体装置１０１に用いられる絶縁基板１は、一例として、主面の大きさが８０ｍｍ×４０ｍｍ、厚み２ｍｍの放熱板としてのＡｌ板１ａと、高熱伝導のセラミックフィラーを混合した厚み０．１５ｍｍの絶縁層１ｂと、厚み７０μｍのアルミニウムからなる回路パターン１ｃとが積層されて形成された、所謂メタルベース基板である。   As an example, the insulating substrate 1 used in the power semiconductor device 101 has a thickness of 0.15 mm in which a main plate has a size of 80 mm × 40 mm and a thickness of 2 mm, and an Al plate 1a as a heat sink and a high thermal conductive ceramic filler are mixed. This is a so-called metal base substrate formed by laminating an insulating layer 1b and a circuit pattern 1c made of aluminum having a thickness of 70 μm.

回路パターン１ｃには、図２に示すような配置形態にて、はんだ２を用いて、ＩＧＢＴ３（絶縁ゲート型バイポーラトランジスタ）及びＦＷＤｉ４（フリーホイーリングダイオード）がそれぞれ接合されている。尚、ＩＧＢＴ３及びＦＷＤｉ４は、電力用半導体素子の一例に相当する。このように回路パターン１ｃには、複数の電力用半導体素子が実装されている。
ＩＧＢＴ３は、一例として、主面の大きさが７ｍｍ×７ｍｍ、厚み２５０μｍの素子であり、その表面には、制御電極であるゲート電極と主電極であるエミッタ電極とを有し、その裏面には、回路パターン１ｃとはんだ付けされる主電極であるコレクタ電極を有する。またＩＧＢＴ３のゲート電極は、Ａｌワイヤ５を用いて回路パターン１ｃに電気的に接続されている。
ＦＷＤｉ４は、一例として、主面の大きさが７ｍｍ×５ｍｍ、厚み２５０μｍの素子であり、その表面には、主電極であるアノード電極４ａを有し、その裏面には回路パターン１ｃとはんだ付けされる主電極であるカソード電極を有する。このようにＦＷＤｉ４は、各表面に単一の電極を有する素子である。 An IGBT 3 (insulated gate bipolar transistor) and an FWDi 4 (free wheeling diode) are joined to the circuit pattern 1c using the solder 2 in the arrangement shown in FIG. The IGBT 3 and FWDi 4 correspond to an example of a power semiconductor element. Thus, a plurality of power semiconductor elements are mounted on the circuit pattern 1c.
As an example, the IGBT 3 is an element having a main surface size of 7 mm × 7 mm and a thickness of 250 μm, and has a gate electrode which is a control electrode and an emitter electrode which is a main electrode on its surface, and a back surface thereof. And a collector electrode which is a main electrode soldered to the circuit pattern 1c. The gate electrode of the IGBT 3 is electrically connected to the circuit pattern 1 c using an Al wire 5.
For example, the FWDi4 is an element having a main surface size of 7 mm × 5 mm and a thickness of 250 μm, and has an anode electrode 4a as a main electrode on the surface thereof and soldered to the circuit pattern 1c on the back surface thereof. A cathode electrode as a main electrode. Thus, FWDi4 is an element having a single electrode on each surface.

図１に示すように、絶縁基板１に実装されたＩＧＢＴ３等の電力用半導体素子に平行または略平行にプリント基板７が配置される。プリント基板７は、本実施形態では、大きさが９０ｍｍ×５０ｍｍで材質ＦＲ−４（Flame Retardant Type 4）の基板である。その基材７ｂの表裏両面には配線回路がそれぞれ形成され、ＩＧＢＴ３等の電力用半導体素子に対面した表面には、図３に示すようなパターンの配線回路７ａが形成されている。   As shown in FIG. 1, a printed circuit board 7 is arranged in parallel or substantially parallel to a power semiconductor element such as an IGBT 3 mounted on an insulating substrate 1. In the present embodiment, the printed circuit board 7 is a board having a size of 90 mm × 50 mm and a material FR-4 (Flame Retardant Type 4). Wiring circuits are formed on both the front and back surfaces of the substrate 7b, and a wiring circuit 7a having a pattern as shown in FIG. 3 is formed on the surface facing the power semiconductor element such as IGBT3.

互いに対向して配置される絶縁基板１とプリント基板７との間には、両者間の電気的接続を行い、基板間接続端子に相当する可撓性端子６が設けられる。このような可撓性端子６は、本実施形態では短冊状の金属製板材で構成され、一例として厚み０．３ｍｍ、幅３ｍｍの黄銅板で形成され、例えば図４に示すように、素子間接続部６０と、素子−回路接続部６１Ａとを有する。   Between the insulating substrate 1 and the printed circuit board 7 arranged to face each other, a flexible terminal 6 is provided which performs electrical connection therebetween and corresponds to an inter-substrate connection terminal. Such a flexible terminal 6 is formed of a strip-shaped metal plate material in the present embodiment, and is formed of, for example, a brass plate having a thickness of 0.3 mm and a width of 3 mm. For example, as shown in FIG. It has the connection part 60 and the element-circuit connection part 61A.

素子間接続部６０は、２つの電力用半導体素子つまりＩＧＢＴ３及びＦＷＤｉ４における各電極間を電気的に接続する部分であり、各電極に接合する接合部６２，６４を有する。尚、接合部６２については接合端部６２と記す場合もある。図４に示すような可撓性端子６において、素子−回路接続部６１Ａに近い接合部６４がＦＷＤｉ４の電極にはんだを用いて電気的及び機械的に固定される。
また、パワー半導体素子であるＩＧＢＴ３及びＦＷＤｉ４では、一般的にインバータ回路などで同電位となるエミッタ電極とアノード電極４ａとは次のように接続される。即ち、図５に示すように、ＦＷＤｉ４上のアノード電極４ａには、はんだ（図示せず）を用いて可撓性端子６の接合部６４を電気的及び機械的に固定する。この接合部６４から延び、パワー半導体素子であるＩＧＢＴ３及びＦＷＤｉ４との絶縁を確保する距離を保つために設けた、接合部６４からの高さ０．３ｍｍの湾曲部６３を介して、可撓性端子６の接合部６２をＩＧＢＴ３のエミッタ電極に電気的及び機械的に固定する。このように、本実施形態では、接合部６２はＩＧＢＴ３の電極とはんだを用いて電気的及び機械的に固定され、接合部６４はＦＷＤｉ４の電極とはんだを用いて電気的及び機械的に固定されている。 The inter-element connection portion 60 is a portion that electrically connects the respective electrodes of the two power semiconductor elements, that is, the IGBT 3 and the FWDi 4, and includes the joint portions 62 and 64 that are joined to the respective electrodes. The joint 62 may be referred to as a joint end 62. In the flexible terminal 6 as shown in FIG. 4, the joint portion 64 close to the element-circuit connection portion 61 </ b> A is electrically and mechanically fixed to the electrode of the FWDi 4 using solder.
Moreover, in IGBT3 and FWDi4 which are power semiconductor elements, generally the emitter electrode and anode electrode 4a which become the same electric potential in an inverter circuit etc. are connected as follows. That is, as shown in FIG. 5, the joint portion 64 of the flexible terminal 6 is electrically and mechanically fixed to the anode electrode 4a on the FWDi 4 using solder (not shown). A flexible portion is provided via a curved portion 63 having a height of 0.3 mm from the joint portion 64 provided to maintain a distance to ensure insulation from the power semiconductor element IGBT3 and FWDi4. The junction 62 of the terminal 6 is electrically and mechanically fixed to the emitter electrode of the IGBT 3. As described above, in this embodiment, the joint 62 is electrically and mechanically fixed using the IGBT3 electrode and solder, and the joint 64 is electrically and mechanically fixed using the FWDi4 electrode and solder. ing.

尚、上述のようにＩＧＢＴ３の裏面電極であるコレクタ電極及びＦＷＤｉ４の裏面電極であるカソード電極は、回路パターン１ｃで接続されている。これらの電極をさらにプリント基板７へ電気的に接続するために、図１内の右端に図示するような、素子−回路接続部６１Ａに類似した蛇腹形状の可撓性の端子１３が設けている。   As described above, the collector electrode that is the back electrode of the IGBT 3 and the cathode electrode that is the back electrode of the FWDi 4 are connected by the circuit pattern 1c. In order to further electrically connect these electrodes to the printed circuit board 7, an accordion-shaped flexible terminal 13 similar to the element-circuit connecting portion 61A as shown at the right end in FIG. 1 is provided. .

素子−回路接続部６１Ａは、接合部６２，６４の一方から延在し素子間接続部６０と一体に形成され、素子間接続部６０をプリント基板７の配線回路７ａに電気的に接続し、かつ、素子間接続部６０に対して折り曲げて屈曲させた屈伸部６１を有する部分である。また素子−回路接続部６１Ａの端部に位置する接合部６５（図４、図５）は、プリント基板７の配線回路７ａに、Ａｇフィラーが混合されている導電性接着剤（図示せず）によって電気的に接続される。このようにして可撓性端子６は、絶縁基板１とプリント基板７との間で、屈伸部６１によって伸縮されて配置される。   The element-circuit connection portion 61A extends from one of the joint portions 62 and 64 and is formed integrally with the inter-element connection portion 60, and electrically connects the inter-element connection portion 60 to the wiring circuit 7a of the printed circuit board 7. And it is a part which has the bending part 61 bent and bent with respect to the connection part 60 between elements. Further, the joining portion 65 (FIGS. 4 and 5) located at the end of the element-circuit connecting portion 61A is a conductive adhesive (not shown) in which an Ag filler is mixed with the wiring circuit 7a of the printed circuit board 7. Is electrically connected. In this way, the flexible terminal 6 is disposed between the insulating substrate 1 and the printed circuit board 7 by being expanded and contracted by the bending / extending portion 61.

また、ＩＧＢＴ３のゲート電極からアルミニウムワイヤを用いて接続された別の回路パターン１ｃと、プリント基板７との接続に用いられる可撓性の端子１４は、回路パターン１ｃ上の端子に接続される場合の可撓性の端子１３に比べて小さい端子を使用している。勿論、このような構成に限定されず、例えば電流容量の小さい電力用半導体装置にあっては、ゲート電極及びエミッタ電極共に、同一形状の可撓性の端子を用いても構わない。   Further, when the flexible circuit 14 used to connect the printed circuit board 7 to another circuit pattern 1c connected from the gate electrode of the IGBT 3 using an aluminum wire is connected to a terminal on the circuit pattern 1c. Compared with the flexible terminal 13, a smaller terminal is used. Of course, the present invention is not limited to such a configuration. For example, in a power semiconductor device having a small current capacity, a flexible terminal having the same shape may be used for both the gate electrode and the emitter electrode.

プリント基板７において、可撓性端子６が接続された配線回路７ａには、外部端子８がはんだ付けされ、配線回路７ａに対向する、プリント基板７の対向面側へ導出されている。   In the printed circuit board 7, the external terminal 8 is soldered to the wiring circuit 7a to which the flexible terminal 6 is connected, and is led out to the facing surface side of the printed circuit board 7 facing the wiring circuit 7a.

絶縁基板１及びプリント基板７の外縁部分には、図１に示すように、主にＰＰＳ（ポリフェニレンサルファイド）からなる樹脂筐体９が取り付けられ、樹脂筐体９と、絶縁基板１及びプリント基板７とは、シリコーン接着剤（図示せず）で接着される。絶縁基板１が取り付けられた状態において、樹脂筐体９の一側面９ａには、絶縁基板１のＡｌ板１ａが面一の状態で露出する。この露出したＡｌ板１ａには、装置外部への放熱のために放熱グリースを介してヒートシンク（共に図示せず）が接続される。このため樹脂筐体９には、ヒートシンク取付用のネジを通すための取付穴（図示せず）が形成されている。   As shown in FIG. 1, a resin housing 9 mainly made of PPS (polyphenylene sulfide) is attached to the outer edge portions of the insulating substrate 1 and the printed circuit board 7, and the resin housing 9, the insulating substrate 1, and the printed circuit board 7. Is bonded with a silicone adhesive (not shown). In a state where the insulating substrate 1 is attached, the Al plate 1a of the insulating substrate 1 is exposed on the one side surface 9a of the resin housing 9 in a flush state. A heat sink (both not shown) is connected to the exposed Al plate 1a via heat radiating grease for heat radiating to the outside of the apparatus. For this reason, the resin housing 9 is formed with an attachment hole (not shown) for passing a screw for attaching the heat sink.

また、樹脂筐体９の内側には、絶縁基板１とプリント基板７との隙間からプリント基板７の上面を覆う部分まで、空間放電、沿面放電に対する絶縁封止用で、絶縁性樹脂の一例に相当するシリコーンゲル１１が注入される。これにより可撓性端子６もシリコーンゲル１１によって樹脂封止される。さらに、樹脂筐体９の一側面９ａに対向する他方側面９ｂには、ＰＰＳからなり外部端子８の導出部を形成した蓋１０が取り付けられる。   In addition, inside the resin housing 9 is an insulating sealing for space discharge and creeping discharge from the gap between the insulating substrate 1 and the printed circuit board 7 to the portion covering the upper surface of the printed circuit board 7. Corresponding silicone gel 11 is injected. Thereby, the flexible terminal 6 is also resin-sealed by the silicone gel 11. Further, a lid 10 made of PPS and having a lead-out portion for the external terminal 8 is attached to the other side surface 9 b facing the one side surface 9 a of the resin housing 9.

絶縁基板１、プリント基板７、及び樹脂筐体９の接着工程は、次のように行う。つまり、絶縁基板１にＩＧＢＴ３及びＦＷＤｉ４を、ＩＧＢＴ３及びＦＷＤｉ４に可撓性端子６の接合部６２、６４を、それぞれはんだ付けし、ＩＧＢＴ３のゲート電極にアルミニウムワイヤ５を接続し、樹脂筐体９と、絶縁基板１及びプリント基板７との接着部にシリコーン接着剤を塗布する。さらに、可撓性端子６における他端の接合部６５に対応した接続部に導電性接着剤を塗布したプリント基板７を重ねて、これらを加熱硬化させることで接着を行う。その際、可撓性端子６の屈伸部６１による反発力でプリント基板７が撓まないように、可撓性端子６のばね定数、押しつけ量が選定される。   The bonding process of the insulating substrate 1, the printed circuit board 7, and the resin housing 9 is performed as follows. That is, the IGBT 3 and FWDi4 are soldered to the insulating substrate 1, the joint portions 62 and 64 of the flexible terminal 6 are soldered to the IGBT3 and FWDi4, respectively, the aluminum wire 5 is connected to the gate electrode of the IGBT3, and the resin housing 9 and Then, a silicone adhesive is applied to the bonding portion between the insulating substrate 1 and the printed circuit board 7. Furthermore, the printed circuit board 7 which apply | coated the electrically conductive adhesive is piled up on the connection part corresponding to the junction part 65 of the other end in the flexible terminal 6, and it adhere | attaches by heat-hardening these. At that time, the spring constant and the pressing amount of the flexible terminal 6 are selected so that the printed circuit board 7 is not bent by the repulsive force of the bending portion 61 of the flexible terminal 6.

以下には、電力用半導体装置１０１をこのような構造とした理由について説明する。
即ち、従来技術説明で既に述べたように、絶縁基板１は、放熱性及び絶縁性を有する反面、電力用半導体装置の中では高価な部品であることから、その面積の縮小化が求められる。これには、配線パターン及びパターン同士の間の絶縁距離によって決定される配線面積の縮小化が効果的である。よって、本実施形態の電力用半導体装置１０１では、絶縁基板１、及びＩＧＢＴ３等の電力用半導体素子の直上に配線を配置する方法、つまり絶縁基板１に積層するように、両面配線したプリント基板７を配置する方法を採っている。特に、本実施形態では、絶縁基板１における回路パターン１ｃの一部又は全部を、電力用半導体装置１０１内のプリント基板７に形成することにより、絶縁基板１の面積を一層縮小する効果を得ている。また、一般的に電力用半導体装置では、半導体素子の回路構成、あるいは素子が扱う電流容量が異なる仕様をラインナップすることが求められる。これに対しては、プリント基板７を多層化することによって対応可能である。つまりプリント基板７の配線パターンと蓋１０とを変更するだけで、外部端子８の配置をニーズに合わせて変更することが可能となることから、部品の共通化が可能となり、部品コストを抑制することが可能となる。 The reason why the power semiconductor device 101 has such a structure will be described below.
That is, as already described in the description of the prior art, the insulating substrate 1 has heat dissipation and insulating properties, but is an expensive component in the power semiconductor device, so that the area thereof is required to be reduced. For this purpose, it is effective to reduce the wiring area determined by the wiring pattern and the insulation distance between the patterns. Therefore, in the power semiconductor device 101 according to the present embodiment, the printed circuit board 7 that is wired on both sides so as to be stacked on the insulating substrate 1 is a method of arranging the wiring immediately above the insulating substrate 1 and the power semiconductor element such as the IGBT 3. The method of arranging is taken. In particular, in the present embodiment, an effect of further reducing the area of the insulating substrate 1 can be obtained by forming part or all of the circuit pattern 1 c in the insulating substrate 1 on the printed circuit board 7 in the power semiconductor device 101. Yes. In general, power semiconductor devices are required to have a lineup of specifications with different circuit configurations of semiconductor elements or current capacities handled by the elements. This can be dealt with by multilayering the printed circuit board 7. That is, it is possible to change the arrangement of the external terminals 8 according to needs simply by changing the wiring pattern of the printed circuit board 7 and the lid 10, so that the parts can be shared and the cost of the parts can be reduced. It becomes possible.

一方、このように絶縁基板１とプリント基板７とを重ねて配置した構成においても、主としてＳｉからなる電力用半導体素子を絶縁基板１にはんだ付けすることで、絶縁基板１の主材料であるＡｌと、電力用半導体素子のＳｉとの熱膨張率差に起因する反りが絶縁基板１に発生する。また、ＩＧＢＴ３等の電力用半導体素子を絶縁基板１にはんだ付けするとき、電力用半導体素子を完全な水平状態にて接続することは困難である。また特に、面積が大きい半導体素子、あるいは図２に示すように多数の素子及び接続点を有する半導体装置にあっては、はんだなどの接合材だけで、絶縁基板１とプリント基板７との間の距離のばらつきを吸収することは、困難である。   On the other hand, even in the configuration in which the insulating substrate 1 and the printed circuit board 7 are arranged so as to overlap with each other, by soldering a power semiconductor element mainly made of Si to the insulating substrate 1, Al that is a main material of the insulating substrate 1 is used. Then, warpage due to the difference in thermal expansion coefficient between Si and the power semiconductor element occurs in the insulating substrate 1. Further, when a power semiconductor element such as the IGBT 3 is soldered to the insulating substrate 1, it is difficult to connect the power semiconductor element in a completely horizontal state. In particular, in a semiconductor element having a large area, or a semiconductor device having a large number of elements and connection points as shown in FIG. 2, only a bonding material such as solder is used between the insulating substrate 1 and the printed circuit board 7. It is difficult to absorb distance variations.

そこで、本実施形態では、絶縁基板１とプリント基板７との間に配置されるＩＧＢＴ３等の電力用半導体素子に接続される可撓性端子６に屈伸部６１を形成して可撓性を持たせた。屈伸部６１を設けることで、絶縁基板１とプリント基板７との距離を近付けるだけで、可撓性端子６が撓み、可撓性端子６自体の傾きを含めた高さのばらつきを吸収することができるとともに、すべての接点の接続を確実に行うことができる。また、絶縁基板１とプリント基板７とを電気的に接続する可撓性の端子１３，１４によっても同様の効果が得られる。よって、電力用半導体装置１０１の組立性及び生産性の向上を図ることができる。   Therefore, in the present embodiment, the bent portion 61 is formed in the flexible terminal 6 connected to the power semiconductor element such as the IGBT 3 disposed between the insulating substrate 1 and the printed circuit board 7 to have flexibility. Let By providing the bending / extending portion 61, the flexible terminal 6 bends only by bringing the insulating substrate 1 and the printed circuit board 7 closer to each other, and the height variation including the inclination of the flexible terminal 6 itself is absorbed. It is possible to connect all the contacts with certainty. The same effect can be obtained by the flexible terminals 13 and 14 that electrically connect the insulating substrate 1 and the printed circuit board 7. Therefore, the assemblability and productivity of the power semiconductor device 101 can be improved.

また、電力用半導体装置１０１では、ＩＧＢＴ３等の電力用半導体素子は発熱し、その放熱板として機能する、絶縁基板１のＡｌ板１ａは、上記発熱伴い熱膨張する。一方、絶縁基板１に積層する形態で配置されるプリント基板７において発生する熱は、電流によるジュール熱が主である。よって、絶縁基板１とプリント基板７との間には温度差が発生し、かつ両者の熱膨張率も異なる。したがって、絶縁基板１とプリント基板７との間に配置されるＩＧＢＴ３等の電力用半導体素子に接続する可撓性端子６には、基板の主面に平行な方向で、ＩＧＢＴ３等の電力用半導体素子間の距離が離れる方向、つまり絶縁基板１及びプリント基板７の板厚方向２０に直交する基板長手方向２１に熱応力が発生する。この熱応力は、可撓性端子６自体、及び可撓性端子６と、絶縁基板１及びプリント基板７における各回路との接続部における劣化を促進する原因になる。
これに対して本実施形態では、可撓性端子６が屈伸部６１で変形可能なことから、上記劣化を効果的に緩和することが可能である。 In the power semiconductor device 101, the power semiconductor element such as the IGBT 3 generates heat, and the Al plate 1a of the insulating substrate 1 that functions as a heat radiating plate thereof thermally expands with the heat generation. On the other hand, the heat generated in the printed circuit board 7 arranged in the form of being laminated on the insulating substrate 1 is mainly Joule heat due to current. Therefore, a temperature difference is generated between the insulating substrate 1 and the printed board 7, and the thermal expansion coefficients of the two are also different. Therefore, the flexible terminal 6 connected to the power semiconductor element such as IGBT 3 disposed between the insulating substrate 1 and the printed circuit board 7 has a power semiconductor such as IGBT 3 in a direction parallel to the main surface of the substrate. Thermal stress is generated in the direction in which the distance between elements is increased, that is, in the substrate longitudinal direction 21 orthogonal to the plate thickness direction 20 of the insulating substrate 1 and the printed substrate 7. This thermal stress causes deterioration in the flexible terminal 6 itself and in the connection portion between the flexible terminal 6 and each circuit in the insulating substrate 1 and the printed circuit board 7.
On the other hand, in the present embodiment, since the flexible terminal 6 can be deformed by the bending / extending portion 61, the deterioration can be effectively reduced.

さらには、屈伸部６１のばね定数を増す、あるいは撓み量を増すことにより、可撓性端子６がプリント基板７へ作用する反発力を大きくし、ＦＷＤｉ４と可撓性端子６の接合部６４との間、及び配線回路７ａと他端の接合部６５との間に作用する圧縮する応力が大きくなる。これにより、はんだあるいは導電性接着剤で接合された可撓性端子６の接合部６４とＦＷＤｉ４とが、ＦＷＤｉ４の断続発熱により発生する熱応力に起因した亀裂あるいは剥離などで劣化した場合でも、電気的及び熱的な接続を維持することができ、信頼性の向上を図ることができる。また、絶縁基板１とプリント基板７との間には、図示するように屈伸部６１と同態様の可撓性の端子１３，１４を設けており、端子１３，１４のばね定数あるいは撓み量を増すことにより、端子１３，１４の接合部の回路パターン１ｃへの圧縮する応力が大きくなる。   Further, by increasing the spring constant of the bending / extending portion 61 or increasing the amount of bending, the repulsive force that the flexible terminal 6 acts on the printed circuit board 7 is increased, and the joint 64 between the FWDi 4 and the flexible terminal 6 And the compressive stress acting between the wiring circuit 7a and the joint 65 at the other end increases. As a result, even when the joint 64 and the FWDi 4 of the flexible terminal 6 joined by solder or a conductive adhesive deteriorate due to cracks or peeling due to thermal stress generated by intermittent heat generation of the FWDi 4, And thermal connection can be maintained, and reliability can be improved. Further, between the insulating substrate 1 and the printed circuit board 7, flexible terminals 13 and 14 having the same form as the bending portion 61 are provided as shown in the figure, and the spring constant or the bending amount of the terminals 13 and 14 is set. By increasing, the compressive stress to the circuit pattern 1c at the joint portion of the terminals 13 and 14 increases.

このような信頼性向上については、屈伸部６１の反発力が大きいほど効果が大きくなるため、ＩＧＢＴ３上及びＦＷＤｉ４上にそれぞれ可撓性端子６を設ける構成も考えられる。しかしながら、かかる技術思想の元で半導体装置を作製する際には、反発力の大きい可撓性端子６を各素子上に配置する場合、本実施形態に示すような半導体素子が多数配置される電力用半導体装置では部品点数が増加して組立性が低下する。さらに、プリント基板７及び固定する蓋１０の撓みを抑制するために、蓋１０を厚くする必要があり、かつ外部端子８を長くする必要が生じる。これによって外部端子８の発熱が増加し、温度が上昇しやすくなり、部材コストも上がる。
そこで、本実施形態のように同電位であるＩＧＢＴ３とＦＷＤｉ４とを一体の端子で接続することによって、プリント基板７が受ける反発力を３分の２程度に軽減することが可能となり、上述の問題点が解消する。この効果は、特に扱う電流が大きい半導体装置、及び昨今多く製造されている、インバータ回路、コンバータ回路、ブレーキ回路を内蔵するような多数の半導体素子を配置する半導体装置において有効である。 For such reliability improvement, the greater the repulsive force of the bending / extending portion 61, the greater the effect. Therefore, a configuration in which the flexible terminals 6 are provided on the IGBT 3 and the FWDi 4 can be considered. However, when a semiconductor device is manufactured based on such a technical idea, when a flexible terminal 6 having a large repulsive force is arranged on each element, power in which a large number of semiconductor elements as shown in this embodiment are arranged. In the semiconductor device for use, the number of parts increases and the assemblability deteriorates. Furthermore, in order to suppress the bending of the printed circuit board 7 and the lid 10 to be fixed, the lid 10 needs to be thick and the external terminal 8 needs to be lengthened. As a result, the heat generation of the external terminal 8 increases, the temperature tends to rise, and the member cost also increases.
Therefore, the repulsive force received by the printed circuit board 7 can be reduced to about two thirds by connecting the IGBT 3 and the FWDi 4 having the same potential with an integral terminal as in the present embodiment, and the above-mentioned problem The point disappears. This effect is particularly effective in a semiconductor device that handles a large current, and a semiconductor device in which a large number of semiconductor elements that incorporate an inverter circuit, a converter circuit, and a brake circuit are arranged in recent years.

また、ＩＧＢＴ３のエミッタ電極内部には、一般的に知られているように、エミッタ電極とはＳｉＯ２などの絶縁層（図示せず）にて絶縁して、ゲート電極からの配線が行われている。よって、ＩＧＢＴ３上に反発力の大きい可撓性端子６を配置した場合、絶縁層の破壊によってＩＧＢＴ３が不作動となる可能性も懸念される。一方、ＦＷＤｉ４のアノード電極４ａについては、エミッタ電極のような絶縁層が設けられていない。これらのことから、大電流を扱う場合、及び高い信頼性を求められる場合において、反発力の大きい屈伸部６１を用いる構成にあっては、可撓性を有する屈伸部６１は、ＦＷＤｉ４上に、つまり表面に単一の電極を有する半導体素子上に、設置する方が好ましい。このように表面に単一の電極を有する半導体素子上に屈伸部６１を配置することで、屈伸部６１の反発力を上げたときでも半導体素子が破損し難く、また、異電極、上述例ではＩＧＢＴ３のゲート電極への配線の妨げとならないという効果が得られる。 Further, as is generally known, the emitter electrode of the IGBT 3 is insulated from the emitter electrode by an insulating layer (not shown) such as SiO 2 and wired from the gate electrode. Yes. Therefore, when the flexible terminal 6 having a large repulsive force is disposed on the IGBT 3, there is a concern that the IGBT 3 may become inoperable due to the breakdown of the insulating layer. On the other hand, the anode layer 4a of FWDi4 is not provided with an insulating layer like an emitter electrode. From these facts, when handling a large current and when high reliability is required, in the configuration using the bending / extending part 61 having a large repulsive force, the bending / extending part 61 having flexibility is on the FWDi4. In other words, it is preferable to install on a semiconductor element having a single electrode on the surface. By disposing the bending / extending portion 61 on the semiconductor element having a single electrode on the surface in this way, the semiconductor element is not easily damaged even when the repulsive force of the bending / extending portion 61 is increased. There is an effect that the wiring to the gate electrode of the IGBT 3 is not hindered.

また、ＩＧＢＴ３のゲート配線のためにアルミニウムワイヤ５をボンディングする際、ボンディングツール（図示せず）と可撓性端子６との干渉を回避するため、およそ３ｍｍ程度の距離を取らなくてはならない。このためＩＧＢＴ３上のエミッタ電極における可撓性端子６の接合面積が減少する。その結果、ＩＧＢＴ３の電流及び発熱がエミッタ電極における接合部に集中し、抵抗損失などの電気特性が低下する。
よって接合面積を確保した上でボンディングツールの干渉を回避するためには、ＩＧＢＴ３上の接合高さを小さくすることが有効であり、そのためには、ＩＧＢＴ３からプリント基板７までの高さが比較的大きな可撓性端子６ではなく、本実施形態で示したように可撓性端子６の板厚である０．３ｍｍ程度の高さとなる湾曲部６３を接合する構造が好適である。 Further, when bonding the aluminum wire 5 for the gate wiring of the IGBT 3, a distance of about 3 mm should be taken in order to avoid interference between a bonding tool (not shown) and the flexible terminal 6. For this reason, the junction area of the flexible terminal 6 in the emitter electrode on the IGBT 3 is reduced. As a result, the current and heat generation of the IGBT 3 are concentrated at the junction in the emitter electrode, and electrical characteristics such as resistance loss are degraded.
Therefore, in order to avoid the interference of the bonding tool while securing the bonding area, it is effective to reduce the bonding height on the IGBT 3, and for that purpose, the height from the IGBT 3 to the printed circuit board 7 is relatively low. Instead of the large flexible terminal 6, a structure in which the curved portion 63 having a height of about 0.3 mm, which is the plate thickness of the flexible terminal 6, as shown in this embodiment is suitable.

以上説明したように、本実施形態の電力用半導体装置１０１は、生産性が従来に比して高く、かつ高温環境下及び長時間使用に適して動作信頼性を有する電力用半導体装置である。
上述の効果を発揮する可撓性端子６の形状は、本実施形態における形状に限定されず、可撓性及び電気抵抗を阻害しない形状であればどのような形態も適用可能である。但し、可撓性端子６として板材を使用する場合、屈伸部６１は、本実施の形態で図４に示すＭ字のように、３個以上の折り曲げ回数を有する、つまり３個以上の折り曲げ部６１ｂ（図４）を有する蛇腹形状が望ましい。
その理由としては、折り曲げ回数が２回である例えばＺ字形状の場合には、先に屈伸部６１の一端を固定し、その後に他端を接続するときに、他端の平面方向における位置合わせが難しくなる、つまり他端において平面方向の位置ずれが生じやすいという欠点があるからである。 As described above, the power semiconductor device 101 of the present embodiment is a power semiconductor device that has higher productivity than conventional ones and has operational reliability suitable for use in a high temperature environment and for a long time.
The shape of the flexible terminal 6 that exhibits the above-described effect is not limited to the shape in the present embodiment, and any shape can be applied as long as the shape does not hinder flexibility and electrical resistance. However, when a plate material is used as the flexible terminal 6, the bending portion 61 has three or more folding times, that is, three or more folding portions, as in the M-shape shown in FIG. 4 in the present embodiment. A bellows shape having 61b (FIG. 4) is desirable.
The reason for this is that, for example, in the case of a Z-shape that is bent twice, when one end of the bending / extending portion 61 is first fixed and then the other end is connected, the other end is aligned in the planar direction. This is because there is a drawback that a positional deviation in the planar direction tends to occur at the other end.

また、本実施の形態１における可撓性端子６では、屈伸部６１における折り曲げ部６１ｂの折り目は、図４に示すように、可撓性端子６の素子間接続部６０の延在方向６０ａ及び板厚方向６０ｂに対して直交する方向、つまり図４の紙面を貫通する方向に沿って延在している。   Further, in the flexible terminal 6 according to the first embodiment, as shown in FIG. 4, the folds of the bent portion 61 b in the bending / extending portion 61 are extended in the extending direction 60 a of the inter-element connection portion 60 of the flexible terminal 6 and It extends along a direction orthogonal to the plate thickness direction 60b, that is, a direction penetrating the paper surface of FIG.

また、可撓性端子６がはんだ付けで接合される場合、図５に示すように、はんだ付けされる可撓性端子６の接合部６４、接合端部６２、他端の接合部６５のいずれにおいても接合面側が電極等の被接合部に向かって凸となるような湾曲形状を有しても良い。このようにすることで、ＩＧＢＴ３、ＦＷＤｉ４の表面電極の高さが異なった場合でも、可撓性端子６と半導体素子との接触面積が安定し、かつはんだあるいは導電性接着剤のフィレットが安定的に形成され、接合性及び信頼性が向上する。   Further, when the flexible terminal 6 is joined by soldering, as shown in FIG. 5, any one of the joining portion 64, the joining end portion 62, and the other joining portion 65 of the flexible terminal 6 to be soldered is used. In this case, the bonding surface side may have a curved shape that is convex toward the bonded portion such as an electrode. By doing in this way, even if the height of the surface electrode of IGBT3 and FWDi4 differs, the contact area of the flexible terminal 6 and a semiconductor element is stabilized, and the fillet of a solder or a conductive adhesive is stable. To improve the bondability and reliability.

また、可撓性端子６の材質としては、本実施の形態で示した黄銅の他、りん青銅も使用可能である。また、可撓性端子６を接合する構造であるため、充分な反発力が必要でない場合、あるいは大電流を通電する場合には、無酸素銅を使用することも可能である。   In addition to the brass shown in the present embodiment, phosphor bronze can be used as the material of the flexible terminal 6. In addition, since the flexible terminal 6 is joined, oxygen-free copper can be used when a sufficient repulsive force is not required or when a large current is applied.

封止材料として組立後の可撓性端子６の反発力による信頼性向上などの効果を考慮して、本実施形態ではシリコーンゲルを用いているが、組立時の接続にのみ可撓性を発揮することで充分となるように、エポキシ樹脂によって封止して接合部周辺を固定した半導体装置とすることも有効である。   In consideration of the effect of improving the reliability due to the repulsive force of the flexible terminal 6 after assembly as a sealing material, silicone gel is used in this embodiment, but it exhibits flexibility only for connection during assembly. It is also effective to provide a semiconductor device in which the periphery of the joint is fixed by sealing with an epoxy resin so as to be sufficient.

本実施の形態で示した効果については、ここで示した材料の他、電力用半導体装置で一般的に用いられる材料を使用しても同様の効果が得られる。例えば、絶縁基板としてメタルベース基板の代わりに、ＡｌＮあるいはＡｌ２Ｏ３などの放熱性に優れるセラミックスに、Ｃｕパターンを貼り付けたセラミック基板、あるいはセラミック基板をＣｕあるいはＡｌなどの高放熱金属ブロックにはんだ付けなどで固着し、放熱性を向上させたものを使用しても良い。
また、電力用半導体素子の構成についても、複数のダイオードチップを並列するなどダイオード上に屈伸部６１を配置する構造であれば同様に適用し効果を発揮することが可能である。 As for the effects shown in the present embodiment, the same effects can be obtained by using materials generally used in power semiconductor devices in addition to the materials shown here. For example, instead of a metal base substrate as an insulating substrate, a ceramic substrate with a Cu pattern attached to a ceramic with excellent heat dissipation such as AlN or Al 2 O 3 , or a ceramic substrate with a high heat dissipation metal block such as Cu or Al You may use what fixed by soldering etc. and improved heat dissipation.
Further, the configuration of the power semiconductor element can be applied in the same manner and exert an effect as long as it has a structure in which the bending portion 61 is arranged on the diode, such as a plurality of diode chips arranged in parallel.

また、上述したようにＩＧＢＴ３及びＦＷＤｉ４の上に可撓性端子６を配置することで、既に説明したがまとめると以下の効果を得ることができる。即ち、
（１）絶縁基板１の面積を縮小することができる。
（２）ＩＧＢＴ３及びＦＷＤｉ４の電力用半導体素子上の可撓性端子６に反発力を持たせることで、電力用半導体素子の厚み方向における各接合部の信頼性を向上することができる。
（３）全ての電力用半導体素子について反発力を有する端子を配置した場合、反発力を抑える蓋１０が端子数に比例して厚くなってしまう。よって、同電位のある電力用半導体素子のみを可撓性端子６で接続することで、蓋１０に関する懸念も解決される。
（４）加圧力に対して破壊しやすいＩＧＢＴ３ではなく、ＦＷＤｉ４上に屈伸部６１を配置することにより、ＦＷＤｉ４の断続発熱により発生する熱応力に起因した亀裂あるいは剥離などで劣化した場合でも、接続を電気的及び熱的接続を維持することができ、信頼性向上を図ることができる。 In addition, as described above, the flexible terminal 6 is disposed on the IGBT 3 and the FWDi 4, and as described above, the following effects can be obtained. That is,
(1) The area of the insulating substrate 1 can be reduced.
(2) By giving a repulsive force to the flexible terminal 6 on the power semiconductor element of IGBT3 and FWDi4, the reliability of each junction part in the thickness direction of the power semiconductor element can be improved.
(3) When terminals having a repulsive force are arranged for all power semiconductor elements, the lid 10 that suppresses the repulsive force becomes thicker in proportion to the number of terminals. Therefore, the concern about the lid 10 is solved by connecting only the power semiconductor elements having the same potential with the flexible terminals 6.
(4) By placing the bending / extending portion 61 on the FWDi4 instead of the IGBT3 that is easily broken against the applied pressure, even if the connection is deteriorated due to cracks or peeling caused by the thermal stress generated by the intermittent heat generation of the FWDi4 The electrical and thermal connection can be maintained, and the reliability can be improved.

実施の形態２．
図６は、本発明の実施の形態２における電力用半導体装置１０２に備わる可撓性端子６−２の形状を示す。上述した実施の形態１の電力用半導体装置１０１と、本実施の形態２における電力用半導体装置１０２との相違部分は可撓性端子６−２であり、電力用半導体装置１０２の基本的な構成は、電力用半導体装置１０１と同様である。よって個々の構成部分の詳細な説明は、ここでは省略する。 Embodiment 2. FIG.
FIG. 6 shows the shape of the flexible terminal 6-2 provided in the power semiconductor device 102 according to the second embodiment of the present invention. The difference between power semiconductor device 101 of the first embodiment described above and power semiconductor device 102 of the second embodiment is flexible terminal 6-2, and the basic configuration of power semiconductor device 102 is as follows. Is the same as that of the power semiconductor device 101. Therefore, detailed description of each component is omitted here.

本実施形態における可撓性端子６−２は、厚さ０．５ｍｍの黄銅製であり、屈伸部６１における折り曲げ部６１ｂの折り目は、図６に示すように、可撓性端子６の素子間接続部６０の延在方向６０ａに沿って延在している。即ち、屈伸部６１の向きが実施の形態１の電力用半導体装置１０１の構成に対して９０度ずれている点で相違する。
以下に、このような構造を採る理由について説明する。 The flexible terminal 6-2 in the present embodiment is made of brass having a thickness of 0.5 mm, and the fold line of the bent portion 61b in the bending / extending portion 61 is between the elements of the flexible terminal 6 as shown in FIG. The connecting portion 60 extends along the extending direction 60a. That is, the difference is that the direction of the bending portion 61 is shifted by 90 degrees with respect to the configuration of the power semiconductor device 101 of the first embodiment.
The reason for adopting such a structure will be described below.

特に、一般的に電力用半導体装置の扱う電流が大きくなると、配線部における電気抵抗を抑制するため、配線にも用いる可撓性端子６の板厚をより厚くする必要がある。一方、可撓性端子を製造する上で、素子間接続部６０の平坦度、換言すると接合部６４と接合端部６２との平坦度を維持した上で屈伸部６１を製造するためには、接合部６２と接合端部６４との間に形成する湾曲部６３を先に曲げ加工し、接合部６２と接合端部６４とを平坦に維持した状態で屈伸部６１を形成する必要がある。ここで可撓性端子６の板厚が大きくなると、屈伸部６１を形成する曲げ型も充分剛性を持ったものが必要である。また屈伸部６１の反発力を用いて電力用半導体装置を組み立てることから、屈伸部６１のばね定数を管理するため、屈伸部６１の曲げ形状は精度良く成形する必要がある。   In particular, in general, when the current handled by the power semiconductor device is increased, it is necessary to increase the thickness of the flexible terminal 6 used also for the wiring in order to suppress the electrical resistance in the wiring portion. On the other hand, in manufacturing the flexible terminal, in order to manufacture the bending / extending portion 61 while maintaining the flatness of the inter-element connection portion 60, in other words, the flatness of the bonding portion 64 and the bonding end portion 62, It is necessary to bend the curved portion 63 formed between the joint portion 62 and the joint end portion 64 first, and to form the bending / extending portion 61 in a state where the joint portion 62 and the joint end portion 64 are kept flat. Here, when the plate thickness of the flexible terminal 6 is increased, the bending die for forming the bending / extending portion 61 needs to have sufficient rigidity. In addition, since the power semiconductor device is assembled using the repulsive force of the bending / extending portion 61, the bending shape of the bending / extending portion 61 needs to be accurately formed in order to manage the spring constant of the bending / extending portion 61.

さらに、湾曲部６３について、本実施形態２のように板厚の大きい可撓性端子６−２の場合には、絶縁基板１と可撓性端子６−２との熱膨張率の差によって接合部６４とＦＷＤｉ４のアノード電極４ａとの接合部、及び接合端部６２とＩＧＢＴ３のエミッタ電極との接合部のそれぞれに発生するせん断応力を、湾曲部６３が撓むことによって緩和する効果を発生する。このように湾曲部６３は、絶縁基板１と可撓性端子６−２との熱膨張差によって、可撓性端子６−２と電力用半導体素子表面との接合部にかかるせん断応力を緩和する。この効果をより有効にするためには、湾曲部６３は、電力用半導体素子からより離れる方向つまり板厚方向６０ｂに高く成形することが望ましいが、その結果、屈伸部６１を成形する際の曲げ型を設置することが著しく困難となった。   Further, in the case of the flexible terminal 6-2 having a large plate thickness as in the second embodiment, the bending portion 63 is joined by the difference in thermal expansion coefficient between the insulating substrate 1 and the flexible terminal 6-2. The shearing stress generated at each of the joint portion between the portion 64 and the anode electrode 4a of the FWDi4 and the joint portion between the joint end portion 62 and the emitter electrode of the IGBT 3 is relaxed by the bending portion 63 being bent. . Thus, the bending portion 63 relieves the shear stress applied to the joint portion between the flexible terminal 6-2 and the power semiconductor element surface due to the difference in thermal expansion between the insulating substrate 1 and the flexible terminal 6-2. . In order to make this effect more effective, the bending portion 63 is preferably formed higher in the direction away from the power semiconductor element, that is, in the plate thickness direction 60b. As a result, the bending portion 61 is bent when the bending portion 61 is formed. It became extremely difficult to install the mold.

このような屈伸部６１の成形が困難となる問題を解消するため、上述のように、屈伸部６１の向きを配線方向つまり素子間接続部６０の延在方向６０ａと直交させた。換言すると、屈伸部６１における折り曲げ部６１ｂの折り目を延在方向６０ａに沿って延在させている。これによって湾曲部６３の形状とはほぼ無関係に屈伸部６１を成形することが可能となり、可撓性端子６−２の生産性向上、並びに、電力用半導体装置１０２の信頼性向上及び大電流化を同時に実現することが可能となった。また、屈伸部６１の圧縮量を大きくしたときに屈伸部６１が倒れる方向に変形した場合でも、湾曲部６３と干渉することがないため、圧縮量の増加及び湾曲部６３の高さを大きくするなど設計製造の自由度を向上させることも可能となる。   In order to solve the problem that it is difficult to form the bent / extended portion 61, the direction of the bent / extended portion 61 is set to be orthogonal to the wiring direction, that is, the extending direction 60a of the inter-element connecting portion 60 as described above. In other words, the fold of the bent part 61b in the bending / extending part 61 is extended along the extending direction 60a. As a result, the bending / extending part 61 can be formed almost independently of the shape of the bending part 63, the productivity of the flexible terminal 6-2 is improved, the reliability of the power semiconductor device 102 is improved, and the current is increased. Can be realized at the same time. In addition, even when the bending / extending portion 61 is deformed in a direction in which the bending / extending portion 61 is tilted when the bending / extending portion 61 is increased, the bending portion 63 does not interfere with the bending portion 63. Therefore, the amount of compression is increased and the bending portion 63 is increased in height. It is also possible to improve the degree of freedom of design and manufacturing.

本実施の形態２で示した効果について、特に湾曲部６３の高さを大きくすることによって接合界面に発生するせん断応力を緩和する効果は、絶縁基板１としてセラミックス基板を用いた際に可撓性端子６−２との熱膨張率差が大きくなることから、より顕著に効果を発揮する。   Regarding the effect shown in the second embodiment, the effect of alleviating the shear stress generated at the bonding interface by increasing the height of the bending portion 63 is particularly flexible when a ceramic substrate is used as the insulating substrate 1. Since the difference in coefficient of thermal expansion with the terminal 6-2 becomes large, the effect is more remarkably exhibited.

また、実施の形態１において説明した種々の電力用半導体装置１０１に対する変形例は、この実施の形態２における電力用半導体装置１０２に対しても適用可能である。   The modifications to the various power semiconductor devices 101 described in the first embodiment can also be applied to the power semiconductor device 102 in the second embodiment.

実施の形態３．
図７、図８、及び図９は、本発明の実施の形態３における電力用半導体装置１０３に備わる可撓性端子６−３の形状を示す。本実施の形態３においても上述した実施の形態１の電力用半導体装置１０１との相違部分は可撓性端子であり、電力用半導体装置１０３の基本的な構成は、電力用半導体装置１０１と同様である。よって個々の構成部分の詳細な説明は省略する。 Embodiment 3 FIG.
7, 8 and 9 show the shape of the flexible terminal 6-3 provided in the power semiconductor device 103 according to the third embodiment of the present invention. Also in the third embodiment, the difference from the power semiconductor device 101 of the first embodiment described above is a flexible terminal, and the basic configuration of the power semiconductor device 103 is the same as that of the power semiconductor device 101. It is. Therefore, detailed description of each component is omitted.

図７に示す可撓性端子６−３Ａは、厚さ０．３ｍｍからなる黄銅製であり、素子間接続部６０が湾曲部６３を有さずに絶縁基板１に概ね平行に配置され、接合部６４及び接合端部６２において突出部６６を有する。この突出部６６は、素子間接続部６０から電力用半導体素子の電極側へ突出し、当該電極と電気的に接続する凸形状で、その高さが一例として０．２ｍｍである。また、可撓性端子６−３では湾曲部６３は設けていないので、突出部６６の高さによって電力用半導体素子３，４との絶縁距離が０．２ｍｍ以上を確保する構成としている。   The flexible terminal 6-3A shown in FIG. 7 is made of brass having a thickness of 0.3 mm, and the inter-element connection portion 60 does not have the bending portion 63 and is arranged substantially in parallel to the insulating substrate 1, and bonded. The part 64 and the joint end part 62 have a protrusion 66. The protruding portion 66 protrudes from the inter-element connection portion 60 to the electrode side of the power semiconductor element and is a convex shape that is electrically connected to the electrode, and its height is 0.2 mm as an example. Moreover, since the bending part 63 is not provided in the flexible terminal 6-3, it is set as the structure which ensures the insulation distance with the power semiconductor elements 3 and 4 0.2 mm or more with the height of the protrusion part 66. FIG.

図８に示す可撓性端子６−３Ｂにおいても、図７の可撓性端子６−３Ａと同様に厚さ０．３ｍｍの黄銅製で、湾曲部６３を有していない。また、可撓性端子６−３Ｂは、接合部６４及び接合端部６２にて、素子間接続部６０の幅方向の片側に形成した折曲片６７ａを、素子間接続部６０から電力用半導体素子３，４の電極側へ折り曲げて、素子間接続部６０と重なり当該電極と電気的に接続する積層部６７を有する。また、可撓性端子６−３Ｂにおいても湾曲部６３は設けていないので、積層部６７の厚さによって電力用半導体素子３，４との絶縁距離を確保している。   The flexible terminal 6-3B shown in FIG. 8 is also made of brass having a thickness of 0.3 mm and does not have the curved portion 63, like the flexible terminal 6-3A of FIG. In addition, the flexible terminal 6-3B is configured such that the bent piece 67a formed on one side in the width direction of the inter-element connection portion 60 at the joint portion 64 and the joint end portion 62 is connected to the power semiconductor from the inter-element connection portion 60. A laminated portion 67 that is bent toward the electrodes of the elements 3 and 4 and overlaps with the inter-element connection portion 60 and is electrically connected to the electrodes. Further, since the bending portion 63 is not provided in the flexible terminal 6-3B, the insulation distance from the power semiconductor elements 3 and 4 is ensured by the thickness of the laminated portion 67.

また、図９の可撓性端子６−３Ｃに示すように、積層部６７は、素子間接続部６０の幅方向の両側に形成した折曲片６７ａのそれぞれを電極側へ折り曲げて作製してもよい。
以下に、このような可撓性端子６−３の構造を採る理由について説明する。 Further, as shown in the flexible terminal 6-3C in FIG. 9, the laminated portion 67 is manufactured by bending each of the bent pieces 67a formed on both sides in the width direction of the inter-element connection portion 60 to the electrode side. Also good.
The reason for adopting such a structure of the flexible terminal 6-3 will be described below.

前述の実施の形態２で説明したように、可撓性端子６−２に対して屈伸部６１を曲げ加工する際に、ＩＧＢＴ３とＦＷＤｉ４との間に湾曲部６３を有すると曲げ加工が困難であると言う課題があった。また、一般的にＩＧＢＴ３とＦＷＤｉ４とを並べた場合、ＩＧＢＴ３に比べてＦＷＤｉ４の発熱密度が小さいことから、電極面積及び電極に対応した素子の面積が小さく設計される。ここで前述の実施の形態２で示した構造においては、ＩＧＢＴ３とＦＷＤｉ４とを接続する素子間接続部６０の端子幅に合わせてＦＷＤｉ４の１辺の長さを決定した場合、例えば図７に示す屈伸部６１の幅Ｗが小さくなるという問題があった。屈伸部６１の幅Ｗが小さくなると、電気抵抗の低減及び放熱性の向上のために、可撓性端子の板厚を大きくする必要があった。尚、元々扱う電流値が大きい場合には当初より充分な断面積を確保することが可能であるが、扱う電流値が小さいときには、屈伸部６１における反発力を維持するため、及び放熱性を維持するために、端子幅を大きくすることが求められる。   As described in the second embodiment, when the bending portion 61 is bent with respect to the flexible terminal 6-2, if the bending portion 63 is provided between the IGBT 3 and the FWDi4, the bending processing is difficult. There was a problem of being there. In general, when IGBT3 and FWDi4 are arranged, the heat generation density of FWDi4 is smaller than that of IGBT3, so that the electrode area and the element area corresponding to the electrode are designed to be small. Here, in the structure shown in the above-described second embodiment, when the length of one side of FWDi4 is determined in accordance with the terminal width of inter-element connection portion 60 that connects IGBT3 and FWDi4, for example, as shown in FIG. There was a problem that the width W of the bent portion 61 was reduced. When the width W of the bent portion 61 is reduced, it is necessary to increase the plate thickness of the flexible terminal in order to reduce electrical resistance and improve heat dissipation. In addition, when the current value handled originally is large, it is possible to secure a sufficient cross-sectional area from the beginning. However, when the current value handled is small, the repulsive force in the bending portion 61 is maintained, and the heat dissipation is maintained. Therefore, it is required to increase the terminal width.

このように可撓性端子における素子間接続部６０の幅と屈伸部６１の幅とが異なる場合には、可撓性端子の電気抵抗、放熱性、及びばね定数のいずれかの特性が低下してしまう。   As described above, when the width of the inter-element connection portion 60 and the width of the bending / extending portion 61 in the flexible terminal are different, any of the characteristics of the electrical resistance, heat dissipation, and spring constant of the flexible terminal is lowered. End up.

このような課題を解決するため、湾曲部を形成しない可撓性端子において、突出部６６あるいは積層部６７を形成することによって、湾曲部を設けることなく電力用半導体素子３，４と可撓性端子６−３Ａ、６−３Ｂ、６−３Ｃとの絶縁距離を確保した上で屈伸部６１を加工するための曲げ型が容易に配置できる構成とした。   In order to solve such a problem, in the flexible terminal that does not form the curved portion, the projecting portion 66 or the laminated portion 67 is formed, so that the power semiconductor elements 3 and 4 and the flexible semiconductor device can be flexibly formed without providing the curved portion. It was set as the structure which can arrange | position the bending die for processing the bending / extension part 61 easily, after ensuring the insulation distance with terminal 6-3A, 6-3B, 6-3C.

本実施形態３で示した構造では、上述のように、ＩＧＢＴ３、ＦＷＤｉ４の間を配線する可撓性端子６−３Ａ等の素子間接続部６０には湾曲部を設けていない。よって、突出部６６あるいは積層部６７と、ＩＧＢＴ３及びＦＷＤｉ４の各電極との間におけるせん断応力を緩和するためには、可撓性端子６−３Ａ等の板厚を小さくするのが好ましい。また、絶縁基板１についても、可撓性端子６−３Ａ等と比較的熱膨張率の近い銅あるいはアルミニウムを放熱板１ａとした金属ベース基板を用いることが好ましい。   In the structure shown in the third embodiment, as described above, the inter-element connection portion 60 such as the flexible terminal 6-3A for wiring between the IGBT 3 and the FWDi 4 is not provided with a bending portion. Therefore, in order to relieve the shear stress between the protruding portion 66 or the laminated portion 67 and each electrode of the IGBT 3 and the FWDi 4, it is preferable to reduce the plate thickness of the flexible terminal 6-3A or the like. As for the insulating substrate 1, it is preferable to use a metal base substrate using copper or aluminum having a thermal expansion coefficient relatively close to that of the flexible terminal 6-3A or the like as the heat radiating plate 1a.

また、図７に示す可撓性端子６−３Ａを用いる場合、０．２ｍｍの高さを有する突出部６６を介してＩＧＢＴ３と接合端部６２、及び、ＦＷＤｉ４と接合部６４とを接合することから、比較的厚い接合部に適したはんだ付けが用いられることが好ましいが、電気的及び機械的に接合される手法であれば他の方法を用いても構わない。   When the flexible terminal 6-3A shown in FIG. 7 is used, the IGBT 3 and the joining end 62, and the FWDi4 and the joining part 64 are joined via the protrusion 66 having a height of 0.2 mm. Therefore, it is preferable to use soldering suitable for relatively thick joints, but other methods may be used as long as they are electrically and mechanically joined.

また、図８に示す可撓性端子６−３Ｂを用いた場合には、可撓性端子６−３Ｂの幅を変化させることなくＩＧＢＴ３及びＦＷＤｉ４の各電極と積層部６７とを面接合することが可能となる。よって、ＩＧＢＴ３及びＦＷＤｉ４の各電極に対して、薄い接合部に適した導電性接着剤を用いられることができる。尚、接合方法は、導電性接着剤の使用に限定されず、電気的及び機械的に接合される手法であれば他の方法を用いても構わない。また、プリント基板７を搭載する前に接合部６４と積層部６７との間に隙間が存在する場合には、この隙間がなくなるまでは、屈伸部６１を撓ませる力よりも小さな力で接合部６４が変形することがあり、また変形によって傾きが発生することから、屈伸部６１のばね定数及び反発力が不安定になることがある。しかしながら、接合部６４の直下の積層部６７は、その一部がＦＷＤｉ４の電極と接触することで、積層部６７の影響を受けず屈伸部６１のばね定数及び反発力が安定するため、好ましい。   When the flexible terminal 6-3B shown in FIG. 8 is used, the electrodes of the IGBT 3 and FWDi4 and the laminated portion 67 are surface-bonded without changing the width of the flexible terminal 6-3B. Is possible. Therefore, a conductive adhesive suitable for a thin joint can be used for each of the IGBT3 and FWDi4 electrodes. The joining method is not limited to the use of a conductive adhesive, and other methods may be used as long as they are electrically and mechanically joined. In addition, when a gap exists between the joint portion 64 and the laminated portion 67 before the printed circuit board 7 is mounted, the joint portion is less than the force that bends the bending / extending portion 61 until the gap is eliminated. 64 may be deformed, and an inclination is generated by the deformation, so that the spring constant and the repulsive force of the bending / extending portion 61 may become unstable. However, the laminated portion 67 directly below the joint portion 64 is preferable because a part of the laminated portion 67 is in contact with the electrode of the FWDi4, so that the spring constant and the repulsive force of the bending and extending portion 61 are stabilized without being affected by the laminated portion 67.

さらに、図９に示す可撓性端子６−３Ｃによれば、ＩＧＢＴ３及びＦＷＤｉ４において、積層部６７を通して対向する２方向から均一に電流が引き出され、電流密度及び発熱密度が分散されることから、電力用半導体素子の電気特性、具体的には抵抗損失を減少させることができる。またこれに付随して、温度上昇が抑制されることから、通電サイクルによって発生する、電力用半導体素子表面の温度サイクルに対する信頼性が向上する。   Furthermore, according to the flexible terminal 6-3C shown in FIG. 9, in the IGBT 3 and FWDi4, current is uniformly drawn from the two opposing directions through the stacked portion 67, and the current density and heat generation density are dispersed. The electrical characteristics of the power semiconductor element, specifically, the resistance loss can be reduced. Further, accompanying this, since the temperature rise is suppressed, the reliability with respect to the temperature cycle of the surface of the power semiconductor element generated by the energization cycle is improved.

また、実施の形態１において説明した種々の電力用半導体装置１０１に対する変形例は、この実施の形態３における電力用半導体装置１０３に対しても適用可能である。   The modifications to the various power semiconductor devices 101 described in the first embodiment are also applicable to the power semiconductor device 103 in the third embodiment.

実施の形態４．
図１０は、本発明の実施の形態４における電力用半導体装置１０４に備わる可撓性端子６−４の形状を示す。また、図１１には図１０で示す可撓性端子６−４の曲げ加工前の展開図を示す。本実施の形態４においても上述した実施の形態１の電力用半導体装置１０１との相違部分は可撓性端子であり、電力用半導体装置１０４の基本的な構成は、電力用半導体装置１０１と同様である。よって個々の構成部分の詳細な説明は省略する。 Embodiment 4 FIG.
FIG. 10 shows the shape of the flexible terminal 6-4 provided in the power semiconductor device 104 according to the fourth embodiment of the present invention. FIG. 11 is a development view before bending of the flexible terminal 6-4 shown in FIG. Also in the fourth embodiment, the difference from the power semiconductor device 101 of the first embodiment described above is a flexible terminal, and the basic configuration of the power semiconductor device 104 is the same as that of the power semiconductor device 101. It is. Therefore, detailed description of each component is omitted.

図１０に示す可撓性端子６−４は、板厚０．３ｍｍの黄銅製であり、概ね図８に示す可撓性端子６−３Ｂと同じ構成を有するが、以下の点で相違する。即ち、図８の可撓性端子６−３Ｂでは、ＦＷＤｉ４の電極との接合部６４における積層部６７を形成する折曲片６７ａは、素子間接続部６０の板厚方向６０ｂにおいて屈伸部６１の投影領域６９のすべてに渡り延在していない。これに対し本実施の形態４における可撓性端子６−４では、図１０に示すように、ＦＷＤｉ４の電極との接合部６４における積層部６７を形成する折曲片６７ａは、素子間接続部６０の板厚方向６０ｂにおいて屈伸部６１の投影領域６９のすべてに渡り延在する。このような構成を採るために、図１１に示すように、接合部６４に対応する折曲片６７ａと、可撓性端子６−４の内、屈伸部６１となる部分との間に、スリット６８を設けている。
以下に、このような構造を採る理由について説明する。 A flexible terminal 6-4 shown in FIG. 10 is made of brass having a plate thickness of 0.3 mm, and generally has the same configuration as the flexible terminal 6-3B shown in FIG. 8, but is different in the following points. That is, in the flexible terminal 6-3B of FIG. 8, the bent piece 67a that forms the laminated portion 67 in the joint portion 64 with the electrode of FWDi4 is the bending portion 61 in the plate thickness direction 60b of the inter-element connection portion 60. It does not extend over the entire projection area 69. On the other hand, in the flexible terminal 6-4 according to the fourth embodiment, as shown in FIG. 10, the bent piece 67a forming the laminated portion 67 in the joint portion 64 with the electrode of FWDi4 has an inter-element connection portion. 60 extends over the entire projection region 69 of the bending portion 61 in the thickness direction 60b. In order to adopt such a configuration, as shown in FIG. 11, a slit is formed between the bent piece 67a corresponding to the joint portion 64 and the portion of the flexible terminal 6-4 that becomes the bent portion 61. 68 is provided.
The reason for adopting such a structure will be described below.

屈伸部６１の圧縮量を大きく構成した場合、屈伸部６１の直下に空間が存在すると、屈伸部６１の圧縮力により、屈伸部６１がＦＷＤｉ４に近づくように変形する。ＦＷＤｉ４の外周に屈伸部６１が近接すると、屈伸部６１とＦＷＤｉ４との絶縁距離が不足する可能性があることから、近接状態でも例えば１ｍｍ程度の充分な絶縁距離を確保する必要があった。チップが大きい場合にはＦＷＤｉ４表面のアノード電極４ａの面積も大きいため、１ｍｍの距離確保は、積層部６７とＦＷＤｉ４との接合面積に影響しないが、一方、チップが小さくＦＷＤｉ４表面のアノード電極４ａの面積が小さい場合には、１ｍｍの距離確保のために接合面積が小さくなるという懸念がある。   When the compression amount of the bending / extending part 61 is configured to be large, if there is a space immediately below the bending / extending part 61, the bending / extending part 61 is deformed so as to approach FWDi 4 by the compressive force of the bending / extending part 61. When the bending / extending part 61 comes close to the outer periphery of the FWDi4, there is a possibility that the insulation distance between the bending / extending part 61 and the FWDi4 may be insufficient. Therefore, it is necessary to secure a sufficient insulating distance of, for example, about 1 mm even in the proximity state. When the chip is large, the area of the anode electrode 4a on the surface of the FWDi4 is large, and securing a distance of 1 mm does not affect the bonding area between the stacked portion 67 and the FWDi4. When the area is small, there is a concern that the bonding area becomes small in order to secure a distance of 1 mm.

そこで、図１０に示すように、板厚方向６０ｂにおける屈伸部６１の投影領域６９のすべてに渡り、換言すると屈伸部６１の折れ曲がり部分の直下部分にまで、折曲片６７ａつまり積層部６７を配置するように構成した。これにより、屈伸部６１の圧縮量を大きく設定した場合でも、屈伸部６１は積層部６７で支持され、ＦＷＤｉ４の外周に近接することはない。よって比較的小さいＦＷＤｉ４においてもアノード電極４ａの面積に対して接合面積を拡大することが可能となり、電流密度及び発熱密度の分散が可能となる。また、屈伸部６１の圧縮量を大きく設定できることから、屈伸部６１の反発力により得られる信頼性向上などの効果を充分発揮することが可能となる。   Therefore, as shown in FIG. 10, the bent piece 67 a, that is, the laminated portion 67 is arranged over the entire projection region 69 of the bent portion 61 in the thickness direction 60 b, in other words, directly below the bent portion of the bent portion 61. Configured to do. Thereby, even when the compression amount of the bending / extending portion 61 is set large, the bending / extending portion 61 is supported by the laminated portion 67 and does not approach the outer periphery of the FWDi4. Therefore, even in a relatively small FWDi 4, the junction area can be expanded with respect to the area of the anode electrode 4 a, and the current density and heat generation density can be dispersed. In addition, since the amount of compression of the bending / extending part 61 can be set large, it is possible to sufficiently exhibit the effect of improving the reliability obtained by the repulsive force of the bending / extending part 61.

また、実施の形態１において説明した種々の電力用半導体装置１０１に対する変形例は、この実施の形態４における電力用半導体装置１０４に対しても適用可能である。   The modifications to the various power semiconductor devices 101 described in the first embodiment can also be applied to the power semiconductor device 104 in the fourth embodiment.

以上説明した各実施の形態を適宜組み合わせた構成を採ることもできる。このような構成では、各実施の形態にて奏する効果が組み合わされる。   A configuration in which the embodiments described above are appropriately combined may be employed. In such a configuration, the effects obtained in each embodiment are combined.

１ 絶縁基板、１ａ 放熱板、１ｂ 絶縁層、１ｃ 回路パターン、３ ＩＧＢＴ、
４ ＦＷＤｉ、４ａ アノード電極、
６，６−２，６−３Ａ，６−３Ｂ，６−３Ｃ，６−４ 可撓性端子、
７ プリント基板、７ａ 配線回路、８ 外部端子、９ 樹脂筐体、
１１ シリコーンゲル、６０ 素子間接続部、６１ 屈伸部、
６１Ａ 素子−回路接続部、６２ 接合端部、６３ 湾曲部、
６４ 接合部、６６ 突出部、６７ 積層部、プリント基板基材、
１０１〜１０４ 電力用半導体装置。 1 Insulating substrate, 1a Heat sink, 1b Insulating layer, 1c Circuit pattern, 3 IGBT,
4 FWDi, 4a Anode electrode,
6,6-2,6-3A, 6-3B, 6-3C, 6-4 flexible terminal,
7 Printed circuit board, 7a Wiring circuit, 8 External terminal, 9 Resin housing,
11 silicone gel, 60 inter-element connection, 61 flexion and extension,
61A element-circuit connection part, 62 junction end part, 63 bending part,
64 joints, 66 protrusions, 67 laminates, printed circuit board base materials,
101-104 Power semiconductor device.

Claims (7)

放熱板に絶縁層を介して形成した回路パターンに複数の電力用半導体素子を実装した第１基板と、表裏両面に配線回路を形成した第２基板と、上記放熱板を一側面に露出させて上記第１基板を保持し、かつ上記電力用半導体素子に対向して配置した上記第２基板を保持する樹脂筐体と、上記第２基板における上記配線回路に接続され上記樹脂筐体の外部へ導出される外部端子と、を備えた電力用半導体装置において、
上記第１基板と上記第２基板との間に設けられる基板間接続端子と、
上記樹脂筐体内に充填され、上記基板間接続端子を封止する絶縁性樹脂と、をさらに備え、
上記基板間接続端子は、２つの上記電力用半導体素子における電極間を電気的に接続する素子間接続部と、この素子間接続部と一体に形成され上記素子間接続部に対して折れ曲がって延在して上記素子間接続部を上記第２基板における配線回路に電気的に接続する素子−回路接続部とを有し、この素子−回路接続部は、一方の電力用半導体素子の上方に位置し可撓性を有する屈伸部を有する、
ことを特徴とする電力用半導体装置。 A first substrate on which a plurality of power semiconductor elements are mounted on a circuit pattern formed on an insulating layer through an insulating layer; a second substrate on which wiring circuits are formed on both front and back surfaces; and the radiator plate is exposed on one side surface. A resin housing that holds the first substrate and that holds the second substrate disposed to face the power semiconductor element, and is connected to the wiring circuit on the second substrate and to the outside of the resin housing. In a power semiconductor device provided with a derived external terminal,
An inter-substrate connection terminal provided between the first substrate and the second substrate;
An insulating resin filled in the resin casing and sealing the inter-substrate connection terminal;
The inter-substrate connection terminal includes an inter-element connection portion that electrically connects the electrodes of the two power semiconductor elements, and is formed integrally with the inter-element connection portion and bends and extends with respect to the inter-element connection portion. And an element-circuit connecting portion that electrically connects the inter-element connecting portion to the wiring circuit on the second substrate, and the element-circuit connecting portion is positioned above one of the power semiconductor elements. And having a flexion / extension part having flexibility,
A power semiconductor device. 上記屈伸部が上方に位置する上記一方の電力用半導体素子は、その表面に単一の電極を有する素子である、請求項１に記載の電力用半導体装置。   2. The power semiconductor device according to claim 1, wherein the one power semiconductor element on which the bending portion is positioned is an element having a single electrode on a surface thereof. 上記素子間接続部は、当該素子間接続部の延在方向に伸縮性を有する湾曲部を有する、請求項１又は２に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein the inter-element connection portion includes a curved portion having elasticity in an extending direction of the inter-element connection portion. 上記基板間接続端子は板材で形成され、上記屈伸部は蛇腹形状であり、この蛇腹形状の折り目を上記素子間接続部の延在方向に沿って配置される、請求項１から３のいずれか１項に記載の電力用半導体装置   The inter-substrate connection terminal is formed of a plate material, the bending / extending portion has a bellows shape, and the bellows-shaped fold is disposed along the extending direction of the inter-element connection portion. The power semiconductor device according to claim 1 上記素子間接続部は、各電力用半導体素子の電極側へ突出し当該電極と電気的に接続する突出部を有する、請求項１に記載の電力用半導体装置。   2. The power semiconductor device according to claim 1, wherein the inter-element connection portion has a protruding portion that protrudes toward an electrode side of each power semiconductor element and is electrically connected to the electrode. 上記基板間接続端子は板材で形成され、上記素子間接続部は、各電力用半導体素子の電極側へ折り曲げられ当該電極と電気的に接続する積層部を有する、請求項１に記載の電力用半導体装置。   The power connection device according to claim 1, wherein the inter-substrate connection terminal is formed of a plate material, and the inter-element connection portion includes a stacked portion that is bent toward the electrode side of each power semiconductor element and is electrically connected to the electrode. Semiconductor device. 上記屈伸部は、上記積層部の板厚方向における当該積層部の主面の投影領域に位置する、請求項６に記載の電力用半導体装置。   The power semiconductor device according to claim 6, wherein the bending portion is located in a projection region of a main surface of the stacked portion in the thickness direction of the stacked portion.
JP2013079786A 2013-04-05 2013-04-05 Power semiconductor device Expired - Fee Related JP6012533B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013079786A JP6012533B2 (en) 2013-04-05 2013-04-05 Power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013079786A JP6012533B2 (en) 2013-04-05 2013-04-05 Power semiconductor device

Publications (2)

Publication Number Publication Date
JP2014204006A JP2014204006A (en) 2014-10-27
JP6012533B2 true JP6012533B2 (en) 2016-10-25

Family

ID=52354174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013079786A Expired - Fee Related JP6012533B2 (en) 2013-04-05 2013-04-05 Power semiconductor device

Country Status (1)

Country Link
JP (1) JP6012533B2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6256309B2 (en) * 2014-11-11 2018-01-10 三菱電機株式会社 Power semiconductor device
DE102015208348B3 (en) 2015-05-06 2016-09-01 Siemens Aktiengesellschaft Power module and method for producing a power module
DE112018000701T5 (en) 2017-02-06 2019-10-17 Mitsubishi Electric Corporation POWER SEMICONDUCTOR MODULE AND POWER CONVERTER DEVICE
CN111542921B (en) 2018-01-05 2024-03-19 三菱电机株式会社 Semiconductor device with a semiconductor device having a plurality of semiconductor chips
CN111868900A (en) * 2018-03-23 2020-10-30 三菱综合材料株式会社 Manufacturing method of electronic component mounting module
JP7059970B2 (en) * 2019-03-11 2022-04-26 株式会社デンソー Semiconductor device
JP7088132B2 (en) * 2019-07-10 2022-06-21 株式会社デンソー Semiconductor devices and electronic devices
JP7170911B2 (en) * 2019-12-02 2022-11-14 三菱電機株式会社 Power semiconductor device and its manufacturing method
JP7294152B2 (en) * 2020-01-14 2023-06-20 セイコーエプソン株式会社 Light source device and projector
DE112020005302T5 (en) * 2020-01-21 2022-11-03 Rohm Co., Ltd. SEMICONDUCTOR COMPONENT
JP2025021309A (en) * 2023-07-31 2025-02-13 株式会社東芝 Semiconductor Device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202548A (en) * 1986-02-28 1987-09-07 Mitsubishi Electric Corp Semiconductor device
JPH0650358U (en) * 1992-12-10 1994-07-08 日本インター株式会社 Composite semiconductor device
US5705848A (en) * 1995-11-24 1998-01-06 Asea Brown Boveri Ag Power semiconductor module having a plurality of submodules
JP3410969B2 (en) * 1997-06-30 2003-05-26 株式会社東芝 Semiconductor device
JP3923258B2 (en) * 2001-01-17 2007-05-30 松下電器産業株式会社 Power control system electronic circuit device and manufacturing method thereof
JP4499577B2 (en) * 2005-01-19 2010-07-07 三菱電機株式会社 Semiconductor device
JP4365388B2 (en) * 2006-06-16 2009-11-18 株式会社日立製作所 Semiconductor power module and manufacturing method thereof
JP2008227131A (en) * 2007-03-13 2008-09-25 Renesas Technology Corp Semiconductor device and its manufacturing method
JP5369798B2 (en) * 2009-03-18 2013-12-18 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP5253455B2 (en) * 2010-06-01 2013-07-31 三菱電機株式会社 Power semiconductor device

Also Published As

Publication number Publication date
JP2014204006A (en) 2014-10-27

Similar Documents

Publication Publication Date Title
JP6012533B2 (en) Power semiconductor device
JP5665729B2 (en) Power semiconductor device
EP3226292B1 (en) Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device
JP5071405B2 (en) Power semiconductor device
JP2013219267A (en) Power module
CN103534801A (en) Semiconductor device and wiring substrate
JP2016018866A (en) Power module
WO2014034411A1 (en) Electric power semiconductor device
JP2008124468A (en) Power module
WO2013171946A1 (en) Method for manufacturing semiconductor device and semiconductor device
JP6711098B2 (en) Heat dissipation structure of semiconductor device
JP5218009B2 (en) Semiconductor device
JP6043049B2 (en) Semiconductor device mounting structure and semiconductor device mounting method
WO2013047231A1 (en) Semiconductor device and method of manufacture thereof
JP2008205100A (en) Power semiconductor device
JP4046623B2 (en) Power semiconductor module and fixing method thereof
JP6755197B2 (en) Semiconductor devices and their manufacturing methods
CN112530915B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
JP2006190728A (en) Electric power semiconductor device
CN111354710A (en) Semiconductor device and method for manufacturing the same
JP5793295B2 (en) Semiconductor device
JP6292066B2 (en) Power semiconductor device
JP6028808B2 (en) Semiconductor device
JP4715283B2 (en) Power converter and manufacturing method thereof
JP2009164511A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151014

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160812

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160823

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160920

R150 Certificate of patent or registration of utility model

Ref document number: 6012533

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees