JP5968968B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device capable of transmitting an electric signal between two circuits having different electric signal potentials.

  When an electric signal is transmitted between two circuits having different electric signal potentials, a photocoupler is often used. The photocoupler has a light emitting element such as a light emitting diode and a light receiving element such as a phototransistor, and converts an inputted electric signal into light by the light emitting element, and returns this light to an electric signal by the light receiving element. An electrical signal is transmitted.

  However, since the photocoupler has a light emitting element and a light receiving element, it is difficult to reduce the size. Further, when the frequency of the electrical signal is high, it becomes impossible to follow the electrical signal. As a technique for solving these problems, a technique for transmitting an electric signal by inductively coupling two inductors has been developed as described in, for example, Patent Document 1.

  Patent Document 2 discloses a technique for forming an inductance using a plurality of wiring layers stacked on a semiconductor substrate via an interlayer insulating film. In this technique, the first arc-shaped wiring pattern that forms the input-side winding and the second arc-shaped wiring pattern that forms the output-side winding are alternately stacked. Each wiring layer is formed with any arc-shaped wiring pattern.

JP-T-2001-513276 Japanese Patent Laid-Open No. 10-163422

  When downsizing an element that transmits an electric signal between two circuits having different electric signal potentials, an inductor is formed in each of the two wiring layers by applying a semiconductor device manufacturing technique. It is conceivable that the inductor faces the insulating film. In this case, since the dielectric strength between the two inductors is not sufficient with respect to the potential difference between the two inductors due to the thin interlayer insulating film, the dielectric strength between the two inductors A technology to improve the quality is desired.

According to the present invention, a substrate;
A multilayer wiring layer formed on the substrate, in which insulating layers and wiring layers are alternately stacked in this order t times (t ≧ 3);
A first inductor provided in an nth wiring layer of the multilayer wiring layer;
A second inductor provided in the m-th wiring layer (t ≧ m ≧ n + 2) of the multilayer wiring layer and positioned above the first inductor;
And any of the wiring layers located between the n-th wiring layer and the m-th wiring layer is provided with an inductor located above the first inductor.

  According to this semiconductor device, at least two or more insulating layers are located between the first inductor and the second inductor. None of these insulating layers is provided with an inductor positioned above the first inductor. Accordingly, the withstand voltage between the first inductor and the second inductor is increased.

  According to the present invention, the withstand voltage between the first inductor and the second inductor can be increased.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is sectional drawing of the semiconductor device in 2nd Embodiment. It is sectional drawing of the semiconductor device in 3rd Embodiment. It is sectional drawing which shows the modification of 3rd Embodiment. It is sectional drawing of the semiconductor device in 4th Embodiment. It is sectional drawing of the semiconductor device in 5th Embodiment. It is sectional drawing of the semiconductor device in 6th Embodiment. It is sectional drawing of the semiconductor device in 7th Embodiment. It is sectional drawing of the semiconductor device in 8th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. This semiconductor device has a substrate 10, a multilayer wiring layer formed on the substrate 10, a first inductor 310, and a second inductor 320. The multilayer wiring layer is formed by alternately stacking insulating layers and wiring layers in this order t times (t ≧ 3) or more. The first inductor 310 is provided in the nth wiring layer of the multilayer wiring layer. The second inductor 320 is provided in the m-th wiring layer (t ≧ m ≧ n + 2) of the multilayer wiring layer and is located above the first inductor 310. An inductor positioned above the first inductor 310 is not provided in any wiring layer positioned between the nth wiring layer and the mth wiring layer. The first inductor 310 and the second inductor 320 constitute a signal transmission element 300 that transmits electrical signals to each other. The electrical signal is, for example, a digital signal, but may be an analog signal.

  In the present embodiment, each of the first inductor 310 and the second inductor 320 is a spiral wiring pattern formed in one wiring layer. The insulating layer may have a structure in which a plurality of interlayer insulating films are stacked, or may be a single interlayer insulating film. In this embodiment, the insulating layer has a structure in which two interlayer insulating films are stacked.

  In the present embodiment, the semiconductor device has a structure in which four layers of wirings 510, 520, 530, and 540 are stacked in this order. The wirings 510, 520, 530, and 540 are Cu wirings formed by a damascene method, and are embedded in grooves formed in the wiring layers 412, 422, 432, and 442, respectively. Pads (not shown) are formed on the uppermost wiring 540. Note that at least one of the wirings 510, 520, 530, and 540 may be an Al alloy wiring.

  An interlayer insulating film 410 for forming a contact plug is provided between the substrate 10 and the lowermost wiring 510. The wirings 510 and 520, the wirings 520 and 530, and the wiring 530, Insulating layers 420, 430, and 440 for forming vias are provided between the respective 540s. On the substrate 10, an insulating layer 410, a wiring layer 412, an insulating layer 420, a wiring layer 422, an insulating layer 430, a wiring layer 432, an insulating layer 440, and a wiring layer 442 are stacked in this order.

Each insulating film constituting the insulating layer and the wiring layer may be a SiO ₂ film or a low dielectric constant film. The low dielectric constant film can be an insulating film having a relative dielectric constant of 3.3 or less, preferably 2.9 or less. As the low dielectric constant film, in addition to SiOC, polyhydrogensiloxane such as HSQ (hydrogensilsesquioxane), MSQ (methylsilsesquioxane), or MHSQ (methylated hydrogensilsesquioxane), Aromatic-containing organic materials such as polyaryl ether (PAE), divinylsiloxane-bis-benzocyclobutene (BCB), or Silk (registered trademark), SOG, FOX (flowable oxide), Cytop, or BCB (Bencyclic cyclone) It can also be used. These porous films can also be used as the low dielectric constant film.

  The first inductor 310 is located in the lowermost wiring layer 412, and the second inductor 320 is located in the uppermost wiring layer 442. Between the first inductor 310 and the second inductor 320, two wiring layers 422 and 432 and three insulating layers 420, 430 and 440 are located.

  The substrate 10 is a first conductivity type (for example, p-type) semiconductor substrate. The semiconductor device further includes a first circuit 100 and a second circuit 200. The first circuit 100 is connected to one of the first inductor 310 and the second inductor 320 constituting the signal transmission element 300, and the second circuit 200 is connected to the other of the first inductor 310 and the second inductor 320. ing. These connections are made through the multilayer wiring layer 400 on the substrate 10. For example, the signal transmission element 300 is located between the first circuit 100 and the second circuit 200, but is not limited thereto. For example, the signal transmission element 300 may be included in the first circuit 100 or may be included in the second circuit 200. The first circuit 100 and the second circuit 200 have different electric signal potentials. In the configuration of FIG. 1, “the electric potentials of the input electric signals are different from each other” means that the electric signals have different amplitudes (the difference between the electric potential indicating 0 and the electric potential indicating 1).

  The first circuit 100 has a first transistor. The first transistor includes a first conductivity type transistor and a second conductivity type transistor. The first-conductivity-type first transistor 121 is formed in the second-conductivity-type well 120, and has two first-conductivity-type impurity regions 124 and a gate electrode 126 that serve as a source and a drain. The second conductivity type first transistor 141 is formed in the first conductivity type well 140, and has two second conductivity type impurity regions 144 and a gate electrode 146 to be a source and a drain. A gate insulating film is located under each of the gate electrodes 126 and 146. These two gate insulating films have substantially the same thickness.

  A second conductivity type impurity region 122 is formed in the well 120, and a first conductivity type impurity region 142 is formed in the well 140. A wiring for supplying a reference potential (ground potential) of the first conductivity type first transistor 121 is connected to the impurity region 122, and a wiring for supplying a reference potential of the second conductivity type first transistor 141 is connected to the impurity region 142. Is connected.

  The second circuit 200 has a second transistor. The second transistor also includes a first conductivity type transistor and a second conductivity type transistor. The first conductivity type second transistor 221 is formed in the second conductivity type well 220 and has two first conductivity type impurity regions 224 and a gate electrode 226 which serve as a source and a drain. The second-conductivity-type second transistor 241 is formed in the first-conductivity-type well 240 and has two second-conductivity-type impurity regions 244 and a gate electrode 246 that serve as a source and a drain. A gate insulating film is located under each of the gate electrodes 226 and 246. In the example shown in the figure, these two gate insulating films are thicker than the gate insulating film of the first transistor included in the first circuit. However, the first transistor and the second transistor may have the same gate insulating film thickness.

  A second conductivity type impurity region 222 is formed in the well 220, and a first conductivity type impurity region 242 is formed in the well 240. A wiring for supplying a reference potential of the second transistor 221 of the first conductivity type is connected to the impurity region 222, and a wiring for supplying a reference potential of the second transistor of the second conductivity type 241 is connected to the impurity region 242. Yes.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. First, a first transistor is formed in a first region of the substrate 10 (region in which the first circuit 100 in FIG. 1 is formed), and in a second region (region in which the second circuit 200 in FIG. 1 is formed) of the substrate 10. A second transistor is formed. Next, the multilayer wiring layer 400 is formed on the first transistor and the second transistor. When the multilayer wiring layer 400 is formed, the first inductor 310 and the second inductor 320 are formed above the third region of the substrate 10 (the region where the signal transmission element 300 in FIG. 1 is formed). In the example shown in FIG. 1, the second inductor 320 can be connected to the second circuit 200 via a pad (not shown) and a bonding wire (not shown) formed on the uppermost wiring layer 442. it can. In the configuration of FIG. 1, “the electric potentials of the input electric signals are different from each other” means that the electric signals have different amplitudes (the difference between the electric potential indicating 0 and the electric potential indicating 1).

  Next, the effect of this embodiment is demonstrated. When electric energy or an electric signal is transmitted through two inductors, higher transmission efficiency can be obtained by bringing the two inductors closer to each other. For this reason, normally, the transfer element is designed so that the two inductors are as close as possible. When the arrangement of the first inductor 310 and the second inductor 320 is designed based on this design concept, the second inductor 320 is arranged in a wiring layer one above the first inductor 310.

  On the other hand, in this embodiment, the first inductor 310 is located in the nth wiring layer, and the second inductor 320 is located in the mth wiring layer (m ≧ n + 2). In addition, no inductor positioned above the first inductor 310 is provided in any wiring layer positioned between the n-th wiring layer and the m-th wiring layer. In other words, the second inductor 320 is not formed in the wiring layer on the first inductor 310 but in a wiring layer separated by two or more. For this reason, the number of insulating films (insulating layers) positioned between the first inductor 310 and the second inductor 320 is increased as compared with the case based on the normal design concept described above, and the first inductor 310 and the second inductor 320 The withstand voltage between the two inductors 320 is increased. This effect is particularly prominent when the first inductor 310 is positioned in the first wiring layer and the second inductor 320 is positioned in the uppermost wiring layer as in the present embodiment.

  Further, the first inductor 310 and the second inductor 320 can be formed only by changing the wiring pattern of each wiring layer. For this reason, it can suppress changing the manufacturing equipment and process conditions of a semiconductor device, and can utilize the existing manufacturing conditions of the existing manufacturing equipment of a semiconductor device.

  Further, the first circuit 100, the second circuit 200, and the signal transmission element 300 are formed on the same substrate 10 in the same process. For this reason, the manufacturing cost of the semiconductor device is reduced, and the semiconductor device is downsized.

  FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment. This semiconductor device is the same as that of the first embodiment except that the second inductor 320 is located in the wiring layer 432 below the uppermost wiring layer 442. In the example shown in FIG. 2, the second inductor 320 can be connected to the second circuit 200 via a pad (not shown) formed on the uppermost wiring layer 442 and a bonding wire. Also in the configuration of FIG. 2, as in the configuration of FIG. 1, “the potentials of the input electric signals are different from each other” means that the amplitudes of the electric signals (the difference between the potential indicating 0 and the potential indicating 1) are different. Means that.

  According to this embodiment, the same effect as that of the first embodiment can be obtained. Further, since the first inductor 310 and the second inductor 320 are close to each other, the signal transmission efficiency is improved, and the power necessary for signal transmission in the signal transmission element 300 is reduced.

  FIG. 3 is a cross-sectional view of the semiconductor device according to the third embodiment. This semiconductor device has the same configuration as that of the first embodiment except that the first circuit 100 and the signal transmission element 300 are formed on the substrate 10 and the second circuit 200 is formed on the substrate 20. is there. In the example shown in this drawing, the first inductor 310 is connected to the first circuit 100 via the multilayer wiring layer 400 on the substrate 10, and the second inductor 320 is formed in the uppermost wiring layer 442 of the substrate 20. The second circuit 200 is connected through a pad (not shown) and a bonding wire (not shown). In the configuration of FIG. 3, “the potentials of the input electric signals are different from each other” means, for example, when the electric signals have different amplitudes (the difference between the potential indicating 0 and the potential indicating 1), There is a case where the potentials indicating 0) are different from each other, or a combination thereof.

  In the example shown in the figure, the number of wiring layers on the substrate 10 and the number of wiring layers on the substrate 20 are the same, but they may be different from each other. Further, in the example shown in this figure, the layers and wirings on the substrate 10 and the layers and wirings on the substrate 20 have the same layer and wiring thickness, but as shown in the modification of FIG. The thickness of these layers and wiring may be different from each other. In the example shown in FIG. 4, each layer and wiring on the substrate 20 are thick, but each layer and wiring on the substrate 10 may be thick.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. In addition, since the first circuit 100 and the second circuit 200 are formed on different substrates 10 and 20, the reference potential of the first transistor of the first circuit 100 and the reference potential of the second transistor of the second circuit 200 are large. Even if they are different (for example, the difference is 100 V or more), these reference potentials can be prevented from being short-circuited. Further, since the first inductor 310 is connected to the first circuit 100 instead of the second circuit 200, the potential difference between the first inductor 310 and the substrate 10 is unlikely to increase. Therefore, even if the first inductor 310 is arranged in the lowermost wiring layer, it is possible to suppress the occurrence of dielectric breakdown between the first inductor 310 and the substrate 10.

  Further, the thickness of the gate insulating film of the first transistor and the gate insulating film of the second transistor can be greatly different without using a complicated process.

  FIG. 5 is a cross-sectional view of a semiconductor device according to the fourth embodiment. In this semiconductor device, the substrate 10 is an SOI (Silicon On Insulator) substrate, and the substrate 10 includes a first region where the first circuit 100 is formed, a second region where the second circuit 200 is formed, The embedded insulating layer 18 is formed between each of the third regions where the signal transmission element 300 is formed, and the first insulating layer 18 is insulated from each other by the embedded insulating layer 18. This is the same as the embodiment.

  The substrate 10 has a structure in which an insulating layer 14 and a silicon layer 16 are stacked in this order on a base substrate (for example, a silicon substrate) 12. The first transistor of the first circuit 100 and the second transistor of the second circuit 200 are formed in the silicon layer 16. The buried insulating layer 18 is buried in the silicon layer 16, and the bottom is in contact with the insulating layer 14. In the example shown in FIG. 5, the second inductor 320 can be connected to the second circuit 200 via a pad (not shown) and a bonding wire (not shown) formed in the uppermost wiring layer 442. it can. In the configuration of FIG. 5, “the potentials of the input electric signals are different from each other” means, for example, when the electric signals have different amplitudes (the difference between the potential indicating 0 and the potential indicating 1), There is a case where the potentials indicating 0) are different from each other, or a combination thereof.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. In addition, in the substrate 10, the first region where the first circuit 100 is formed and the second region where the second circuit 200 is formed are insulated from each other. Even if the reference potential and the reference potential of the second transistor of the second circuit 200 are greatly different (for example, the difference is 100 V or more), it is possible to suppress a short circuit between these reference potentials.

  FIG. 6 is a cross-sectional view of the semiconductor device according to the fifth embodiment. In this semiconductor device, the buried insulating layer 18 is not provided between the first region of the substrate 10 where the first circuit 100 is formed and the second region where the signal transmission element 300 is formed. The configuration is the same as that of the semiconductor device according to the fourth embodiment except that the region and the second region are electrically connected. The first inductor 310 is connected to the first circuit 100. In the example shown in FIG. 6, the second inductor 320 can be connected to the second circuit 200 via a pad (not shown) and a bonding wire (not shown) formed on the uppermost wiring layer 442. it can. In the configuration of FIG. 6, “the electric potentials of the input electric signals are different from each other” means, for example, when the electric signals have different amplitudes (the difference between the electric potential indicating 0 and the electric potential indicating 1), There is a case where the potentials indicating 0) are different from each other, or a combination thereof.

  Also in this embodiment, the first region and the third region of the substrate 10 are insulated from the second region. For this reason, the same effect as the fourth embodiment can be obtained. In addition, the first region and the third region are electrically connected, but the first inductor 310 is connected to the first circuit 100 instead of the second circuit 200, and therefore, between the first inductor 310 and the substrate 10. The possibility that the potential difference becomes large is low. Therefore, even if the first inductor 310 is disposed in the lowermost wiring layer 412, it is possible to suppress the occurrence of dielectric breakdown between the first inductor 310 and the substrate 10.

  FIG. 7 is a cross-sectional view of the semiconductor device according to the sixth embodiment. This semiconductor device is the same as that of the fourth embodiment except that a plurality of embedded insulating layers 18 are provided apart from each other on the substrate 10 located below the first inductor 310. In the example shown in FIG. 7, the second inductor 320 can be connected to the second circuit 200 via a pad (not shown) and a bonding wire (not shown) formed on the uppermost wiring layer 442. it can. In the configuration of FIG. 7, “the potentials of the input electric signals are different from each other” means that, for example, when the amplitudes of the electric signals (difference between the potentials indicating 0 and 1) are different from each other, the reference potentials ( There is a case where the potentials indicating 0) are different from each other, or a combination thereof.

  According to this embodiment, the same effect as that of the fourth embodiment can be obtained. A plurality of buried insulating layers 18 are provided on the substrate 10 located below the first inductor 310 so as to be separated from each other. For this reason, it can suppress that an eddy current arises in the board | substrate 10 with the magnetic flux which the 1st inductor 310 and the 2nd inductor 320 form, and the Q value of the signal transmission element 300 can be made small.

  FIG. 8 is a cross-sectional view of the semiconductor device according to the seventh embodiment. This semiconductor device uses a buried insulating layer 19 separated from the insulating layer 14 in place of the buried insulating layer 18 in contact with the insulating layer 14 in the substrate 10 positioned below the first inductor 310. Except for this point, the second embodiment is the same as the sixth embodiment. The buried insulating layer 19 has an STI (Shallow Trench Isolation) structure and can be formed in the same process as the element isolation films of the first transistor of the first circuit 100 and the second transistor of the second circuit 200. In the example shown in FIG. 8, the second inductor 320 can be connected to the second circuit 200 via a pad (not shown) and a bonding wire (not shown) formed in the uppermost wiring layer 442. it can. In the configuration of FIG. 8, “the electric potentials of the input electric signals are different from each other” means, for example, when the electric signals have different amplitudes (the difference between the electric potential indicating 0 and the electric potential indicating 1), There is a case where the potentials indicating 0) are different from each other, or a combination thereof.

  According to this embodiment, the same effect as that of the sixth embodiment can be obtained. The same effect can be obtained by using a LOCOS (Local Oxidation Of Silicon) oxide film instead of the buried insulating layer 19.

  FIG. 9 is a cross-sectional view of a semiconductor device according to the eighth embodiment. The semiconductor device according to the present embodiment is the same as that of the first embodiment except that the buried insulating layer 19 shown in the seventh embodiment is formed on the substrate 10 located below the first inductor 310. It is the same composition as. In the example shown in FIG. 9, the second inductor 320 can be connected to the second circuit 200 via a pad (not shown) and a bonding wire (not shown) formed in the uppermost wiring layer 442. it can. In the configuration of FIG. 9, “the electric potentials of the input electric signals are different from each other” means that the electric signals have different amplitudes (the difference between the electric potential indicating 0 and the electric potential indicating 1).

  According to this embodiment, the same effect as that of the first embodiment can be obtained. In addition, the generation of eddy current in the substrate 10 can be suppressed, and the Q value of the signal transmission element 300 can be reduced. The same effect can be obtained by using a LOCOS oxide film instead of the buried insulating layer 19.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

10 substrate 12 base substrate 14 insulating layer 16 silicon layer 18 buried insulating layer 19 buried insulating layer 20 substrate 100 first circuit 120 well 121 first transistor 122 of first conductivity type impurity region 124 impurity region 126 gate electrode 140 well 141 Second conductivity type first transistor 142 Impurity region 144 Impurity region 146 Gate electrode 200 Second circuit 220 Well 221 First conductivity type second transistor 222 Impurity region 224 Impurity region 226 Gate electrode 240 Well 241 Second conductivity type second transistor 2 transistor 242 impurity region 244 impurity region 246 gate electrode 300 signal transmission element 310 first inductor 320 second inductor 400 multilayer wiring layer 410 insulating layer 412 wiring layer 420 insulating layer 422 wiring layer 430 insulating layer 432 wiring layer 440 Edge layer 442 Wiring layer 510 Wiring 520 Wiring 530 Wiring 540 Wiring

Claims (5)

A substrate,
A multilayer wiring layer formed on the substrate, in which insulating layers and wiring layers are alternately stacked in this order t times (t ≧ 3);
A first inductor provided in the nth wiring layer of the multilayer wiring layer and connected to the first circuit;
A second inductor provided in the m-th wiring layer (t ≧ m ≧ n + 2) of the multilayer wiring layer and positioned above the first inductor;
With
None of the wiring layers located between the nth wiring layer and the mth wiring layer is provided with a wiring located immediately above the first inductor,
A second circuit connected to the second inductor;
The substrate is an SOI (Silicon On Insulator) substrate,
The SOI substrate includes an insulating layer and a semiconductor layer on the insulating layer,
Wherein said semiconductor layer of the SOI substrate has a buried insulating layer for insulating the second region where the first region and the second circuit wherein the first circuit is disposed is placed,
The first inductor and the second inductor are formed above a third region of the SOI substrate located between the first region and the second region,
The buried insulating layer insulates the third region from the first region and the second region ;
The buried insulating layer includes a first buried insulating layer between the first region and the third region, a second buried insulating layer between the second region and the third region, and the first region. A buried insulating layer and a third buried insulating layer between the second buried insulating layers,
A bottom portion of the first buried insulating layer is in contact with the insulating layer of the SOI substrate;
A bottom portion of the second buried insulating layer is in contact with the insulating layer of the SOI substrate;
A semiconductor device wherein a bottom portion of the third buried insulating layer is not in contact with the insulating layer of the SOI substrate . The semiconductor device according to claim 1,
The m-th wiring layer is the uppermost wiring layer, and includes a bonding wire connected to the second inductor. The semiconductor device according to claim 1,
The first circuit includes a first transistor formed in a first region of the substrate,
The second circuit is a semiconductor device having a second transistor formed in a second region of the substrate. The semiconductor device according to claim 3.
The first transistor and the second transistor are semiconductor devices having different reference potentials. The semiconductor device according to claim 1,
The semiconductor device, wherein the nth wiring layer is the lowermost wiring layer.

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