JP5889171B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

  In recent years, improvement in the characteristics of power devices has been demanded from the viewpoint of energy saving. Therefore, in addition to conventional power devices using Si (silicon), power devices using SiC (silicon carbide) are promising as next-generation high breakdown voltage / low loss power switching elements. Power devices include field effect transistors (FET) having a metal, insulator (eg, silicon oxide), semiconductor (Metal Insulator (eg, Oxide) Semiconductor: MIS (eg, MOS)) structure, Schottky diodes, etc. There is. For example, in a MOSFET using SiC, an element structure conforming to the element structure of a conventional MOSFET using Si is employed. Since SiC has a larger band gap than Si, an SiC-MOSFET can operate at a higher temperature than a conventional Si-MOSFET that has been operated at less than 200 ° C.

In power devices, Al is mainly used as a metal material for wiring, and Al, including Al and Si, Cu (copper), Ti (titanium), Pd (palladium), etc. Al-based material was used. However, when an Al-based material is used for the metal material of the wiring, in a high temperature operation exceeding 200 ° C., the metal material and an electrode connected to the semiconductor region in the semiconductor substrate, a silicon film formed on the surface of the semiconductor substrate, etc. As a result, the reliability of the device is likely to deteriorate due to oxidation of the surface of the metal material.

In consideration of the problems of the Al-based material as described above, Patent Document 1 proposes using a Cu-based material as a wiring metal in an SiC power device. Patent Document 2 discloses that a Cu electrode and its barrier metal are etched by RIE.

International Publication No. 2007/108439 JP-A-11-186237

When Cu or metallization containing Cu is used for the electrode, it is necessary to form a barrier metal in order to suppress diffusion of Cu into the semiconductor substrate at high temperatures and deterioration of element characteristics. The diffusion of Cu into the barrier metal is interfacial diffusion that diffuses the interface (surface) of the barrier metal compared to volume diffusion that diffuses through the pores of the barrier metal and grain boundary diffusion that diffuses the grain boundary of the barrier metal. Therefore, the barrier metal diffusion preventing effect is determined by the length between Cu along the barrier metal surface and the element structure formed on the substrate. The element structure part that forms the base of the barrier metal includes an interlayer insulating film formed of SiO ₂ , a gate electrode formed of polysilicon, etc., and the diffusion rate of Cu in these materials is very high. It is necessary to increase the length between Cu and the element structure along the surface. However, in Patent Document 1, the length between the Cu along the barrier metal surface and the element structure formed on the substrate is only the thickness of the barrier metal, and a sufficient diffusion preventing effect may not be obtained. there were.

  Further, the Cu-based electrode has poor adhesion to the barrier metal compared to the Al-based electrode. A power device requires a thick film having an electrode thickness exceeding 5 μm from the viewpoint of heat dissipation and assembly. By forming the Cu-based electrode with a thick film, it is possible to make the heat distribution in the chip uniform by increasing the heat capacity. Moreover, the rise in the temperature at the time of a short circuit can be suppressed and a withstand amount improves. At the time of wire bonding, a strong force is applied because a wire having a large diameter is hit. If the electrode is thin, the device is damaged and the element is destroyed. Since a Cu wire bond requires more force than an Al wire bond, a thicker film is required than an Al-based electrode.

  When a thick Cu electrode exceeding 5 μm is used, the film stress of Cu increases, and film peeling tends to occur. Film peeling occurs from the Cu film edge as the starting point, and in order to suppress Cu peeling, it is necessary to prevent the film peeling from occurring as the starting point. One factor that causes film peeling at the edge of the Cu film is that a particularly large edge stress at the edge of the barrier metal is applied to Cu and the surface of the barrier metal. Therefore, if the edge of the Cu film and the edge of the barrier metal are close as in the semiconductor device of Patent Document 2, peeling of the Cu film becomes a problem.

  In view of the above-described problems, an object of the present invention is to provide an SiC semiconductor device that suppresses film peeling of a Cu electrode and has a high effect of preventing diffusion of Cu into an element structure and a method for manufacturing the same.

A silicon carbide semiconductor device according to the present invention includes a silicon carbide semiconductor element, a barrier metal formed on the silicon carbide semiconductor element, and an end of the contact surface formed with the barrier metal at the end of the barrier metal. And a Cu electrode having a thickness of 5 μm or more, which is more receded.

The method for manufacturing a silicon carbide semiconductor device according to the present invention includes (a) a step of forming a barrier metal on the silicon carbide semiconductor element, and (b) an end portion of a contact surface with the barrier metal on the barrier metal. A step of forming a Cu electrode having a thickness of 5 μm or more that is recessed from the end of the metal, and (c) a step of anisotropically etching the barrier metal vertically using the Cu electrode as a mask. b) is a step of forming the Cu electrode so that the width of at least a part other than the bottom contacting the barrier metal is wider than the width of the bottom.

A silicon carbide semiconductor device according to the present invention includes a silicon carbide semiconductor element, a barrier metal formed on the silicon carbide semiconductor element, and an end of the contact surface formed with the barrier metal at the end of the barrier metal. And a Cu electrode having a thickness of 5 μm or more, which is more receded. Since the distance between the Cu electrode and the silicon carbide semiconductor element along the surface of the barrier metal is increased by the amount of displacement between the end of the barrier metal and the end of the Cu electrode, the silicon carbide of Cu along the surface of the barrier metal Suppresses diffusion into semiconductor elements. Further, the stress at the end of the barrier metal is prevented from being applied to the end of the Cu electrode, and the film peeling of the Cu electrode is suppressed.

The method for manufacturing a silicon carbide semiconductor device according to the present invention includes (a) a step of forming a barrier metal on the silicon carbide semiconductor element, and (b) an end portion of a contact surface with the barrier metal on the barrier metal. A step of forming a Cu electrode having a thickness of 5 μm or more that is recessed from the end of the metal, and (c) a step of anisotropically etching the barrier metal vertically using the Cu electrode as a mask. b) is a step of forming the Cu electrode so that the width of at least a part other than the bottom contacting the barrier metal is wider than the width of the bottom. According to this manufacturing method, the barrier metal is formed wider than the width at which the Cu electrode is in contact with the barrier metal. Therefore, the distance between Cu and the silicon carbide semiconductor element along the barrier metal surface can be increased, and a high Cu diffusion preventing effect can be obtained. Further, since stress generated at the end of the barrier metal is prevented from being applied to the end of the Cu electrode, film peeling of the Cu electrode is suppressed.

It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the structure of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the structure of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the manufacturing process of the silicon carbide semiconductor device of this invention. It is a figure which shows the structure of the silicon carbide semiconductor device of this invention.

<A. Embodiment 1>
In this specification, the first conductivity type is n-type and the second conductivity type is p-type as the semiconductor conductivity type, but the opposite conductivity type may be used.

<A-1. Configuration>
FIG. 8 is a configuration diagram showing one unit cell of the silicon carbide semiconductor device of the first embodiment. In the first embodiment, a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will be described as an example of a silicon carbide semiconductor device. The SiC-MOSFET of the first embodiment includes an n ⁺ type semiconductor substrate 1, an n ⁻ type SiC layer 2 formed on the semiconductor substrate 1, and a well region selectively formed on the surface of the SiC layer 2. 3 and a source region 4 and a contact region 5 selectively formed on the surface of the well region 3. Semiconductor substrate 1 and SiC layer 2 constitute SiC wafer 6. Further, the SiC-MOSFET of the first embodiment includes a gate oxide film 7 formed over the well region 3 and the SiC layer 2, a gate electrode 8 formed on the gate oxide film 7, and the source region 4. A source electrode 10 formed on the gate electrode 8, an interlayer insulating film 9 covering the gate electrode 8 to ensure insulation from the source electrode 10, a barrier metal 13 formed on the source electrode 10 and the interlayer insulating film 9, and a barrier metal And Cu electrode 12 formed on 13.

<A-2. Manufacturing process>
A method for manufacturing the SiC-MOSFET having the structure shown in FIG. 8 will be described with reference to FIGS. First, an n ⁻ type SiC layer 2 made of SiC is formed on one surface of an n ⁺ type semiconductor substrate 1 using an epitaxial crystal growth method (FIG. 1). As the semiconductor substrate 1, for example, an n ⁺ type SiC substrate is suitable. The semiconductor substrate 1 and the SiC layer 2 constitute a SiC wafer 6.

  Next, impurities are ion-implanted into the surface of the SiC wafer 6, specifically, at a predetermined interval in the surface of the SiC layer 2 constituting the SiC wafer 6, using a resist as a mask, to form a p-type well. Region 3 is selectively formed (FIG. 2). Examples of the p-type impurity in the SiC layer 2 include boron (B) and aluminum (Al). After the ion implantation, the resist is removed.

  Next, impurities are ion-implanted into the surface of each well region 3 using a resist as a mask to selectively form an n-type source region 4 (FIG. 2). Examples of the n-type impurity in the well region 3 include phosphorus (P) and nitrogen (N). After the ion implantation, the resist is removed.

Next, a p-type (second conductivity type) impurity is ion-implanted into the surface of the well region 3 using a resist as a mask, and a p ⁺ type (second conductivity type) is adjacent to the periphery of the source region 4. ) Contact region 5 is formed (FIG. 2). Here, the impurity concentration of the contact region 5 is set to be relatively higher than the impurity concentration of the well region 3. Examples of the p-type impurity in the well region 3 include boron (B) and aluminum (Al). After the ion implantation, the resist is removed.

Next, the SiC wafer 6 is annealed in an inert gas atmosphere such as argon (Ar). Thereby, the implanted ions are electrically activated, and crystal defects formed by the ion implantation are recovered. Further, a gate oxide film 7 made of silicon dioxide (SiO ₂ ) is formed on one surface of the SiC wafer 6, specifically, on the SiC wafer 6 on the ion-implanted side by a thermal oxidation method (FIG. 3). The gate oxide film 7 formed in this step is a thermal oxide film.

  Next, after a polysilicon film is formed on the gate oxide film 7 by a chemical vapor deposition method, unnecessary portions are removed by a wet etching method or a dry etching method such as RIE using the resist as a mask, and the gate electrode 8 is removed. (FIG. 4).

  Next, an interlayer insulating film 9 is formed on the surfaces of the gate oxide film 7 and the gate electrode 8 (FIG. 5). Next, using the resist as a mask, the interlayer insulating film 9 and the gate oxide film 7 are removed by wet etching or dry etching such as RIE so that the contact region 5 and part of the source region 4 are exposed ( FIG. 6). Thereafter, the resist is removed.

  Next, a conductive film is formed on the contact region 5 and the source region 4 exposed by removing the interlayer insulating film 9 and the gate oxide film 7 by physical vapor deposition such as sputtering. Thereafter, unnecessary portions of the conductive film formed on the surface of the interlayer insulating film 9 are removed by a wet etching method or a dry etching method such as reactive ion etching using the resist as a mask, so that the contact region 5 and a part of the conductive film are partially removed. A source electrode 10 is formed on the source region 4 (FIG. 7). Next, the drain electrode 11 is formed on the back surface of the semiconductor substrate 1.

  Next, a barrier metal 13 and a Cu electrode 12 are formed on the fabricated element structure (FIG. 8). 1 to 8 show a unit cell which is the minimum basic element structure of a MOSFET, but in FIGS. 9 to 21, a group of a plurality of unit cells is referred to as an element structure portion 20, and a barrier formed on the element structure portion 20. The end portions of the metal 13 and the Cu electrode 12 will be described in detail. In the present specification, a configuration including the SiC wafer 6 and the element structure portion 20, that is, a configuration in which the barrier metal 13 and the Cu electrode 12 are removed from the MOSFET illustrated in FIG. 8 is also referred to as a silicon carbide semiconductor element.

  First, a barrier metal 13 for preventing Cu diffusion is deposited on the surface of the element structure 20 (FIG. 9). Examples of the material of the barrier metal 13 include metals such as W, Ta, Mo, Nb, Ir, Ru, Hf, Rh, V, Zr, Pt, Ti, and Pd, TiN, TiSiN, WN, WSiN, TaN, TaSiN, A nitride such as ZrN, AlN, BN, CrN, or NbN, or a metal carbide such as TaC, TiC, WC, or NbC can be used. A laminated structure of any combination of these, for example, Ti / TiN, Ti / TaN, Ta / TaN, etc. can also be used. The laminated structure may be three or more layers. Vapor deposition, sputtering, CVD, etc. can be used for film formation. The thickness of the barrier metal 13 is 10 to 500 nm.

  Next, a Cu underlayer 12a serving as a base for forming a Cu plating film is deposited on the barrier metal 13 by vapor deposition, sputtering, CVD, or the like (FIG. 9). The thickness of the Cu underlayer 12a is, for example, 100 to 1000 nm. Then, by applying, exposing, and developing the resist 21, the resist 21 is patterned and formed on a portion where the Cu plating on the Cu underlayer 12a is not desired to be formed (FIG. 10). It is desirable that the thickness of the resist 21 be larger than the thickness of the plating Cu to be deposited later. The shape of the edge portion of the resist 21 is such that a part of the width other than the resist bottom is narrower than the resist bottom. Specifically, this shape is realized by adjusting the energy and focus during exposure. In FIG. 10, the resist 21 is formed so that the width of the resist top is the narrowest. However, as long as the width of a part other than the resist bottom is narrower than the resist bottom, like the resist 22 shown in FIG. The middle part (resist middle) may be the narrowest. In the resists 21 and 22, the difference between the narrowest portion and the width of the resist bottom is the difference between the Cu electrode 12 along the final barrier metal 13 surface and the element structure portion 20 formed on the SiC wafer 6. The length can be increased, and the time when Cu diffuses through the interface of the barrier metal 13 and reaches the element structure portion 20 to affect the device characteristics, that is, the device life due to Cu diffusion can be increased accordingly. Here, the difference between the narrowest portion of the resists 21 and 22 and the width of the resist bottom is at least 10 times the thickness of the barrier metal 13. In this way, a practically desirable effect can be obtained with respect to the effect of preventing Cu from diffusing into the element structure portion 20.

  Next, Cu is plated to form a Cu plating layer 12b (FIG. 12). Since the Cu plating layer 12b is formed in a portion where the resist 21 is not present, the shape that follows the shape of the side wall of the resist 21, that is, the upper portion is wider than the bottom portion. The thickness of the Cu plating layer 12b is, for example, 5 to 100 μm. In FIG. 12, since the resist 21 has the narrowest shape at the top, the Cu plating layer 12b has the widest shape at the top. However, when the middle part of the resist 21 has the narrowest shape as shown in FIG. 13, the Cu plating layer 12b has the widest shape at the middle part. In any case, the Cu plating layer 12b only needs to have a portion wider than the bottom portion above the bottom portion. From the viewpoint of heat dissipation of the power device and assembly, the thickness of the Cu plating layer 12b is set to 5 μm or more. By forming the Cu-based electrode with a thick film, it is possible to make the heat distribution in the chip uniform by increasing the heat capacity. Moreover, the rise in the temperature at the time of a short circuit can be suppressed and a withstand amount improves. At the time of wire bonding, a strong force is applied because a wire having a large diameter is hit. If the electrode is thin, the device is damaged and the element is destroyed. Since a Cu wire bond requires more force than an Al wire bond, a thicker film is required than an Al-based electrode. In such a case, the present invention is useful for preventing Cu from diffusing into the element structure portion 20.

  Next, the resist 21 and the Cu underlayer 12a are removed (FIGS. 14 and 15). For removing the resist 21, an organic solvent or oxygen plasma treatment is used, and for removing the Cu underlayer 12a, an acid solution such as sulfuric acid, hydrochloric acid, acetic acid, phosphoric acid, nitric acid, hydrofluoric acid or a mixed solution thereof, or a peroxidized solution thereof. What added hydrogen can be used.

  Next, the barrier metal 13 is anisotropically etched vertically using the Cu plating layer 12b as a mask (FIG. 16). An example of the conditions for etching by RIE using TiN as the barrier metal 13 is chlorine (Cl2) gas as the process gas and the pressure is 0.1 Pa. Here, an example of etching TiN has been shown, but as long as anisotropic etching is performed vertically, other conditions may be used for pressure, gas type, and the like. In addition, when a barrier metal 13 other than TiN is used, an appropriate gas type may be selected. Although an example using RIE for anisotropic etching has been shown, Ar ion milling, sputter etching, or the like can also be used.

  Thus, the Cu electrode 12 composed of the Cu underlayer 12a and the Cu plating layer 12b was formed. The barrier metal 13 is formed wider than the width of the Cu electrode 12 in contact with the barrier metal 13. Thereby, the length between the Cu electrode 12 along the barrier metal 13 surface and the element structure part 20 formed on the SiC wafer 6 can be lengthened, and a high Cu diffusion preventing effect can be obtained. Moreover, since it can suppress that the big stress which generate | occur | produces at the edge of the barrier metal 13 applies to Cu film edge used as the starting point of Cu film peeling, Cu film peeling can be suppressed. This is particularly effective when using a thick Cu electrode exceeding 5 μm, where film peeling is likely to occur. Thereby, a highly reliable power semiconductor can be realized.

  In this embodiment, the SiC-MOSFET is described as an example of the power semiconductor element. However, the present invention can be applied to an SBD, JFET, IGBT, or PN diode to form a highly reliable Cu electrode. .

<A-3. Effect>
The silicon carbide semiconductor device of the present embodiment includes a silicon carbide semiconductor element (SiC wafer 6, element structure portion 20), a barrier metal 13 formed on element structure portion 20, a barrier metal 13, and a barrier. An end portion of the contact surface with the metal 13 is provided with a Cu electrode 12 that is recessed from the end portion of the barrier metal 13. Further, the Cu electrode 12 has a shape in which at least a part of the width other than the bottom contacting the barrier metal 13 is wider than the width of the bottom. By selectively forming the Cu electrode 12 on the barrier metal 13, the distance between the Cu electrode 12 and the element structure portion 20 along the surface of the barrier metal 13 can be reduced between the end of the barrier metal 13 and the Cu electrode 12. Since it becomes longer by the positional deviation amount of the end portion, the diffusion of Cu to the element structure portion 20 along the surface of the barrier metal 13 is suppressed. Further, the stress at the end of the barrier metal 13 is prevented from being applied to the end of the Cu electrode 12, and the film peeling of the Cu electrode 12 is suppressed.

  According to said structure, even if the thickness of Cu electrode 12 is 5 micrometers or more, it is possible to suppress film peeling of Cu electrode 12.

  Further, by making the distance from the end of the barrier metal 13 to the end of the Cu electrode 12 in contact with the barrier metal 13 more than 10 times the thickness of the barrier metal 13, the diffusion of Cu into the silicon carbide semiconductor element can be improved. The suppressing effect is particularly exerted.

  The method for manufacturing a silicon carbide semiconductor device of the present embodiment includes (a) a step of forming a barrier metal 13 on a silicon carbide semiconductor element (SiC wafer 6, element structure portion 20), and (b) on the barrier metal 13. A step of forming a Cu electrode 12 in which the end of the contact surface with the barrier metal 13 recedes from the end of the barrier metal 13, and (c) the barrier metal 13 is vertically anisotropic with the Cu electrode 12 as a mask. The step (b) is a step of forming the Cu electrode 12 such that at least a part of the width other than the bottom contacting the barrier metal 13 is wider than the width of the bottom. The barrier metal 13 is formed wider than the width at which the Cu electrode 12 contacts the barrier metal 13. Therefore, the distance between Cu and the element structure portion 20 along the surface of the barrier metal 13 can be increased, and a high Cu diffusion preventing effect can be obtained. Moreover, since the stress generated at the end of the barrier metal 13 is prevented from being applied to the end of the Cu electrode 12, film peeling of the Cu electrode 12 is suppressed.

  Step (b) is a step of forming the Cu electrode 12 with a thickness of 5 μm or more. When the Cu electrode 12 is formed as thick as 5 μm or more, the film stress increases and there is a concern about peeling of the Cu electrode 12. However, the positions of the end of the Cu electrode 12 and the end of the barrier metal 13 are different. Is prevented from being applied to the end of the Cu electrode 12, and film peeling can be suppressed.

  Step (b) includes (b1) a step of depositing a Cu underlayer on the barrier metal by sputtering, vapor deposition, or CVD, and (b2) selective electroplating using a resist on the Cu underlayer. A step of forming a Cu plating layer with (b3) a portion of the Cu underlayer on which the Cu plating layer is not formed, sulfuric acid, hydrochloric acid, acetic acid, phosphoric acid, nitric acid, hydrofluoric acid, or a mixed solution thereof, or a peroxide thereof Removing with a solution to which hydrogen has been added. Through the above steps, it is possible to form a Cu electrode 12 having a desired shape.

  The step (b2) is a step of forming the Cu plating layer 12b by using the resists 21 and 22 whose widths at least a part other than the bottom are narrower than the width of the bottom. As a result, at least a part of the width other than the bottom of the Cu plating layer 12b is formed wider than the width of the bottom, so that the width of the barrier metal 13 is reduced to the Cu electrode 12 by etching in the vertical direction using the Cu plating layer 12b. A structure wider than the width in contact with can be formed.

<B. Second Embodiment>
<B-1. Manufacturing process>
In the first embodiment, Cu film formation is performed using a resist having a shape that is narrower than the resist bottom, and the width of the upper part of the Cu is wider than that of the Cu bottom. Silicon carbide semiconductor device in which the length between Cu along the barrier metal surface and the element structure formed on the substrate is increased by anisotropic etching perpendicularly using this Cu film as a mask, and a method for manufacturing the same Explained. The silicon carbide semiconductor device in the first embodiment can obtain an effect of preventing Cu diffusion and can prevent peeling of the Cu film. In the second embodiment, a silicon carbide semiconductor device capable of obtaining a high Cu diffusion preventing effect and preventing Cu film peeling and a manufacturing method thereof will be described. Since steps other than the Cu and barrier metal forming step are the same as those described in the first embodiment with reference to FIGS. 1 to 8, description thereof is omitted here.

  First, a barrier metal for preventing Cu diffusion is deposited on the substrate surface as in the first embodiment (FIG. 9). As barrier metals, metals such as W, Ta, Mo, Nb, Ir, Ru, Hf, Rh, V, Zr, Pt, Ti, Pd, TiN, TiSiN, WN, WSiN, TaN, TaSiN, ZrN, AlN, A nitride such as BN, CrN, or NbN, or a metal carbide such as TaC, TiC, WC, or NbC can be used. A laminated structure of any combination of these, for example, Ti / TiN, Ti / TaN, Ta / TaN, etc. can also be used. The laminated structure may be three or more layers. Vapor deposition, sputtering, CVD, etc. can be used for film formation. The thickness of the barrier metal is 10 to 500 nm. On this barrier metal, Cu as a base for Cu plating film formation is deposited by vapor deposition, sputtering, CVD or the like (FIG. 9). The thickness is, for example, 100 to 1000 nm.

  Next, by applying, exposing and developing a resist 22, a resist 23 is patterned and formed on a portion where the Cu plating layer 12b on the Cu underlayer 12a is not desired to be formed (FIG. 17). The resist 22 is different from the first embodiment in that the thickness of the resist 22 is made thinner than the thickness of the Cu plating layer 12b deposited later. By forming the Cu plating layer 12b using the resist 22 as a mask, the Cu plating layer 12b is formed beyond the resist 22 as shown in FIG. 12b also grows in the lateral direction and has a wide shape.

  Next, the resist 22 and Cu12a are removed (FIGS. 19 and 20). An organic solvent or oxygen plasma treatment was used to remove the resist 22, and an acid solution such as sulfuric acid, hydrochloric acid, acetic acid, phosphoric acid, nitric acid or hydrofluoric acid or a mixed solution thereof was added to the Cu12a, or hydrogen peroxide was added thereto. Things can be used.

  Next, the barrier metal 13 is anisotropically etched vertically using the Cu plating layer 12b as a mask (FIG. 21). Here, as an example of conditions for etching by RIE using TiN as the barrier metal, chlorine (Cl 2) gas is used as the process gas and the pressure is set to 0.1 Pa. Here, an example in which TiN is etched is shown, but the pressure, gas type, and the like are not limited to these conditions as long as anisotropic etching can be performed vertically. In addition, when a barrier metal 13 other than TiN is used, an appropriate gas type may be selected. Although an example using RIE for anisotropic etching has been shown, Ar ion milling, sputter etching, or the like can also be used.

  According to this embodiment, it is possible to obtain a barrier metal / Cu wiring structure having a barrier metal 13 wider than the width of the Cu electrode in contact with the barrier metal 13. The width of the barrier metal 13 is the same as the width of the upper part of the Cu plating layer 12b formed beyond the resist 22. The length between the Cu electrode 12 and the element structure 20 formed on the SiC wafer 6 along the final barrier metal 13 interface by the difference between the upper width of the Cu plating layer 12b and the opening width of the resist 22 The time during which Cu diffuses at the interface of the barrier metal 13 to reach the element structure 20 and affects the device characteristics, that is, the device life due to Cu diffusion can be extended accordingly. When the Cu plating layer 12b is formed beyond the resist 22, the lateral growth rate of the Cu plating layer 12b is equal to the vertical growth rate, so the difference between the upper width of the Cu plating layer 12b and the resist opening width is , Equal to the difference between the thickness of the Cu plating layer 12 b and the thickness of the resist 22. Here, the difference between the thickness of the resist 22 and the thickness of the Cu plating layer 12 b is at least 10 times the thickness of the barrier metal 13.

  Thereby, the length between the Cu electrode 12 along the barrier metal 13 interface and the element structure part 20 formed on the SiC wafer 6 can be lengthened, and a high Cu diffusion preventing effect can be obtained. Moreover, since it can suppress that the big stress which generate | occur | produces at the edge of the barrier metal 13 applies to the edge of the Cu electrode 12 used as the starting point of Cu film peeling, Cu film peeling can be suppressed.

<B-2. Effect>
In the method for manufacturing the silicon carbide semiconductor device described in the second embodiment, Cu plating layer 12b thicker than the thickness of resist 23 is selectively formed by electroplating using resist 23 on Cu underlayer 12a. Therefore, since the Cu plating layer 12b is formed so that the width of the portion exceeding the thickness of the resist 23 is wider than the width of the bottom portion, the width of the barrier metal becomes the Cu electrode 12 by etching in the vertical direction using the Cu plating layer 12b. A structure wider than the width in contact with can be formed.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 semiconductor substrate, 2 SiC layer, 3 well region, 4 source region, 5 contact region, 6 SiC wafer, 7 gate oxide film, 8 gate electrode, 9 interlayer insulation film, 10 source electrode, 11 drain electrode, 12 Cu electrode, 12a Cu underlayer, 12b Cu plating layer, 13 barrier metal, 20 element structure, 21-23 resist.

Claims (7)

A silicon carbide semiconductor element;
A barrier metal formed on the silicon carbide semiconductor element;
A Cu electrode formed on the barrier metal and having a thickness of 5 μm or more, wherein an end portion of a contact surface with the barrier metal recedes from an end portion of the barrier metal;
Silicon carbide semiconductor device. The Cu electrode has a shape in which the width of at least a portion other than the bottom contacting the barrier metal is wider than the width of the bottom.
The silicon carbide semiconductor device according to claim 1. The distance from the end of the barrier metal to the end of the Cu electrode in contact with the barrier metal is 10 times or more the thickness of the barrier metal.
The silicon carbide semiconductor device according to claim 1 or 2. (A) forming a barrier metal on the silicon carbide semiconductor element;
  (B) forming, on the barrier metal, a Cu electrode having a thickness of 5 μm or more, wherein an end of a contact surface with the barrier metal is recessed from an end of the barrier metal;
  (C) a step of anisotropically etching the barrier metal vertically using the Cu electrode as a mask,
  The step (b) is a step of forming the Cu electrode such that at least a part of the width other than the bottom contacting the barrier metal is wider than the width of the bottom.
A method for manufacturing a silicon carbide semiconductor device. The step (b)
  (B1) a step of depositing a Cu underlayer on the barrier metal by any one of sputtering, vapor deposition, and CVD;
  (B2) a step of selectively forming a Cu plating layer by electroplating using a resist on the Cu underlayer;
  (B3) The Cu underlayer where the Cu plating layer is not formed is removed with sulfuric acid, hydrochloric acid, acetic acid, phosphoric acid, nitric acid, hydrofluoric acid, or a mixed solution thereof, or a solution obtained by adding hydrogen peroxide to these. A process,
A method for manufacturing a silicon carbide semiconductor device according to claim 4. The step (b2) is a step of forming the Cu plating layer using the resist in which at least part of the width other than the bottom is narrower than the width of the bottom.
A method for manufacturing a silicon carbide semiconductor device according to claim 5. The step (b2) is a step of forming the Cu plating layer thicker than the thickness of the resist.
A method for manufacturing a silicon carbide semiconductor device according to claim 5.

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