JP5888917B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory that stores one data in a plurality of memory cells.

  2. Description of the Related Art A semiconductor memory in which 1-bit data is stored in a pair of memory cells is known as a semiconductor memory for achieving high speed and low power consumption (see, for example, Patent Document 1 or 2). In this semiconductor memory, a pair of memory cells is composed of two transistors, and a common word line is connected to the gate ends of these transistors, and a bit line is individually connected to each drain end.

  When data is written to the semiconductor memory, a predetermined amount of charge is accumulated only in one or the other of the pair of memory cells based on the data value (0 or 1). In order to reach a predetermined amount of charge to be accumulated in the memory cell, data is read at each stage while increasing the write voltage applied to the memory cell in stages, and the read current value is predetermined. A verify process for determining whether or not the threshold value has fallen below the threshold value is executed. At this time, if the read current value falls below a predetermined threshold value, it is determined that the writing to the memory cell is completed. When data is read from the pair of memory cells after the data writing is completed, a current is sent from the memory cell in which no charge is stored, while a current is sent from the memory cell in which a predetermined amount of charge is stored. Not sent out. Therefore, when reading data from such a semiconductor memory, a difference between read signals read from the pair of memory cells via the respective bit lines is obtained by a differential amplifier circuit, and the data is read based on the difference. The data value (0 or 1) is determined.

  In addition, when data written in a memory cell is rewritten, the data is once erased and then newly written. Note that the state in which data is erased is a charge accumulation state in which current is sent from a pair of transistors at the time of reading.

  Accordingly, when data is written by the above-described verify process in a state where this data is erased, substantially the same current is sent from the pair of memory cells at the initial stage of the verify process. The circuit becomes unstable.

  Therefore, originally, in the state where the data is erased, it must be determined that the data value “1” is written, but since the differential amplifier circuit becomes unstable, the determination result is incorrect. There was a problem that would occur.

Japanese Patent No. 2537264 JP 2008-117510 A

  An object of the present invention is to provide a semiconductor memory capable of improving the accuracy of read data.

  A semiconductor memory according to the present invention is a semiconductor memory having a plurality of memory cells each including a first memory element connected to a first bit line and a second memory element connected to a second bit line, Temporary read data is obtained by determining a value of data read from the memory cell based on a difference between read signals read from one of the memory cells via the first and second bit lines. And obtaining an erase state detection signal indicating whether one of the memory cells is in a data erase state by detecting whether a current flows through both the first and second bit lines. An erasure state detecting unit that outputs the provisional read data as read data from one of the memory cells when the erase state detection signal does not indicate the data erase state. State detection signal has a read data output unit for outputting the data value of the fixed as the read data to indicate the data erased state.

  In the present invention, when determining the value of the read data based on the difference between the read signals read from the memory cell via the first and second bit lines, current is applied to both the first and second bit lines. If it is flowing, it is determined that the memory cell is in the data erasure state, and at this time, a fixed data value is output as read data regardless of the data value determined as described above. Therefore, it is possible to accurately generate a read data signal indicating the state even from a memory cell in a data erase state in which current is sent to both the first and second bit lines during reading.

1 is a block diagram showing a configuration of a semiconductor memory according to the present invention. It is a circuit diagram which shows the internal structure of the memory cell TC. 3 is a time chart showing a precharge operation by a precharge unit 7; 4 is a circuit diagram showing an internal configuration of a data determination unit 8. FIG. 3 is a circuit diagram showing an internal configuration of an erase state detection unit 9. FIG. 2 is a time chart showing a read operation in the semiconductor memory shown in FIG. 1.

  The semiconductor memory according to the present invention has a provisional read data value (RD) based on a difference between read signals read from the memory cell (TC) via the first and second bit lines (BL, BLC). Whether or not the memory cell is in the data erasure state is detected by detecting whether or not a current flows through both the first and second bit lines (9). At this time, if the memory cell is not in the data erased state, the above-described provisional read data value is output as it is as read data, while if the memory cell is in the data erased state, a fixed data value is read out. Output as data (10).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory according to the present invention.

In FIG. 1, in the memory cell block 1, word lines WL _{0 to} WL _n and a pair of bit lines (BL ₀ , BLV ₀ ) to (BL _m , BLV _m ) are formed so as to cross each other. Memory cells TC _{00 to} TC _mn are arranged at the intersection of a pair of bit lines and word lines.

  FIG. 2 is a circuit diagram showing an example of the internal configuration of each memory cell TC.

  In FIG. 2, each of the memory cells TC is an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and includes a transistor Q1 as a first memory element and a transistor Q2 as a second memory element. Composed. A ground potential GND is applied to the source terminals of the transistors Q1 and Q2, and a word line WL is connected to each gate terminal. A bit line BL as a first bit line is connected to the drain terminal of the transistor Q1, and a bit line BLV as a second bit line is connected to the drain terminal of the transistor Q2. Here, if the bit line BLV is set to the ground potential while supplying the word line selection signal of the logic level 1 to the word line WL, and the write voltage is applied to the bit line BL, only Q1 of the transistors Q1 and Q2 is applied. The transistor is turned on, and charges are accumulated on the transistor Q1 side. When a word line selection signal of logic level 1 is supplied to the word line WL in such a state, only one of the transistors Q1 and Q2 in which no charge is accumulated, that is, the transistor Q2 is turned on and current is sent to the bit line BLV. The Note that the transistor Q1 in which charge is accumulated is turned off, and no current is sent to the bit line BL. This state is a state in which logic level 1 data is written. On the other hand, when the bit line BL is set to the ground potential while supplying the word line selection signal of the logic level 1 to the word line WL and the write voltage is applied to the bit line BLV, only Q2 of the transistors Q1 and Q2 is turned on. The charge is accumulated on the transistor Q2 side. When a word line selection signal of logic level 1 is supplied to the word line WL in such a state, only one of the transistors Q1 and Q2 in which no charge is accumulated, that is, the transistor Q1 is turned on and current is sent to the bit line BL. The Note that the transistor Q2 in which charge is accumulated is turned off, and no current is sent to the bit line BLV. This state is a state in which data of logic level 0 is written.

  When the input buffer 2 is supplied with data to be written (hereinafter referred to as write data) and address data indicating the write address as input data signals, the input buffer 2 captures and stores them. At this time, the input buffer unit 2 supplies the address data to the row decoder 3 and also supplies the address data and write data to the column decoder 4. In addition, when the address data indicating the address of the data to be read is supplied as the input data signal, the input buffer unit 2 temporarily captures and stores the address data, and stores the address data in the row decoder 3 and the column decoder 4. To supply.

The row decoder 3 has a logic level 1 word line selection signal for setting the word line WL to the selected state for the word line WL corresponding to the address indicated by the address data among the word lines WL _{0 to} WL _n. Is supplied to each of the other word lines WL, and a logic level 0 word line selection signal for setting the word line WL to a non-selected state is supplied.

The column decoder 4 selects a pair of bit lines BL and BLV corresponding to the address indicated by the address data from each of the pair of bit lines (BL ₀ , BLV ₀ ) to (BL _m , BLV _m ). A power bit line selection signal is supplied to the bit line selection unit 6.

  Each time the address data as described above is supplied or the value of the address data changes, the control unit 5 performs a pulse-like precharge signal preb that becomes a logic level 0 for the precharge period PT as shown in FIG. Is supplied to the precharge unit 7. Further, the controller 5 immediately after the application of the pulse by the precharge signal preb, that is, in response to the transition of the precharge signal preb from the logic level 0 state to the logic level 1 state as shown in FIG. An activation signal senn that transitions from a state to a logic level 0 state is generated and supplied to the data determination unit 8.

The bit line selection unit 6 selects a pair of bit lines BL and BLV indicated by the bit line selection signal from the pair of bit lines (BL ₀ , BLV ₀ ) to (BL _m , BLV _m ), The selected bit lines BL and BLV are electrically connected to the pair of output lines IO and IOV. As a result, the bit line selection unit 6 supplies read signals read on the selected bit lines BL and BLV to the data determination unit 8 and the erased state detection unit 9 via the pair of output lines IO and IOV, respectively. .

  The precharge unit 7 includes two transistors 71 and 72 each of which is a p-channel MOSFET. A power supply voltage VDD is applied to the source terminals of the transistors 71 and 72, and a precharge signal preb is supplied to each gate terminal. The drain terminal of the transistor 71 is connected to the output line IO, and the drain terminal of the transistor 72 is connected to the output line IOV. The transistors 71 and 72 are turned on only while the precharge signal preb is in the logic level 0 state, and perform a so-called precharge operation in which the power supply voltage VDD is applied to the pair of output lines IO and IOV. By such a precharge operation, the voltages on the output lines IO and IOV rise to the level corresponding to the logic level 1 as shown in FIG.

  The data determination unit 8 is activated in response to the logic level 0 activation signal senn supplied from the control unit 5 and is read on each of the output lines IO and IOV via the bit lines BL and BLV. A difference signal (described later) indicating the difference between the signals is generated. Then, the data determination unit 8 supplies the binarized version of the difference signal to the OR gate 10 as provisional read data RD indicating the provisional value of the data read from the memory cell TC. In short, the data determination unit 8 determines the provisional value of the data read from the memory cell TC based on the difference between the read signals read from the memory cell TC via the bit lines BL and BLV. Then, provisional read data RD indicating the provisional value is generated.

  FIG. 4 is a circuit diagram illustrating an example of an internal configuration of the data determination unit 8.

  As shown in FIG. 4, the data determination unit 8 includes a differential amplifier circuit composed of transistors 81 to 85, which are p-channel MOSFETs, and transistors 86 to 88, each of which is an n-channel MOSFET. It comprises a buffer 89 as a circuit.

  In FIG. 4, the power supply voltage VDD is applied to the source terminal of the transistor 81, and the activation signal senn is supplied to the gate terminal. The source terminal of each of the transistors 82 and 83 is connected to the drain terminal of the transistor 81. An output line IOV is connected to the gate terminal of the transistor 82, and the source terminal of the transistor 84 and the drain terminal of the transistor 86 are connected to the drain terminal thereof. An output line IO is connected to the gate terminal of the transistor 83, and the source terminals of the transistors 85 and 86 are connected to the drain terminal thereof. The activation signal senn is supplied to the gate terminal of the transistor 86. The activation signal senn is supplied to the gate terminal of the transistor 84, and the drain terminal of the transistor 87 and the gate terminal of the transistor 88 are connected to the drain terminal, respectively. The activation signal senn is supplied to the gate terminal of the transistor 85, and the drain terminal of the transistor 88 and the gate terminal of the transistor 87 are connected to the drain terminal, respectively. A ground potential GND is applied to the source terminals of the transistors 87 and 88. The connection point between the drain terminals of the transistors 85 and 88 is connected to the input terminal of the buffer 89. The buffer 89 supplies the OR gate 10 with data indicating the logical level 1 when the signal level at the connection point is higher than the binary determination threshold value, and indicating the logical level 0 when the signal level is lower than the binary determination threshold value.

  In the configuration of the data determination unit 8 as shown in FIG. 4, the transistor 81 is set to the off state and the transistor 86 is set to the on state while the activation signal senn is in the logic level 1 state. As a result, the supply of the power supply voltage VDD to the transistors 82 and 83 is interrupted, and the drain terminals of the transistors 82 and 83 are short-circuited, so that the data determination unit 8 is deactivated. Thereafter, when the activation signal senn transitions from the logic level 1 to the logic level 0, the supply of the power supply voltage VDD to the transistors 82 and 83 is started via the transistor 81, and the drain terminals of the transistors 82 and 83 are also connected. The short circuit state between each other is released. As a result, a signal obtained by amplifying the difference between the level of the signal supplied to the gate terminal of the transistor 82 via the output line IOV and the level of the signal supplied to the gate terminal of the transistor 83 via the output line IO is a difference. The signal S is sent from the connection point between the drain terminals of the transistors 85 and 88. The buffer 89 supplies the binary signal of the difference signal S to the OR gate 10 as temporary read data RD. For example, when data is read from a memory cell TC in which data of logic level 1 is written, current is sent only to the BLV side of the pair of bit lines BL and BLV, and a signal corresponding to this send current is sent. The data is supplied to the data determination unit 8 via the output line IOV. At this time, a current is sent to the output line IOV and no current is sent from the output line IO, and there is a difference in positive polarity between the signal level on the output line IOV and the signal level on the output line IO. Arise. Therefore, the data determination unit 8 generates provisional read data RD corresponding to the logic level 1 having a level higher than the binary determination threshold based on the difference value between the two. On the other hand, when data is read from the memory cell TC in which data of logic level 0 is written, current is sent only to the BL side of the pair of bit lines BL and BLV, and a signal corresponding to this send current is generated. The data is supplied to the data determination unit 8 via the output line IO. At this time, since current is sent to the output line IO and no current is sent from the output line IOV, the signal level on the output line IOV and the signal level on the output line IO are negative. Differences occur. Therefore, the data determination unit 8 generates provisional read data RD corresponding to the logical level 0 having a level lower than the binary determination threshold based on the difference value between the two.

  The erase state detection unit 9 changes the state of the current flowing through each of the pair of output lines IO and IOV only while the activation signal senn is in the state of logic level 0 indicating that the operation of the data determination unit 8 is activated. Based on this, it is detected whether or not the memory cell TC is in the data erase state. Then, the erase state detection unit 9 supplies an erase state detection signal edn indicating whether or not the memory cell TC is in the data erase state to the OR gate 10. Note that the data erase state of the memory cell TC means that after the data is written to the memory cell TC, the data is erased, so that the amounts of residual charges in the transistors Q1 and Q2 of the memory cell TC are both 0. It is in a state. At this time, when data is read from the memory cell TC in the data erased state, current is sent to both the pair of output lines IO and IOV. On the other hand, when data is read from the memory cell TC in which data is written, current is sent only to one of the pair of output lines IO and IOV.

  FIG. 5 is a circuit diagram showing an example of the internal configuration of the erased state detecting unit 9.

  As shown in FIG. 5, the erase state detection unit 9 includes transistors 91 to 93 that are p-channel MOSFETs, transistors 94 and 95 that are n-channel MOSFETs, and an AND gate 96, respectively.

  In FIG. 5, the power supply voltage VDD is applied to the source terminal of the transistor 91, and the activation signal senn is supplied to the gate terminal. The source terminal of each of the transistors 92 and 93 is connected to the drain terminal of the transistor 91. An IOV of the pair of output lines IO and IOV is connected to the gate terminal of the transistor 92, and the drain terminal of the transistor 94 is connected to its drain terminal. The ground potential GND is applied to the source terminal of the transistor 94, and the activation signal senn is supplied to the gate terminal. The gate terminal of the transistor 93 is connected to IO of the pair of output lines IO and IOV, and the drain terminal of the transistor 93 is connected to the drain terminal of the transistor 95. The ground potential GND is applied to the source terminal of the transistor 95, and the activation signal senn is supplied to the gate terminal. A connection point connecting the drain terminals of the transistors 93 and 95 and the first input terminal of the AND gate 96 are connected. A connection point connecting the drain terminals of the transistors 92 and 94 and the second input terminal of the AND gate 96 are connected. The AND gate 96 calculates the logical product of the signal supplied to the first input terminal and the signal supplied to the second input terminal, and indicates whether the memory cell TC is in the erased state based on the logical product result. The erase state detection signal edn is supplied to the OR gate 10.

  In the configuration of the erase state detection unit 9 as shown in FIG. 5, both the transistors 94 and 95 are set to the on state while the activation signal senn is in the logic level 1 state. As a result, both the first and second input terminals of the AND gate 96 are supplied with a logic level 0 signal corresponding to the ground potential GND. Accordingly, during this time, the AND gate 96 generates the erased state detection signal edn indicating the logic level 1. Thereafter, when the activation signal senn transitions from the logic level 1 to the logic level 0, supply of the power supply voltage VDD to the transistors 92 and 93 via the transistor 91 is started. Thus, the transistor 93 supplies the detection signal e corresponding to the current flowing into the output line IO via the bit line BL to the first input terminal of the AND gate 96. At this time, if a current flows on the output line IO, a detection signal e having a level corresponding to the logic level 1 is sent to the drain terminal of the transistor 93 accordingly. On the other hand, when no current flows on the output line IO, the detection signal e having the ground potential GND corresponding to the logic level 0 is sent to the drain terminal of the transistor 93. During this time, the transistor 92 supplies the detection signal en corresponding to the current flowing through the output line IOV to the second input terminal of the AND gate 96. At this time, if a current is flowing on the output line IOV, the detection signal en having a level corresponding to the logic level 1 is sent to the drain terminal of the transistor 92 accordingly. On the other hand, when no current flows on the output line IOV, the detection signal en having the ground potential GND corresponding to the logic level 0 is sent to the drain terminal of the transistor 92. Therefore, in the AND gate 96, the memory cell TC is in the erased state only when both the detection signals e and en are at the logic level 1, that is, when both currents are flowing through the pair of output lines IO and IOV. An erasure state detection signal edn of logic level 1 indicating this is generated and supplied to the OR gate 10. Note that when one of the detection signals e and en is at a logic level 0, that is, when the memory cell TC is in a data-written state, the AND gate 96 does not indicate that the memory cell TC is in an erased state. Is generated and supplied to the OR gate 10.

  The OR gate 10 obtains a logical sum of the provisional read data RD supplied from the data determination unit 8 and the erase state detection signal edn supplied from the erase state detection unit 9, and reads the logical sum result from the memory cell TC. It is sent out as a read data signal indicating the value of the output data. That is, the OR gate 10 outputs the provisional read data RD as it is as a read data signal when the erase state detection signal edn of logic level 0 indicating that the memory cell TC is not in the erase state is supplied. On the other hand, when the erase state detection signal edn of logic level 1 indicating that the memory cell TC is in the erase state is supplied, the OR gate 10 receives the erase state detection signal edn regardless of the value of the provisional read data RD. A read data signal having a logic level 1 indicated by is output.

  Next, regarding the data read operation by the semiconductor memory described above, an operation in the case where data is read from the memory cell TC in which data is written, and an operation in the case where data is read from the memory cell TC in the data erase state This will be explained separately.

  FIG. 6A is a time chart showing an operation when data is read from the memory cell TC in which data is written.

  As shown in FIG. 6A, in response to the logic level 0 precharge signal preb supplied from the control unit 5, first, the precharge unit 7 precharges the pair of output lines IO and IOV individually. By such a precharge operation, the voltages on the output lines IO and IOV are raised to a level corresponding to the logic level 1 as shown in FIG. As the voltages of the output lines IO and IOV rise, the voltages on the pair of bit lines BL and BLV selected by the bit line selection unit 6 also rise. Next, the data determination unit 8 starts its operation in response to the logic level 0 activation signal senn supplied from the control unit 5. When a word line selection signal of logic level 1 is supplied from the row decoder 3, a current is applied only to one bit line side of the pair of bit lines BL and BLV connected to the memory cell TC to which data has been written. Is sent out. FIG. 6A shows a state in which current is sent only to the BL side of the bit lines BL and BLV, and the voltage on the bit line BL and the output line IO is gradually reduced accordingly. . At this time, since no current is sent to the bit line BLV, the voltages on the bit line BLV and the output line IOV do not change as shown in FIG. As described above, since no current is sent to the IOV of the pair of output lines OV and IOV, the erase state detection unit 9 detects the erase state of logic level 0 as shown in FIG. The signal edn is supplied to the OR gate 10. As a result, the OR gate 10 sends the provisional read data RD supplied from the data determination unit 8 as it is as a read data signal indicating the data read from the memory cell TC.

  On the other hand, FIG. 6B is a time chart showing an operation when data is read from the memory cell TC in the data erase state.

  As shown in FIG. 6B, in response to the logic level 0 precharge signal preb supplied from the control unit 5, the precharge unit 7 first precharges the pair of output lines IO and IOV individually. By such a precharge operation, the voltages on the output lines IO and IOV are raised to a level corresponding to the logic level 1 as shown in FIG. As the voltages of the output lines IO and IOV rise, the voltages on the pair of bit lines BL and BLV selected by the bit line selector 6 also rise. Next, the data determination unit 8 starts its operation in response to the logic level 0 activation signal senn supplied from the control unit 5. When a word line selection signal of logic level 1 is supplied from the row decoder 3, current is sent to both the pair of bit lines BL and BLV connected to the memory cell TC in the data erased state. Accordingly, the voltages on the bit lines BL and BLV and the output lines IO and IOV gradually decrease. As described above, since the current is sent to both the pair of output lines OV and IOV, the output result of the data determination unit 8, that is, the provisional read data RD may become unstable. Here, the erasure state detection unit 9 supplies the OR gate 10 with an erasure state detection signal edn for transitioning from the logic level 0 to the logic level 1 as shown in FIG. As a result, the OR gate 10 outputs a read data signal indicating a logic level 1 as read data regardless of the provisional read data RD supplied from the data determination unit 8.

  As described above, in the semiconductor memory shown in FIG. 1, the erasure state detection unit 9 outputs whether or not current is sent to the bit lines BL and BLV connected to the memory cell TC to be read. By detecting via the lines IO and IOV, it is detected whether or not the memory cell TC is in the data erase state. Here, when it is detected that the memory cell TC is not in the data erasure state, that is, when data is written in the memory cell TC, the data determination unit 8 is operated by the OR gate 10 as the read data output unit. The provisional read data RD obtained in the above is output as a read data signal as it is. On the other hand, when the memory cell TC is in the data erase state, a read data signal indicating a predetermined fixed data value (for example, logic level 1) is output regardless of the provisional read data RD.

  Therefore, a correct read data signal can be stably output even from a memory cell in a data erase state in which current is sent to a pair of bit lines (BL, BLV) connected to the memory cell at the time of reading. Can be generated.

DESCRIPTION OF SYMBOLS 1 Memory cell block 5 Control part 7 Precharge part 8 Data determination part 9 Erase state detection part 10 OR gate

Claims (3)

A semiconductor memory having a plurality of memory cells each including a first memory element connected to a first bit line and a second memory element connected to a second bit line,
Temporary read data is obtained by determining a value of data read from the memory cell based on a difference between read signals read from one of the memory cells via the first and second bit lines. A data determination unit to obtain;
An erasure state detection unit for generating an erasure state detection signal indicating whether one of the memory cells is in a data erasure state by detecting whether or not a current flows through both the first and second bit lines; ,
When the erase state detection signal does not indicate the data erase state, the provisional read data is output as read data from one of the memory cells, while the erase state detection signal indicates the data erase state. And a read data output unit for outputting a fixed data value as the read data. The data determination unit is configured to amplify a difference between read signals read through the first and second bit lines to obtain a differential signal, and to binarize the differential signal A binarization circuit that uses the provisional read data as
It said read data output unit, a semiconductor memory according to claim 1, wherein prior Ki暫 a constant read data calculated logical sum of the erase state detection signal the logical sum result and outputs as the read data. A precharge unit for precharging each of the first and second bit lines over a precharge period;
The erase state detection unit is in an inactive state during the precharge period, transitions to an active state immediately after the end of the precharge period, and whether or not a current flows through the first and second bit lines. 3. The semiconductor memory according to claim 1, wherein a detection operation is started.

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