JP5883276B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device having improved phase tracking characteristics.

  When switching an AC motor driven by a commercial power supply to drive at the output of the inverter device quickly, or by configuring a redundant system using a plurality of inverter devices, a drive system with a highly reliable power conversion device When one inverter device fails, when switching to a stand-by inverter device quickly, it is necessary to switch the output frequency and the phase of the inverter device to coincide with the idling AC motor quickly.

  For this purpose, it is common to use a so-called PLL (Phase Locked Loop) circuit to control the output frequency and phase of the inverter device to match the idling AC motor. In terms of accuracy and response speed, the performance was not necessarily sufficient. In order to prevent overcurrent when switching operation is performed in a state where phase matching is insufficient, a proposal has been made to correct the phase based on the polarity of the effective current when switching operation is performed (for example, Patent Documents). 1).

Japanese Patent Laid-Open No. 7-123782 (page 3-4, FIG. 1)

  According to the technique disclosed in Patent Document 1, it is possible to some extent to take measures when a phase detection error of the PLL circuit or a phase error due to operation delay occurs. However, there is a problem that an overcurrent at the time of switching operation is instantaneously generated, and that there is a time delay until the control is performed and the inverter device is stably operated.

  The present invention has been made in view of the above, and an object of the present invention is to provide a power conversion device capable of quickly correcting a phase error of a PLL circuit and suppressing occurrence of an overcurrent during switching operation.

In order to achieve the above object, the power converter of the present invention has an AC power supply as an input, outputs a desired frequency / voltage to drive an AC motor, and includes an output switch and a voltage detector on the output side. When switching from an inverter device, a bypass switch provided to drive the AC motor directly from an AC power source, and operating the AC motor by closing the bypass switch to the operation by the inverter device, PLL control means for matching the internal phase of the inverter device following the phase of the AC motor, and the PLL control means,
Phase difference detection means for detecting the phase difference from the detection voltage of the voltage detector and the internal phase of the inverter device, and the phase difference is proportionally integrated and controlled by the PI controller and corrected via the first switch. PI control means for outputting as a pre-internal phase, a phase correction means for outputting the output of the phase difference detection means via a second switch, and adding this to the pre-correction internal phase as an internal phase; and A delay that delays a predetermined time by receiving an integration initial value setting means that differentiates the output of the phase difference detection means and sets the integration initial value of the PI control means via a switch, and a signal input to the output switch. The input of the first switch is switched from 0 to the output of the PI controller and the input of the second switch is shortened by a PI control operation start signal which is the output of the delay means. The return zero again after switching from between 0 to the phase difference detecting the phase difference detecting means, it is characterized in that and was to closing the switch of the output of the integration initial value setting means.

  According to the present invention, it is possible to provide a power converter that can quickly correct the phase error of the PLL circuit and suppress the occurrence of overcurrent during switching operation.

The circuit block diagram of the power converter device which concerns on Example 1 of this invention. The operation | movement time chart of the PLL control circuit of the power converter device which concerns on Example 1 of this invention. The circuit block diagram of the power converter device which concerns on Example 2 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  Hereinafter, the power converter concerning Example 1 of the present invention is explained with reference to FIG.1 and FIG.2. FIG. 1 is a circuit configuration diagram of a power conversion apparatus according to Embodiment 1 of the present invention.

  An AC voltage is supplied from the AC power source to the inverter device 2 via the input circuit breaker 1. The inverter device 2 converts the commercial frequency AC voltage into an AC voltage having a desired frequency and voltage, and drives the AC motor 3. Further, a bypass switch 25 is provided to drive the AC motor 3 directly from the output of the input circuit breaker 1. The bypass switch 25 is used, for example, when the AC motor 3 is directly driven by an AC power source in order to reduce the loss of the inverter device 2 after the AC motor 3 is accelerated to the rated speed by the inverter device 2.

  The inverter device 2 has an input switch 21 on the input side, and an appropriate voltage is supplied to the power converter 22 via an AC reactor, a transformer, or the like as necessary. Although the illustration of the internal circuit of the power converter 22 is omitted, normally, the alternating current is converted into direct current by a converter, and then the direct current is again converted into alternating current for driving the alternating current motor 3 by an inverter. The inverter is composed of a plurality of switching elements, and these switching elements are on / off controlled by a switching command from a control unit (not shown). For this control, so-called PWM control is often employed. The AC motor 3 is driven via the output switch 24.

  The output of the power converter 22 (the output of the inverter device 2) is detected by the voltage detector 23 and given to the PLL control circuit 4. The PLL control circuit 4 has a function of quickly matching the frequency and phase of the inverter of the power converter 22 and the AC motor 3 when switching quickly from direct driving of the AC motor 3 by the bypass switch 25 to driving by the inverter device 2 again. Have. The configuration of this internal circuit will be described below.

  The voltages of the U, V, and W phases detected by the voltage detector 23 are given to the orthogonal coordinate converter 41. The orthogonal coordinate converter 41 is given an internal phase of an inverter of the power converter 22 to be described later. When the phase difference between the AC motor 3 and the internal phase is Δθ, the orthogonal coordinate converter 41 has VsinΔθ and VcosΔθ. Can be requested. Here, V is the voltage amplitude of each phase. By inputting the Vsin Δθ and Vcos Δθ to the phase difference detector 42, Δθ can be obtained. That is, the phase difference detector 42 obtains tan Δθ from Vsin Δθ and Vcos Δθ, and obtains Δθ from Δθ = arctan (tan Δθ).

  The phase difference Δθ obtained by the phase difference detector 42 is given to the PI control circuit 43. The output of the PI control circuit 43 is given to the integration circuit 45 via the switch 44, and the added value of the output of the integration circuit 45 and the correction output of the switch 46 described later becomes the aforementioned internal phase. The phase difference Δθ that is the input of the PI control circuit 43 is differentiated by the differential calculator 47, and the speed of the AC motor 3 is obtained. The speed of the AC motor 3 is configured to be given as an integral initial value of the PI control circuit 43 via the switch 48.

  When switching from the direct drive state of the AC motor 3 to the drive by the inverter device 2 again, the output switch 24 is turned on with the bypass switch 25 opened and the AC motor 3 free-running. The transient disturbance at the time of the input signal is avoided by the delay circuit 49, and the operation of the PI control circuit 43 is started by the output of the delay circuit 49. Before this operation is started, the input “0” is selected for both the switch 44 and the switch 46, and therefore the internal phase is 0. From this state, the switch 44 is switched to the output side of the PI control circuit 43 and the switch 46 is switched to the phase difference Δθ side which is the input of the PI control circuit 43 by the PI control operation start signal which is the output of the delay circuit 49. Note that the switching unit 46 is switched via the one-shot circuit 50. That is, in the case of digital control, correction is performed only once, and is immediately returned to zero. Further, as described above, the switch 48 is closed by the PI control operation start signal, and the current speed of the AC motor 3 is given as the integral initial value of the PI control circuit 43.

  Detailed operation in the above configuration will be described with reference to an operation time chart of the PLL control circuit in FIG. FIG. 2A shows the time transition of the U-phase voltage and the internal phase from the PI control start time. FIG. 2B shows an enlarged time transition of the internal phase from the PI control start time. That is, FIG. 2B corresponds to the region P in FIG. The operation will be described below with reference to FIG.

  The phase transition indicated by the solid line is the actual voltage phase transition of the U-phase voltage. On the other hand, the phase transition indicated by the broken line is the transition of the internal phase when the normal PLL circuit operation is performed. In the normal PLL circuit operation, when the PI control operation start signal of the PLL circuit in FIG. 1 is given, only the switch 44 is switched to the output side of the PI control circuit 43, the switch 46 remains at 0 and is opened and closed. The device 48 also means an operation without closing. Here, the internal phase at the start of the PI control operation is set to 90 ° for convenience. At this time, the switch 46 immediately switches to the phase difference Δθ that is the input of the PI control circuit 43. Then, the internal phase shifts by the phase difference Δθ as shown in the figure, reaches the point A in FIG. 2B, and instantaneously matches the voltage phase of the solid line. In the state where the switch 48 is not closed, the internal phase due to the operation of the PI control circuit 43 tends to be the phase transition of the one-dot chain line in the figure and toward the point B. However, the switch 48 is closed simultaneously with the switching operation of the switches 44 and 46, and the integral initial value of the PI control circuit 43 coincides with the speed of the AC motor 3, so that the slope of the phase change is corrected, and as a result This coincides with the change in voltage phase. When digital control is performed, it takes at least one sampling time for the differentiator 47 to detect the phase change, that is, the speed. Therefore, if the minimum sampling time is one digital control, the inverter of the power converter 22 and the AC motor It is possible to match the phase of 3 and the frequency. In the case where speed fluctuation during one sampling period becomes a problem in only one sampling period, the acceleration may be detected by detecting the speed for two sampling periods, and the speed corrected by the acceleration may be obtained.

  As described above, according to the first embodiment, when the gate block of the inverter of the power converter 22 is released and energized immediately after the start of the PI control operation, the phase error of the PLL circuit is quickly corrected and the switching operation is performed. It is possible to suppress the occurrence of overcurrent. Here, the time immediately after the start of the PI control operation may be, for example, after one sampling time or two sampling times. Further, the output of the inverter device 2 may be started after confirming that the phase difference Δθ at this time is within a predetermined value.

  FIG. 3 is a circuit configuration diagram of the power conversion apparatus according to the second embodiment of the present invention. In each part of the second embodiment, the same parts as those of the power conversion apparatus according to the first embodiment of the present invention shown in FIG. The second embodiment is different from the first embodiment in that a regular inverter device 2A is provided instead of the bypass switch 25, and a configuration in which the inverter device 2 is replaced with a standby inverter device 2B.

  Since both the common inverter device 2A and the standby inverter device 2B have the same internal configuration as the inverter device 2 described in the first embodiment, the description thereof is omitted.

  The PLL control circuit 4 in the second embodiment has the same configuration as that of the first embodiment, and its operation is also the same. Therefore, also in the case of the second embodiment, if the gate block of the inverter of the power converter 22 is released and energized immediately after the start of the PI control operation, the phase error of the PLL circuit is quickly corrected to generate an overcurrent during switching operation. Can be suppressed.

  Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the second embodiment, the switching from the normal inverter device to the standby inverter device has been described. However, this is not always the case when the normal inverter device fails. This switching may be performed for maintenance of the regular inverter device. Further, if a PLL control circuit that operates with the output of the voltage detector 23A of the normal inverter device is prepared, the reverse switching from the standby inverter device to the normal inverter device is also possible. Therefore, the second embodiment means that the drive switching between the two inverter devices is possible regardless of the terms of normal use and standby.

DESCRIPTION OF SYMBOLS 1 Input circuit breaker 2 Inverter apparatus 2A Regular inverter apparatus 2B Standby inverter apparatus 3 AC motor 4 PLL control circuit 21, 21A, 21B Input switch 22, 22A, 22B Power converter 23, 23A, 23B Voltage detector 24, 24A, 24B Output switch 25 Bypass switch 41 Cartesian coordinate converter 42 Phase difference calculator 43 PI control circuit 44 Switcher 45 Integrator 46 Switcher 47 Differential calculator 48 Switch 49 Delay circuit 50 One-shot circuit

Claims (6)

An AC power source is input, an AC motor is driven by outputting a desired frequency / voltage, an inverter device having an output switch and a voltage detector on the output side;
A bypass switch provided to drive the AC motor directly from an AC power source;
PLL control means for following the phase of the AC motor and matching the internal phase of the inverter device when switching from the state in which the bypass switch is closed and the AC motor is operated to the operation by the inverter device Comprising
The PLL control means includes:
A phase difference detection means for detecting a phase difference from the detection voltage of the voltage detector and the internal phase of the inverter device;
PI control means for proportionally integrating and controlling this phase difference by a PI controller, and outputting it as an uncorrected internal phase via a first switch;
Phase correction means for outputting the output of the phase difference detection means through a second switch, and adding this to the internal phase before correction as an internal phase;
An integration initial value setting means for differentiating the output of the phase difference detection means and setting the integration initial value of the PI control means via a switch;
Delay means for receiving a signal input by the output switch and delaying the signal for a predetermined time;
By the PI control operation start signal that is the output of the delay means,
Switching the input of the first switch from 0 to the output of the PI controller;
And, after switching the input of the second switch from the short period 0 to the phase difference detected by the phase difference detecting means, it returns to 0 again.
In addition, the power conversion device characterized in that the output switch of the integral initial value setting means is closed. AC power source is input, a desired frequency / voltage is output to drive an AC motor, and a normal inverter device provided with an output switch and a voltage detector on the output side;
A standby inverter device having an AC power supply as an input, outputting a desired frequency / voltage to drive an AC motor, and having an output switch and a voltage detector on the output side;
PLL control means for following the phase of the AC motor and matching the internal phase of the standby inverter device when switching from the state in which the AC motor is operated by the common inverter device to the operation by the standby inverter device Equipped,
The PLL control means includes:
A phase difference detection means for detecting a phase difference from a detection voltage of the voltage detector of the standby inverter device and an internal phase of the standby inverter device;
PI control means for proportionally integrating and controlling this phase difference by a PI controller, and outputting it as an uncorrected internal phase via a first switch;
Phase correction means for outputting the output of the phase difference detection means through a second switch, and adding this to the internal phase before correction as an internal phase;
An integration initial value setting means for differentiating the output of the phase difference detection means and setting the integration initial value of the PI control means via a switch;
Delay means for receiving a signal input by the output switch and delaying the signal for a predetermined time;
By the PI control operation start signal that is the output of the delay means,
Switching the input of the first switch from 0 to the output of the PI controller;
And, after switching the input of the second switch from the short period 0 to the phase difference detected by the phase difference detecting means, it returns to 0 again.
In addition, the power conversion device characterized in that the output switch of the integral initial value setting means is closed.   2. The power converter according to claim 1, wherein the output of the inverter device is started after a predetermined time after a PI control operation start signal which is an output of the delay means is issued.   3. The power conversion apparatus according to claim 2, wherein after the PI control operation start signal, which is an output of the delay means, is issued, the output of the standby inverter device is started after a predetermined time.   The output of the inverter device is started if the phase difference is equal to or less than a predetermined value after a predetermined time after a PI control operation start signal as an output of the delay means is issued. Item 4. The power conversion device according to Item 1.   After the PI control operation start signal, which is the output of the delay means, is issued, the output of the standby inverter device is started if the phase difference is equal to or less than a predetermined value after a predetermined time. The power conversion device according to claim 2.

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