JP5866044B1 - Light emitting device manufacturing method and light emitting device - Google Patents

Abstract

Manufacturing of a light-emitting element capable of suppressing a change in crystal quality of a group III nitride semiconductor due to a pitch of irregularities even when a substrate having concaves or convexes formed with a period whose surface forms a diffractive surface is used. A method and a light emitting device manufactured by the manufacturing method are provided. A semiconductor multilayer portion including a light emitting layer and made of a group III nitride semiconductor is formed on a substrate surface on which convex portions are formed with a period larger than an optical wavelength of light emitted from the light emitting layer and smaller than a coherent length of light. A method of manufacturing a light emitting device to be grown, wherein a buffer layer 10 is formed along a substrate surface including a convex portion 2C, and at least one convex portion is included on the buffer layer so as to have a facet surface and are separated from each other. The crystal nuclei 11 are grown, and the planarization layer 12 is grown on the buffer layer in which a plurality of crystal nuclei are formed. [Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a light emitting element and a light emitting element.

  A group III nitride semiconductor formed on the surface of the sapphire substrate and including a light emitting layer, and light emitted from the light emitting layer formed on the surface side of the sapphire substrate is incident and is larger than the optical wavelength of the light and smaller than the coherent length of the light. There is known an LED element comprising a diffractive surface in which concave or convex portions are formed at a period, and an Al reflective film that is formed on the back side of the substrate and reflects light diffracted by the diffractive surface and re-enters the diffractive surface (See Patent Document 1). In this LED element, the light transmitted by the diffraction action is re-incident on the diffraction surface, and the light is transmitted again using the diffraction action on the diffraction surface, so that the light can be extracted outside the element in a plurality of modes.

International Publication No. 2011/0276779

  By the way, if concave or convex portions are formed on the substrate surface with a period that forms a diffractive surface, the crystal quality of the group III nitride semiconductor greatly changes due to the pitch of the concave and convex portions when a group III nitride semiconductor is grown on the surface thereafter. Turned out to be.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to use a substrate having a concave or convex portion formed at a period in which the surface forms a diffractive surface, even if the substrate has a concave and convex pitch III. It is an object of the present invention to provide a method for manufacturing a light emitting device capable of suppressing a change in crystal quality of a group nitride semiconductor and a light emitting device manufactured by this manufacturing method.

  In order to achieve the above object, in the present invention, a semiconductor stacked portion including a light emitting layer and made of a group III nitride semiconductor has a convex portion with a period larger than the optical wavelength of light emitted from the light emitting layer and smaller than the coherent length of the light. A method of manufacturing a light emitting device for growing on a substrate surface on which a buffer layer is formed, wherein a buffer layer is formed along the substrate surface including the convex portion, and at least one convex portion is included on the buffer layer. There is provided a method for manufacturing a light emitting device, in which a plurality of crystal nuclei having facet surfaces and spaced apart from each other are grown, and a planarization layer is grown on a buffer layer in which the plurality of crystal nuclei are formed.

  In the method for manufacturing a light emitting element, the plurality of crystal nuclei may have a flat upper surface.

  In the method for manufacturing a light emitting element, the buffer layer may be formed by sputtering using AlN as a target.

  In the method for manufacturing a light emitting element, the plurality of crystal nuclei may be grown to a height of 900 nm or less.

  Further, in the present invention, the semiconductor light-emitting element is manufactured by the method for manufacturing a light-emitting element, and the semiconductor stacked unit includes the buffer layer, the plurality of crystal nuclei, and the planarization layer, The oxygen concentration may be higher than that of the planarizing layer.

  According to the present invention, even if a substrate in which concave portions or convex portions are formed with a period whose surface forms a diffractive surface is used, a change in crystal quality of the group III nitride semiconductor due to the pitch of the concave and convex portions can be suppressed.

FIG. 1 is a schematic cross-sectional view of an LED element showing an embodiment of the present invention. 2A and 2B are explanatory diagrams showing the diffraction action of light at the interface having different refractive indexes, where FIG. 2A shows a state of reflection at the interface, and FIG. 2B shows a state of transmission through the interface. 3A and 3B show a sapphire substrate, in which FIG. 3A is a schematic perspective view, FIG. 3B is a schematic explanatory view showing an AA cross section, and FIG. 3C is a schematic enlarged explanatory view. FIG. 4 is an example of a chart showing a change in growth temperature in the early stage of growth of the group III nitride semiconductor. FIG. 5 is a schematic plan view showing the formation state of crystal nuclei. FIG. 6 is an SEM image of the sample body A. FIG. 7 is an SEM image of the sample body B. FIG. 8 is an SEM image of the sample body C. FIG. 9 is an SEM image of the sample body D. FIG. 10 is an SEM image of the sample body E. FIG. 11 is an SEM image of the sample body F. FIG. 12 is a graph showing the relationship between the pitch of convex portions and the threading dislocation density for a sample body in which crystal nuclei are formed and a sample body in which crystal nuclei are not formed. FIG. 13 is an example of a chart showing a change in growth temperature in the early stage of growth of a group III nitride semiconductor when no crystal nucleus is formed. FIG. 14 is a graph showing the relationship between crystal nucleus height and threading dislocation density. FIG. 15 is a schematic cross-sectional view of an LED element showing a modification.

FIG. 1 is a schematic cross-sectional view of an LED element showing an embodiment of the present invention.
As shown in FIG. 1, the LED element 1 includes a sapphire substrate 2 on which a semiconductor stacked portion 19 made of a group III nitride semiconductor layer is formed. The LED element 1 is a flip chip type, and light is mainly extracted from the back side of the sapphire substrate 2. The semiconductor stacked unit 19 includes a buffer layer 10, a planarizing layer 12, an n-type GaN layer 13, a light emitting layer 14, an electron blocking layer 16, and a p-type GaN layer 18 in this order from the sapphire substrate 2 side. A plurality of crystal nuclei 11 are formed on the buffer layer 10. A p-side electrode 27 is formed on the p-type GaN layer 18, and an n-side electrode 28 is formed on the n-type GaN layer 12.

  As shown in FIG. 1, the buffer layer 10 is formed on the surface of the sapphire substrate 2 and is made of AlN. The buffer layer 10 is formed along the substrate surface including the convex portion 2 c, and the unevenness of the sapphire substrate 2 is inherited on the surface of the buffer layer 10. In the present embodiment, the buffer layer 10 is formed by a MOCVD (Metal Organic Chemical Vapor Deposition) method, but a sputtering method can also be used. When the sputtering method is used, it is preferable that the sputtering is not reactive reactive with Al as a target but AlN as a target. In reactive sputtering using Al as a target, since the temperature is relatively high, migration may adversely affect the coating state of the substrate surface. Moreover, since it is necessary to make it high temperature and a high vacuum, an apparatus becomes complicated and manufacturing cost will increase. In contrast, sputtering with AlN as a target does not cause these problems. The planarization layer 12 is formed on the buffer layer 10 and is made of undoped u-GaN. The n-type GaN layer 13 as the first conductivity type layer is formed on the planarization layer 12 and is composed of n-GaN. The light emitting layer 14 is formed on the n-type GaN layer 13 and is made of GalnN / GaN, and emits blue light by injection of electrons and holes. Here, blue light refers to light having a peak wavelength of 430 nm or more and 480 nm or less, for example. In the present embodiment, the peak wavelength of light emission of the light emitting layer 14 is 450 nm.

  The electron blocking layer 16 is formed on the light emitting layer 14 and is made of p-AIGaN. The p-type GaN layer 18 as the second conductivity type layer is formed on the electron block layer 16 and is made of p-GaN. The buffer layer 10 to the p-type GaN layer 18 are formed by epitaxial growth of a group III nitride semiconductor. In addition, when a voltage is applied to the first conductive type layer and the second conductive type layer at least including the first conductive type layer, the active layer, and the second conductive type layer, the active layer is formed by recombination of electrons and holes. The layer structure of the semiconductor layer is arbitrary as long as it emits light.

  The surface of the sapphire substrate 2 forms a vertical moth-eye surface 2a, and the surface of the sapphire substrate 2 is formed with a flat portion 2b and a plurality of convex portions 2c periodically formed on the flat portion 2b. In the present embodiment, the semiconductor laminated portion 19 is formed without a gap around each convex portion 2c. The shape of each convex portion 2c may be a truncated cone shape such as a cone or a polygonal pyramid, or a truncated cone shape such as a truncated cone or a truncated polygonal truncated cone. Each convex portion 2 c is designed to diffract light emitted from the light emitting layer 14. In the present embodiment, the light verticalizing action can be obtained by the convex portions 2c arranged periodically. Here, the light verticalizing action means that the light intensity distribution is reflected and transmitted with respect to the interface between the sapphire substrate 2 and the semiconductor laminated portion 19 rather than before the light is incident on the vertical moth-eye surface. It is biased in the vertical direction.

2A and 2B are explanatory diagrams showing the diffraction action of light at the interface having different refractive indexes, where FIG. 2A shows a state of reflection at the interface, and FIG. 2B shows a state of transmission through the interface.
Here, from the Bragg diffraction condition, when light is reflected at the interface, the condition that the reflection angle θ _ref should satisfy with respect to the incident angle θ _in is:
d · n1 · (sin θ _in −sin θ _ref ) = m · λ (1)
It is. Here, n1 is the refractive index of the medium on the incident side, λ is the wavelength of the incident light, and m is an integer. When light is incident on the sapphire substrate 2 from the semiconductor laminated portion 19, n1 is the refractive index of the group III nitride semiconductor. As shown in FIG. 2A, light incident on the interface is reflected at a reflection angle θ _ref that satisfies the above equation (1).

On the other hand, from the Bragg diffraction condition, when light is transmitted at the interface, the condition that the transmission angle θ _out should satisfy with respect to the incident angle θ _in is:
d · (n1 · sin θ _in −n2 · sin θ _out ) = m ′ · λ (2)
It is. Here, n2 is the refractive index of the medium on the exit side, and m ′ is an integer. For example, when light is incident on the sapphire substrate 2 from the semiconductor stacked portion 19, n2 is the refractive index of sapphire. As shown in FIG. 2B, light incident on the interface is transmitted at a transmission angle θ _out that satisfies the above equation (2).

In order for the reflection angle θ _ref and the transmission angle θ _out that satisfy the diffraction conditions of the above expressions (1) and (2) to exist, the period of the surface of the sapphire substrate 2 is the optical wavelength inside the element (λ / n1) and (λ / n2) must be larger. Therefore, the surface of the sapphire substrate 2 is set to have a period longer than (λ / n1) or (λ / n2) so that diffracted light exists.

As shown in FIG. 1, the p-side electrode 27 includes a diffusion electrode 21 formed on the p-type GaN layer 18, a dielectric multilayer film 22 formed in a predetermined region on the diffusion electrode 21, and a dielectric multilayer film. 22 and a metal electrode 23 formed on the substrate 22. The diffusion electrode 21 is formed on the entire surface of the p-type GaN layer 18 and is made of a transparent material such as ITO (Indium Tin Oxide). The dielectric multilayer film 22 is configured by repeating a plurality of pairs of a first material and a second material having different refractive indexes. For example, the dielectric multilayer film 22 may be made of ZrO ₂ (refractive index: 2.18) as the first material, SiO ₂ (refractive index: 1.46) as the second material, and five pairs. The dielectric multilayer film 22 may be formed using a material different from ZrO ₂ and SiO _2. For example, AlN (refractive index: 2.18), Nb ₂ O ₃ (refractive index: 2.4), Ta ₂ O ₃ (refractive index: 2.35) or the like may be used. The metal electrode 23 covers the dielectric multilayer film 22 and is made of a metal material such as Al. The metal electrode 23 is electrically connected to the diffusion electrode 21 through a via hole 22 a formed in the dielectric multilayer film 22.

The n-side electrode 28 is formed on the exposed n-type GaN layer 12 by etching the n-type GaN layer 12 from the p-type GaN layer 18. The n-side electrode 28 includes a diffusion electrode 24 formed on the n-type GaN layer 12, a dielectric multilayer film 25 formed in a predetermined region on the diffusion electrode 24, and a metal formed on the dielectric multilayer film 25. Electrode 26. The diffusion electrode 24 is formed on the entire surface of the n-type GaN layer 12 and is made of a transparent material such as ITO (Indium Tin Oxide). The dielectric multilayer film 25 is configured by repeating a plurality of pairs of a first material and a second material having different refractive indexes. In the dielectric multilayer film 25, for example, the first material can be ZrO ₂ (refractive index: 2.18), the second material can be SiO ₂ (refractive index: 1.46), and the number of pairs can be five. The dielectric multilayer film 25 may be formed using a material different from ZrO ₂ and SiO ₂ , for example, AlN (refractive index: 2.18), Nb ₂ O ₃ (refractive index: 2.4), Ta ₂ O ₃ (refractive index: 2.35) or the like may be used. The metal electrode 26 covers the dielectric multilayer film 25 and is made of a metal material such as Al. The metal electrode 26 is electrically connected to the diffusion electrode 24 through a via hole 25 a formed in the dielectric multilayer film 25.

  In the LED element 1, the p-side electrode 27 and the n-side electrode 28 form a reflecting portion. The p-side electrode 27 and the n-side electrode 28 each have a higher reflectance as the angle is closer to the vertical. In addition to the light emitted directly from the light-emitting layer 14 and directly incident on the reflecting portion, the light reflected by the vertical moth-eye surface 2a of the sapphire substrate 2 and changed in angle toward the perpendicular to the interface is incident. . That is, the intensity distribution of light incident on the reflecting portion is biased toward the vertical as compared with the case where the surface of the sapphire substrate 2 is a flat surface.

Next, the sapphire substrate 2 will be described in detail with reference to FIG. 3A and 3B show a sapphire substrate, in which FIG. 3A is a schematic perspective view, FIG. 3B is a schematic explanatory view showing an AA cross section, and FIG. 3C is a schematic enlarged explanatory view.
As shown in FIG. 3A, the verticalized moth-eye surface 2a has an intersection of virtual triangular lattices at a predetermined period so that the center of each convex portion 2c is the position of the apex of the regular triangle in plan view. It is formed in alignment with. In addition, you may arrange | position so that the center of each convex part 2c may become the position of the vertex of an isosceles triangle. The period of each convex part 2c is larger than the optical wavelength of the light emitted from the light emitting layer 14, and smaller than the coherent length of the said light. In addition, the period here means the distance of the peak position of the height in the adjacent convex part 2c. The optical wavelength means a value obtained by dividing the actual wavelength by the refractive index. Furthermore, the coherent length corresponds to a distance until the periodic vibrations of the waves cancel each other and the coherence disappears due to the difference in the individual wavelengths of the photon group having a predetermined spectral width. The coherent length lc is approximately lc = (λ ² / Δλ), where λ is the wavelength of light and Δλ is the half width of the light. Here, the period of each convex part 2c is 1 time or more of the optical wavelength, and the diffractive action gradually works effectively for incident light having an angle greater than or equal to the critical angle, and is 2 of the optical wavelength of the light emitted from the light emitting layer 14. If it is larger than twice, the number of transmission modes and reflection modes is sufficiently increased, which is preferable. Moreover, it is preferable that the period of each convex part 2c is below half of the coherent length of the light emitted from the light emitting layer 14.

  In the present embodiment, the length of one side of the regular triangle forming the virtual triangular lattice is 460 nm, and the period of each convex portion 2c is 460 nm. Since the wavelength of light emitted from the light emitting layer 14 is 450 nm and the refractive index of the group III nitride semiconductor layer is 2.4, the optical wavelength is 187.5 nm. Moreover, since the half width of the light emitted from the light emitting layer 14 is 27 nm, the coherent length of the light is 7500 nm. That is, the period of the verticalized moth-eye surface 2a is greater than twice the optical wavelength of the light emitting layer 14 and less than or equal to half the coherent length.

  In the present embodiment, as shown in FIG. 3C, each convex portion 2c of the verticalized moth-eye surface 2a includes a side surface 2d extending upward from the flat portion 2b, and a center side of the convex portion 2c from the upper end of the side surface 2d. And a curved upper surface 2f formed continuously with the curved portion 2e. As will be described later, the curved portion 2e is formed by dropping the corners by wet etching of the convex portion 2c before the curved portion 2e formed with the corners formed by the meeting portions of the side surface 2d and the upper surface 2f. Note that wet etching may be performed until the flat upper surface 2f disappears and the entire upper side of the convex portion 2c becomes the curved portion 2e. In this embodiment, specifically, each convex part 2c has a base end diameter of 380 nm and a height of 400 nm. The vertical moth-eye surface 2a of the sapphire substrate 2 is a flat portion 2b in addition to the convex portions 2c.

  Here, a method for producing the sapphire substrate 2 for the LED element 1 will be described. The manufacturing method of this embodiment includes a mask layer forming step, a resist film forming step, a pattern forming step, a residual film removing step, a resist alteration step, a mask layer etching step, and a sapphire substrate etching step, A mask layer removing step and a curved portion forming step.

First, a sapphire substrate 2 before processing is prepared, and the sapphire substrate 2 is cleaned with a predetermined cleaning liquid prior to etching. Next, a mask layer is formed on the sapphire substrate 2 (mask layer forming step). In this embodiment, the mask layer has a SiO ₂ layer on the sapphire substrate 2 and a Ni layer on the SiO ₂ layer. The mask layer may be a single layer. The mask layer is formed by a sputtering method, a vacuum evaporation method, a CVD method, or the like.

  Next, a resist film is formed on the mask layer (resist film forming step). In the present embodiment, a thermoplastic resin such as an epoxy resin is used as the resist film, and the resist film is formed to have a uniform thickness by a spin coating method. As the resist film, for example, a photocurable resin can be used in addition to the thermoplastic resin.

  Then, the resist film is heated and softened together with the sapphire substrate 2, and the resist film is pressed with a mold. An uneven structure is formed on the contact surface of the mold, and the resist film is deformed along the uneven structure. Thereafter, the resist film is cooled and cured together with the sapphire substrate 2 while keeping the pressed state. Then, by separating the mold from the resist film, the concavo-convex structure is transferred to the resist film (pattern forming step). In this embodiment, the period of the concavo-convex structure is 460 nm. Moreover, in this embodiment, the diameter of the convex part of an uneven structure is 100 nm or more and 300 nm or less, for example, 230 nm. Further, the height of the convex portion is not less than 100 nm and not more than 300 nm, for example, 250 nm. In this state, a residual film is formed in the concave portion of the resist film.

The sapphire substrate 2 on which the resist film is formed as described above is attached to the substrate holding table of the plasma etching apparatus. Then, for example, the residual film is removed by plasma ashing to expose the mask layer (residual film removing step). In the present embodiment, O ₂ gas is used as a processing gas for plasma ashing.

  Then, the resist film is exposed to plasma under alteration conditions to alter the resist film and increase the etching selectivity (resist alteration step). In the present embodiment, Ar gas is used as a process gas for modifying the resist film. In the present embodiment, as the condition for alteration, the bias output of the power source in the plasma etching apparatus for inducing plasma to the sapphire substrate 2 side is set to be lower than the etching condition described later.

  Thereafter, the mask layer is etched using the resist film exposed to plasma under the etching conditions and having a high etching selectivity (mask layer etching process). In this embodiment, Ar gas is used as a processing gas for etching the resist film. Thereby, a pattern is formed in the mask layer.

  Here, the processing gas, the antenna output, the bias output, and the like can be changed as appropriate for the alteration condition and the etching condition, but it is preferable to change the bias output using the same processing gas as in this embodiment. In addition to lowering the bias output relative to the etching conditions, the resist can be cured even if the antenna output is reduced or the gas flow rate is reduced.

Next, the sapphire substrate 2 is etched using the mask layer as a mask (sapphire substrate etching step). In this embodiment, etching is performed with the resist film remaining on the mask layer. Further, plasma etching is performed using a chlorine-based gas such as BCl ₃ gas as a processing gas.

  Then, as the etching proceeds, the verticalized moth-eye surface 2 a is formed on the sapphire substrate 2. In the present embodiment, the height of the concavo-convex structure of the verticalized moth-eye surface 2a is 400 nm. Note that the height of the concavo-convex structure can be made larger than 400 nm. Here, if the height of the concavo-convex structure is relatively shallow, for example, 300 nm, the etching may be finished with the resist film remaining.

Thereafter, the mask layer remaining on the sapphire substrate 2 is removed using a predetermined stripping solution (mask layer removing step). In this embodiment, after removing the Ni layer by using high-temperature nitric acid, the SiO ₂ layer is removed by using hydrofluoric acid. Even if the resist film remains on the mask layer, it can be removed together with the Ni layer with high-temperature nitric acid. However, if the residual amount of the resist film is large, the resist film is previously removed by O ₂ ashing. It is preferable.

  Then, the curved portion is formed by removing the corners of the convex portion 2c by wet etching (curved portion forming step). Here, the etching solution is arbitrary, but for example, a phosphoric acid aqueous solution heated to about 170 ° C., so-called “hot phosphoric acid” can be used. In addition, this bending part formation process can be abbreviate | omitted suitably. Through the above steps, the sapphire substrate 2 having a concavo-convex structure on the surface is produced.

  A semiconductor laminated portion 19 made of a group III nitride semiconductor is epitaxially grown on the vertical moth-eye surface 2a of the sapphire substrate 2 manufactured as described above (semiconductor forming step), and the p-side electrode 27 and the n-side electrode 28 are formed. (Electrode forming step). Then, the LED element 1 is manufactured by dividing into a plurality of LED elements 1 by dicing.

  In the present embodiment, the group III in the order of the buffer layer 10, the planarization layer 12, the n-type GaN layer 13, the light emitting layer 14, the electron block layer 16, and the p-type GaN layer 18 on the vertical moth-eye surface 2 a of the sapphire substrate 2. Nitride semiconductors are stacked. When recesses or projections are formed on the surface of the sapphire substrate 2 with a period forming a diffractive surface, the crystal quality of the group III nitride semiconductor is increased by the pitch of the recesses and projections when the planarizing layer 12 and subsequent layers are grown under normal growth conditions. Has been found to change significantly. Prior to the growth of the planarization layer 12, the inventors of the present application grow a plurality of crystal nuclei 11 under growth conditions that promote facet formation rather than the growth conditions of the planarization layer 12, thereby increasing the pitch of the unevenness. It was found that the change in crystal quality of group III nitride semiconductors can be suppressed.

  Specifically, as shown in FIG. 1, each crystal nucleus 11 has a plurality of side surfaces 11 a made of facets and a flat upper surface 11 b. In the present embodiment, the upper surface 11b is a c-plane of GaN. Each crystal nucleus 11 has a hexagonal shape in plan view and a trapezoidal shape in cross section. As shown in FIG. 5, each crystal nucleus 11 is formed so as to include at least one convex portion 2c. Further, the crystal nuclei 11 are formed apart from each other, and before the planarization layer 12 is formed, the planar portion of the buffer layer 10 and some of the convex portions 2c are exposed.

FIG. 4 is an example of a chart showing a change in growth temperature in the early stage of growth of the group III nitride semiconductor.
As shown in FIG. 4, in this embodiment, the buffer layer 10 is grown at a temperature lower than the growth temperature of the planarization layer 12. Thereafter, each crystal nucleus 11 is grown at a temperature higher than the growth temperature of the buffer layer 10 and lower than the growth temperature of the planarization layer 12. After each crystal nucleus 11 is grown, a planarization layer 12 is grown. In order to make growth conditions advantageous for facet formation, the temperature in the reactor is decreased, the pressure in the reactor is increased, the supply amount of NH ₃ is decreased, and the supply amount of (CH ₃ ) ₃ Ga is decreased. It may be possible to reduce the V / III ratio. By providing each crystal nucleus 11 under a predetermined condition, the semiconductor stacked portion 19 can be made to have good crystal quality without being affected by the period of the convex portion 2c.

The buffer layer 10 can be formed, for example, by supplying NH ₃ at 2200 sccm and (CH ₃ ) ₃ Ga at 20 sccm while maintaining the V / III ratio at 1016 and the temperature in the reactor at 540 ° C. for a predetermined time. . Each crystal nucleus 11 can be formed, for example, by supplying NH ₃ at 2200 sccm and (CH ₃ ) ₃ Ga at 20 sccm while maintaining the V / III ratio at 1016 and the temperature in the reactor at 950 ° C. for a predetermined time. it can. The planarization layer 12 is formed, for example, by supplying NH ₃ at 8000 sccm and (CH ₃ ) ₃ Ga at 45 sccm while maintaining the V / III ratio at 1016 and the reactor temperature at 1040 ° C. for a predetermined time. be able to. In other words, the growth conditions of each crystal nucleus 11 can be met only by increasing the temperature in the reactor with respect to the growth conditions of the buffer layer 10. Further, the growth condition of the planarization layer 12 is such that the supply amount of NH ₃ and (CH ₃ ) ₃ Ga is increased without changing the V / III ratio with respect to the growth condition of each crystal nucleus 11, and in the reactor This can be dealt with by increasing the temperature.

Here, it was confirmed by a plurality of sample bodies A-F that crystal nuclei 11 separated from each other were formed in a state in which the convex portion 2 c was formed on the surface of the sapphire substrate 2. For all the sample bodies, the height of the convex portion 2c of the sapphire substrate 2 was 400 nm, and the period was 460 nm.
Sample A was prepared by supplying 2200 sccm of NH ₃ and 20 sccm of (CH ₃ ) ₃ Ga while maintaining the V / III ratio at 1016 and the temperature in the reactor at 900 ° C. Sample B was prepared by supplying 2200 sccm of NH ₃ and 20 sccm of (CH ₃ ) ₃ Ga while maintaining the V / III ratio at 1016 and the temperature in the reactor at 950 ° C. Sample body C was prepared by supplying NH ₃ at 2200 sccm and (CH ₃ ) ₃ Ga at 20 sccm while maintaining the V / III ratio at 1016 and the temperature in the reactor at 965 ° C. The sample body D was prepared by supplying NH ₃ at 2200 sccm and (CH ₃ ) ₃ Ga at 20 sccm while maintaining the V / III ratio at 1016 and the temperature in the reactor at 980 ° C. The sample body E was prepared by supplying 1100 sccm of NH ₃ and 10 sccm of (CH ₃ ) ₃ Ga while maintaining the V / III ratio at 1016 and the temperature in the reactor at 900 ° C. The sample body F was prepared by supplying 1100 sccm of NH ₃ and 20 sccm of (CH ₃ ) ₃ Ga while maintaining the V / III ratio at 508 and the temperature in the reactor at 900 ° C.

6 is an SEM image of the sample body A, FIG. 7 is an SEM image of the sample body B, FIG. 8 is an SEM image of the sample body C, FIG. 9 is an SEM image of the sample body D, and FIG. FIG. 11 shows an SEM image of the sample body F, respectively.
As shown in FIGS. 6 to 9, as the growth temperature of the crystal nucleus 11 increases, the height of the crystal nucleus 11 and the size in plan view increase, and the density of the crystal nucleus 11 decreases. Specifically, the height of each crystal nucleus 11 of the sample body A is 200 nm to 400 nm, the size in plan view is 14 μm ² on average, and the ratio of the convex portions 2 c in an exposed state without being included in the crystal nucleus 11 is the whole. The ratio of the area covered with each crystal nucleus 11 on the surface on the sapphire substrate 2 side was 39%. Further, the height of each crystal nucleus 11 of the sample body B is 780 nm to 820 nm, the size in plan view is 53 μm ² on average, and the ratio of the convex portions 2 c in an exposed state without being included in the crystal nucleus 11 is 27 in the whole. The ratio of the area covered with each crystal nucleus 11 on the surface on the sapphire substrate 2 side was 20%. In addition, the height of each crystal nucleus 11 of the sample body C is 980 nm to 1200 nm, the size in plan view is 76 μm ² on average, and the ratio of the protruding portion 2 c that is exposed without being included in the crystal nucleus 11 is 61%. The ratio of the area covered with each crystal nucleus 11 on the surface on the sapphire substrate 2 side was 17%. Further, the height of each crystal nucleus 11 of the sample body D is 1500 nm to 1700 nm, the average size in plan view is 106 μm ² , and the ratio of the convex portion 2 c exposed without being included in the crystal nucleus 11 is 76%. The ratio of the area covered with each crystal nucleus 11 on the surface on the sapphire substrate 2 side was 16%. As a result, when the growth temperature of the crystal nuclei 11 is increased, the ratio of the convex portions 2c exposed without being included in the crystal nuclei 11 is increased, and the surface of the sapphire substrate 2 is covered with each crystal nuclei 11. It is understood that the area percentage decreases.

  Further, as shown in FIGS. 6 and 10, by slowing the growth rate of the crystal nuclei 11, the height of the crystal nuclei 11 and the size in plan view are increased, and the density of the crystal nuclei 11 is decreased. Further, when the growth rate of the crystal nuclei 11 is slowed, the ratio of the convex portions 2c exposed without being included in the crystal nuclei 11 increases, and the area covered with each crystal nuclei 11 on the surface on the sapphire substrate 2 side. The percentage of decrease.

  Further, as shown in FIGS. 6 and 11, by reducing the V / III ratio during the growth of the crystal nucleus 11, the height of the crystal nucleus 11 and the size in plan view are increased, and the density of the crystal nucleus 11 is increased. Becomes smaller. Further, when the growth rate of the crystal nuclei 11 is slowed, the ratio of the convex portions 2c exposed without being included in the crystal nuclei 11 increases, and the area covered with each crystal nuclei 11 on the surface on the sapphire substrate 2 side. The percentage of decrease.

  FIG. 12 is a graph showing the relationship between the pitch of convex portions and the threading dislocation density for a sample body in which crystal nuclei are formed and a sample body in which crystal nuclei are not formed. As a sample body in which crystal nuclei were formed, the above-mentioned sample body B was produced under the temperature conditions as shown in FIG. Specifically, it was manufactured through a cleaning step S1, a buffer layer growth step S2, a crystal nucleus formation step S3, and a planarization layer formation step S4. Although the temperature conditions and growth time of each process are arbitrary, the specific temperature and time in sample body preparation are as follows. In the cleaning step S1, the temperature in the reactor was kept at 1000 ° C. for 10 minutes. In the buffer layer growth step S2, the buffer layer 10 was grown at a temperature in the reactor of 540 ° C. for 2 minutes. In the crystal nucleus forming step S3, each crystal nucleus 11 was grown at a temperature in the reactor of 950 ° C. for 30 minutes. In the planarization layer forming step S4, the planarization layer 12 was grown at a temperature in the reactor of 1040 ° C. for 60 minutes. Further, as shown in FIG. 13, the sample body G that does not form crystal nuclei was transferred to the planarization layer forming step S4 without passing through the crystal nucleation step S3 after the buffer layer forming step S2. The growth conditions of the buffer layer 10 and the planarization layer 12 were the same as those of the sample body B in which crystal nuclei were formed.

  As shown in FIG. 12, when the crystal nuclei 11 were formed, the threading dislocation density was almost constant regardless of the pitch of the protrusions 2c. On the other hand, when the crystal nuclei 11 were not formed, the threading dislocation density was increased as the pitch of the convex portions 2c was shortened. The reason why the threading dislocation density increases when the crystal nuclei 11 are not formed is that the migration of Ga atoms in the planarization layer 12 is hindered by the presence of the convex portions 2c, and as a result, small nuclei are formed at a high density. This is thought to be because it is difficult to reduce the dislocation.

Further, when the oxygen concentration was measured for the crystal nuclei 11 and the flattening layer 12, the oxygen concentration was higher in the crystal nuclei 11 than in the flattening layer 12 in any sample body. Specifically, oxygen of 1 × 10 ¹⁷ / cm ³ or more was detected for the crystal nucleus 11, but oxygen was not detected for the planarization layer 12. In the measurement, an apparatus having an oxygen detection limit of 5 × 10 ¹⁶ / cm ³ was used. Therefore, it can be said that the oxygen concentration of the planarization layer 12 is less than 5 × 10 ¹⁶ / cm ³ . That is, whether or not the crystal nucleus 11 is used during the growth of the semiconductor multilayer portion 19 can be determined by examining the oxygen concentration in the semiconductor multilayer portion 19.

FIG. 14 is a graph showing the relationship between the maximum height of each crystal nucleus and the threading dislocation density. Regarding the relationship between the height of each crystal nucleus 11 and the threading dislocation density, the sample body G in which the crystal nucleus 11 is not formed and the height of each crystal nucleus 11 can be regarded as 0 nm, and the height of each crystal nucleus 11 are Sample A having a thickness of 200 nm to 400 nm, Sample B having a height of each crystal nucleus 11 of 780 nm to 820 nm, Sample C having a height of each crystal nucleus 11 of 980 nm to 1200 nm, and the height of each crystal nucleus 11 Was investigated using a sample body D of 1500 nm to 1700 nm.
As shown in FIG. 14, when at least one of the crystal nuclei 11 is formed higher than the convex portion 2c, it is understood that the threading dislocation density is sufficiently low.

  In addition, for each of the sample bodies A to D and G, it was observed whether or not the thickness of the semiconductor laminated portion 19 was 3.0 μm and was flat, and the height of each crystal nucleus 11 was 0 nm, 200 nm to 400 nm, and 780. The sample bodies A, B, and G of ˜820 nm were flat, but a slight surface pit was confirmed for the sample body C having a height of 980 nm to 1200 nm, and a lot of sample bodies D having a height of 1500 nm to 1700 nm were observed. A surface pit was confirmed. Thereby, from the viewpoint of flatness of the semiconductor stacked portion 19, the height of each crystal nucleus is preferably 900 nm or less.

  As described above, since the crystal nuclei 11 are formed before the planarization layer 12 is formed, the threading dislocation density of the semiconductor stacked portion 19 is made substantially constant regardless of the period of the convex portions 2c. Can do. In particular, as in this embodiment, when the period of the protrusions 2c is 1000 nm or less, a relatively large threading dislocation density reduction effect can be obtained.

  In particular, in this embodiment, since the upper surface of each crystal nucleus 11 is formed flat, the thickness until the flattening layer 12 becomes flat can be reduced. Further, since the crystal nuclei 11 are formed apart from each other, the density of crystal nuclei on the substrate is small and the number of dislocation generation sources is small, so that the defect density of the subsequently formed planarization layer 12 is reduced. be able to.

  In the above-described embodiment, the flip-chip type LED element 1 is shown. However, for example, as shown in FIG. 15, a face-up type LED element 101 may be used. The semiconductor stacked portion 119 of the LED element 101 includes a buffer layer 110, a crystal nucleus 111, a planarization layer 112, an n-type GaN layer 113, a light emitting layer 114, an electron blocking layer 116, and a p-type GaN layer 118 from the sapphire substrate 102 side. It has in this order. A p-side electrode 127 is formed on the p-type GaN layer 118 and an n-side electrode 128 is formed on the n-type GaN layer 113.

  In the LED element 101 of FIG. 15, the surface of the sapphire substrate 102 forms a verticalized moth-eye surface 102a. On the surface of the sapphire substrate 102, a flat portion 102b and a plurality of convex portions 102c periodically formed on the flat portion 102b are formed. The p-side electrode 127 includes a diffusion electrode 121 formed on the p-type GaN layer 118 and a pad electrode 122 formed on a part of the diffusion electrode 121. The n-side electrode 128 is formed on the exposed n-type GaN layer 113 by etching the n-type GaN layer 113 from the p-type GaN layer 118.

  As shown in FIG. 15, a dielectric multilayer film 124 is formed on the back side of the sapphire substrate 102. The dielectric multilayer film 124 is configured by repeating a plurality of pairs of a first material and a second material having different refractive indexes. The dielectric multilayer film 124 is covered with an Al layer 126 that is a metal layer. In the light emitting element 101, the dielectric multilayer film 124 and the Al layer 126 form a reflecting portion, and light emitted from the light emitting layer 114 and transmitted through the vertical moth-eye surface 102a by the diffraction action is reflected by the reflecting portion. Then, the light transmitted by the diffractive action is re-incident on the diffractive surface 102a, and is transmitted again by using the diffractive action on the diffractive surface 102a, so that the light can be extracted outside the element in a plurality of modes.

  Also in the LED element 101 configured as described above, since the crystal nuclei 111 are formed before the planarization layer 112 is formed, the threading dislocation of the semiconductor stacked portion 119 is performed regardless of the period of the convex portion 102c. The density can be made almost constant.

  Moreover, in the said embodiment, although what used the sapphire substrate 2 as a board | substrate of the LED element 1 was shown, of course, another board | substrate may be sufficient. In addition, after the crystal nucleus 11 is formed, the u-GaN planarization layer 12 and the n-type GaN layer 13 are sequentially formed. For example, after the crystal nucleus 11 is formed, the n-type GaN layer is formed. 13 may be formed. In this case, the n-type GaN layer 13 also serves as a planarizing layer.

  While the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

DESCRIPTION OF SYMBOLS 1 LED element 2 Sapphire substrate 2a Verticalization moth eye surface 2b Flat part 2c Protrusion part 2d Side surface 2e Curved part 2f Upper surface 2g Transmission moth eye surface 2h Flat part 2i Convex part 10 Buffer layer 11 Crystal nucleus 12 Flattening layer 13 n-type GaN layer 14 Light emitting layer 16 Electron blocking layer 18 p-type GaN layer 19 Semiconductor laminated portion 21 Diffusion electrode 22 Dielectric multilayer film 22a Via hole 23 Metal electrode 24 Diffusion electrode 25 Dielectric multilayer film 25a Via hole 26 Metal electrode 27 P side electrode 28 N side electrode 101 LED element 102 Sapphire substrate 102a Verticalized moth-eye surface 110 Buffer layer 111 Crystal nucleus 11
112 planarization layer 113 n-type GaN layer 114 light-emitting layer 116 electron block layer 118 p-type GaN layer 119 semiconductor laminated portion 122 pad electrode 124 dielectric multilayer 126 Al layer 127 p-side electrode 128 n-side electrode

Claims (3)

A light emitting device for growing a semiconductor stacked portion made of a group III nitride semiconductor including a light emitting layer on a substrate surface on which convex portions are formed with a period larger than an optical wavelength of light emitted from the light emitting layer and smaller than a coherent length of the light A manufacturing method of
Forming a buffer layer along the substrate surface including the protrusions;
A plurality of crystal nuclei having facet surfaces and spaced apart from each other are grown on the buffer layer so as to contain at least one of the convex portions and have a height of 900 nm or less.
A method for manufacturing a light emitting device, wherein a planarization layer is grown on the buffer layer in which the plurality of crystal nuclei are formed.   The light emitting device manufacturing method according to claim 1, wherein the plurality of crystal nuclei have a flat upper surface.   The method for manufacturing a light-emitting element according to claim 1, wherein the buffer layer is formed by sputtering using AlN as a target.

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