JP5828998B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor element that activates impurities by heating a substrate such as a semiconductor wafer into which impurities are implanted.

  In the semiconductor device manufacturing process, impurity introduction is an indispensable step for forming a pn junction in a semiconductor wafer. Currently, impurities are generally introduced by ion implantation and subsequent annealing. The ion implantation method is a technique in which impurity elements such as boron (B), arsenic (As), and phosphorus (P) are ionized and collided with a semiconductor wafer at a high acceleration voltage to physically perform impurity implantation. The implanted impurities are activated by annealing. At this time, if the annealing time is about several seconds or more, the implanted impurities are deeply diffused by heat, and as a result, the junction depth becomes deeper than required, and there is a possibility that good device formation may be hindered.

  Therefore, an annealing method for heating a semiconductor wafer in an extremely short time has been studied, and Patent Document 1 discloses activation of impurities implanted in a source / drain region using laser annealing (LSA). ing. Further, cited document 2 discloses that impurities are activated by heating in a short time by flash lamp annealing (FLA).

JP 2007-281318 A JP 2008-98640 A

  By the way, as a result of implanting high energy ions by the ion implantation method, many defects are introduced into the silicon crystal of the semiconductor wafer. Such a defect tends to be introduced at a position slightly deeper than the ion implantation layer. When performing the annealing process after ion implantation, it is desirable to perform the recovery of the introduced defects together with the activation of the impurities.

  However, when heat treatment is performed for a very short time of several milliseconds by laser annealing or flash lamp annealing, the temperature rise rate of the surface of the semiconductor wafer is faster than the heat transferred to the inside of the wafer by the heat conduction of silicon. Therefore, although the temperature of the ion-implanted layer can be increased, it is difficult to increase the temperature to the depth position where the defect is introduced. However, if the semiconductor wafer is irradiated with extremely high energy light, the temperature can be raised to a depth position where the defect is introduced even in an extremely short time irradiation of several milliseconds, and the defect is recovered. However, there is a problem that the surface temperature is significantly increased to damage the semiconductor wafer, and in the worst case, the semiconductor wafer is shattered.

  Further, when the annealing process is performed after the gate electrode is formed, there is a problem that the gate electrode itself is deteriorated by the conventional extremely short time irradiation.

The present invention has been made in view of the above problems, and a method for manufacturing a semiconductor device capable of both activating implanted impurities and recovering introduced defects while suppressing damage to the substrate. The purpose is to provide.

To solve the above problems, a first aspect of the invention, by heating the substrate in which impurities are implanted in the manufacturing method of a semiconductor element for activation of the impurity, the a predetermined region of the semiconductor devices formed on the substrate comprising an impurity implantation step of implanting an impurity, and a light irradiation step of performing the heating by irradiating light upon surface 10 milliseconds to 1,000 milliseconds following the time range of the substrate including the predetermined region, the light The irradiation step includes an output increase step for increasing the emission output to a target value over a period of 1 millisecond to 100 milliseconds, and after the output increase step, the emission output is within ± 30% of the target value. A constant power irradiation process that maintains 5 milliseconds or more and 100 milliseconds or less within the range of fluctuation, and after the constant power irradiation process, the light emission output is 1 millisecond or more and 100 milliseconds or less. Seen containing an output attenuation step for attenuating over the following time second, a, in the light irradiation step, controlling the current flowing through the flash lamp by applying a pulse signal to the gate of the switching element connected to the flash lamp characterized in that it.

According to a second aspect of the present invention, in the semiconductor element manufacturing method according to the first aspect of the present invention, the semiconductor element is a field effect transistor, and the predetermined region is a source / drain region .

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect , the predetermined region further includes an extension region of the field effect transistor .

The invention of claim 4 is formed in the method of manufacturing a semiconductor device according to the invention of claim 2 or claim 3, prior to the light irradiation step, the gate electrode of the field effect transistor on the surface of the substrate The method further includes the step of forming a gate electrode.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to fourth aspects, the light irradiation in the light irradiation step is performed from a flash lamp.

According to the first to fifth aspects of the present invention, impurities are implanted into a predetermined region of the semiconductor element formed on the substrate, and the surface of the substrate including the predetermined region is in a time range of 10 milliseconds to 1000 milliseconds. As the total heat received by the surface of the substrate increases, the surface temperature gradually rises and then gradually drops, suppressing the damage to the substrate and implanting it. Both the activation of the introduced impurities and the recovery of the introduced defects can be performed. Further, after increasing the light emission output to the target value over a period of 1 millisecond or more and 100 milliseconds or less, the light emission output is changed within the range of fluctuation within ± 30% from the target value to 5 milliseconds or more and 100. This is suitable for performing light irradiation on a substrate on which a metal gate electrode is formed, because the emission output is attenuated over a period of 1 millisecond or more and 100 milliseconds or less.

It is a longitudinal cross-sectional view which shows the structure of the heat processing apparatus suitable for enforcing the heat processing method which concerns on this invention. It is sectional drawing which shows the gas path of the heat processing apparatus of FIG. It is sectional drawing which shows the structure of a holding | maintenance part. It is a top view which shows a hot plate. It is a longitudinal cross-sectional view which shows the structure of the heat processing apparatus of FIG. It is a figure which shows the drive circuit of a flash lamp. It is a figure which shows the structure of the semiconductor element formed in a semiconductor wafer. It is a flowchart which shows the outline of the element formation procedure to a semiconductor wafer. It is a figure which shows the change of the surface temperature of the semiconductor wafer after preheating is started. It is a figure which shows an example of the correlation with the waveform of a pulse signal, and the electric current which flows into a circuit. It is a figure which shows an example of the light emission output profile of a flash lamp. It is a figure which shows the other example of the light emission output profile of a flash lamp. It is a figure which shows the other example of the light emission output profile of a flash lamp. It is a figure which shows the other example of the light emission output profile of a flash lamp. It is a figure which shows the other example of the light emission output profile of a flash lamp. It is a flowchart which shows the other example of the element formation procedure to a semiconductor wafer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, an example of a heat treatment apparatus suitable for carrying out the heat treatment method according to the present invention will be outlined. FIG. 1 is a longitudinal sectional view showing a configuration of a heat treatment apparatus 1 suitable for carrying out the heat treatment method according to the present invention. The heat treatment apparatus 1 is a flash lamp annealing apparatus that heats a semiconductor wafer W by irradiating light from a flash lamp onto a substantially circular semiconductor wafer W as a substrate.

  The heat treatment apparatus 1 includes a substantially cylindrical chamber 6 that accommodates a semiconductor wafer W, and a lamp house 5 that houses a plurality of flash lamps FL. Further, the heat treatment apparatus 1 includes a control unit 3 that controls each operation mechanism provided in the chamber 6 and the lamp house 5 to execute the heat treatment of the semiconductor wafer W.

  The chamber 6 is provided below the lamp house 5 and includes a chamber side 63 having a substantially cylindrical inner wall and a chamber bottom 62 covering the lower part of the chamber side 63. A space surrounded by the chamber side 63 and the chamber bottom 62 is defined as a heat treatment space 65. An upper opening 60 is formed above the heat treatment space 65, and a chamber window 61 is attached to the upper opening 60 to be closed.

  The chamber window 61 constituting the ceiling portion of the chamber 6 is a disk-shaped member made of quartz and functions as a quartz window that transmits the light emitted from the lamp house 5 to the heat treatment space 65. The chamber bottom 62 and the chamber side 63 constituting the main body of the chamber 6 are formed of, for example, a metal material having excellent strength and heat resistance such as stainless steel, and a ring on the upper side of the inner side surface of the chamber side 63. 631 is formed of an aluminum (Al) alloy or the like having durability superior to stainless steel against deterioration due to light irradiation.

  Further, in order to maintain the airtightness of the heat treatment space 65, the chamber window 61 and the chamber side portion 63 are sealed by an O-ring. That is, the O-ring is sandwiched between the lower surface peripheral portion of the chamber window 61 and the chamber side portion 63, the clamp ring 90 is brought into contact with the upper peripheral portion of the chamber window 61, and the clamp ring 90 is attached to the chamber side portion 63. The chamber window 61 is pressed against the O-ring by screwing.

  The chamber bottom 62 has a plurality (in this embodiment) for supporting the semiconductor wafer W from the lower surface (surface opposite to the side irradiated with light from the lamp house 5) through the holding portion 7. 3) support pins 70 are provided upright. The support pin 70 is made of, for example, quartz and is fixed from the outside of the chamber 6 and can be easily replaced.

The chamber side 63 has a transfer opening 66 for carrying in and out the semiconductor wafer W, and the transfer opening 66 can be opened and closed by a gate valve 185 that rotates about a shaft 662. In a portion of the chamber side 63 opposite to the transfer opening 66, an inert gas such as nitrogen (N ₂ ) gas, helium (He) gas, argon (Ar) gas, etc. Alternatively, an introduction path 81 for introducing oxygen (O ₂ ) gas or the like is formed, one end of which is connected to an air supply mechanism (not shown) via a valve 82, and the other end is formed inside the chamber side portion 63. Connected to the gas introduction buffer 83. A discharge passage 86 for discharging the gas in the heat treatment space 65 is formed in the transfer opening 66 and is connected to an exhaust mechanism (not shown) through a valve 87.

  FIG. 2 is a cross-sectional view of the chamber 6 cut along a horizontal plane at the position of the gas introduction buffer 83. As shown in FIG. 2, the gas introduction buffer 83 is formed over about ３ of the inner periphery of the chamber side 63 on the opposite side of the transfer opening 66 shown in FIG. Then, the processing gas guided to the gas introduction buffer 83 is supplied into the heat treatment space 65 from the plurality of gas supply holes 84.

  The heat treatment apparatus 1 also includes a substantially disk-shaped holding unit 7 that holds the semiconductor wafer W in a horizontal position in the chamber 6 and performs preheating of the semiconductor wafer W held before light irradiation, and a holding unit. And a holding unit elevating mechanism 4 that elevates 7 with respect to the chamber bottom 62 which is the bottom surface of the chamber 6. 1 includes a substantially cylindrical shaft 41, a moving plate 42, guide members 43 (three arranged around the shaft 41 in the present embodiment), a fixed plate 44, a ball screw 45, It has a nut 46 and a motor 40. A substantially circular lower opening 64 having a smaller diameter than the holding portion 7 is formed in the chamber bottom 62 which is the lower portion of the chamber 6, and the stainless steel shaft 41 is inserted through the lower opening 64 to hold the holding portion. 7 (strictly speaking, the hot plate 71 of the holding unit 7) is connected to the lower surface of the holding unit 7 to support it.

  A nut 46 that is screwed into the ball screw 45 is fixed to the moving plate 42. The moving plate 42 is slidably guided by a guide member 43 that is fixed to the chamber bottom 62 and extends downward, and is movable in the vertical direction. Further, the moving plate 42 is connected to the holding unit 7 via the shaft 41.

  The motor 40 is installed on a fixed plate 44 attached to the lower end of the guide member 43, and is connected to the ball screw 45 via the timing belt 401. When the holding part 7 is raised and lowered by the holding part raising / lowering mechanism 4, the motor 40 as the driving part rotates the ball screw 45 under the control of the control part 3, and the moving plate 42 to which the nut 46 is fixed follows the guide member 43. Move vertically. As a result, the shaft 41 fixed to the moving plate 42 moves along the vertical direction, and the holding unit 7 connected to the shaft 41 moves between the delivery position of the semiconductor wafer W shown in FIG. 1 and the semiconductor wafer W shown in FIG. Move up and down smoothly between the processing positions.

  On the upper surface of the moving plate 42, a mechanical stopper 451 having a substantially semi-cylindrical shape (a shape obtained by cutting the cylinder in half along the longitudinal direction) is provided so as to extend along the ball screw 45. If the upper limit of the mechanical stopper 451 is struck against the end plate 452 provided at the end of the ball screw 45, the moving plate 42 is prevented from rising abnormally. Thereby, the holding part 7 does not rise above a predetermined position below the chamber window 61, and the collision between the holding part 7 and the chamber window 61 is prevented.

  The holding unit lifting mechanism 4 has a manual lifting unit 49 that manually lifts and lowers the holding unit 7 when performing maintenance inside the chamber 6. The manual elevating part 49 has a handle 491 and a rotating shaft 492. By rotating the rotating shaft 492 via the handle 491, the ball screw 45 connected to the rotating shaft 492 is rotated via the timing belt 495 to hold the holding part. 7 can be moved up and down.

  A telescopic bellows 47 that surrounds the shaft 41 and extends downward is provided below the chamber bottom 62, and its upper end is connected to the lower surface of the chamber bottom 62. On the other hand, the lower end of the bellows 47 is attached to the bellows lower end plate 471. The bellows lower end plate 471 is attached by being screwed to the shaft 41 by a flange-shaped member 411. The bellows 47 is contracted when the holding portion 7 is raised with respect to the chamber bottom 62 by the holding portion lifting mechanism 4, and the bellows 47 is expanded when the holding portion 7 is lowered. When the holding unit 7 moves up and down, the airtight state in the heat treatment space 65 is maintained by the expansion and contraction of the bellows 47.

  FIG. 3 is a cross-sectional view showing the configuration of the holding unit 7. The holding unit 7 is installed on a hot plate (heating plate) 71 that preheats the semiconductor wafer W (so-called assist heating), and an upper surface of the hot plate 71 (a surface on the side where the holding unit 7 holds the semiconductor wafer W). The susceptor 72 is provided. As described above, the shaft 41 that moves up and down the holding unit 7 is connected to the lower surface of the holding unit 7. The susceptor 72 is made of quartz (or may be aluminum nitride (AIN) or the like), and a pin 75 for preventing displacement of the semiconductor wafer W is provided on the upper surface thereof. The susceptor 72 is installed on the hot plate 71 with its lower surface in surface contact with the upper surface of the hot plate 71. Thus, the susceptor 72 diffuses the thermal energy from the hot plate 71 and transmits it to the semiconductor wafer W placed on the upper surface of the susceptor 72, and can be removed from the hot plate 71 and cleaned during maintenance.

  The hot plate 71 includes an upper plate 73 and a lower plate 74 made of stainless steel. A resistance heating wire 76 such as a nichrome wire for heating the hot plate 71 is disposed between the upper plate 73 and the lower plate 74, and is filled with a conductive nickel (Ni) solder and sealed. The end portions of the upper plate 73 and the lower plate 74 are bonded by brazing.

  FIG. 4 is a plan view showing the hot plate 71. As shown in FIG. 4, the hot plate 71 includes a disc-shaped zone 711 and an annular zone 712 that are concentrically arranged in a central portion of a region facing the held semiconductor wafer W, and a zone 712. There are four zones 713 to 716 obtained by equally dividing a peripheral substantially annular region into four equal parts in the circumferential direction, and a slight gap is formed between the zones. The hot plate 71 is provided with three through holes 77 through which the support pins 70 are inserted, every 120 ° on the circumference of the gap between the zone 711 and the zone 712.

  In each of the six zones 711 to 716, heaters are individually formed so that mutually independent resistance heating wires 76 circulate, and each zone is individually formed by a heater built in each zone. Heated. The semiconductor wafer W held by the holding unit 7 is heated by heaters built in the six zones 711 to 716. Each of the zones 711 to 716 is provided with a sensor 710 that measures the temperature of each zone using a thermocouple. Each sensor 710 passes through the inside of a substantially cylindrical shaft 41 and is connected to the control unit 3.

  When the hot plate 71 is heated, the resistance heating wire disposed in each zone is set so that the temperature of each of the six zones 711 to 716 measured by the sensor 710 becomes a predetermined temperature. The amount of power supplied to 76 is controlled by the control unit 3. The temperature control of each zone by the control unit 3 is performed by PID (Proportional, Integral, Derivative) control. In the hot plate 71, the temperature of each of the zones 711 to 716 is continuously measured until the heat treatment of the semiconductor wafer W (when plural semiconductor wafers W are continuously processed, the heat treatment of all the semiconductor wafers W) is completed. Then, the power supply amount to the resistance heating wire 76 disposed in each zone is individually controlled, that is, the temperature of the heater built in each zone is individually controlled, and the temperature of each zone becomes the set temperature. Maintained. The set temperature of each zone can be changed by an offset value set individually from the reference temperature.

  The resistance heating wires 76 respectively disposed in the six zones 711 to 716 are connected to a power supply source (not shown) via a power line passing through the inside of the shaft 41. On the way from the power supply source to each zone, the power lines from the power supply source are arranged so as to be electrically insulated from each other inside a stainless tube filled with an insulator such as magnesia (magnesium oxide). The The interior of the shaft 41 is open to the atmosphere.

  Next, the lamp house 5 includes a light source composed of a plurality of (30 in this embodiment) xenon flash lamps FL inside the housing 51, and a reflector 52 provided so as to cover the light source, It is configured with. A lamp light emission window 53 is attached to the bottom of the casing 51 of the lamp house 5. The lamp light radiation window 53 constituting the floor of the lamp house 5 is a plate-like member made of quartz. By installing the lamp house 5 above the chamber 6, the lamp light emission window 53 faces the chamber window 61. The lamp house 5 heats the semiconductor wafer W by irradiating the semiconductor wafer W held by the holding unit 7 in the chamber 6 with light from the flash lamp FL through the lamp light emission window 53 and the chamber window 61.

  Each of the plurality of flash lamps FL is a rod-shaped lamp having a long cylindrical shape, and the longitudinal direction of each of the flash lamps FL is along the main surface of the semiconductor wafer W held by the holding unit 7 (that is, along the horizontal direction). They are arranged in a plane so as to be parallel to each other. Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane.

  FIG. 6 is a diagram showing a driving circuit for the flash lamp FL. As shown in the figure, a capacitor 93, a coil 94, a flash lamp FL, and a switching element 96 are connected in series. The flash lamp FL includes a rod-shaped glass tube (discharge tube) 92 in which xenon gas is sealed and an anode and a cathode are disposed at both ends thereof, and a trigger electrode provided on the outer peripheral surface of the glass tube 92. 91. A predetermined voltage is applied to the capacitor 93 by the power supply unit 95, and a charge corresponding to the applied voltage is charged. A voltage can be applied from the trigger circuit 97 to the trigger electrode 91. The timing at which the trigger circuit 97 applies a voltage to the trigger electrode 91 is controlled by the control unit 3.

  In the present embodiment, an insulated gate bipolar transistor (IGBT) is used as the switching element 96. The IGBT is a bipolar transistor in which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is incorporated in a gate portion, and is a switching element suitable for handling high power. A pulse signal is applied from the pulse generator 31 of the control unit 3 to the gate of the switching element 96.

  Even when a pulse is output to the gate of the switching element 96 with the capacitor 93 charged and a high voltage is applied to both ends of the glass tube 92, the xenon gas is normally an insulator, so In this state, electricity does not flow in the glass tube 92. However, when the trigger circuit 97 applies a voltage to the trigger electrode 91 to break the insulation, an electric current instantaneously flows in the glass tube 92 due to the discharge between the two end electrodes, and the excitation of the xenon atoms or molecules at that time Light is emitted.

  Further, the reflector 52 of FIG. 1 is provided above the plurality of flash lamps FL so as to cover all of them. The basic function of the reflector 52 is to reflect the light emitted from the plurality of flash lamps FL toward the holding unit 7. The reflector 52 is formed of an aluminum alloy plate, and the surface (the surface facing the flash lamp FL) is roughened by blasting to exhibit a satin pattern. The roughening process is performed when the surface of the reflector 52 is a perfect mirror surface, and a regular pattern is generated in the intensity of the reflected light from the plurality of flash lamps FL, so that the surface temperature distribution of the semiconductor wafer W is obtained. This is because the uniformity of the is reduced.

  The control unit 3 controls the various operation mechanisms provided in the heat treatment apparatus 1. The configuration of the control unit 3 as hardware is the same as that of a general computer. That is, the control unit 3 stores a CPU that performs various arithmetic processes, a ROM that is a read-only memory that stores basic programs, a RAM that is a readable and writable memory that stores various information, control software, data, and the like. It is configured with a magnetic disk. The control unit 3 includes a pulse generator 31 and a waveform setting unit 32 and is connected to the input unit 33. As the input unit 33, various known input devices such as a keyboard, a mouse, and a touch panel can be employed. The waveform setting unit 32 sets the waveform of the pulse signal based on the input content from the input unit 33, and the pulse generator 31 generates the pulse signal according to the waveform.

  In addition to the above configuration, the heat treatment apparatus 1 is used for various cooling purposes in order to prevent excessive temperature rise of the chamber 6 and the lamp house 5 due to the heat energy generated from the flash lamp FL and the hot plate 71 during the heat treatment of the semiconductor wafer W. It has the structure of For example, water-cooled tubes (not shown) are provided on the chamber side 63 and the chamber bottom 62 of the chamber 6. The lamp house 5 has an air cooling structure provided with a gas supply pipe 55 and an exhaust pipe 56 for exhausting heat by forming a gas flow therein (see FIGS. 1 and 5). Air is also supplied to the gap between the chamber window 61 and the lamp light emission window 53 to cool the lamp house 5 and the chamber window 61.

  Next, device formation on the semiconductor wafer W will be described. FIG. 7 is a view showing the structure of the semiconductor element formed on the semiconductor wafer W. As shown in FIG. FIG. 8 is a flowchart showing an outline of an element formation procedure on the semiconductor wafer W. In the present embodiment, a field effect transistor is formed as a semiconductor element on the semiconductor wafer W. First, the gate insulating film 14 and the gate electrode 15 are formed on the silicon substrate 11 (step S1). The gate electrode 15 is a complete metal gate (full metal gate) formed of an alloy of magnesium (Mg), lanthanum (La), and hafnium (Hf). The gate electrode 15 is selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), molybdenum (Mo), and tungsten (W). It may be configured to include at least one kind of metal. The gate insulating film 14 is, for example, a high dielectric constant insulating film made of a material having a relative dielectric constant higher than that of a silicon oxide film, as hafnium (Hf), zirconium (Zr), aluminum (Al), yttrium (Y). , Lanthanum (La), and at least one selected from the group consisting of magnesium (Mg). Note that the sidewall 16 is not formed at the stage of step S1.

  After forming the gate electrode 15, impurities (ions) are implanted into the extension region 13 of the silicon substrate 11 by ion implantation (step S2). The extension region 13 is an electrical connection between the source / drain region 12 and the channel. Subsequently, a light irradiation heat treatment (annealing) is performed on the surface of the semiconductor wafer W including the extension region 13 by the heat treatment apparatus 1 to activate the implanted impurities (step S3). The light irradiation heat treatment by the heat treatment apparatus 1 will be further described later.

  Thereafter, a side wall 16 of ceramics (silicon nitride (SiN) in this embodiment) is formed for measuring the gate electrode 15 (step S4). Subsequently, impurities are implanted into the source / drain regions 12 of the silicon substrate 11 by ion implantation (step S5). Then, a light irradiation heat treatment is performed again on the surface of the semiconductor wafer W including the source / drain regions 12 by the heat treatment apparatus 1 to activate the impurities implanted into the source / drain regions 12 (step S6). The light irradiation heat treatment in step S6 is the same as the process in step S3.

  Next, the light irradiation heat treatment of the semiconductor wafer W by the heat treatment apparatus 1 executed in steps S3 and S6 of FIG. 8 will be described in detail. The processing target is the semiconductor wafer W in which impurities are implanted into the extension region 13 or the source / drain region 12, and the activation of the impurities is performed by light irradiation heat treatment by the heat treatment apparatus 1. The processing procedure of the heat treatment apparatus 1 described below proceeds by the control unit 3 controlling each operation mechanism of the heat treatment apparatus 1.

  First, the holding unit 7 is lowered from the processing position shown in FIG. 5 to the delivery position shown in FIG. The “processing position” is the position of the holding unit 7 when the semiconductor wafer W is irradiated with light from the flash lamp FL, and is the position in the chamber 6 of the holding unit 7 shown in FIG. Further, the “delivery position” is the position of the holding unit 7 when the semiconductor wafer W is carried in and out of the chamber 6, and is the position of the holding unit 7 shown in FIG. The reference position of the holding unit 7 in the heat treatment apparatus 1 is the processing position. Before the processing, the holding unit 7 is located at the processing position, and this is lowered to the delivery position at the start of processing. As shown in FIG. 1, when the holding portion 7 is lowered to the delivery position, the holding portion 7 comes close to the chamber bottom portion 62, and the tip of the support pin 70 penetrates the holding portion 7 and protrudes above the holding portion 7.

  Next, when the holding unit 7 is lowered to the delivery position, the valve 82 and the valve 87 are opened, and normal temperature nitrogen gas is introduced into the heat treatment space 65 of the chamber 6. Subsequently, the gate valve 185 is opened to open the transfer opening 66, and the semiconductor wafer W into which impurities are implanted is transferred into the chamber 6 through the transfer opening 66 by a transfer robot outside the apparatus, and a plurality of support pins 70.

  The purge amount of nitrogen gas into the chamber 6 when the semiconductor wafer W is loaded is about 40 liters / minute, and the supplied nitrogen gas is moved from the gas introduction buffer 83 in the direction of the arrow AR4 shown in FIG. Then, the exhaust gas is exhausted by utility exhaust via the discharge path 86 and the valve 87 shown in FIG. A part of the nitrogen gas supplied to the chamber 6 is also discharged from an outlet (not shown) provided inside the bellows 47. In each step described below, nitrogen gas is continuously supplied to and exhausted from the chamber 6, and the supply amount of the nitrogen gas is variously changed according to the processing process of the semiconductor wafer W.

  When the semiconductor wafer W is loaded into the chamber 6, the transfer opening 66 is closed by the gate valve 185. The holding unit lifting mechanism 4 raises the holding unit 7 from the delivery position to a processing position close to the chamber window 61. In the process in which the holding unit 7 is lifted from the delivery position, the semiconductor wafer W is transferred from the support pins 70 to the susceptor 72 of the holding unit 7 and is placed and held on the upper surface of the susceptor 72. When the holding unit 7 is raised to the processing position, the semiconductor wafer W held by the susceptor 72 is also held at the processing position.

  Each of the six zones 711 to 716 of the hot plate 71 is heated to a predetermined temperature by a heater (resistive heating wire 76) individually incorporated in each zone (between the upper plate 73 and the lower plate 74). ing. When the holding unit 7 rises to the processing position and the semiconductor wafer W comes into contact with the holding unit 7, the semiconductor wafer W is preheated by the heater built in the hot plate 71 and the temperature gradually rises.

  FIG. 9 is a diagram showing a change in the surface temperature of the semiconductor wafer W since the preheating is started. Preheating is performed for a time tp at the processing position, and the temperature of the semiconductor wafer W rises to a preset preheating temperature T1. The preheating temperature T1 is set to about 200 ° C. to 800 ° C., preferably about 350 ° C. to 600 ° C. (in this embodiment, 600 ° C.) at which impurities added to the semiconductor wafer W are not likely to diffuse due to heat. . The time tp for preheating the semiconductor wafer W is about 3 seconds to 200 seconds (60 seconds in the present embodiment). The distance between the holding unit 7 and the chamber window 61 can be arbitrarily adjusted by controlling the rotation amount of the motor 40 of the holding unit lifting mechanism 4.

  After the preheating time of time tp has elapsed, light irradiation heating of the semiconductor wafer W by the flash lamp FL is started at time A. When irradiating light from the flash lamp FL, charges are accumulated in the capacitor 93 by the power supply unit 95 in advance. Then, a pulse signal is output from the pulse generator 31 of the control unit 3 to the switching element 96 in a state where charges are accumulated in the capacitor 93.

  FIG. 10 is a diagram illustrating an example of the correlation between the waveform of the pulse signal and the current flowing through the circuit. Here, a pulse signal having a waveform as shown in FIG. The waveform of the pulse signal can be defined by inputting from the input unit 33 a recipe in which a pulse width time (on time) and a pulse interval time (off time) are sequentially set. When the operator inputs such a recipe from the input unit 33 to the control unit 3, the waveform setting unit 32 of the control unit 3 sets a pulse waveform as shown in FIG. In the pulse waveform shown in FIG. 10A, first, a plurality of pulses PA having a relatively long width and a short interval, a plurality of pulses PB having a shorter width and a longer interval, and a plurality of pulses having a longer interval than that. PCs are set in order. Then, the pulse generator 31 outputs a pulse signal according to the pulse waveform set by the waveform setting unit 32. As a result, a pulse signal having a waveform as shown in FIG. 10A is applied to the gate of the switching element 96, and the on / off driving of the switching element 96 is controlled.

  In addition, the control unit 3 controls the trigger circuit 97 and applies a voltage to the trigger electrode 91 in synchronization with the timing when the pulse signal output from the pulse generator 31 is turned on. Thus, when the pulse signal input to the gate of the switching element 96 is on, a current always flows between the two end electrodes in the glass tube 92, and light is emitted by excitation of the xenon atoms or molecules at that time. The control unit 3 outputs a pulse signal having the waveform of FIG. 10A to the gate of the switching element 96, and applies a voltage to the trigger electrode 91 in synchronization with the timing when the pulse signal is turned on, whereby the flash lamp A current having a waveform as shown in FIG. 10B flows in a circuit including FL. That is, the value of the current flowing in the glass tube 92 of the flash lamp FL increases when the pulse signal input to the gate of the switching element 96 is on, and the current value decreases when the pulse signal is off. Each current waveform corresponding to each pulse is defined by a constant of the coil 94.

  A current having a waveform as shown in FIG. 10B flows, and the flash lamp FL emits light. The light emission output of the flash lamp FL is substantially proportional to the current flowing through the flash lamp FL. Therefore, the output waveform (light emission output profile) of the light emission output of the flash lamp FL has a pattern as shown in FIG. With the output waveform from the flash lamp FL as shown in FIG. 11, light irradiation is performed on the surface (including the source / drain region 12 and the extension region 13) of the semiconductor wafer W held by the holding unit 7 at the processing position.

  When the flash lamp FL is caused to emit light without using the switching element 96 as in the prior art, the electric charge accumulated in the capacitor 93 is instantaneously consumed by one light emission. For this reason, the output waveform from the flash lamp FL becomes a single pulse with a sudden rise and fall width of about 0.1 to 10 milliseconds (light emission output profile indicated by a dotted line in FIG. 11).

  On the other hand, as in the present embodiment, the switching element 96 is connected in the circuit and the pulse signal as shown in FIG. As a result, the electric charge accumulated in the capacitor 93 is divided and consumed, and the flash lamp FL repeatedly blinks in a very short time. However, as shown in FIG. 10B, before the current value becomes completely “0”, the next pulse is applied to the gate of the switching element 96 to increase the current value again. For this reason, the light emission output does not completely become “0” while the flash lamp FL is repeatedly blinking, and the light emission output of the flash lamp FL is indicated by a solid line in FIG. Draw a pattern like this.

  The light emission output profile shown by the solid line in FIG. 11 can be regarded as performing three levels of light irradiation. That is, it is constituted by an output increasing process in which the light emission output rises relatively slowly, a constant output irradiation process in which the light emission output is maintained substantially flat thereafter, and an output attenuation process in which the light emission output attenuates relatively slowly thereafter. Three-stage irradiation is performed.

  More specifically, first, the pulse generator 31 intermittently outputs a plurality of pulses PA having a relatively long width and a short interval to the gate of the switching element 96. As a result, the switching element 96 is repeatedly turned on and off, and a current having a sawtooth waveform with a current value increasing as a whole flows through the circuit including the flash lamp FL while repeatedly increasing and decreasing. As a result, as shown in FIG. 11, the light emission output from the flash lamp FL increases from 0 to the target value L1. The process in which the light emission output of the flash lamp FL increases from 0 to the target value L1 in this way is the output increase process, and the light irradiation time t1 is in the range of 1 millisecond or more and 100 milliseconds or less. In other words, the output increasing step is a step of increasing the light emission output of the flash lamp FL from 0 to the target value L1 over a time period of 1 millisecond or more and 100 milliseconds or less.

  Next, the pulse generator 31 intermittently outputs a plurality of pulses PB having a shorter width and a longer interval than the plurality of pulses PA to the gate of the switching element 96. As a result, the switching element 96 is repeatedly turned on and off, and a current having a sawtooth waveform in which the average value becomes substantially constant flows through the circuit including the flash lamp FL. As a result, as shown in FIG. 11, the flash lamp FL emits light with a substantially flat output waveform in which the light emission output is within the range of fluctuation within ± 30% from the target value L1. The process in which the flash lamp FL emits light with such a substantially flat output waveform is the constant output irradiation process, and the light irradiation time t2 is in the range of 5 milliseconds to 100 milliseconds. That is, the constant power irradiation step is a step of maintaining the light emission output of the flash lamp FL within a range of fluctuation within ± 30% from the target value L1 in the range of 5 milliseconds to 100 milliseconds.

  Subsequently, the pulse generator 31 intermittently outputs a plurality of pulses PC having a longer interval than the plurality of pulses PB to the gate of the switching element 96. As a result, a current having a sawtooth waveform in which the current value decreases as a whole flows through the circuit including the flash lamp FL while the switching element 96 is repeatedly turned on and off repeatedly. As a result, as shown in FIG. 11, the light emission output from the flash lamp FL attenuates from the target value L1 to zero. Thus, the process in which the light emission output of the flash lamp FL is attenuated from the target value L1 to 0 is the output attenuation process, and the light irradiation time t3 is in the range of 1 to 100 milliseconds. In other words, the output attenuation step is a step in which the light emission output of the flash lamp FL is attenuated from the target value L1 to 0 over a time period of 1 millisecond or more and 100 milliseconds or less. In the present embodiment, the total light irradiation time of the flash lamp FL in one heat treatment, that is, the light irradiation time t1 in the output increasing process, the light irradiation time t2 in the constant output irradiation process, and the output attenuation process. The total of the light irradiation time t3 is 10 milliseconds or more and 1000 milliseconds or less.

  By irradiating light from the flash lamp FL with an output waveform as shown in FIG. 11, the surface temperature of the semiconductor wafer W gradually increases from the preheating temperature T1 to the target processing temperature T2, and then gradually. Lower the temperature. Since the change in the surface temperature of the semiconductor wafer W becomes gradual, thermal damage to the semiconductor wafer W can be reduced and cracking can be prevented. Further, when the surface temperature of the semiconductor wafer W is raised to the target processing temperature T2, the impurities implanted into the source / drain region 12 and / or the extension region 13 of the semiconductor wafer W are sufficiently activated. Is called. Further, the total amount of heat received by the surface of the semiconductor wafer W is increased as compared with the conventional case, and the recovery of defects introduced into the semiconductor wafer W during ion implantation can be promoted. Furthermore, since the surface temperature of the semiconductor wafer W is gradually raised and gradually lowered, the deterioration of the metal gate electrode 15 can be prevented. The processing temperature T2 is 1000 ° C. or higher.

  However, although the surface temperature of the semiconductor wafer W gradually increases and then decreases gradually, this is in comparison with conventional laser annealing and flash lamp annealing, and the total light emission time of the flash lamp FL is Since it is 1000 milliseconds or less, the temperature rises and falls in a significantly shorter time than light irradiation heating using a halogen lamp or the like.

  After the light irradiation heating by the flash lamp FL is completed, the semiconductor wafer W waits for about 10 seconds at the processing position, and then the holding unit 7 is lowered again to the delivery position shown in FIG. Is passed from the holding portion 7 to the support pin 70. Subsequently, the transfer opening 66 closed by the gate valve 185 is opened, and the semiconductor wafer W placed on the support pins 70 is unloaded by the transfer robot outside the apparatus, and the light of the semiconductor wafer W in the heat treatment apparatus 1 is transferred. Irradiation heat treatment is completed.

  As described above, nitrogen gas is continuously supplied to the chamber 6 during the heat treatment of the semiconductor wafer W in the heat treatment apparatus 1, and the supply amount is about 30 liters / minute when the holding unit 7 is located at the processing position. When the holding unit 7 is located at a position other than the processing position, the rate is about 40 liters / minute.

  In the present embodiment, as shown by the solid line in FIG. 11, the light emission output of the flash lamp FL is increased to the target value L1 over a time period of 1 millisecond or more and 100 milliseconds or less, and then from the target value L1. Within a range of fluctuation within ± 30%, 5 milliseconds or more and 100 milliseconds or less are maintained, and thereafter, it is attenuated from the target value L1 to 0 over a period of 1 milliseconds or more and 100 milliseconds or less. That is, as compared with the conventional flash lamp annealing shown by the dotted line in FIG. 11, the light emission output of the flash lamp FL is gradually increased and kept constant for a while and then gradually decreased. As a result, the total amount of heat received on the surface of the semiconductor wafer W increases more than before, but the surface temperature rises more slowly than before and then gradually falls. As a result, it is possible to both activate the implanted impurities and recover defects introduced during ion implantation while suppressing damage to the semiconductor wafer W.

  Further, as in this embodiment, when the gate electrode 15 is formed and then the extension region 13 and the source / drain region 12 are formed and light irradiation heat treatment is performed by the flash lamp FL (in the case of a so-called gate first process). In addition, the gate electrode 15 can be prevented from being deteriorated.

  While the embodiments of the present invention have been described above, the present invention can be modified in various ways other than those described above without departing from the spirit of the present invention. For example, the output waveform of the light emission output of the flash lamp FL is not limited to the example of FIG. 11, but may be as shown in FIGS. 12 to 15 also show conventional single-pulse light emission output profiles with dotted lines. 12 to 15, the total light irradiation time of the flash lamp FL in one heat treatment is not less than 10 milliseconds and not more than 1000 milliseconds.

  In the example shown in FIG. 12, after increasing the light emission output of the flash lamp FL to the target value L1 at the same ascending rate, the constant output irradiation step and the subsequent output attenuation step similar to those in the above embodiment are performed. Is going. Specifically, after the pulse generator 31 outputs a relatively long single pulse instead of the plurality of pulses PA, the plurality of pulses PB and the plurality of pulses PC similar to those in FIG. Output to the gate. As a result, the light emission output of the flash lamp FL is raised to the target value L1, and then maintained within the range of fluctuation within ± 30% from the target value L1, and then maintained at 5 milliseconds to 100 milliseconds, and thereafter 1 millimeter. Attenuation is performed from the target value L1 to 0 over a period of time not less than the second and not more than 100 milliseconds.

  If the light irradiation heat treatment is performed from the flash lamp FL with the light emission output profile shown in FIG. 12, the temperature rise of the surface temperature of the semiconductor wafer W becomes somewhat rapid, but the temperature drop is moderate, and the surface is similar to the above embodiment. The total amount of heat received increases from the conventional level. As a result, substantially the same effect as the above embodiment can be obtained.

  In the example shown in FIG. 13, after performing the same output increasing process as that in the above embodiment and the subsequent constant output irradiation process, the energization to the flash lamp FL is completely stopped to reduce the light emission output to zero. Yes. Specifically, after the pulse generator 31 outputs a plurality of pulses PA and a plurality of pulses PB similar to those in FIG. 10A to the gate of the switching element 96, the pulse output is stopped. As a result, the light emission output of the flash lamp FL is increased from 0 to the target value L1 over a time period of 1 millisecond or more and 100 milliseconds or less, and subsequently within a range of fluctuation within ± 30% from the target value L1. 5 to 100 milliseconds and then rapidly decreases to zero.

  When the light irradiation heat treatment is performed from the flash lamp FL with the light emission output profile shown in FIG. 13, the temperature of the surface of the semiconductor wafer W is slightly decreased, but the temperature is increased gradually. The total amount of heat received increases from the conventional level. As a result, substantially the same effect as the above embodiment can be obtained.

  In the example shown in FIG. 14, the light emission output of the flash lamp FL is reduced in two stages after the output increase process similar to that in the above embodiment. Specifically, first, the pulse generator 31 outputs a plurality of pulses PA similar to those in FIG. 10A to the gate of the switching element 96, whereby the light emission output of the flash lamp FL increases from 0 to the target value L1. The ascent process is executed. The light irradiation time t1 in the output increasing process is in the range of 1 millisecond or more and 100 milliseconds or less. That is, in the output increasing process, the light emission output of the flash lamp FL is increased from 0 to the target value L1 (first target value) over a time period of 1 millisecond or more and 100 milliseconds or less.

  Next, the pulse generator 31 intermittently outputs a plurality of pulses similar to the plurality of pulses PB in FIG. 10A, so that the light emission output is within a range of fluctuation within ± 30% from the target value L1. The first constant output irradiation process is performed in which the flash lamp FL emits light with a substantially flat output waveform falling within the range. The light irradiation time t4 in the first constant output irradiation step is in the range of 5 milliseconds to 100 milliseconds. In other words, in the first constant output irradiation step, the light emission output of the flash lamp FL is maintained within a range of fluctuation within ± 30% from the target value L1 and not less than 5 milliseconds and not more than 100 milliseconds.

  Next, the pulse generator 31 intermittently outputs a plurality of pulses similar to the plurality of pulses PC of FIG. 10A, so that the light emission output of the flash lamp FL changes from the target value L1 to the target value L2 (second value). A first output attenuation step is performed to attenuate to a target value. The target value L2 is smaller than the target value L1. The light irradiation time t5 in the first output attenuation step is in the range of 1 millisecond or more and 100 milliseconds or less. That is, in the first output attenuation step, the light emission output of the flash lamp FL is attenuated from the target value L1 to the target value L2 over a time period of 1 millisecond or more and 100 milliseconds or less.

  Subsequently, the pulse generator 31 intermittently outputs a plurality of pulses similar to the plurality of pulses PB in FIG. 10A, so that the light emission output is within a fluctuation range within ± 30% from the target value L2. The second constant output irradiation process is performed in which the flash lamp FL emits light with a substantially flat output waveform that falls within the range. The light irradiation time t6 in the second constant output irradiation step is in the range of 5 milliseconds to 100 milliseconds. In other words, in the second constant power irradiation step, the light emission output of the flash lamp FL is maintained within a range of fluctuation within ± 30% from the target value L2 in the range of 5 milliseconds to 100 milliseconds.

  Thereafter, the pulse generator 31 intermittently outputs a plurality of pulses similar to the plurality of pulses PC of FIG. 10A, whereby the light emission output of the flash lamp FL is attenuated from the target value L2 to zero. A two-output attenuation process is performed. The light irradiation time t7 in the second output attenuation step is in the range of 1 millisecond or more and 100 milliseconds or less. That is, in the second output attenuation step, the light emission output of the flash lamp FL is attenuated from the target value L2 to 0 over a time period of 1 millisecond or more and 100 milliseconds or less. By executing these steps, the flash lamp FL emits light with a light emission output profile as shown by the solid line in FIG.

  Even if the light irradiation heat treatment is performed from the flash lamp FL with the light emission output profile shown in FIG. 14, the total heat received on the surface of the semiconductor wafer W is increased more than before, but the surface temperature is gradually increased from the conventional temperature. Decrease the temperature slowly. As a result, it is possible to both activate the implanted impurities and recover defects introduced during ion implantation while suppressing damage to the semiconductor wafer W.

  Further, in the example shown in FIG. 15, after the light emission output of the flash lamp FL is increased to the target value L3 at the same ascending rate, the light emission output of the flash lamp FL is gradually reduced. Specifically, first, the pulse generator 31 outputs a relatively long single pulse to the gate of the switching element 96 instead of the plurality of pulses PA in FIG. An output increasing process that increases from 0 to the target value L3 is executed. The target value L3 is approximately the same as the peak value of the light emission output in the conventional single pulse. The light irradiation time t8 in the output increasing process is 5 milliseconds or less. That is, in the output increasing process of FIG. 15, the light emission output of the flash lamp FL is increased from 0 to the target value L3 when it is 5 milliseconds or less.

  Thereafter, the pulse generator 31 intermittently outputs a plurality of pulses similar to the plurality of pulses PC of FIG. 10A, whereby the light emission output of the flash lamp FL is attenuated from the target value L3 to 0. Execute the process. The light irradiation time t9 in the output attenuation process is in the range of 1 millisecond or more and 100 milliseconds or less. That is, in the output attenuation step, the light emission output of the flash lamp FL is attenuated from the target value L3 to 0 over a time period of 1 millisecond or more and 100 milliseconds or less. By executing these steps, the flash lamp FL emits light with a light emission output profile as shown by the solid line in FIG.

  If the light irradiation heat treatment is performed from the flash lamp FL with the light emission output profile shown in FIG. 15, the temperature rise of the surface of the semiconductor wafer W is rapid, but the temperature drop is gradual, and the surface receives the same as in the above embodiment. The total amount of heat increases from the conventional level. As a result, substantially the same effect as the above embodiment can be obtained.

The light emission output profiles illustrated in FIGS. 11 to 15 may be properly used depending on the purpose of the light irradiation heat treatment. The light emission output profile (FIGS. 11, 13, and 14) including a pattern in which the light emission output gradually rises raises the surface temperature of the semiconductor wafer W gently, so that the damage to the semiconductor wafer W is small and the semiconductor wafer is reduced. Effective for preventing cracking of W. In addition, the light emission output profile (FIGS. 11, 12, 14, and 15) including a pattern in which the light emission output gradually decreases is effective for defect recovery . The light emission output profile shown in FIG. 11 is suitable when the gate electrode 15 is a metal, and the light emission output profile shown in FIG. 15 is suitable when the material of the gate electrode 15 is polysilicon.

  In the above embodiment, the source / drain region 12 is formed after the gate electrode 15 is formed. However, the extension region 13 and the source / drain region 12 are formed, and the light irradiation heat treatment by the flash lamp FL is performed. The gate electrode 15 may be formed after performing the above (so-called gate last process). FIG. 16 is a flowchart showing an outline of a procedure for forming elements on the semiconductor wafer W in the gate-last process.

  In the procedure of FIG. 16, first, impurities are implanted into the extension region 13 of the silicon substrate 11 by ion implantation (step S11). Subsequently, impurities are also implanted into the source / drain regions 12 of the silicon substrate 11 (step S12). At this stage, the gate electrode 15 is not yet formed. Then, a light irradiation heat treatment is performed by the heat treatment apparatus 1 on the surface of the semiconductor wafer W including the extension regions 13 and the source / drain regions 12 into which the impurities have been implanted, and the implanted impurities are activated (step S13). After the impurity activation process is completed, the gate electrode 15 is formed (step S14). Even if the light irradiation heat treatment (step S13) of such a gate-last process is performed with the light emission output profile shown in FIG. 11 from the flash lamp FL, the total amount of heat received by the surface of the semiconductor wafer W is increasing from the conventional level. However, the surface temperature rises more slowly than before, and then gradually falls. As a result, it is possible to both activate the implanted impurities and recover defects introduced during ion implantation while suppressing damage to the semiconductor wafer W. In addition, you may make it perform light irradiation heat processing of step S13 by the light emission output profile as shown in FIGS.

  In the above embodiment, the field effect transistor is formed on the semiconductor wafer W. However, the present invention is not limited to this, and also when forming other types of transistors or semiconductor elements such as thyristors and diodes. The light irradiation heat treatment according to the present invention may be performed on the surface of the semiconductor wafer W into which impurities are implanted.

  The setting of the waveform of the pulse signal is not limited to inputting parameters such as the pulse width one by one from the input unit 33. For example, the operator directly inputs the waveform graphically from the input unit 33. Alternatively, the waveform previously set and stored in the storage unit such as a magnetic disk may be read, or may be downloaded from the outside of the heat treatment apparatus 1.

  In the above embodiment, the voltage is applied to the trigger electrode 91 in synchronization with the timing at which the pulse signal is turned on. However, the timing at which the trigger voltage is applied is not limited to this. You may make it apply at fixed intervals irrespective of the waveform of a signal. If the current width of the pulse signal is narrow and the current value of the current flowing through the flash lamp FL by a certain pulse remains above a predetermined value, energization is started by the next pulse. Since the current continues to flow through the lamp FL, it is not necessary to apply a trigger voltage for each pulse. As shown in FIG. 10A of the above embodiment, when all the space widths of the pulse signal are narrow, the trigger voltage may be applied only when the first pulse is applied. A current waveform as shown in FIG. 10B can be formed only by outputting the pulse signal of FIG. 10A to the gate of the switching element 96 without applying a voltage. That is, the application timing of the trigger voltage is arbitrary as long as the current flows through the flash lamp FL when the pulse signal is turned on.

  In the above embodiment, the lamp house 5 is provided with 30 flash lamps FL. However, the present invention is not limited to this, and the number of flash lamps FL can be any number. The flash lamp FL is not limited to a xenon flash lamp, and may be a krypton flash lamp.

  In the above-described embodiment, the IGBT is used as the switching element 96. However, the present invention is not limited to this, and other transistors other than the IGBT may be used. The waveform of the input pulse signal may be used. Any element can be used as long as the circuit can be turned on and off accordingly. However, since a considerable amount of power is consumed for the light emission of the flash lamp FL, it is preferable to employ an IGBT or a GTO (Gate Turn Off) thyristor suitable for handling a large amount of power as the switching element 96.

  Further, as long as the light emission can be performed with the light emission output profiles shown in FIGS. 11 to 15, the circuit configuration may be different from that of FIG. 6. For example, a plurality of power supply circuits having different coil constants may be provided as one. It may be connected to the flash lamp FL.

  Further, in the above embodiment, the light irradiation heat treatment is performed by the heat treatment apparatus 1 provided with the flash lamp FL, but the present invention is not limited to this, and the light irradiation heat treatment similar to the above embodiment is performed by the laser annealing apparatus. May be performed. That is, as long as light irradiation can be performed with the light emission output profiles shown in FIGS. 11 to 15, the light source is not limited to the flash lamp FL, and light with an irradiation time of 10 milliseconds to 1000 milliseconds. What is necessary is just what can be irradiated, for example, a laser may be sufficient.

  The substrate to be processed by the heat treatment apparatus according to the present invention is not limited to a semiconductor wafer, and may be a glass substrate having a silicon film formed on the surface thereof. Further, the technique according to the present invention may be applied to bonding of metal and silicon or crystallization of polysilicon.

DESCRIPTION OF SYMBOLS 1 Heat processing apparatus 3 Control part 4 Holding part raising / lowering mechanism 5 Lamphouse 6 Chamber 7 Holding part 12 Source / drain area 13 Extension area 15 Gate electrode 16 Side wall 31 Pulse generator 32 Waveform setting part 33 Input part 60 Upper opening 61 Chamber window 65 Heat treatment space 71 Hot plate 72 Susceptor 91 Trigger electrode 92 Glass tube 93 Capacitor 94 Coil 95 Power supply unit 96 Switching element 97 Trigger circuit FL Flash lamp W Semiconductor wafer

Claims (5)

A method of manufacturing a semiconductor device, wherein a substrate into which impurities are implanted is heated to activate the impurities,
An impurity implantation step of implanting the impurity into a predetermined region of the semiconductor devices formed on the substrate,
A light irradiation step of irradiating the light conducting the heating at the surface 10 milliseconds to 1,000 milliseconds following the time range of the substrate including the predetermined region,
With
The light irradiation step includes
An output increasing step for increasing the light emission output to a target value over a period of 1 millisecond or more and 100 milliseconds or less;
A constant output irradiation step of maintaining the light emission output within a range of fluctuation within ± 30% from the target value after the output increasing step;
An output attenuation step of attenuating the light emission output over a period of 1 millisecond or more and 100 milliseconds or less after the constant power irradiation step;
Only including,
In the light irradiation step, a method of manufacturing a semiconductor device characterized by controlling a current flowing through the flash lamp by applying a pulse signal to the gate of the switching element connected to the flash lamp. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor element is a field effect transistor;
The method of manufacturing a semiconductor device, wherein the predetermined region is a source / drain region . In the manufacturing method of the semiconductor device according to claim 2 ,
The method of manufacturing a semiconductor device, wherein the predetermined region further includes an extension region of the field effect transistor . In the manufacturing method of the semiconductor element of Claim 2 or Claim 3 ,
A method for manufacturing a semiconductor device, further comprising a gate electrode formation step of forming a gate electrode of the field effect transistor on the surface of the substrate before the light irradiation step . In the manufacturing method of the semiconductor element in any one of Claims 1-4 ,
A method of manufacturing a semiconductor device, wherein the light irradiation in the light irradiation step is performed from a flash lamp .

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