JP5811544B2 - Integrated device, information processing system, and processing method - Google Patents

Description

  The present invention relates to an electronic device, an integrated device, an information processing system, and a processing method.

  An example of a technique related to duplexing of buses is described in Patent Document 1. Patent Document 1 describes duplexing using one system bus and one serial bus.

  An example of a technique related to a general-purpose input / output register connected to the same bus as the CPU is described in Patent Document 2. In the technique of Patent Document 2, an external connection terminal of a semiconductor integrated circuit and a debug system are connected. In the normal mode other than the debug mode of this technique, transmission / reception to / from the general-purpose input / output register is performed via the external connection terminal. In the debug mode of this technique, the external connection terminal is used for supplying a clock.

JP-A-9-81469 JP 2007-34881 A

  The technique described in Patent Document 1 has a problem that if one serial bus does not operate normally, control using the serial bus cannot be performed, the entire operation cannot be performed, and reliability is low.

  In the technique described in Patent Document 2, there is only one bus. Therefore, if the bus does not operate normally, the entire operation cannot be performed and the reliability is low.

  An object of the present invention is to provide an electronic device, an integrated device, an information processing system, and a processing method that solve the above problems.

  The electronic device of the present invention is directly connected to the first bus, and is connected to the second bus via a second electronic device connected to the second bus. And access from the third electronic device connected to the second bus directly from the first bus or via the second bus and the second electronic device. receive.

  The processing method of the present invention receives access to the first electronic device directly from the first bus or via the second bus and the second electronic device.

  The present invention has the effect of improving reliability.

It is a block diagram which shows the structure of 1st Embodiment. It is a block diagram which shows the structure of 2nd Embodiment. It is a flowchart which shows operation | movement of 2nd Embodiment. It is a block diagram which shows the structure of the information processing system with which 3rd Embodiment is applied. It is a flowchart which shows operation | movement of 3rd Embodiment. It is a detailed block which shows the structure of a slave device. It is a detailed block which shows the structure of a slave device. It is a detailed block diagram which shows the structure of a selector. It is a detailed block diagram which shows the structure of a register selector. It is a detailed block diagram which shows the structure of an arbitration circuit.

  Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the first exemplary embodiment of the present invention. Referring to FIG. 1, the electronic device 001 of the first embodiment is directly connected to the first bus, and is connected to the second bus via the second electronic device.

  The electronic device 001 accesses the first bus and the third electronic device connected to the second bus directly from the first bus or the second bus and the second bus. Receive via electronic device.

  Next, the effect of the first embodiment will be described.

  The first embodiment has a configuration in which the electronic device 001 can be accessed via the second bus and the second electronic device even if the first bus does not operate normally. Therefore, the first embodiment has an effect of improving the reliability.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 2 is a block diagram showing the configuration of the second embodiment. Referring to FIG. 2, the integrated device 01A of the second embodiment includes an electronic device 10A, an electronic device 20A, an electronic device 30A, an electronic device 40A, an electronic device 80A, a bus 50A, a bus 60A, and a connection line 05A. Including. The electronic device 30A and the electronic device 40A may not exist. The electronic device 10A and the electronic device 20A are the electronic device 001 of the first embodiment. The bus 50A and the bus 60A are the first bus and the second bus of the first embodiment, respectively.

  The electronic device 80A is connected to the electronic device 10A and the electronic device 30A via the bus 50A, and is connected to the electronic device 20A and the electronic device 40A via the bus 60A. The electronic device 10A and the electronic device 20A are connected via a connection line 05A.

  Next, the operation of the second embodiment will be described. FIG. 3 is a flowchart showing the operation of the second embodiment.

  The electronic device 80A tries to access the electronic device 10A (step A1 / YES in FIG. 3). Here, “access” means, for example, outputting a request, writing, reading, and the like. If the bus 50A connected to the electronic device 10A is not operating normally (step A2 / NO), the electronic device 80A outputs a request for the electronic device 10A on the bus 60A (step A3).

  When the electronic device 20A receives a request for the electronic device 10A from the electronic device 80A, the electronic device 20A outputs the request to the electronic device 10A via the connection line 05A (step A4).

  When the electronic device 10A receives the request from the electronic device 80A from the electronic device 20A via the connection line 05A (step A6 / NO), the electronic device 10A processes the request and outputs a response to the electronic device 80A via the connection line 05A. (Step A7).

  When the electronic device 20A receives a response from the electronic device 10A to the electronic device 80A via the connection line 05A, the electronic device 20A outputs the response to the electronic device 80A via the bus 60A (step A8). When the electronic device 80A receives the response via the bus 60A, the electronic device 80A performs processing for the response (step A10).

  When the bus 50A to which the electronic device 10A is connected is operating normally (step A2 / YES), the electronic device 80A directly outputs a request for the electronic device 10A to the electronic device 10A on the bus 50A ( Step A5). When the electronic device 10A receives the request from the electronic device 80A via the bus 50A, the electronic device 10A processes the request and outputs a response to the electronic device 80A to the electronic device 80A via the bus 50A (step A9). When the electronic device 80A receives the response via the bus 50A, the electronic device 80A performs processing for the response (step A10).

  Examples of the reason why the bus 50A does not operate normally include malfunction of the bus 50A itself, malfunction due to failure of the electronic device 30A, and the like.

  Further, when the electronic device 80A tries to access the electronic device 20A and the bus 60A to which the electronic device 20A is connected does not operate normally, the electronic device 80A passes through the bus 50A and the electronic device 10A. Output a request to Also at this time, the connection line 05A is used.

  Further, it is possible to connect the electronic device 30A and the electronic device 40A with a connection line (not shown) to operate the electronic device 10A and the electronic device 20A, respectively.

  In the above description, the number of buses is 2, but the number of buses is not limited. There is no limit to the number of electronic devices connected to the bus. Electronic devices on different buses can be connected by connection lines in any combination.

  Next, the effect of the second embodiment will be described. In the second embodiment, an electronic device connected to a different bus is connected by a connection line, and an attempt is made to access a target electronic device on a certain bus. In this configuration, the request is delivered to the target electronic device via the electronic device and the connection line.

  Therefore, the second embodiment has an effect of improving reliability because the target electronic device can be accessed even if the operation of the bus to which the target electronic device is connected is not normal.

  Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 4 is a block diagram illustrating a configuration of an information processing system 020 to which the third exemplary embodiment is applied. Referring to FIG. 4, the information processing system 020 includes an integrated device 010, a CPU 701 (Central Processing Unit), a CPU 702, a CPU 703, a CPU 704, a system bus 910, a main storage device 920, and a bus adapter 930.

  Further, the information processing system 020 includes an I / O bus 940, an I / O processor 951, an I / O processor 952, an I / O device 961, an I / O device 962, an I / O device 963, and an I / O device. 964.

  The integration device 010 is one type of the integration device 01A of the second embodiment. The integrated device 010 includes a service processor 800, a slave device 100, a slave device 200, a slave device 300, a slave device 400, a serial bus 500, a serial bus 600, and a connection line 050. The serial bus 500 and the serial bus 600 can realize, for example, specifications of I2C (Inter-Integrated Circuit) and SMBus (System Management Bus).

  The service processor 800 and the slave devices 100 to 400 are each one of the electronic device 80A and the electronic device 10A to the electronic device 40A of the second embodiment. The serial bus 500, the serial bus 600, and the connection line 050 are each one of the bus 50A, the bus 60A, and the connection line 05A of the second embodiment.

  The service processor 800 is a processor that performs management, operation, configuration control, monitoring, and the like of the information processing system 020 via the slave device 100 to the slave device 400, for example. For example, in response to an instruction from the service processor 800, the slave devices 100 and 200 cause the CPUs 701 to 704 to execute reset, clock selection, and the like.

  The service processor 800 accesses the slave device 100 and the slave device 300 directly via the serial bus 500. The service processor 800 accesses the slave device 200 and the slave device 400 directly via the serial bus 600.

  Slave device 100 and slave device 200 are directly connected via connection line 050. The slave device 100 and the slave device 300 are connected to the CPU 701 and the CPU 702, and exchange control information and data. The slave device 100 and the slave device 300 have different roles. The slave device 200 and the slave device 400 are connected to the CPU 703 and the CPU 704, and exchange control information and data. The slave device 200 and the slave device 400 have different roles.

  Further, a system in which the slave device 100 and the slave device 200 are both connected to the CPUs 701 to 704 and play different roles is also possible. The slave device 100 to the slave device 400 include a main storage device 920, a bus adapter 930, an I / O processor 951, an I / O processor 952, an I / O device 961 to an I / O device 964 for overall management. Can be connected. That is, the connection is not limited to that shown in FIG.

  Next, the operation of the third embodiment will be described with reference to the drawings. FIG. 5 is a flowchart showing the operation of the third embodiment.

  The service processor 800 tries to access the slave device 100 (step B1 / YES in FIG. 3). If the serial bus 500 to which the slave device 100 is connected does not operate normally (step B2 / NO), the service processor 800 outputs a request for the slave device 100 on the serial bus 600 (step B3). .

  When the slave device 200 receives a request for the slave device 100 from the service processor 800, the slave device 200 outputs the request to the slave device 100 via the connection line 050 (step B4).

  When the slave device 100 receives a request from the service processor 800 from the slave device 200 via the connection line 050 (step B6 / NO), the slave device 100 processes the request and outputs a response to the electronic device 80A via the connection line 050. (Step B7).

  When the slave device 200 receives a response from the slave device 100 to the service processor 800 via the connection line 050, the slave device 200 outputs the response to the service processor 800 via the serial bus 600 (step B8). When the service processor 800 receives the response via the serial bus 600, the service processor 800 performs processing for the response (step B10).

  When the serial bus 500 to which the slave device 100 is connected is operating normally (step B2 / YES), the service processor 800 directly outputs a request for the slave device 100 to the slave device 100 on the serial bus 500. (Step B5).

  When receiving the request from the service processor 800 via the serial bus 500, the slave device 100 processes the request and outputs a response to the service processor 800 to the service processor 800 via the serial bus 500 (step B9). When the service processor 800 receives the response via the serial bus 500, the service processor 800 performs processing for the response (step B10).

  Next, the slave device 100 and the slave device 200 of the integrated device 010 will be described in detail.

  FIG. 6 is a detailed block diagram showing the configuration of the slave device 100. FIG. 7 is a detailed block diagram showing the configuration of the slave device 200. The slave device 100 in FIG. 6 and the slave device 200 in FIG. 7 are connected by the connection line 050 as indicated by the same number in the figure.

  Referring to FIG. 6, the slave device 100 includes a selector 101, a data register 102, an address register 103, a state monitoring circuit 104, a self device identification circuit 105, another device identification circuit 106, a register selector 107, and an arbitration circuit 108. . Furthermore, the slave device 100 includes an output generation register 109, an input / output register 110, an input / output register 111,..., And an input / output register 11n.

  Referring to FIG. 7, the slave device 200 includes a selector 201, a data register 202, an address register 203, a state monitoring circuit 204, a self device identification circuit 205, another device identification circuit 206, a register selector 207, and an arbitration circuit 208. . Further, the slave device 200 includes an output generation register 209, an input / output register 210, an input / output register 211,..., And an input / output register 21n.

  The input / output registers 110 to 21n may be general-purpose input / output registers as described in Patent Document 2, for example.

  In the slave device 100 and the slave device 200, elements having the same name have the same function.

  The request from the service processor 800 includes, for example, start information, slave address, write designation information (or read designation information), data (internal address), data (write data), and end information. The start information indicates that the service processor 800 starts a request for the slave device 100 to the slave device 400.

  The slave address indicates one slave device to be requested (written or read) and one input / output register. The write designation information indicates that “the request is a write”, and the read designation information indicates that “the request is a read”.

  Data (internal address) specifies the internal address of the input / output register indicated by the slave address. Data (write data) is data to be written in the area of the slave address and the internal address of the input / output register designated by the data (internal address) in the case of a write request. The end information indicates that the service processor 800 ends the request for the slave devices 100 to 400.

  The selector 101 of the slave device 100 is connected to the serial bus 500 or the serial bus 600. The selector 101 selects a request from the service processor 800 via the serial bus 500 or the serial bus 600 based on a switching signal from the arbitration circuit 208 and outputs the request to the inside of the slave device 100.

  That is, the selector 101 outputs the selected request to the data register 102, the address register 103, and the state monitoring circuit 104. The selector 101 also selects and outputs whether the data from the output generation register 109 is output to the service processor 800 via the serial bus 500 or the serial bus 600 according to the switching signal output from the arbitration circuit 208. To do.

  The selector 101 receives a control signal indicating an output from the output generation register 109. The selector 101 outputs to the serial bus 500 or the serial bus 600 only when the control signal indicating the output indicates validity (ON).

  FIG. 8 is a detailed block diagram illustrating an example of the configuration of the selector 101. Referring to FIG. 8, the buffers 120 to 123 are, for example, tristate buffers. Control signals to the buffers 120 to 123 are generated by the gate 124, the gate 125, and AND circuits 126, AND 127, AND 128, and AND 129 which are AND circuits.

  When the control signal indicating the output from the output generation register 109 is ON (logic “1”) and the switching signal from the arbitration circuit 208 indicates the serial bus 500 (logic “0”), the buffer 120 generates the output. Data from the register 109 is output to the serial bus 500.

  When the control signal indicating the output is ON and the switching signal indicates the serial bus 600 (logic “1”), the buffer 122 transfers the data from the output generation register 109 to the serial bus 600 via the slave device 200. Output.

  When the control signal indicating the output is off (logic “0”) and the switching signal indicates the serial bus 500, the buffer 121 receives the request on the serial bus 500 and outputs it to the inside.

  The data register 102 stores the data from the selector 101 and outputs the data to the register selector 107 and the input / output registers 110 to 11n.

  The address register 103 stores the slave address from the selector 101 and outputs it to the own device identification circuit 105, the other device identification circuit 106, the register selector 107, and the register selector 207.

  The state monitoring circuit 104 monitors whether the slave device 100 is operating based on the slave address, start information, end information, and the like from the selector 101, and outputs the operation state of the slave device 100 to the arbitration circuit 208.

  The own device identification circuit 105 identifies whether the received slave address matches the slave address corresponding to the input / output register 110 to the input / output register 11n in the slave device 100, and outputs the identification result to the register selector 107. .

  The other device identification circuit 106 identifies whether or not the received slave address matches the slave address corresponding to the input / output register 210 to the input / output register 21n in the slave device 200, and outputs the identification result to the arbitration circuit 108. .

  The register selector 107 stores the first data (internal address) output from the data register 102 in itself. The register selector 107 also stores the internal address stored in itself, the slave address from the address register 103, the slave address from the address register 203, the identification result from the own device identification circuit 105, and the switching from the arbitration circuit 208. Based on the signal, it is determined in which of the input / output register 110 to the input / output register 11n data is to be written or from which data is to be read, and is output as a selection signal.

  FIG. 9 is a detailed block diagram illustrating an example of the configuration of the register selector 107. Referring to FIG. 9, the internal address register 171 stores data (internal address) from the data register 102. The selection circuit 172 selects and outputs either the address register 103 or the slave address from the address register 203 based on the switching signal from the arbitration circuit 208. The internal address register 171 outputs a signal indicating that the internal address is stored to the ACK generation circuit 174.

  The selection signal generation circuit 173 generates and outputs selection signals to the input / output registers 110 to 11n based on the slave address from the selection circuit 172 and the internal address from the internal address register 171. If the identification result from the self device identification circuit 105 indicates a match, the ACK generation circuit 174 generates an ACK signal when the internal address is stored in the internal address register 171 and outputs the ACK signal to the output generation register 109.

  That is, when the register selector 107 receives a match as an identification result from its own device identification circuit 105, the register selector 107 adopts the slave address stored in the address register 103, and uses the input / output register 110 to the input / output register 11n as selection signals. Output to.

  Further, when the register selector 107 receives a mismatch as the identification result and the switching signal from the arbitration circuit 208 indicates the serial bus 600, the input / output registers 110 to 11n using the slave address from the address register 203 as a selection signal. Output to.

  The arbitration circuit 108 generates a response to the service processor 800 based on the identification result from the other device identification circuit 106 and the operation state of the slave device 200 from the state monitoring circuit 204. That is, the arbitration circuit 108 responds with an ACK (acknowledgement) or does not respond (NACK (non-acknowledgement)).

  The arbitration circuit 108 outputs a switching signal to the selector 201 and the register selector 207.

  FIG. 10 is a detailed block diagram illustrating an example of the configuration of the arbitration circuit 108. Referring to FIG. 10, upon receiving an identification result indicating a match from the other device identification circuit 106, the arbitration subcircuit 181 outputs an arbitration result according to the operation state of the slave device 200 from the state monitoring circuit 204. When the slave device 200 is operating, an arbitration result indicating that the slave device 200 has lost arbitration is output. When the slave device 200 is not operating, an arbitration result indicating that the arbitration is won is output.

  The switching signal generation circuit 182 generates a switching signal according to the arbitration result from the arbitration partial circuit 181. The switching signal generation circuit 182 outputs a selection signal for selecting the serial bus 500 to the selector 201 when the arbitration result wins and selects the serial bus 600 when the arbitration result is lost.

  The ACK generation circuit 183 generates an ACK signal according to the arbitration result from the arbitration subcircuit 181. If the arbitration result is a win, an ACK signal is generated. If the arbitration result is a loss, nothing is done (that is, ACK is not transmitted).

  That is, when the service processor 800 writes data to the input / output registers 21n in the slave device 200, the selector 201 selects the serial bus 500 if the slave device 200 is not operating. Become.

  The input / output registers 110 to 11n write data to the area of the data register 102 designated by the internal address of the selection signal from the register selector 107, or read (output) data to the output generation register 109.

  For example, the input / output register 110 to the input / output register 11n are connected to the CPU 701 and the CPU 702, and exchange control information and data.

  Therefore, the input / output register 110 to the input / output register 11n are composed of an input register, an output register, an input / output switching register, an input / output inversion register, and the like, and an internal address corresponding to each register is assigned. .

  The output generation register 109 generates an output signal based on the data and the ACK signal from the register selector 107, the arbitration circuit 108, or the input / output register 110 to the input / output register 11n, and outputs the output signal to the selector 101. This output signal includes a control signal indicating an output to the serial bus 500 and the serial bus 600.

  Next, operations of the slave device 100 and the slave device 200 will be described.

  The service processor 800 writes to or reads from the input / output register 110 in the slave device 100. The slave device 100 and the slave device 200 operate differently depending on whether the slave address specified by the service processor 800 specifies an input / output register in its own device or an input / output register in another device. .

  In the following, description will be given in the order of writing and reading when an input / output register in the device is designated, and writing and reading when an input / output register in another device is designated.

  Note that description of start information and end information is omitted.

  [Case 1] The operation when the service processor 800 writes to the input / output register 110 in the slave device 100 via the serial bus 500 (step B2 / YES in FIG. 5) will be described.

  The slave device 100 receives the slave address indicating the input / output register 110 and the write designation information from the service processor 800 via the serial bus 500. The slave address is stored in the address register 103 via the selector 101. The own device identification circuit 105 and the other device identification circuit 106 receive the slave address from the address register 103 and identify the address of the device.

  In this case, since the slave address indicates the input / output register 110, the own device identification circuit 105 identifies the own device address and outputs an identification result indicating coincidence. A signal indicating its own device address is output to the register selector 107. The register selector 107 sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, and the serial bus 500 to notify that data preparation is ready.

  Next, the service processor 800 outputs data (internal address) to the selector 101 via the serial bus 500. The internal address from the selector 101 is stored in the data register 102 and output to the register selector 107. The register selector 107 stores the internal address, and sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, and the serial bus 500.

  Next, the service processor 800 outputs data (write data) to the selector 101 via the serial bus 500. Write data is stored in the data register 102 via the selector 101. The register selector 107 selects an area of the input / output register 110 based on the slave address in the address register 103 and the internal address stored in the register selector 107. The input / output register 110 stores the data from the data register 102 in the area selected by the register selector 107. After the data storage is completed, the input / output register 110 sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, and the serial bus 500.

  [Case 2] Next, the operation when the service processor 800 reads from the input / output register 110 in the slave device 100 via the serial bus 500 (step B2 / YES in FIG. 5) will be described.

  In the case of reading, as in the case of writing, the service processor 800 outputs the slave address, the write designation information, and the internal address to the slave device 100 via the serial bus 500. The data register 102 and the register selector 107 store internal addresses.

  Thereafter, since it is a case of reading, the slave address and read designation information are output from the service processor 800 to the slave device 100 via the serial bus 500. The slave address is stored in the address register 103 via the selector 101. The own device identification circuit 105 and the other device identification circuit 106 receive the slave address from the address register 103 and identify the address of the device.

  In this case, since the slave address indicates the input / output register 110, the own device identification circuit 105 identifies the own device address and outputs an identification result indicating coincidence. A signal indicating its own device address is output to the register selector 107.

  The register selector 107 sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, and the serial bus 500 to notify that preparation for reading is completed.

  Next, the register selector 107 selects an area of the input / output register 110 based on the slave address in the address register 103 and the internal address stored therein. The input / output register 110 reads data from the designated area and sequentially outputs the data to the service processor 800 via the output generation register 109, the selector 101, and the serial bus 500.

  [Case 3] Next, the operation when the service processor 800 writes to the input / output register 110 in the slave device 100 via the serial bus 600 (step B2 / NO in FIG. 5) will be described.

  The slave device 200 receives the slave address indicating the input / output register 110 of the slave device 100 and the write designation information from the service processor 800 via the serial bus 600. The slave address is stored in the address register 203 via the selector 201.

  The own device identification circuit 205 and the other device identification circuit 206 receive the slave address from the address register 203 and identify the address of the device. In this case, since the slave address indicates the input / output register 110, the other device identification circuit 206 identifies the other device address and outputs an identification result indicating coincidence to the arbitration circuit 208.

  When the arbitration circuit 208 receives the identification result indicating the coincidence of the other device addresses, the arbitration circuit 208 determines whether the slave device 100 is operating based on the operation state of the slave device 100 from the state monitoring circuit 104. If the slave device 100 is in operation, data cannot be written to the input / output register 110 in the slave device 100. In this case, the arbitration circuit 208 does not output ACK to the service processor 800.

  On the other hand, when the slave device 100 is not in operation, data can be written to the input / output register 110 in the slave device 100. In this case, the arbitration circuit 208 sequentially outputs ACK to the service processor 800 via the output generation register 209, the selector 201, and the serial bus 600.

  Further, the arbitration circuit 208 enables the slave device 100 to receive data (internal address) and data (write data) that are subsequently output from the service processor 800. That is, the arbitration circuit 208 outputs a switching signal for switching the selector 101 to the serial bus 600 side to the selector 101. The selector 101 switches the connection to the serial bus 600 side by the switching signal.

  Next, the service processor 800 outputs data (internal address) to the selector 101 via the serial bus 600. The selector 101 stores the internal address in the data register 102 and outputs it to the register selector 107. The register selector 107 stores the internal address from the data register 102 and sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, the slave device 200, and the serial bus 600.

  Next, the service processor 800 outputs data (write data) to the selector 101 via the serial bus 600 and the slave device 200. Write data is stored in the data register 102 via the selector 101.

  The register selector 107 selects the area of the input / output register 110 based on the slave address in the address register 203 and the internal address stored in itself. The input / output register 110 stores the data from the data register 102 in the area selected by the register selector 107. After the data storage is completed, the input / output register 110 sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, the slave device 200, and the serial bus 600.

  [Case 4] Next, the operation when the service processor 800 reads from the input / output register 110 in the slave device 100 via the serial bus 600 (step B2 / NO in FIG. 5) will be described.

  In the case of reading, as in the case of writing, the slave device 200 receives the slave address indicating the input / output register 110 of the slave device 100 and the write designation information from the service processor 800 via the serial bus 600. The slave address is stored in the address register 203 via the selector 201.

  The own device identification circuit 205 and the other device identification circuit 206 receive the slave address from the address register 203 and identify the address of the device. In this case, since the slave address indicates the input / output register 110, the other device identification circuit 206 identifies the other device address and outputs an identification result indicating coincidence to the arbitration circuit 208.

  When the arbitration circuit 208 receives the identification result indicating the coincidence of the other device addresses, the arbitration circuit 208 determines whether the slave device 100 is operating based on the operation state of the slave device 100 from the state monitoring circuit 104. If the slave device 100 is in operation, data cannot be read from the input / output register 110 in the slave device 100. In this case, the arbitration circuit 208 does not output ACK to the service processor 800.

  On the other hand, when the slave device 100 is not in operation, data can be read from the input / output register 110 in the slave device 100. In this case, the arbitration circuit 208 sequentially outputs ACK to the service processor 800 via the output generation register 209, the selector 201, and the serial bus 600.

  Further, the arbitration circuit 208 enables the slave device 100 to receive data (internal address) that is subsequently output from the service processor 800. That is, the arbitration circuit 208 outputs a switching signal for switching the selector 101 to the serial bus 600 side to the selector 101. The selector 101 switches the connection to the serial bus 600 side by the switching signal.

  Next, the service processor 800 outputs data (internal address) to the selector 101 via the serial bus 600 and the slave device 200. The selector 101 stores the internal address in the data register 102 and outputs it to the register selector 107. The register selector 107 stores the internal address and sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, the slave device 200, and the serial bus 600.

  Next, the service processor 800 outputs the slave address and read designation information to the slave device 100 via the serial bus 600 and the slave device 200. The slave address is stored in the address register 103 via the selector 101 of the slave device 100. The own device identification circuit 105 and the other device identification circuit 106 receive the slave address from the address register 103 and identify the address of the device.

  In this case, since the slave address indicates the input / output register 110, the self device identification circuit 105 identifies the self device address and outputs an identification result indicating coincidence to the register selector 107.

  Next, the register selector 107 sequentially outputs ACK to the service processor 800 via the output generation register 109, the selector 101, the slave device 200, and the serial bus 600 to notify that it is ready for reading.

  Next, the register selector 107 selects an area of the input / output register 110 based on the slave address in the address register 203 and the internal address in the register selector 107. The selected input / output register 110 reads data from the designated area and sequentially outputs the data to the service processor 800 via the output generation register 109, the selector 101, the slave device 200, and the serial bus 600.

  In the above, the service processor 800 only needs to recognize whether the request is output to the slave device 100 via the serial bus 500 or the serial bus 600, and does not need to recognize whether the request is sent via the slave device 200. .

  In addition, the slave device 100 may select whether to output a response to the service processor 800 via the serial bus 500 or the serial bus 600 according to the switching signal from the slave device 200.

  Next, the effect of the third embodiment will be described.

  As described above, in the third embodiment, the input / output registers 110 to 11n and the input / output registers 210 to 21n can be accessed via either the serial bus 500 or the serial bus 600. is there.

  Therefore, even if the serial bus 500 does not operate normally due to a failure of the slave device 300, the input / output registers 110 to 11n in the slave device 100 can be accessed via the serial bus 600 and the slave device 200. .

  That is, the third embodiment has an effect of improving reliability.

  In the third embodiment, the slave device 100 is connected to the CPUs 701 and 702, and the slave device 200 is connected to the CPUs 703 and 704. Therefore, as compared with a configuration in which one slave device is connected to all of the CPUs 701 to 704, the third embodiment has an effect that the number of physical pins of each slave device is reduced and a chip can be easily manufactured. .

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

[Appendix 1]
Connected directly to the first bus, and connected to the second bus via a second electronic device connected to the second bus, the first bus and the second bus Receiving an access from a third electronic device connected to the electronic device directly from the first bus or via the second bus and the second electronic device apparatus.

[Appendix 2]
The first electronic device, the second electronic device, the third electronic device, the first bus, and the second bus, which are the electronic devices according to appendix 1,
An integrated device comprising:

[Appendix 3]
If the first bus does not operate normally, access the first electronic device via the second bus and the second electronic device;
The second electronic device includes the third electronic device that accesses the second electronic device via the first bus and the first electronic device when the second bus does not operate normally. The accumulation device according to attachment 2.

[Appendix 4]
Upon receiving access to the first bus and the second electronic device via the first electronic device, control the second electronic device to receive access via the first bus The first electronic device to
Upon receiving access to the first electronic device via the second bus and the second electronic device, control the first electronic device to receive access via the second bus Said second electronic device to:
The integrated device according to supplementary note 3, characterized by comprising:

[Appendix 5]
The second electronic device, and the first electronic device responding via the second bus for access via the second bus and the second electronic device;
The first electronic device and the second electronic device responding via the first bus with respect to access via the first bus and the first electronic device;
The integrated device according to appendix 4, characterized by comprising:

[Appendix 6]
A first slave device which is the first electronic device including a first input / output register;
A second slave device, which is the second electronic device, including a second input / output register;
When the first bus does not operate normally, the first input / output register is accessed via the second bus and the second slave device;
A service that is the third electronic device that accesses the second input / output register via the first bus and the first slave device when the second bus does not operate normally. A processor;
The accumulation device according to appendix 5, characterized by including:

[Appendix 7]
When access to the second input / output register is received from the service processor via the first bus, an ACK is returned if the second slave device is not operating, and an ACK if the second slave device is operating. The first slave device not responding with
When access to the first input / output register is received from the service processor via the second bus, an ACK is returned if the first slave device is not operating, and an ACK is received if operating. The second slave device not responding with
The stacking device according to appendix 6, characterized by comprising:

[Appendix 8]
The accumulation device according to appendix 7,
A first CPU connected to the first slave device;
A second CPU connected to the second slave device;
An information processing system comprising:

[Appendix 9]
A processing method comprising: receiving an access to a first electronic device directly from a first bus or via a second bus and a second electronic device.

[Appendix 10]
If the first bus does not operate normally, access the first electronic device via the second bus and the second electronic device;
The processing method according to appendix 9, wherein when the second bus does not operate normally, the second electronic device is accessed via the first bus and the first electronic device.

[Appendix 11]
Upon receiving access to the first bus and the second electronic device via the first electronic device, control the second electronic device to receive access via the first bus And
Upon receiving access to the first electronic device via the second bus and the second electronic device, control the first electronic device to receive access via the second bus The processing method according to appendix 10, wherein:

[Appendix 12]
For access via the second bus and the second electronic device, respond via the second electronic device and the second bus;
The first electronic device and the second electronic device responding via the first bus with respect to access via the first bus and the first electronic device;
The processing method according to appendix 11, characterized by comprising:

[Appendix 13]
When access to the second input / output register is received via the first bus, if the second electronic device is not operating, it responds with ACK, and if it is operating, it does not respond with ACK. ,
When access to the first input / output register is received via the second bus, an ACK is returned if the first electronic device is not operating, and an ACK is returned if the first electronic device is operating. The processing method according to appendix 12, characterized by:

001 electronic device 01A integrated device 80A electronic device 50A bus 60A bus 05A connection line 10A electronic device 20A electronic device 30A electronic device 40A electronic device 010 integrated device 020 information processing system 500 serial bus 600 serial bus 100 slave device 101 selector 102 data register 103 Address register 104 Status monitoring circuit 105 Self device identification circuit 106 Other device identification circuit 107 Register selector 108 Arbitration circuit 109 Output generation register 110 Input / output register 111 Input / output register 11n Input / output register 120 Buffer 121 Buffer 122 Buffer 123 Buffer 124 Gate 125 gate 126 AND
127 AND
128 AND
129 AND
171 Internal address register 172 Selection circuit 173 Selection signal generation circuit 174 ACK generation circuit 181 Arbitration partial circuit 182 Switching signal generation circuit 183 ACK generation circuit 200 Slave device 201 Selector 202 Data register 203 Address register 204 Status monitoring circuit 205 Self device identification circuit 206 Other device identification circuit 207 Register selector 208 Arbitration circuit 209 Output generation register 210 Input / output register 211 Input / output register 21n Input / output register 300 Slave device 400 Slave device 050 Connection line 701 CPU
702 CPU
703 CPU
704 CPU
910 System bus 920 Main storage device 930 Bus adapter 940 I / O bus 951 I / O processor 952 I / O processor 961 I / O device 962 I / O device 963 I / O device 964 I / O device

Claims (3)

A first electronic device connected to the first bus;
A second electronic device connected to the second bus;
A first electronic device connected to the first bus and the second bus;
The third electronic device includes:
If the first bus does not operate normally, access the first electronic device via the second bus and the second electronic device;
If the second bus does not operate normally, the second electronic device is accessed via the first bus and the first electronic device ;
When the first electronic device receives access to the second electronic device via the first bus and the first electronic device, the first electronic device sends the second electronic device via the first bus. Control to receive access,
When the second electronic device receives access to the first electronic device via the second bus and the second electronic device, the second electronic device passes the second bus to the first electronic device. Control to receive access,
Further, the first electronic device responds to the access via the second bus and the second electronic device via the second electronic device and the second bus. ,
The second electronic device responds to the access via the first bus and the first electronic device via the first electronic device and the first bus,
A first slave device which is the first electronic device including a first input / output register;
A second slave device, which is the second electronic device, including a second input / output register;
If the first bus does not operate normally, the second bus and the second slave device access the first input / output register, and the second bus operates normally. If not, a service processor that is the third electronic device that accesses the second input / output register via the first bus and the first slave device, and
When the first slave device receives an access to the second input / output register via the first bus from the service processor, the first slave device responds with an ACK if the second slave device is not operating. ACK is not responded if it is in operation.
When the second slave device receives an access to the first input / output register from the service processor via the second bus, the second slave device responds with an ACK if the first slave device is not operating. ACK is not responded if it is in operation.
Integrated device.   An integrated device according to claim 1;
  A first CPU connected to the first slave device;
  A second CPU connected to the second slave device;
Including an information processing system.   A first electronic device connected to a first bus; a second electronic device connected to a second bus; the first bus; and a third electronic device connected to the second bus. An integrated device comprising: an electronic device;
  The third electronic device includes:
  If the first bus does not operate normally, access the first electronic device via the second bus and the second electronic device;
  If the second bus does not operate normally, the second electronic device is accessed via the first bus and the first electronic device;
  When the first electronic device receives access to the second electronic device via the first bus and the first electronic device, the first electronic device sends the second electronic device via the first bus. Control to receive access,
  When the second electronic device receives access to the first electronic device via the second bus and the second electronic device, the second electronic device passes the second bus to the first electronic device. Control to receive access,
  Further, the first electronic device responds to the access via the second bus and the second electronic device via the second electronic device and the second bus. ,
  The second electronic device responds to the access via the first bus and the first electronic device via the first electronic device and the first bus,
  A first slave device which is the first electronic device including a first input / output register;
  A second slave device, which is the second electronic device, including a second input / output register;
  If the first bus does not operate normally, the second bus and the second slave device access the first input / output register, and the second bus operates normally. If not, a service processor that is the third electronic device that accesses the second input / output register via the first bus and the first slave device, and
  When the first slave device receives an access to the second input / output register via the first bus from the service processor, the first slave device responds with an ACK if the second slave device is not operating. ACK is not responded if it is in operation.
  When the second slave device receives an access to the first input / output register from the service processor via the second bus, the second slave device responds with an ACK if the first slave device is not operating. ACK is not responded if it is in operation.
A processing method for an integrated device.

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